RT8167AGQW - Richtek - Product.Network

RT8167A

DS8167A-00 January 2012 www.richtek.com

Dual Single-Phase PWM Controller for CPU Core/GFX

Power Supply

Features

zG-NAVPTM (Green Native Active Voltage Positioning)

Topology

zDual Output Controller with Two Built-in Gate

Drivers

zSerial VID Interface

z0.5% DAC Accuracy

zDifferential Remote Output Voltage Sensing

zBuilt-in ADC f or Platform Programming

zDiode Emulation Mode (DEM) at Light Load

Condition

zDroop Enable/Disable

zFa st Transient Response

zVR12/IMVP7 Compatible Power Management

States

zVR Ready Indicator

zThermal Throttling Indicator

zCurrent Monitor Output

zSwitching Frequency up to 1MHz per Phase

zProtection : OVP, UVP, NVP, OCP, UVLO

zSmall 48-Lead WQFN Package

zRoHS Compliant and Halogen Free

Applications

zVR12 / IMVP7 Intel CPU Core Supply

zA VP Step-down Converter

zNotebook/ Netbook/ Desktop Computer CPU Core

Supply

Ordering Information

Note :

Richtek products are :

` RoHS compliant and compatible with the current

requirements of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

General Description

The RT8167A is a dual single-phase synchronous Buck

PWM controller with integrated gate drivers, compliant

with Intel V R12/IMVP7 specification. A seri al VID (SVID)

interfa ce is built-in in the RT8167A to communicate with

Intel VR12/IMVP7 compliant CPU. The integrated

differential remote output voltage sensing function and

built-in high accuracy DAC achieve accurate output voltage

regulation.

The RT8167A supports VR12/ IMVP7 compatible power

management states and VID on-the-fly function. The

RT8167A operates in two power management states

including DEM in PS2 and Forced-CCM in PS1/PS0.

Richtek's proprietary G-NAVPTM (Green Native A VP) makes

A VP (Active Voltage Positioning) design ea sier and more

robust. By utilizing the G-NAVPTM topology, DEM and CCM

efficiency can be improved.

The RT8167A integrates high a ccuracy ADC for platform

setting functions, such as no-load offset or over current

level. Individual VR ready output signals are provided for

both CORE VR and GFX VR. The IC also features complete

fault protection functions, including over voltage, under

voltage, negative voltage, over current and under voltage

lockout. The RT8167A is available in a WQFN-48L 6x6

small foot print package.

Marking Information

RT8167AGQW : Product Number

YMDNN : Date Code

Package Type

QW : WQFN-48L 6x6 (W-Type)

RT8167A

Lead Plating System

G : Green (Halogen Free and Pb Free)

RT8167A

GQW

YMDNN

RT8167A

DS8167A-00 January 2012 www.richtek.com

Functional Pin Description

Pin No. Pin N ame Pin Function

1 IS EN1P Positive Curren t Sense Input of CORE VR

2 IS EN1N Negative Current Sense Input of CORE VR

3 COMP CORE VR Compensation. T his pin is the output node of the error amplifier.

4 FB CORE VR Feedback. This is the negative input node of the error amplifier.

5 RGND Return Ground for CORE VR. This pin is the negative i nput for differential remote

voltage sensing.

6 IMON Current Monitor Output of CORE VR. The output voltage VIMON of this pin is

proportional to the output current. For digital output current reporting, detailed

VIMON is generated by built-in ADC.

7 IMONFB

This pin is used to externally set the current monitor output gain of CORE VR.

Connect this pin with one r esistor RIMONFB to CO RE VCC_SENSE wh ile IMON pin

is connected to ground with another resistor, RIMON. The current monitor output

gain can be set by the ratio of these two resistor s.

8 DRPEN Droop Enable Mode Setting of CORE VR. An internal 80μA current source is

connected to the DRPEN pin and flows out of this pin for 10μs. Connect this pin to

VCC to enable droop function. Connect this pin to GND to disable droop function.

9 OFS Output Voltage No-Load Offset Setting of C ORE VR. C onnect to a resistive voltage

divider from VCC to GND to set the pin voltage VOFS for offset setting. Connect this

pin to GND for no offset setting.

10 OFSA Output Voltage No-Load Offset Setting of GFX VR. Connect to a resistive voltage

divider from VCC to GND to set the pin vo l tage VOFSA for offset setting . Conne ct this

pin to GND for no offset setting.

Pin Configurations

WQFN-48L 6x6

(TOP VIEW)

ISEN1P

COMP

VCC

GFXPS2

OFSA

OFS

DRPEN

IMONFB

RGND

IMON

ISEN1N

SETINIA

SETINI

TMPMAX

ICCMAX

ICCMAXA

TSEN

VR_READY

OCSET

TSENA

OCSETA

IBIAS

ISENAP

FBA

COMPA

VRA_READY

DRPENA

VDIO

VCLK

IMONFBA

RGNDA

IMONA

ISENAN

TONSET

BOOT

UGATE

PHASE

LGATE

PVCC

TONSETA

LGATEA

PHASEA

UGATEA

BOOTA

GND

242322212019181716151413

373839404142434445464748

VRHOT

ALERT

RT8167A

DS8167A-00 January 2012 www.richtek.com

Pin No. Pin Name Pin Function

11 GFXPS2 Forced DEM Enable Setting of GFX VR . Connec t to VCC f or forced-DEM setting

and connect to GND for following SVID power state command.

12 VCC 5V Po wer Supply Input of Contr o ller. Bypa ss this pin to GND with a 1 μF or greater

ceramic capacitor.

13 SETINIA Initial Startup V ol tage VINI_GFX S etting of GFX VR. Connect to a resistive voltage

divider from V CC to GND to set the pin voltage VSETINIA for GFX VR initial startup

voltage VINI_GFX setting. Connect this pin to GND for 0V VINI_GFX setting.

14 SETINI Initial Startup Voltage VINI_CORE Setting of CORE VR. Connect to a resistive

voltage divider from VCC to GND to set the pin voltage VSETINI f or CORE VR init ial

star tup voltage VINI_CORE setting. Co nnect this pin to GND for 0V VINI_CORE setting.

15 TMPMAX Maximum Temperature Setting of CORE VR. Connect to a resistive voltage divider

from V CC to GND to set the pin voltage VTMPMAX for TMPMAX setting.

16 ICCMAX Maximum Current Setting of CORE VR. Connect to a resistive voltage divider from

VCC to GND to set the p in voltage VICCMAX for ICCMAX setting.

17 ICCMAXA

Maximum Current Setting of GFX VR. Connec t to a resis tive vol tage divider from

VCC to GND to set the p in voltage VICCMAXA for ICCMAXA se tting.

18 TSEN Ther m al Monitor S ense Pin of CORE VR.

19 OCSET Over Current Protection Setting of COR E VR. Connect to a resistive voltage divider

from VCC to GND to set the pin voltage VOCSET from 0 to 3.3V for CORE VR over

current protection threshold.

20 TSENA Ther m al Monitor S ense Pin of GFX V R.

21 OCSETA Over Current Protec tion Setting of GFX VR. C onnect to a res istive voltage divider

from VCC to GND to adjust the pin voltage VOCSETA from 0 to 3. 3V fo r GFX VR over

current protection threshold.

22 IBIAS Inter n al bias current setting. Connect a 53.6kΩ resistor from IBIAS pin to GND.

23 VRHOT Ther m al Monitor Output (Active Low). Connect a pull high resistor from VR HOT pin

to 1.05V.

24 VR_READY

Voltage Ready Indicator of CORE VR. Connect a pull high resistor from

VR_READ Y pin to 1.05V.

25 VRA_READY

Voltage Ready Indicator GFX VR . Connect a pull high resistor from VRA_READY

pin to 1.05V.

26 DRPENA Droop Enable Mode Setting of GFX VR. An internal 80μA current source is

connected to DRPENA pin and flows out of this pin for 10μs. Connect this pin to

VCC to enable droop function. Connect this pin to GND to disable droop function.

27 ALERT SVID Alert Pin (Active Low). Connect a 75 Ω r esistor from ALERT pin to 1.05V.

28 VDIO Controller and CPU Data Transmission Interface. Connecting a 64.9Ω resistor

between VDIO pin to 1.05V.

29 VCLK Synchronous Clock from the CPU. Connect a 64.9Ω resistor from VCLK pin to

1.05V.

30 IMONFBA

This pin is used to externally set the current monitor output gain of GFX VR.

Connect this pin with one resistor RIMONFBA to GFX VCC_SENSE while IMON pin

is connected to ground with another resistor RIMONA. The current monitor output

gain can be set by the ratio of these two resistor s.

31 IMONA Current Monitor Output of GFX VR. The output voltage VIMONA of this pin is

proportional to the output current. For digital output current reporting, detailed

VIMONA is generated by built-in ADC.

RT8167A

4DS8167A-00 January 2012www.richtek.com

Pin No. Pin Name Pin Function

32 RGNDA

Return Ground for GFX VR. This pin is the negative input for differential

remote voltage sensing.

33 FBA GFX VR Feedback. This is the negative input node of the err or amplifier.

34 COMPA GF X VR Compensation. This pin is the output node of the err or amplifier.

35 IS ENAN Negative Current Sense Input of GFX VR.

36 IS ENAP Positive Current Sense Input of GFX VR.

37 TONSETA On-Time Setting of GFX VR . Connect this pin to VIN w ith one resistor.

38 EN Chip Enable (Active High).

39 BOOTA

Bootstrap F lying Capacitor Connection for GFX VR. This pin powers the high

side MOSFET drivers. Connect this pin to PHASEA with an external ceramic

capacitor.

40 UGATEA

High Side MO SFET Floating Gate Driver Output for GFX VR. Connec t this

pin to the gate of high side MOSFET.

41 PHASEA

Switching Node Connection for GFX VR. PHASEA is also the zero cross

dete ct input for GFX V R. Connect this pin to the high side MOSFET sour ces

together with the low side MOSFE T dr ains and the inductor.

42 LGATEA

Synchronous-Rectifier Gate Driver Output of GF X VR. Connect this pin to the

gate of low side MOSFE T.

43 PVCC 5V Power Supply of Driver. Bypass this pin to GND with a 1μF or greater

ceramic capacitor.

44 LGATE

Synchronous-Rectifier Gate Driver Output of CORE VR. Connect this pin to

the gate of low side MOSFET.

45 PHASE

Switching Node Connection for CORE VR. PHASE is the internal lower

supply rail for the UGATE. PHASE is also the zero cross detect input for

CORE VR. Connect this pin to the high side MOSFET sources together with

the low side MOSFET drains and the inductor .

46 UGATE

High Side MOS FE T Floating Gate Driver Output for CORE V R. Connect this

pin to the gate of high side MOSFET.

47 BOOT Bootstrap Flying Capacitor Connection for CORE VR. This pin powers the

high side MOSFET drivers. Connect this pin to PHASE with an external

ceramic capacitor.

48 TONSET On-T ime Setting of CORE VR. Connect this pin to VIN with one resistor.

49 (Exposed pad) GND Gro und. The exposed pad must be so ld ered to a larg e PC B and connected to

GND for m aximum power dissipation.

RT8167A

DS8167A-00 January 2012 www.richtek.com

Typical Application Circuit

Figure 1. Dual Output Application Circuit

ß = 3380ß = 3380

VCC

C19

GND

49 (Exposed Pad)

PHASE

VDIO

38EN

IBIAS

R64

R59

R58

TSENA

TSEN

VCC

R62R63

10OFSA

11GFXPS2

VCC

16ICCMAX

R37R38R39

ICCMAXA

R47R48R49

TMPMAX

ICCMAX

ICCMAXA

TMPMAX

OFS

R40

R50

R41

OFSA

OFS

R51

R42

R52

GFXPS2

26DRPENA

8DRPEN

OCSETA

R19

R18

R17

13SETINIA

R20R21R22

SETINI

R31R32R33

R30

R29

R28

OCSET

DRPENA

DRPEN

OCSETA

SETINIA

SETINI

OCSET

29VCLK

28VDIO

25VRA_READY

24VR_READY

ALERT

VRHOT

VCLK

ALERT

R8R7R6

VCCP

VRA_READY

VR_READY

R9 R10 R11

VRHOT

RT8167A

VCC

TONSET

VIN

5V to 25V

BOOT

UGATEVCORE

ISEN1N

ISEN1P1R14

R13

C12

C11

IMONFB

R23

PVCCC8

R12

RNTC1

R15

R16

LGATE

C10

R24

IMON

C13R35R34

R36

TONSETAVIN

R43

C14

R44

RNTCA

VGFX

UGATEA

LGATEA

BOTTA

PHASEA

C16

C15

R45

R46

ISENAN

ISENAP36

FBA

C23

C22

IMONFBA

C20

R60

R61

C21

GFX VCC_SENSE

R68

GFX VSS_SENSE

VGFX

R65R67

R66

IMONA

C24R69

R70

IMONA

COMPA34

RGNDA

R55

R54

C17

R53

COMPR25

CORE VCC_ SENSE

R27

RGND5

R26

VCORE

CORE VSS_SENSE

IMON

Optional

R56

R57

C18

Optional

C25

2.2

1µF

130 130 150 10k 10k 75

10k

8.7k

27k

10k

10kNC

100k

150k

51k

10k

1.6k

5.1k

33k

10k

12k

10k

12k

R72

750

R71

750

1k1k53.6k

130k5.1

0.1µF

00.1µF

10µF

1µH

4.7k

Optional

1µF

3.9k

C26

330µF

/9m330µF

/9m

4.7k

2.4k

0.068µF

10k

Optional

71k10k100

100

620k

39k

0.1µF

10µF

2µH

5V to 25

Optional

C27

330µF

/15m330µF

/15m

11k

1.2k

0.1µF

10k

OptionalOptional

100

42k10k

100

180k

1.8M

0.1µF

RNTCTA

RNTCT1

DCR 7.6m

DCR 14.6m

RT8167A

6DS8167A-00 January 2012www.richtek.com

Figure 2. Single Output Application Circuit

0.1µF

VCC

5VVCC

OFSA

VCLK

VCLK28

VDIO

VDIO27

ALERT

VCCP

VR_READY

VRHOT23

ALERT

VRHOT

VCORE

1µF

R11 0

R12

10µF

0.1µF

R4 0

R5 0

VIN

5V to 25

130k R3

5.1

RT8167A

TONSET

ISEN1N

ISEN1P1

PVCC43

BOOT

UGATE

PHASE

LGATE

IMON

COMP

IMONFB

RGND

VCC

GND

Floating

GND

VCC

GND

Floating

VCC

GND

VCC

GND

VCC

GND

UGATEA

LGATEA

TONSETA

BOOTA

PHASEA

VRA_READY

GFXPS2

ICCMAXA

ISENAN

ISENAP

IMONA

COMPA

FBA

IMONFBA

RGNDA

SETINIA

TSENA

OCSETA

DRPENA

GND

49 (Exposed Pad)

IBIAS

R38

53.6k

NTCT1

10k

R36

12k

TSEN

VCC

R37

ICCMAX

TMPMAX

OFS

VCC

R30

51k R31

150k

R33

33k R34

5.1k

ICCMAX

TMPMAX

R32

OFS

R35

DRPEN

R16

10k

VCC

R17

8.7k R18

10k

SETINI

R28

10k R29

R27

OCSET

DRPEN

SETINI

OCSET

R21

71k

C12

C11

R23

100

R19

10k

R22

10k

C10

R20

IMON

C13

0.1µF

R24

CORE VCC_SENSE

R26

R25

VCORE

CORE VSS_SENSE

Optional

R14

4.7k

R15

2.4k

R13 3.9k

RNTC1

4.7k

Optional

R8R7R6 R9

R10

130 130 150 10k 75

2.2

1µF

Optional

C25

R39

750

0.068µF

1µH

330µF

/9m

Optional

330µF

/9m

620k

39k

100k

Optional Optional

C26

ß = 3380

DCR 7.6m

RT8167A

DS8167A-00 January 2012 www.richtek.com

Function Block Diagram

ICCMAXA

COMP

RGND

TSEN

ISEN1N

ISEN1P

OCSET

FBA

COMPA

ERROR

AMP

GFX VR OCP

GFX VR

Protection Si gnal

ISENAN

ICCMAX

TMPMAX

Control & Protection Logic

MUX

ADC

SVID XCVR

VDIO

VCLK

TONSETA

ISENAP

OCSETA

VR_READY

VRA_READY

RGNDA

PWM CMP

GFX VR

VID/OFS control

Slew Rate Control

VREFA

VREF

VCC

VREF

IMONFB

UVLO

GFX VR

OV/UV/NV

IBIAS

TONSET

GFX VR

Current Monitor

VREFA

IMONFBA

IMONA

BOOT

UGATE

PHASE

LGATE

PVCC

GFX VR CCRCOT

PWM Generator

BOOTA

UGATEA

PHASEA

LGATEA

OFS

SETINIA

SETINI

TSENA

DRPENA

DRPEN

IMON

OFSA Droop Enabler

GFX 0LL EN

CORE 0LL EN

CORE VR

Current Monitor

GND

CORE VR

CCRCOT

PWM Generator

Droop Enabler

CORE 0LL EN

PVDD

Driver logic

control

DAC

OFS Control

Offset

Cancellation

GFX VR

Slew Rate control

ERROR

AMP

CORE VR

VID/OFS Control

Slew Rate Control

DAC

OFS Control

Offset

Cancellation

CORE VR

Slew Rate control

Driver logic

control

GFX VR Slew

Rate control

CORE VR Slew

Rate control

GFX VR

VID/OFS Control

CORE VR

VID/OFS Control

GFX 0LL EN

CORE 0LL VCS

GFX 0LL VCS

CORE 0LL VCS CORE 0LL EN

GFX 0LL VCS

CORE VR

Protection Signa l

GFX VR

Protection Signal

CORE VR

OCP

CORE VR

Protection Signal

CORE VR

OV/UV/NV

2.14V

PWM CMP

VREFA

VREF

Current

Sense AMP

Current

Sense AMP

GFX VR

Operation Mode

CORE VR

Operation Mode

GFX VR

Operation Mode

CORE VR

Operation Mode

GFXPS2

VRHOT

ALERT

-X4.8

X4.8

RT8167A

8DS8167A-00 January 2012www.richtek.com

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 VDAC Voltage

0 0 0 0 0 0 0 0 0 0 0.000

0 0 0 0 0 0 0 1 0 1 0.250

0 0 0 0 0 0 1 0 0 2 0.255

0 0 0 0 0 0 1 1 0 3 0.260

0 0 0 0 0 1 0 0 0 4 0.265

0 0 0 0 0 1 0 1 0 5 0.270

0 0 0 0 0 1 1 0 0 6 0.275

0 0 0 0 0 1 1 1 0 7 0.280

0 0 0 0 1 0 0 0 0 8 0.285

0 0 0 0 1 0 0 1 0 9 0.290

0 0 0 0 1 0 1 0 0 A 0.295

0 0 0 0 1 0 1 1 0 B 0.300

0 0 0 0 1 1 0 0 0 C 0.305

0 0 0 0 1 1 0 1 0 D 0.310

0 0 0 0 1 1 1 0 0 E 0.315

0 0 0 0 1 1 1 1 0 F 0.320

0 0 0 1 0 0 0 0 1 0 0.325

0 0 0 1 0 0 0 1 1 1 0.330

0 0 0 1 0 0 1 0 1 2 0.335

0 0 0 1 0 0 1 1 1 3 0.340

0 0 0 1 0 1 0 0 1 4 0.345

0 0 0 1 0 1 0 1 1 5 0.350

0 0 0 1 0 1 1 0 1 6 0.355

0 0 0 1 0 1 1 1 1 7 0.360

0 0 0 1 1 0 0 0 1 8 0.365

0 0 0 1 1 0 0 1 1 9 0.370

0 0 0 1 1 0 1 0 1 A 0.375

0 0 0 1 1 0 1 1 1 B 0.380

0 0 0 1 1 1 0 0 1 C 0.385

0 0 0 1 1 1 0 1 1 D 0.390

0 0 0 1 1 1 1 0 1 E 0.395

0 0 0 1 1 1 1 1 1 F 0.400

0 0 1 0 0 0 0 0 2 0 0.405

0 0 1 0 0 0 0 1 2 1 0.410

0 0 1 0 0 0 1 0 2 2 0.415

Table 1. IMVP7/VR12 Compliant VID Table

RT8167A

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VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage

0 0 1 0 0 0 1 1 2 3 0.420

0 0 1 0 0 1 0 0 2 4 0.425

0 0 1 0 0 1 0 1 2 5 0.430

0 0 1 0 0 1 1 0 2 6 0.435

0 0 1 0 0 1 1 1 2 7 0.440

0 0 1 0 1 0 0 0 2 8 0.445

0 0 1 0 1 0 0 1 2 9 0.450

0 0 1 0 1 0 1 0 2 A 0.455

0 0 1 0 1 0 1 1 2 B 0.460

0 0 1 0 1 1 0 0 2 C 0.465

0 0 1 0 1 1 0 1 2 D 0.470

0 0 1 0 1 1 1 0 2 E 0.475

0 0 1 0 1 1 1 1 2 F 0.480

0 0 1 1 0 0 0 0 3 0 0.485

0 0 1 1 0 0 0 1 3 1 0.490

0 0 1 1 0 0 1 0 3 2 0.495

0 0 1 1 0 0 1 1 3 3 0.500

0 0 1 1 0 1 0 0 3 4 0.505

0 0 1 1 0 1 0 1 3 5 0.510

0 0 1 1 0 1 1 0 3 6 0.515

0 0 1 1 0 1 1 1 3 7 0.520

0 0 1 1 1 0 0 0 3 8 0.525

0 0 1 1 1 0 0 1 3 9 0.530

0 0 1 1 1 0 1 0 3 A 0.535

0 0 1 1 1 0 1 1 3 B 0.540

0 0 1 1 1 1 0 0 3 C 0.545

0 0 1 1 1 1 0 1 3 D 0.550

0 0 1 1 1 1 1 0 3 E 0.555

0 0 1 1 1 1 1 1 3 F 0.560

0 1 0 0 0 0 0 0 4 0 0.565

0 1 0 0 0 0 0 1 4 1 0.570

0 1 0 0 0 0 1 0 4 2 0.575

0 1 0 0 0 0 1 1 4 3 0.580

0 1 0 0 0 1 0 0 4 4 0.585

0 1 0 0 0 1 0 1 4 5 0.590

RT8167A

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VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage

0 1 0 0 0 1 1 0 4 6 0.595

0 1 0 0 0 1 1 1 4 7 0.600

0 1 0 0 1 0 0 0 4 8 0.605

0 1 0 0 1 0 0 1 4 9 0.610

0 1 0 0 1 0 1 0 4 A 0.615

0 1 0 0 1 0 1 1 4 B 0.620

0 1 0 0 1 1 0 0 4 C 0.625

0 1 0 0 1 1 0 1 4 D 0.630

0 1 0 0 1 1 1 0 4 E 0.635

0 1 0 0 1 1 1 1 4 F 0.640

0 1 0 1 0 0 0 0 5 0 0.645

0 1 0 1 0 0 0 1 5 1 0.650

0 1 0 1 0 0 1 0 5 2 0.655

0 1 0 1 0 0 1 1 5 3 0.660

0 1 0 1 0 1 0 0 5 4 0.665

0 1 0 1 0 1 0 1 5 5 0.670

0 1 0 1 0 1 1 0 5 6 0.675

0 1 0 1 0 1 1 1 5 7 0.680

0 1 0 1 1 0 0 0 5 8 0.685

0 1 0 1 1 0 0 1 5 9 0.690

0 1 0 1 1 0 1 0 5 A 0.695

0 1 0 1 1 0 1 1 5 B 0.700

0 1 0 1 1 1 0 0 5 C 0.705

0 1 0 1 1 1 0 1 5 D 0.710

0 1 0 1 1 1 1 0 5 E 0.715

0 1 0 1 1 1 1 1 5 F 0.720

0 1 1 0 0 0 0 0 6 0 0.725

0 1 1 0 0 0 0 1 6 1 0.730

0 1 1 0 0 0 1 0 6 2 0.735

0 1 1 0 0 0 1 1 6 3 0.740

0 1 1 0 0 1 0 0 6 4 0.745

0 1 1 0 0 1 0 1 6 5 0.750

0 1 1 0 0 1 1 0 6 6 0.755

0 1 1 0 0 1 1 1 6 7 0.760

0 1 1 0 1 0 0 0 6 8 0.765

0 1 1 0 1 0 0 1 6 9 0.770

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VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage

0 1 1 0 1 0 1 0 6 A 0.775

0 1 1 0 1 0 1 1 6 B 0.780

0 1 1 0 1 1 0 0 6 C 0.785

0 1 1 0 1 1 0 1 6 D 0.790

0 1 1 0 1 1 1 0 6 E 0.795

0 1 1 0 1 1 1 1 6 F 0.800

0 1 1 1 0 0 0 0 7 0 0.805

0 1 1 1 0 0 0 1 7 1 0.810

0 1 1 1 0 0 1 0 7 2 0.815

0 1 1 1 0 0 1 1 7 3 0.820

0 1 1 1 0 1 0 0 7 4 0.825

0 1 1 1 0 1 0 1 7 5 0.830

0 1 1 1 0 1 1 0 7 6 0.835

0 1 1 1 0 1 1 1 7 7 0.840

0 1 1 1 1 0 0 0 7 8 0.845

0 1 1 1 1 0 0 1 7 9 0.850

0 1 1 1 1 0 1 0 7 A 0.855

0 1 1 1 1 0 1 1 7 B 0.860

0 1 1 1 1 1 0 0 7 C 0.865

0 1 1 1 1 1 0 1 7 D 0.870

0 1 1 1 1 1 1 0 7 E 0.875

0 1 1 1 1 1 1 1 7 F 0.880

1 0 0 0 0 0 0 0 8 0 0.885

1 0 0 0 0 0 0 1 8 1 0.890

1 0 0 0 0 0 1 0 8 2 0.895

1 0 0 0 0 0 1 1 8 3 0.900

1 0 0 0 0 1 0 0 8 4 0.905

1 0 0 0 0 1 0 1 8 5 0.910

1 0 0 0 0 1 1 0 8 6 0.915

1 0 0 0 0 1 1 1 8 7 0.920

1 0 0 0 1 0 0 0 8 8 0.925

1 0 0 0 1 0 0 1 8 9 0.930

1 0 0 0 1 0 1 0 8 A 0.935

1 0 0 0 1 0 1 1 8 B 0.940

1 0 0 0 1 1 0 0 8 C 0.945

1 0 0 0 1 1 0 1 8 D 0.950

RT8167A

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VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage

1 0 0 0 1 1 1 0 8 E 0.955

1 0 0 0 1 1 1 1 8 F 0.960

1 0 0 1 0 0 0 0 9 0 0.965

1 0 0 1 0 0 0 1 9 1 0.970

1 0 0 1 0 0 1 0 9 2 0.975

1 0 0 1 0 0 1 1 9 3 0.980

1 0 0 1 0 1 0 0 9 4 0.985

1 0 0 1 0 1 0 1 9 5 0.990

1 0 0 1 0 1 1 0 9 6 0.995

1 0 0 1 0 1 1 1 9 7 1.000

1 0 0 1 1 0 0 0 9 8 1.005

1 0 0 1 1 0 0 1 9 9 1.010

1 0 0 1 1 0 1 0 9 A 1.015

1 0 0 1 1 0 1 1 9 B 1.020

1 0 0 1 1 1 0 0 9 C 1.025

1 0 0 1 1 1 0 1 9 D 1.030

1 0 0 1 1 1 1 0 9 E 1.035

1 0 0 1 1 1 1 1 9 F 1.040

1 0 1 0 0 0 0 0 A 0 1.045

1 0 1 0 0 0 0 1 A 1 1.050

1 0 1 0 0 0 1 0 A 2 1.055

1 0 1 0 0 0 1 1 A 3 1.060

1 0 1 0 0 1 0 0 A 4 1.065

1 0 1 0 0 1 0 1 A 5 1.070

1 0 1 0 0 1 1 0 A 6 1.075

1 0 1 0 0 1 1 1 A 7 1.080

1 0 1 0 1 0 0 0 A 8 1.085

1 0 1 0 1 0 0 1 A 9 1.090

1 0 1 0 1 0 1 0 A A 1.095

1 0 1 0 1 0 1 1 A B 1.100

1 0 1 0 1 1 0 0 A C 1.105

1 0 1 0 1 1 0 1 A D 1.110

1 0 1 0 1 1 1 0 A E 1.115

1 0 1 0 1 1 1 1 A F 1.120

1 0 1 1 0 0 0 0 B 0 1.125

1 0 1 1 0 0 0 1 B 1 1.130

RT8167A

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VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage

1 0 1 1 0 0 1 0 B 2 1.135

1 0 1 1 0 0 1 1 B 3 1.140

1 0 1 1 0 1 0 0 B 4 1.145

1 0 1 1 0 1 0 1 B 5 1.150

1 0 1 1 0 1 1 0 B 6 1.155

1 0 1 1 0 1 1 1 B 7 1.160

1 0 1 1 1 0 0 0 B 8 1.165

1 0 1 1 1 0 0 1 B 9 1.170

1 0 1 1 1 0 1 0 B A 1.175

1 0 1 1 1 0 1 1 B B 1.180

1 0 1 1 1 1 0 0 B C 1.185

1 0 1 1 1 1 0 1 B D 1.190

1 0 1 1 1 1 1 0 B E 1.195

1 0 1 1 1 1 1 1 B F 1.200

1 1 0 0 0 0 0 0 C 0 1.205

1 1 0 0 0 0 0 1 C 1 1.210

1 1 0 0 0 0 1 0 C 2 1.215

1 1 0 0 0 0 1 1 C 3 1.220

1 1 0 0 0 1 0 0 C 4 1.225

1 1 0 0 0 1 0 1 C 5 1.230

1 1 0 0 0 1 1 0 C 6 1.235

1 1 0 0 0 1 1 1 C 7 1.240

1 1 0 0 1 0 0 0 C 8 1.245

1 1 0 0 1 0 0 1 C 9 1.250

1 1 0 0 1 0 1 0 C A 1.255

1 1 0 0 1 0 1 1 C B 1.260

1 1 0 0 1 1 0 0 C C 1.265

1 1 0 0 1 1 0 1 C D 1.270

1 1 0 0 1 1 1 0 C E 1.275

1 1 0 0 1 1 1 1 C F 1.280

1 1 0 1 0 0 0 0 D 0 1.285

1 1 0 1 0 0 0 1 D 1 1.290

1 1 0 1 0 0 1 0 D 2 1.295

1 1 0 1 0 0 1 1 D 3 1.300

1 1 0 1 0 1 0 0 D 4 1.305

1 1 0 1 0 1 0 1 D 5 1.310

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14 DS8167A-00 January 2012www.richtek.com

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage

1 1 0 1 0 1 1 0 D 6 1.315

1 1 0 1 0 1 1 1 D 7 1.320

1 1 0 1 1 0 0 0 D 8 1.325

1 1 0 1 1 0 0 1 D 9 1.330

1 1 0 1 1 0 1 0 D A 1.335

1 1 0 1 1 0 1 1 D B 1.340

1 1 0 1 1 1 0 0 D C 1.345

1 1 0 1 1 1 0 1 D D 1.350

1 1 0 1 1 1 1 0 D E 1.355

1 1 0 1 1 1 1 1 D F 1.360

1 1 1 0 0 0 0 0 E 0 1.365

1 1 1 0 0 0 0 1 E 1 1.370

1 1 1 0 0 0 1 0 E 2 1.375

1 1 1 0 0 0 1 1 E 3 1.380

1 1 1 0 0 1 0 0 E 4 1.385

1 1 1 0 0 1 0 1 E 5 1.390

1 1 1 0 0 1 1 0 E 6 1.395

1 1 1 0 0 1 1 1 E 7 1.400

1 1 1 0 1 0 0 0 E 8 1.405

1 1 1 0 1 0 0 1 E 9 1.410

1 1 1 0 1 0 1 0 E A 1.415

1 1 1 0 1 0 1 1 E B 1.420

1 1 1 0 1 1 0 0 E C 1.425

1 1 1 0 1 1 0 1 E D 1.430

1 1 1 0 1 1 1 0 E E 1.435

1 1 1 0 1 1 1 1 E F 1.440

1 1 1 1 0 0 0 0 F 0 1.445

1 1 1 1 0 0 0 1 F 1 1.450

1 1 1 1 0 0 1 0 F 2 1.455

1 1 1 1 0 0 1 1 F 3 1.460

1 1 1 1 0 1 0 0 F 4 1.465

1 1 1 1 0 1 0 1 F 5 1.470

1 1 1 1 0 1 1 0 F 6 1.475

1 1 1 1 0 1 1 1 F 7 1.480

1 1 1 1 1 0 0 0 F 8 1.485

RT8167A

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VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage

1 1 1 1 1 0 0 1 F 9 1.490

1 1 1 1 1 0 1 0 F A 1.495

1 1 1 1 1 0 1 1 F B 1.500

1 1 1 1 1 1 0 0 F C 1.505

1 1 1 1 1 1 0 1 F D 1.510

1 1 1 1 1 1 1 0 F E 1.515

1 1 1 1 1 1 1 1 F F 1.520

RT8167A

16 DS8167A-00 January 2012www.richtek.com

Recommended Operating Conditions (Note 4)

zSupply Voltage of Controller , VCC -------------------------------------------------------------------- 4.5V to 5.5V

zSupply V oltage of Gate Driver , VPVCC ---------------------------------------------------------------- 4.5V to 5.5V

zBattery Input Voltage, VIN ------------------------------------------------------------------------------ 5V to 25V

zJunction T emperature Range--------------------------------------------------------------------------- −40°C to 125°C

zAmbient T emperature Range--------------------------------------------------------------------------- −40°C to 85°C

Absolute Maximum Ratings (Note 1)

zVCC to GND ----------------------------------------------------------------------------------------------- −0.3V to 6.5V

zPVCC to GND --------------------------------------------------------------------------------------------- −0.3V to 6.5V

zRGNDx to GND ------------------------------------------------------------------------------------------- −0.3V to 0.3V

zTONSETx to GND ---------------------------------------------------------------------------------------- −0.3V to 28V

zOthers------------------------------------------------------------------------------------------------------- −0.3V to (VCC + 0.3V)

zBOOTx to PHASEx-------------------------------------------------------------------------------------- −0.3V to 6.5V

zPHASEx to GND

D C------------------------------------------------------------------------------------------------------------ −0.3V to 28V

<20ns ------------------------------------------------------------------------------------------------------- −8V to 32V

zUGATEx to PHASEx

D C------------------------------------------------------------------------------------------------------------ −0.3V to (BOOTx − PHASEx)

<20ns ------------------------------------------------------------------------------------------------------- −5V to 7.5V

zLGA TEx to GND

D C------------------------------------------------------------------------------------------------------------ −0.3V to (PVCC − 0.3V)

<20ns ------------------------------------------------------------------------------------------------------- −2.5V to 7.5V

zPower Dissipation, PD @ TA = 25°C

WQFN−48L 6x6------------------------------------------------------------------------------------------- 2.857W

zPa ckage Thermal Re sistance (Note 2)

WQFN−48L 6x6, θJA ------------------------------------------------------------------------------------- 35°C/W

WQFN−48L 6x6, θJC------------------------------------------------------------------------------------- 6°C/W

zJunction T emperature------------------------------------------------------------------------------------ 150°C

zLead Temperature (Soldering, 10 sec.)-------------------------------------------------------------- 2 60°C

zStorage T emperature Range --------------------------------------------------------------------------- −65°C to 150°C

zESD Susceptibility (Note 3)

HBM (Human Body Mode) ----------------------------------------------------------------------------- 2kV

MM (Ma chine Mode) ------------------------------------------------------------------------------------- 200V

Electrical Characteristics

Parameter Symbol Test Conditions Min Typ Max Unit

S upply I nput VCC/VPVCC V

EN = 1.05V, Not Swit ching 4. 5 5 5. 5 V

Input Voltage Range VIN B at tery In put V ol t age 5 -- 25 V

Supply Current

(VCC + P VCC) IVCC + IPVCC V

EN = 1.05V, Not Swit ching - - 12 20 m A

Supply Current

(TON SE Tx) ITONSETx V

FB =1V, VIN = 12V, RTON = 1 0 0kΩ -- 110 -- μA

(VCC = 5V, TA = 25°C, unless otherwise specified)

RT8167A

DS8167A-00 January 2012 www.richtek.com

Parameter Symbol Test Conditions Min Typ Max Unit

Shutdown Current

(PVCC + VCC) IV CC_SHDN

+ I PVCC_SHDN VEN = 0V -- -- 5 μA

Shutdown Current

(TONSETx) ITONSETx_SHDN V

EN = 0V -- -- 5 μA

TON Settin g

TONSETx Voltage VTONSETx I

RTON = 80μA, VFBx = 1V 0.9 5 1.075 1.2 0V

On-Time tON I

RTON = 80μA, VFBx = 1V 31 5 35 0 38 5 ns

TONSET x I npu t Current

Ran ge IRTON V

FBx = 1.1V 25 -- 280 μA

Minimu m Off- Time TOFF_MIN -- 350 -- ns

Droop E nable / Disable

DRPENx Internal

Cur rent Source IDRPENx EN goes high within 10μs -- 80 -- μA

Droop Enable Threshold VDRPENx Detect V DRPENx, EN goes hig h

within 10μs 4.5 -- --

Droop Disable

Threshold VDRPENx Detect V DRPENx, EN goes hig h

within 10μs -- -- 2 V

GFX VR Forc ed DEM

GFXPS2x Enabl e

Threshold VGFXPS 4.3 -- -- V

GFXPS2x Di sable

Threshold VGFXPS -- -- 0.7 V

R ef er enc es and Syste m O utp ut Voltage

VIDSVID S etti ng = 1.0 00V~1 .52 0V

OFSSVID Setti ng = 0V −0.5 0 0.5 %VID

VIDSVID S etti ng = 0.8 00V~1 .00 0V

OFSSVID Setti ng = 0V −5 0 5

VIDSVID S etti ng = 0.5 00V~0 .80 0V

OFSSVID Setti ng = 0V −8 0 8

VIDSVID S etti ng = 0.2 50V~0 .50 0V

OFSSVID Setti ng = 0V −8 0 8

DAC Accuracy

(PS0/PS1) VFBx

VIDSVID Setting = 1.100V

OFSSVID Setting = −0.640V~ 0.635V −10 0 10

VINI_CORE = 0V, VINI_GFX = 0V 0 0.3125 0.5125

VINI_CORE = 0.9V , VINI_GFX = 0.9V 0.7375 0.9375 1.1375

VINI_CORE = 1V, VINI_GFX = 1V 1.3625 1.5625 1.7625

SET INIx Volta ge VSETINIx

VINI_CORE = 1.1V , VINI_GFX = 1 .1V 2 .6125 -- 5

Offset = 100mV 68 72 --

Offset = 50mV 52 56 60

Offset = −50mV 36 40 44

Offset = −100mV 20 24 28

Ex tern al OF Sx Vo lta ge VOFSx

N o Off se t Vol tage 0 8 12

%VCC

Impedance of OFSx Pin ROFSx 1 -- -- MΩ

RT8167A

18 DS8167A-00 January 2012www.richtek.com

Parameter Symbol Test Conditions Min Typ Max Unit

IBIAS Pin Voltage VIBIAS R

IBIAS = 53 .6 kΩ 2.09 2.14 2.19 V

SetVID Slow 2.5 3. 12 5 3.75

Dy nam ic VID S lew Rat e SRDVID SetVID Fast 10 12.5 15 mV/μs

E rror Amplifier

DC Gain ADC R

L = 4 7kΩ (Note5) 70 80 -- dB

Gain-Bandwidt h Pr oduct G BW CLOAD = 5pF (Note5) -- 10 -- MHz

Sle w Rat e SRCOMP CLOAD = 10pF (G ain = −4, RLOAD_COMP

= 4 7kΩ, VCOMPx = 0. 5V to 3V ) -- 5 -- V/μs

Output Voltage Range V COMP R

L = 4 7kΩ 0.5 -- 3.6 V

MAX So urce/Sink

Current ICOMP V

COMP = 2V - - 250 -- μA

Im pedance of F Bx RFBx 1 -- -- MΩ

Cu r rent Se ns e Am p lif ie r

Input Offset Voltage VOFS_CSA −1 -- 1 mV

I mpedance o f Neg. I nput RISENxN 1 -- -- MΩ

I mpedance of Pos. Inp ut RISENxP 1 -- -- MΩ

C ur ren t Sense

Differ ential Input R ange VCSDIx VFBx = 1.1V,

VCSDIx = VISENxP − VISENxN −50 -- 100 mV

C ur ren t Sense DC G ai n

(Loop) AI V

FBx = 1.1V, −30mV < VCSDIx < 50mV -- 10 -- V/V

VISEN Lin eari ty VISEN_ACC V

DAC = 1 .1V −30m V < V ISEN_IN < 50mV −1 -- 1 %

Dig ita l Cu rre nt Monitor

Current M o n itor Output

Vol tage (Droop Enabled) VIMONx_ENLL VFBx = 1V, VISENxN = 0 .9V,

VRIMONFBx = 10k, RIMONx = 1 60k -- 1.6 -- V

Current M o n itor Output

Vol tage (Droop Disabled) VIMONx_DISLL VCS DIx = VISENxP − VISENxN = 10 0mV

VFBx = 1V, VRIMONFBx = 10k,

RIMONx = 80k -- 1.6 -- V

IMO N Vol tage Range VIMON 0 -- 3.3 V

Digital IMON LSB 3.3V / 255 = 12.94mV -- 12. 94 - - mV

VIMONx = 388.3mV, DIOUT [ 7 : 0] = 30 27 30 33 Deci mal

VIMONx = 776.5mV, DIOUT [ 7 : 0] = 60 57 60 63 Deci mal

D igi t al C ode of IMON CDIMON

VIMONx = 1164.7mV, DIOU T [7 : 0] = 90 87 90 93 Dec imal

U pdat e Per i od of Di gital

Current M o n itor tIMON -- 1600 -- μs

Gate Driver

U pper Driver S our ce RUGATEx_sr VBOOTx − VPHASEx = 5 V

VBOOTx − VUGATEx = 0. 1 V -- 1 -- Ω

U pper Driver Sink RUGATEx_sk V

UGATEx = 0 .1V - - 1 -- Ω

Low er Driver S our c e RLGATEx_sr PVCC = 5 V, PVCC − VLGATEx = 0. 1V -- 1 -- Ω

Low er Driver Si nk RLGATEx_sk V

LGATEx = 0. 1V -- 0.5 - - Ω

I nt ern al Bo ot Char ging

Sw i tch O n- Re sist ance RBOOTx PVCC to BOO Tx - - 30 -- Ω

RT8167A

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Parameter Symbol Test Conditions Min Typ Max Unit

Ze ro Cu rren t De tec tion

Threshold VZCD_TH V

ZCD_TH = GND − VPHASEx -- 10 -- mV

Protection

U nder V ol tage Lock- out

Threshold VUVLO VCC Fal ling edge 4.04 4. 24 -- V

U nder V ol tage Lock- out

Hysteresis ΔVUVLO -- 100 -- mV

Over Voltage P rot ection

Threshold VOVP Respect to VOUT_MAXSVID, with

1μs filter ti me 100 150 200 mV

U nder Vol t age Protecti on

Threshold VUVP VUVP = VISENxN − V

REFx, 0.8V <

VREFx <1 .5 2 V, with 3μs filter time −350 −300 −250 mV

Negative Voltage

P ro te c tion Thr eshold VNVP V

NVP = VISENxN − GND −100 −50 -- mV

C ur rent Se nse Ga in for

O ver Curr ent Protection AOC VOCSET = 2.4V

VISENxP − VISENxN = 50mV -- 48 -- V/V

Logi c In puts

Logic-High VIH Wit h res pect to 1V, 70% 0.7 -- -- V

E N I nput

Threshold

Voltage Logic-Low VIL Wit h res pect to 1V, 30% -- - - 0.3 V

Leakage Current of EN −1 -- 1 μA

VIH With respect to Inte l Spec. 0.65 -- -- V

VCLK,V DIO Input

Threshold Vol tage VIL With respect to Intel Spec. -- -- 0.45 V

Leakage Current of

VCLK, VDIO ILEAK_IN −1 -- 1 μA

ALERT

A LER T Low Vol t age VALERT IALERT_ SI NK = 4mA -- -- 0.4 V

V R R eady

V Rx_READY Low Volt age VVRx_READY I

VR x_ R EADY_ SINK = 4mA - - -- 0.4 V

VRx_READY Delay tVRx_READY V

ISENxN = VBOOT to VVRx_READY hi gh 70 100 1 60 μs

Thermal Throt tling

VRH OT O u t p ut Vo l tag e VVRHOT IVRHOT_SINK = 40mA -- 0.4 -- V

H igh Im pedance Out put

AL ERT, VRx _REA DY,

VRHOT ILEAK_OUT −1 -- 1 μA

Temper at ur e Zone

TSEN Thr es hold for

Tmp_Zone [7] transition 100°C -- 1.8725 -- V

TSEN Thr es hold for

Tmp_Zone [6] transition 97°C -- 1.8175 -- V

TSEN Thr es hold for

Tmp_Zone [5] transition 94°C -- 1.7625 -- V

TSEN Thr es hold for

Tmp_Zone [4] transition 91°C -- 1.7075 -- V

TSEN Thr es hold for

Tmp_Zone [3] transition

VTSENx

88°C -- 1.6525 -- V

RT8167A

20 DS8167A-00 January 2012www.richtek.com

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in

the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may

affect device reliability.

Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is

measured at the exposed pad of the package.

Note 3. Devices are ESD sensitive. Handling precaution is recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

Note 5. Guaranteed by design.

Parameter Symbol Test Conditions Min Typ Max Unit

TSEN Thr es hold for

Tmp_Zone [ 2] t r ansition 85°C -- 1.5975 -- V

TSEN Thr es hold for

Tmp_Zone [ 1] t r ansition 82°C -- 1.5425 -- V

TSEN Thr es hold for

Tmp_Zone [ 0] t r ansition

VTSENx

75°C -- 1.4875 -- V

U pdat e Per i od t TSEN -- 1600 -- μs

ADC

Latency tLAT -- -- 400 μs

CICCMAX1 V

ICCMAX = 0 .637 V 29 32 35 deci mal

CICCMAX2 V

ICCMAX = 1 .264 2V 61 64 67 deci mal

D igi t al C ode of I CC M AX

CICCMAX3 V

ICCMAX = 2 .518 6V 125 128 1 31 deci ma l

CICCMAXA1 V

ICCMAXA = 0.1666V 5 8 11 decimal

CICCMAXA2 V

ICCMAXA = 0.3234V 13 16 19 decimal D igi t al C ode of I CC M AX A

CICCMAXA3 V

ICCMAXA = 0.637V 29 32 35 decim al

CTMPMAX1 V

TMPMAX = 1.6758V 82 85 88 deci mal

CTMPMAX2 V

TMPMAX = 1.9698V 97 100 103 decima l D igi t al C ode of TM PMAX

CTMPMAX3 V

TMPMAX = 2.4598V 122 125 1 28 deci ma l

RT8167A

DS8167A-00 January 2012 www.richtek.com

Typical Operating Characteristics

Boot VID = 1V

Time (100μs/Div)

CORE VR Power On from EN

(2V/Div)

VCORE

(500mV/Div)

VR_READY

(2V/Div)

UGATE

(20V/Div)

Time (100μs/Div)

CORE VR Power Off from EN

Boot VID = 1V

(2V/Div)

VCORE

(500mV/Div)

VR_READY

(2V/Div)

UGATE

(20V/Div)

VID = 1.1V

Time (100μs/Div)

CORE VR OCP

ILOAD

(10A/Div)

VCORE

(1V/Div)

VR_READY

(1V/Div)

UGATE

(20V/Div)

Time (40μs/Div)

CORE VR OVP and NVP

VID = 1.1V

LGATE

(10V/Div)

VCORE

(1V/Div)

VR_READY

(1V/Div)

UGATE

(20V/Div)

0.7V to 1.2V, Slew Rate = Slow, ILOAD = 4A

Time (40μs/Div)

CORE VR Dynamic VID Up

VDIO

(2V/Div)

VCLK

(2V/Div)

VCORE

(500mV/Div)

ALERT

(2V/Div)

Time (40μs/Div)

CORE V R D ynamic VID Down

1.2V to 0.7V, Slew Rate = Slow, ILOAD = 4A

ALERT

(2V/Div)

VCORE

(500mV/Div)

VDIO

(2V/Div)

VCLK

(2V/Div)

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22 DS8167A-00 January 2012www.richtek.com

Time (10μs/Div)

CORE VR Dynamic VID Up

0.7V to 1.2V, Slew Rate = Fast, ILOAD = 4A

VDIO

(2V/Div)

VCLK

(2V/Div)

VCORE

(500mV/Div)

ALERT

(2V/Div)

Time (10μs/Div)

CORE V R D ynamic VID Down

1.2V to 0.7V, Slew Rate = Fast, ILOAD = 4A

VCORE

(500mV/Div)

ALERT

(2V/Div)

VDIO

(2V/Div)

VCLK

(2V/Div)

VID = 1.1V, ILOAD = 1A to 8A, Slew Time = 150ns

Time (100μs/Div)

CORE VR Load Transient

VCORE

(20mV/Div)

ILOAD

(A/Div)

Time (100μs/Div)

CORE VR Load Transient

VID = 1.1V, ILOAD = 8A to 1A, Slew Time = 150ns

VCORE

(20mV/Div)

ILOAD

(A/Div)

VID = 1.1V, PS0 to PS2, ILOAD = 0.2A

Time (100μs/Div)

CORE VR Mode Transition

UGATE

(20V/Div)

VCLK

(1V/Div)

LGATE

(10V/Div)

VCORE

(20mV/Div)

Time (100μs/Div)

CORE VR Mode Transition

VID = 1.1V, PS2 to PS0, ILOAD = 0.2A

UGATE

(20V/Div)

VCORE

(20mV/Div)

VCLK

(1V/Div)

LGATE

(10V/Div)

RT8167A

DS8167A-00 January 2012 www.richtek.com

Time (100μs/Div)

GFX VR OCP

ILOAD

(5A/Div)

VGFX

(1V/Div)

VRA_READY

(1V/Div)

UGATEA

(20V/Div)

Time (40μs/Div)

GFX VR OVP and NVP

VID = 1.1V

LGATEA

(10V/Div)

VGFX

(1V/Div)

VRA_READY

(1V/Div)

UGATEA

(20V/Div)

Time (100μs/Div)

GFX VR Power On from EN

Boot VID = 1V

(2V/Div)

VGFX

(500mV/Div)

VRA_READY

(2V/Div)

UGATEA

(20V/Div)

Time (100μs/Div)

GFX VR Power Off from EN

Boot VID = 1V

UGATEA

(20V/Div)

(2V/Div)

VGFX

(500mV/Div)

VRA_READY

(2V/Div)

TSEN Sweep from 1.7V to 1.9V

Time (10ms/Div)

CORE VR Thermal Monitoring

VRHOT

(500mV/Div)

TSEN

(V/Div)

1.9

1.7

CORE VR VREF vs. Temperature

0.90

0.92

0.94

0.96

0.98

1.00

1.02

1.04

1.06

1.08

1.10

-50 -25 0 25 50 75 100 125

Tempera tur e (°C )

VREF (V)

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Time (40μs/Div)

GFX VR Dynamic VID

0.7V to 1.2V, Slew Rate = Slow, ILOAD = 1.25A

VDIO

(2V/Div)

VCLK

(2V/Div)

VGFX

(500mV/Div)

ALERT

(2V/Div)

Time (40μs/Div)

GFX VR Dynamic VID

ALERT

(2V/Div)

VGFX

(500mV/Div)

1.2V to 0.7V, Slew Rate = Slow, ILOAD = 1.25A

VDIO

(2V/Div)

VCLK

(2V/Div)

Time (10μs/Div)

GFX VR Dynamic VID

0.7V to 1.2V, Slew Rate = Fast, ILOAD = 1.25A

VDIO

(2V/Div)

VCLK

(2V/Div)

VGFX

(500mV/Div)

ALERT

(2V/Div)

Time (10μs/Div)

GFX VR Dynamic VID

ALERT

(2V/Div) 1.2V to 0.7V, Slew Rate = Fast, ILOAD = 1.25A

VDIO

(2V/Div)

VCLK

(2V/Div)

VGFX

(500mV/Div)

Time (100μs/Div)

GFX VR Load Transient

VID = 1.1V, ILOAD = 1A to 4A, Slew Time = 150ns

VGFX

(20mV/Div)

ILOAD

(A/Div)

Time (100μs/Div)

GFX VR Load Transient

VID = 1.1V, ILOAD = 4A to 1A, Slew Time = 150ns

VGFX

(20mV/Div)

ILOAD

(A/Div)

RT8167A

DS8167A-00 January 2012 www.richtek.com

Time (100μs/Div)

GFX VR Mode Transition

VID = 1.1V, PS2 to PS0, ILOAD = 0.1A

UGATEA

(20V/Div)

VGFX

(20mV/Div)

VCLK

(1V/Div)

LGATEA

(10V/Div)

Time (100μs/Div)

GFX VR Mode Transition

VID = 1.1V, PS0 to PS2, ILOAD = 0.1A

UGATEA

(20V/Div)

VCLK

(1V/Div)

LGATEA

(10V/Div)

VGFX

(20mV/Div)

Time (10ms/Div)

GFX VR Thermal Monitoring

TSENA Sweep from 1.7V to 1.9V

1.9

1.7

TSENA

(V/Div)

VRHOT

(500mV/Div)

GFX VR VREF vs. Temperature

0.90

0.92

0.94

0.96

0.98

1.00

1.02

1.04

1.06

1.08

1.10

-50-250 255075100125

Temperat ur e (°C )

VREF (V)

RT8167A

26 DS8167A-00 January 2012www.richtek.com

management states and VID on-the-fly function. The power

management states include DEM in PS2/PS3 and Forced-

CCM in PS1/PS0. The VID on-the-fly function has three

different slew rates : Fa st, Slow and Decay . The RT8167A

integrates a high accuracy ADC for platform setting

functions, such as no-load offset and over current level.

The controller supports both DCR and sense-resistor

current sensing. The RT8167A provides VR ready output

signals of both CORE VR and GFX VR. It also features

complete fault protection functions including over voltage,

under voltage, negative voltage, over current a nd under

voltage lockout. The RT8167A is available in a WQFN-

48L 6x6 small f oot print pack age.

De sign Tool

To help users reduce efforts a nd errors caused by manual

calculations, a user-friendly design tool is now available

on request. This design tool calculates all necessary

design parameters by entering user's requirements.

Please conta ct Richtek's representatives for details.

Serial VID (SVID) Interface

SVID is a three-wire serial synchronous interface defined

by Intel. The three wire bus includes VDIO, VCLK and

ALERT signals. The master (Intel's VR12/IMVP7 CPU)

initiates and terminates SVID transa ctions a nd drives the

V DIO, VCLK, a nd ALERT during a transaction. The slave

(RT8167A) receives the SVID transactions and acts

accordingly.

Application Information

The RT8167A is a VR12/IMVP7 compliant, dual single-

phase synchronous Buck PWM controller for the CPU

CORE V R a nd GFX VR. The gate drivers are embedded

to facilitate PCB design and reduce the total BOM cost. A

serial VID (SVID) interface is built-in in the RT8167A to

communicate with Intel V R12/IMVP7 compliant CPU.

The RT8167A adopts G-NA VPTM (Green Native A VP), which

is Richtek's proprietary topology derived from finite DC

gain compensator, making it an easy setting PWM

controller to meet AVP requirements. The load line can

be ea sily progra mmed by setting the DC gain of the error

a mplifier. The RT8167A has fa st transient response due to

the G-NAVPTM commanding variable switching frequency .

G-NAVPTM topology also represents a high efficiency

system with green power concept. With G-NAVPTM

topology , the RT8167A becomes a green power controller

with high efficiency under heavy load, light load, and very

light load conditions. The RT8167A supports mode

transition function between CCM and DEM. These different

operating states allow the overall power system to have

low power loss. By utilizing the G-NAVPTM topology, the

operating frequency of RT8167A varies with output voltage,

load and VIN to further enhance the efficiency even in CCM.

The built-in high accuracy DAC converts the SVID code

ranging from 0.25V to 1.52V with 5mV per step. The

differential remote output voltage sense and high a ccuracy

DAC allow the system to have high output voltage accuracy .

The RT8167A supports VR12/IMVP7 compatible power

RT8167A

DS8167A-00 January 2012 www.richtek.com

Standard Serial VID Command

Code Commands Ma ster Payload

Contents Slave Payload

Contents Description

00h not supported N/A N/A N/A

01h SetVID_Fast VID code N/A Se t new tar get VID code, VR ju mps to n ew VID

target with controlled default “fast” slew rate

12.5mV/μs.

02h SetVID_Slow VID code N/A Se t new tar get VID code, VR ju mps t o n ew VID

target with controlled default “slow” slew rate

3.125mV/μs.

03h SetVID_Decay VID code N/A

Se t new tar get VID code, VR ju mps t o n ew VID

target, but does not control the slew rate. The

output voltage decays at a rate proporti onal to

the load current

04h SetPS By te indic ating

power states N/A Set power state

05h SetRegADR

Pointer of registers

in data table N /A Set the pointer of the data register

06h SetReg DAT New data r egis ter

content N/A Write the contents to the data register

07h GetReg

Pointer of registers

in data table

Specified

Contents

Slave returns the contents of the specified

08h

1Fh not supported N/A N/A N/A

RT8167A

28 DS8167A-00 January 2012www.richtek.com

Data and Configuration Register

Index Register Name Description Access Default

00h Vend or I D Vendor ID, defa ult 1Eh. RO, V endor 1 Eh

01h Pr oduct ID Product ID . RO, V endor 65h

02h Pr oduct Revisi on Product Revision. RO, V endor 01h

05h Protocol ID SVID Protocol ID. RO, Vendor 01h

06h VR_Capability Bi t mapped regi s t er , iden ti fies the S VID VR capabilit ies

and whi ch of the opt ional telemetry r egister ar e

supported. RO, V endor 81h

10h Status_1 Data regi s ter contai ni ng the st at us of V R. R -M, W- PWM 00h

11 h S t at us -2 Da ta r egi ster contai ning the st at us of t ra ns missi on. R -M , W- PWM 00h

12h Temperature

Zone Data regi ster show i ng temper at ur e z one t hat have been

entered. R-M, W-P WM 00h

15h Output_Current Data r egi s ter show i ng direc t AD C conversion of aver aged

output current . R-M, W-P WM 00h

1C h Status_2_l ast read The r egi ster cont ai ns a copy of t he s t atus_2. R -M, W- P WM 00h

21h ICC_Max Da ta r egi ster contai ning the m axi mu m ICC of pl at form

supports.

Bi nary for m at i n A mp , IE 64h = 10 0A. RO, Platform --

22h Temp_Max

Da ta re gist er cont aining the temperature m ax t he platform

suppo rts.

Bi nary for m at i n °C , I E 64h = 100°C

Only fo r CORE VR

RO, Plat form - -

24h SR-Fast Data regist er containing the capabil ity of fast sl ew rate the

platform can sustains. Binary format in mV/μs, IE 0A h =

10mV/μs. RO 0Ah

25h SR-Slow D at a regist er cont aining the capabil ity of slow slew rate.

Binary format in mV/μs I E 02h = 2. 5m V/ μs. RO 02h

30h VOUT_Max The register i s pr ogr am med by the mas t er a nd s et s the

maximum VID. RW, Master BFh

31h VI D Sett ing Data r egi s ter contai ni ng c urr ently progra mmed VID . RW, Mas t er 00h

32h Power St at e R egi ster contai ning the curr ent programm ed power state. RW, Master 00h

33h Offset Se t of fset in VID st eps. RW, Master 00h

34h Mu lt i VR Conf ig Bit mapped dat a register which conf igures m ul tiple VRs

behavior on the same bus. RW, Master 00h

35h Pointer S cratch pad regist er for temporary storage of the

SetRegADR pointer register. RW, Master 30h

Notes :

RO = Read Only

RW = Read/Write

R-M = Read by Master

W-PWM = Write by PWM only

Vendor = hard coded by VR vendor

Platform = programmed by platform

Master = programmed by the master

PWM = programmed by the VR control IC

RT8167A

DS8167A-00 January 2012 www.richtek.com

ICCMAX, ICCMAXA and TMPMAX

The RT8167A provides ICCMAX, ICCMAXA and TMPMAX

pins for platform users to set the maximum level of output

current or VR temperature: ICCMAX for CORE VR

maximum current, ICCMAXA for GFX VR maximum

current, and TMPMAX for CORE VR maximum

temperature.

To set ICCMAX, ICCMAXA and TMPMAX, platform

designers should use resistive voltage dividers on these

three pins. The current of the divider should be several

milli-Amps to avoid noise effect. The three items share

the sa me algorithms : the ADC divides 5V into 255 levels.

Therefore, LSB = 5/255 = 19.6mV, which means 19.6mV

a pplied to ICCMAX pin equals to 1A setting. For exa mple,

if a platform designer wants to set TMPMAX to 120°C, the

voltage applied to TMPMAX should be 120 x 19.6mV =

2.352V. The ADC circuit inside these three pins will

decode the voltage a pplied and store the maximum current/

temperature setting into ICC_MAX and Temp_Max

registers. The ADC monitors a nd decodes the voltage at

these three pins only after EN = high. If EN = low, the

RT8167A will not take any action even when the VR output

current or temperature exceeds its maximum setting at

these ADC pins. The maximum level settings at these

ADC pins are different from over current protection or over

temperature protection. That means, these maximum level

setting pins are only for platform users to define their

system operating conditions and these messages will only

be utilized by the CPU.

Precise Reference Current Generation

The RT8167A includes extensive analog circuits inside

the controller. These analog circuits need very precise

reference voltage/current to drive these a nalog device s.

The RT8167A will auto-generate a 2.14V voltage source

at IBIAS pin, and a 53.6kΩ resistor is required to be

connected between IBIAS and analog ground. Through

this connection, the RT8167A generates a 40μA current

from IBIAS pin to analog ground a nd this 40μA current will

be mirrored inside the RT8167A for internal use. Other

types of connection or other values of resista nce a pplied

at the IBIAS pin may cause failure of the RT8167A's analog

circuits. Thus a 53.6kΩ resistor is the only recommended

component to be connected to the IBIAS pin. The

resistance accuracy of this resistor is recommended to

be at least 1%.

Figure 4. IBIAS Setting

IBIAS

53.6k

Current

Mirror

2.14V

Power Ready Detection and Power On Reset (POR)

During start-up, the RT8167A detects the voltage on the

voltage input pins : VCC and EN. When VCC > VUVLO,

the RT8167A will recognize the power state of system to

be ready (POR = high) and wait for enable command at

EN pin. After POR = high a nd EN > VENTH, the RT8167A

will enter start-up sequence for both CORE VR a nd GFX

VR. If the voltage on any voltage pin drops below POR

threshold (POR = low), the RT8167A will enter power down

sequence and all the functions will be disabled. SVID will

be invalid within 300μs after chip becomes enabled. All

the protection latches (OVP, OCP, UVP, OTP) will be

cleared only after POR = low. EN = low will not clear

these latches.

Figure 3. Power Ready Detection a nd Power On Reset

(POR)

UVLO

ENTH

POR

Chip EN

VCC

RT8167A

30 DS8167A-00 January 2012www.richtek.com

Figure 6. SETINI and SETINIA Pin Voltage Setting

Start Up Sequence

The RT8167A utilizes internal soft-start sequence which

strictly follows Intel VR12/IMVP7 start up sequence

specifications. After POR = high a nd EN = high, a 300μs

delay is needed for the controller to determine whether all

the power inputs are ready for entering start up sequence.

If pin voltage of SETINI/SETINIA is zero, the output voltage

of CORE/GFX VR is programmed to stay at 0V. If pin

voltage of SETINI/SETINIA is not zero, VR output voltage

will ra mp up to initial boot voltage (VINI_CORE, VINI_GFX) after

both POR = high a nd EN = high. After the output voltage

of CORE/GFX V R rea ches target initial boot voltage, the

controller will keep the output voltage at the initial boot

voltage and wait for the next SVID commands. After the

RT8167A receives valid VID code (typically SetVID_Slow

command), the output voltage will ramp up/down to the

target voltage with specified slew rate. After the output

voltage reaches the target voltage, the RT8167A will send

out VR_READY signal to indicate the power state of the

RT8167A is ready. The VR_READY circuit is an open-

drain structure so a pull-up resistor is recommended for

connecting to a voltage source.

Power Down Sequence

Similar to the start up sequence, the RT8167A also utilizes

a soft shutdown mecha nism during turn-off. After POR =

low, the internal reference voltage (positive terminal of

compensation EA) starts ra mping down with 3.125mV/μs

slew rate, and output voltage will follow the reference

voltage to 0V. After output voltage drops below 0.2V, the

RT8167A shuts down a nd all functions are disabled. The

VR_READY will be pulled down immediately after POR =

low.

VINI_CORE and VINI_GFX Setting

The initial start up voltage (VINI_CORE, VINI_GFX) of the

RT8167A can be set by platform users through SETINI

and SETINIA pins. V oltage divider circuit is recommended

to be a pplied to SETINI and SETINIA pins. The VINI_CORE/

VINI_GFX relate to SETINI/SETINIA pin voltage setting as

shown in Figure 6. Recommended voltage setting at SETINI

a nd SETINIA pins are also shown in Figure 6.

Figure 5. ADC Pin s Setting

A/D

Converter

ICCMAX

ICCMAXA

TMPMAX

VCC

VINI_CORE

VINI_GFX Recommended

SETINI/SETINIA Pin Voltage

1.1V 5

8x VCC≒3.125V or VCC

1V 3

8x VCC≒1.875V

0.9V 3

16 x VCC≒0.9375V

0V 1

16 x VCC≒0.3125V or GND

VCC (5V)

GND

1/8 VCC

1/4 VCC

1/2 VCC

VINI_CORE= 0.9V

VINI_GFX= 0.9V

VINI_CORE = 1.1V

VINI_GFX= 1.1V

VINI_CORE= 1V

VINI_GFX= 1V

VINI_CORE= 0V

VINI_GFX= 0V

RT8167A

DS8167A-00 January 2012 www.richtek.com

Figure 7 (a). Power sequence for RT8167A (VINI_CORE = VINI_GFX = 0V)

Figure 7 (b). Power sequence for RT8167A (VINI_CORE 0, VINI_GFX 0V)

≠ ≠

SVID Valid xx

VCORE

VR_READY 100µs

POR

0.2V

CORE VR

Operation Mode CCM CCM

0.2V

VGFX

SVID defined

CCM SVID defined

GFX VR

Operation Mode

100µs

VRA_READY

CCM

300µs

Off

VCC

EN Chip

(Internal Signal)

Off

VRA_READY

EN Chip

(Internal Signal)

SVID Valid xx

VCORE

VR_READY 100µs

POR

0.2V

CORE VR

Operation Mode CCM CCMOff

0.2V

VGFX

SVID defined

CCMOff SVID defined

GFX VR

Operation Mode CCM

250µs

Off

VCC

100µs

300µs

VINI_GFX

VINI_CORE

50µs

RT8167A

32 DS8167A-00 January 2012www.richtek.com

Figure 8. Simplified Schematic for Droop a nd Remote

Sense in CCM

Disable GFX VR : Before EN = High

GFX VR enable or disable is determined by the internal

circuitry that monitors the ISENAN voltage during start

up. Before EN = high, GFX VR detects whether the voltage

of ISENAN is higher than “VCC − 1V” to disable GFX

VR. The unused driver pins ca n be connected to GND or

left floating.

GFX VR Forced-DEM Function Enable : After

VRA_Ready = High

The GFX VR's forced-DEM function can be enabled or

disabled with GFXPS2 pin. The RT8167A detects the

voltage of GFXPS2 for forced-DEM function. If the voltage

at GFXPS2 pin is higher than 4.3V, the GFX VR operates

in forced-DEM. If this voltage is lower tha n 0.7V , the GFX

VR f ollows SVID power state command.

Loop Control

Both CORE a nd GFX V R a dopt Richtek's proprietary G-

NAVPTM topology. G-NAVPTM is based on the finite-gain

valley current mode with CCRCOT (Constant Current

Ripple Consta nt On T i me) topology. The output voltage,

VCORE or VGFX, will decrease with increasing output load

current. The control loop consists of PWM modulator with

power stage, current sense amplifier and error amplifier

as shown in Figure 8.

Similar to the valley current mode control with finite

compensator gain, the high side MOSFET on-time is

determined by the CCRCOT PWM generator . When load

current increa ses, VCS increa ses, the steady state COMP

voltage also increases which makes the output voltage

decrease, thus achieving AVP.

Droop Function Enable

The CORE/GFX VR's droop function can be enabled or

disabled with DRPEN/DRPENA pin. After EN = high within

10μs, the RT8167A will source 80μA current from DRPEN/

DRPENA pin to the external resistor to determine the

voltage level. If the voltage at DRPEN/DRPENA pin is lower

than 3.5V , then the VR will operate in droop-disabled mode.

If the voltage is higher than 4V, then the VR will operate in

droop-enabled mode.

Droop Setting (with Temperature Compensation)

It's very easy to achieve the Active Voltage Positioning

(AVP) by properly setting the error amplifier gain due to

the native droop chara cteristics. The target is to have

VOUT = VREFx − ILOAD x RDROOP (1)

Then solving the switching condition VCOMPx = VCSx in

Figure 8 yields the desired error a mplif ier gain a s

where AI is the internal current sense amplifier gain and

RSENSE is the current sense resistance. If no external sense

resistor is present, the DCR of the inductor will act as

RSENSE. RDROOP is the resistive slope value of the converter

output a nd is the desired static output i mpedance.

Figure 9. Error Amplifier Gain (AV) Influence on VOUT

Accuracy

AV1

AV2

AV2 > AV1

VOUT

Load Current

I SENSE

VDROOP

AR1 R (2)

VIN

ISENxP

ISENxN

FBx

RGNDx

High Side

MOSFET L

RXCX

R2 CORE/GFX VR

VCC_SENSE

COMPx

VCSx

C2 C1

VREFx

GFX/CORE VR

CCRCOT

PWM Generator

Driver

Logic

Control

CByp

UGATEx

PHASEx

LGATEx

CORE/GFX VR

VSS_SENSE

VOUT

(VCORE/VGFX)

CMP

Low Side

MOSFET

RT8167A

DS8167A-00 January 2012 www.richtek.com

Loop Compensation

Optimized compensation of the CORE VR allows for best

possible load step response of the regulator's output. A

type-I compensator with one pole and one zero is adequate

for a proper compensation. Figure 10 shows the

compensation circuit. It wa s previously mentioned that to

determine the resistive feedback components of error

amplifier gain, C1 and C2 must be calculated for the

compensation. The target is to achieve consta nt resistive

output impedance over the widest possible frequency

range.

The pole frequency of the compensator must be set to

compensate the output capacitor ESR zero :

where C is the ca pacitance of the output ca pacitor and RC

is the ESR of the output capa citor. C2 can be calculated

as follows :

The zero of compensator has to be placed at half of the

switching frequency to filter the switching-related noise.

Such that,

TON Setting

High frequency operation optimizes the application by

trading off efficiency due to higher switching losses with

smaller component size. This may be a cceptable in ultra-

portable devices where the load currents are lower and

the controller is powered from a lower voltage supply . Low

frequency operation offers the best overall efficiency at

SENSE, HOT NTC, HOT NTC, COLD

SENSE, COLD

SENSE, HOT

SENSE, COLD

R1b

R(R1a//R ) (R1a//R )

×−

⎛⎞

−

⎜⎟

⎝⎠

(8)

f2CR

=×π× × (9)

C2 R2

= (10)

(1 1)

()

NTC, 25 C SW

C1 R1b R1a // R f

=+×π×

Since the DCR of inductor is temperature dependent, it

affects the output a ccuracy in high temperature conditions.

Temperature compensation is recommended for the

lossless inductor DCR current sense method. Figure 10

shows a simple but effective way of compensating the

temperature variations of the sense resistor using an NTC

thermistor pla ced in the feedback path.

Figure 10. Loop Setting with Temperature Compensation

Usually, R1a is set to equal RNTC (25°C), while R1b is

selected to linearize the NTC's temperature characteristic.

For a given NTC, the design would be to obtain R1b a nd

R2 and then C1 and C2. According to (2), to compensate

the temperature variations of the sense resistor , the error

amplifier gain (AV) should have the same temperature

coefficient with RSENSE. Hence

From (2), we can have Av at a ny temperature (T) as

The standard formula for the resistance of NTC thermistor

as a function of temperature is given by :

where RNTC, 25 is the thermistor's nominal resistance at

room temperature, β (beta) is the thermistor's material

constant in Kelvins, and T is the thermistor's actual

temperature in Celsius.

The DCR value at different temperatures can be calculated

using the equation below :

DCRT = DCR25 x [1+0.00393 x (T-25)] (6)

where 0.00393 is the temperature coefficient of copper.

For a given NTC thermistor , solving (4) at room temperature

(25°C) yields

V, HOT SENSE, HOT

V, COLD SENSE, COLD

= (3)

V, T NTC, T

AR1a / /R R1b

=+ (4)

(

)

(

)

{

}

T+273 298

NTC, T NTC, 25

RR e

⎡⎤

β−

⎢⎥

⎣⎦

= (5)

VCC_SENSE

+VSS_SENSE

FBx

RGNDx

COMPx

C2 C1

R2 R1b

R1a

NTC

VREFx

R2 = AV, 25 x (R1b + R1a // RNTC, 25) (7)

where AV, 25°C is the error a mplifier gain at room temperature

obtained from (2). R1b can be obtained by substituting

(7) to (3),

RT8167A

34 DS8167A-00 January 2012www.richtek.com

Figure 11. On-Ti me Setting with RC Filter

(12)

××

<= −

-12 TONSETx

ONx REFx IN REFx

28 10 R

t (V 1.2V) VV

(13)

≥

×× ×

=−

ONx REFx -12 TONSETx REFx

IN REFx

t (V 1.2V)

23.33 10 R V

(14)

−

−−

=×

−

⎡⎤

+× +−

⎣⎦

⎡⎤

+× −

⎣⎦

S(MAX) ON HS Delay

REFx(MAX) LOAD(MAX) ON_LS FET DROOP

IN(MAX) LOAD(MAX) ON_LS FET ON_HS FET

f(kHz)

VI R DCRR

VI R R

the expense of component size a nd board space. Figure

11 shows the on-time setting circuit. Connect a resistor

(RTONSETx) between VIN and TONSETx to set the on-time

of UGATEx :

where tONx is the UGA TEx turn on period, VIN is the input

voltage of converter, and VREFx is the internal reference

voltage.

When VREFx is larger than 1.2V, the equivalent switching

frequency may be over the maximum design range, making

it una cceptable. Therefore, the VR implements a pseudo-

constant-frequency technology to avoid this disadvantage

of CCRCOT topology. When VREFx is larger than 1.2V,

the on-time equation will be modified to :

On-time tra nslates roughly to switching frequencies. The

on-times guara nteed in the Electrical Characteristics are

influenced by switching delays in external high side

MOSFET. Also, the dead-time effect increa ses the effective

on-time, reducing the switching frequency. It occurs only

in CCM during dynamic output voltage transitions when

the inductor current reverses at light or negative load

currents. With reversed inductor current, PHASEx goes

high earlier than normal, extending the on-time by a period

equal to the high side MOSFET rising dead time.

For better efficiency of the given load range, the maximum

switching frequency is suggested to be :

where fS(MAX) is the maximum switching frequency, tHS-

Delay is the turn on delay of high side MOSFET, VREFx(MAX)

is the maximum application DAC voltage of application,

VIN(MAX) is the maximum application input voltage,

ILOAD(MAX) is the maximum loa d of a pplication, RON_LS-FET

is the low side MOSFET RDS(ON), RON_HS-FET is the high

side MOSFET RDS(ON), DCRL is the inductor DCR, and

RDROOP is the load line setting.

GFX/CORE

VR CCRCOT

PWM

Generator

TONSETx RTONSETx R1

VIN

VREFx

On-Time

Differential Remote Sense Setting

The CORE/GFX VR includes differential, remote-sense

inputs to eliminate the effects of voltage drops along the

PC board tra c es, CPU intern al power routes and socket

contacts. The CPU contains on-die sense pins CORE/

GFX VCC_SENSE and VSS_SENSE. Connect RGNDx to CORE/

GFX VSS_SENSE. Connect FBx to CORE/GFX VCC_SENSE

with a resistor to build the negative input path of the error

a mplifier. The precision voltage reference VREFx is referred

to RGND f or accurate remote sen sing.

Current Sense Setting

The current sense topology of the CORE/GFX VR is

continuous inductor current sensing. Therefore, the

controller can be less noise sensitive. Low offset a mplifiers

are used for loop control a nd over current detection. The

internal current sense a mplifier gain (AI) is fixed to be 10.

The ISENxP and ISENxN denote the positive and negative

input of the current sense amplifier .

Users can either use a current sense resistor or the

inductor's DCR for current sensing. Using inductor's DCR

allows higher eff iciency a s shown in Figure 12. To let

then the transient performance will be optimum. For

example, choose L = 0.36μH with 1mΩ DCR and

CX = 100nF, to yields for RX :

LRC

DCR =× (15)

X0.36 H

R3.6k

1m 100nF

==Ω

Ω× (16)

LDCR

RXCX

VOUT

(VCORE/VGFX)

CByp

ISENxP

ISENxN

PHASEx

VCSx

Figure 12. Lossless Inductor Sensing

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Considering the inducta nce tolerance, the resistor RX ha s

to be tuned on board by exa mining the tra nsient voltage.

If the output voltage tra nsient has a n initial di p below the

minimum loa d line requirement with a slow recovery, RX

is too small. V ice versa, if the re sistance is too large the

output voltage transient will only have a small initial dip

a nd the recovery will be too fast, causing a ring-ba ck.

Using current-sense resistor in series with the inductor

can have better a ccuracy , but the efficiency is a trade-off.

Considering the equivalent inductance (LESL) of the current

sense resistor , a RC filter is recommended. The RC filter

calculation method is similar to the above-mentioned

inductor DCR sensing method.

No-Load Offset

The RT8167A provides a no-load offset function which ha s

four-level offsets of output voltage for the CORE/GFX VR.

The no-load offset function is implemented through the

OFSx pin. A voltage divider circuit is recommended to be

a pplied to OFSx pins. The output offset voltage relation to

the OFSx pin voltage setting is shown in Figure 13.

Recommended voltage setting at OFS and OFSA pins

are also shown in Figure 13.

VCC (5V)

GND

0.16 VCC

0.32 VCC

0.48 VCC

0.64 VCC

Offset Voltage =100mV

Offset Voltage = 50mV

Offset Voltage = -50mV

Offset Voltage = -100mV

Offset Voltage = 0mV

Offset

Voltage Recommended

OFS/OFSA Pin Voltage

10 0mV 0.8 x VCC≒4V or VCC

50mV 0.56 x VCC≒2.8V

−50mV 0.4 x VCC≒2V

−100mV 0.24 x VCC≒1.2V

0mV GND

Figure 13. OFS a nd OFSA Pins Voltage Setting

Operation Mode Transition

The RT8167A supports operation mode transition function

in CORE/GFX VR for the SetPS command of Intel's VR12/

IMVP7 CPU. The default operation mode of the RT8167A's

CORE/GFX VR is PS0, which is CCM operation. The other

operation mode is PS2 (DEM operation).

Figure 14. Thermal Monitoring Circuit

To meet Intel's VR12/IMVP7 specification, platform users

have to set the TSEN voltage to meet the temperature

variation of VR from 75% to 100% VR max temperature.

For example, if the VR max temperature is 100°C, platform

users have to set the TSEN voltage to be 1.4875V when

VR temperature reaches 75°C and 1.8725V when VR

temperature reaches 100°C. Detailed voltage setting

versus temperature variation is shown in Table 2.

Thermometer code is implemented in the Temperature

Zone register.

TSENx

VCC

RNTC

After receiving SetPS comma nd, the CORE/GFX VR will

immediately change to the new operation state. When

VR receives SetPS command of PS2 operation mode,

the V R operates as a DEM controller.

If VR receives dynamic VID cha nge comma nd (SetVID),

VR will automatically enter PS0 operation mode. After

output voltage reaches target voltage, VR will stay at PS0

state and ignore former SetPS command. Only by

re-sending SetPS command after SetVID command will

VR be forced into PS2 operation state again.

Thermal Monitoring and Temperature Reporting

CORE/GFX VR provides thermal monitoring function via

sensing TSEN pin voltage. Through the voltage divider

resistors R1, R2, R3 and RNTC, the voltage of TSEN will

be proportional to VR temperature. When VR temperature

rises, the TSENx voltage also rises. The ADC circuit of

VR monitors the voltage variation at TSENx pin from 1.47V

to 1.89V with 55mV resolution, and this voltage is decoded

into digital format and stored into the Temperature Zone

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36 DS8167A-00 January 2012www.richtek.com

Table 2. Temperature Zone Register

VRHOT SVID

Thermal

Alert

Comparator Tr ip Poin ts

Te mp er atu re s S caled to m aximu m =

100%

V oltage Represents A s ser t bi t

Mi nimum Level

b7 b6 b5 b4 b3 b2 b1 b0

100% 97% 94% 91% 88% 85% 82% 75%

1.855V 1.8V

1.745

V 1.69

V 1.635

V 1.58

V 1.52

5V 1.47

TSE N Pi n Vol t age Temperature_Zone

1.855 ≤ VTSEN 1111_1111

1.800 ≤ VTSEN ≤ 1.835 0111_11 11

1.745 ≤ VTSEN ≤ 1.780 0011_1 11 1

1.690 ≤ VTSEN ≤ 1.725 0001_111 1

1.635 ≤ VTSEN ≤ 1.670 0000_111 1

1.580 ≤ VTSEN ≤ 1.615 0000_011 1

1.525 ≤ VTSEN ≤ 1.560 0000_ 0011

1.470 ≤ VTSEN ≤ 1.505 0000_000 1

VTSEN < 1. 470 0000_000 0

Current Monitoring and Current Reporting

The CORE/GFX VR provides current monitoring function

via sensing the voltage difference of IMONFBx pin and

output voltage. Figure 15 shows the current monitoring

setting principle. The equivalent output current will be

sensed from IMONFBx pin and mirrored to IMONx pin.

The resistor connected to IMONx pin determines voltage

gain of the IMON output.

The RT8167A supports two temperature reporting,

VRHOT(hardware reporting) and ALERT(software

reporting), to fulfill VR12/IMVP7 specification. VRHOT is

an open-drain structure which sends out active-low VRHOT

signals. When TSEN voltage rises above 1.855V (100%

of VR temperature), the VRHOT sign al will be set to low .

When TSEN voltage drops below 1.8V (97% of VR

temperature), the VRHOT signal will be reset to high. When

TSEN voltage rises above 1.8V (97% of VR temperature),

The RT8167A will update the bit1 data from 0 to 1 in the

Status_1 register and a ssert ALERT. When TSEN voltage

drops below 1.745V (94% of VR temperature), VR will

update the bit1 data from 1 to 0 in the Status_1 register

and a ssert ALERT.

The temperature reporting function for the GFX VR can be

disabled by pulling TSENA pin to VCC in case the

temperature reporting function for the GFX VR is not used

or the GFX VR is disabled. When the GFX VR's

temperature reporting function is disabled, the RT8167A

will reject the SVID command of getting the

Temperature_Zone register content of the GFX VR.

However , note that the temperature reporting function for

the CORE V R is always active. CORE VR's temperature

reporting function can not be disabled by pulling TSEN

pin to VCC.

Figure 15. Current Monitor Setting Principle

RIMONFB

VCC_SENSE

IMONFBx

VIMON

RIMON

Current Monitor

IMONx

VREFx

VREFx + 2 (VISENxP - VISENxN)

0LL EN

IMIrror

The voltage of IMONFBx is different when VR operates in

droop enable mode and droop disable mode :

Droop enable mode : VIMONFBx = VREFx (17)

Droop disable mode :

VIMONFBx = VREFx + 2 (VISENxP − VISENxN) (18)

The current monitor indicator VIMON equation is shown a s:

IMONFBx CC_SENSE IMON

IMON IMONFB

(I V ) R

−×

= (19)

where VIMONFBx is the pin voltage of IMONFBx, VCC_SENSE

is the output voltage of CORE/GFX VR, and RIMON an d

RIMONFB are the current monitor current setting resistors.

The maximum voltage of current monitoring will be limited

at 3.3V. Platform designers have to design the RIMON to

meet the maximum voltage of IMON at full load.

When VR operates in droop enable mode, find RIMON and

RIMONFB based on :

IMON(MAX)

IMON

IMONFB (MAX) DROOP

RIR

=× (20)

where VIMON(MAX) is the maximum voltage at full load,

RDROOP is the load line setting of VR, and IMAX is the full

load current of VR.

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Figure 17. OCP Setting with Temperature Compensation

OCSETx

VCC

ROC1b

ROC2

ROC1a NTC

Usually, ROC1a is selected to be equal to the thermistor's

nominal resista nce at room temperature. Ideally, VOCSET

is assumed to have the sa me te mperature coeff icient as

RSENSE (Inductor DCR) :

According to the basic circuit calculation, VOCSET can be

obtained at a ny temperature :

OCSET, HOT SENSE, HOT

OCSET, COLD SENSE, COLD

= (24)

OC2

OCSET, T CC OC1a NTC, T OC1b OC2

R//R R R

=× ++

(25)

Re-write (24) from (25), to get VOCSET at room temperature

OC1a NTC, COLD OC1b OC2 SENSE, HOT

OC1a NTC, HOT OC1b OC2 SENSE, COLD

R//R R R R

++=

++ (26)

(27)

OCSET, 25

OC2

CC OC1a NTC, 25 OC1b OC2

V R//R R R

×++

(23)

OC1 OC2 OCSET

RR 1

⎛⎞

=× −

⎜⎟

⎝⎠

Figure 16. OCP Setting without Temperature

Compensation

VCC

OCSETx

ROC1

ROC2

The current limit is triggered when inductor current

exceeds the current limit threshold ILIMIT, defined by

VOCSET. The driver will be f orced to turn off UGATE until

the over current condition is cleared. If the over current

condition remains valid for 15 PWM cycles, VR will trigger

OCP latch. Latched OCP forces both UGA TE and LGA TE

to go low. When OCP is triggered in one of VRs, the

other VR will enter into soft shutdown sequence. The OCP

latch mechanism will be masked when VRx_READY =

low , which mea ns that only the current li mit will be a ctive

when VOUT is ramping up to initial voltage (or VREFx).

If inductor DCR is used as the current sense component,

then temperature compensation is recommended for

protection under all conditions. Figure 17 shows a typical

OCP setting with temperature compensation.

When VR operate in droop disable mode, RIMON and

RIMONFB ca n be obtained according to equation below :

IMON(MAX)

IMON

IMONFB (MAX) SENSE

RIR2

=×× (21)

where VIMON(MAX) is the maximum voltage at full load,

RSENSE is the equivalent resistance of current sense circuit,

a nd IMAX is the full load current of V R.

The ADC circuit of the CORE/GFX VR monitors the voltage

variation at the IMON pin from 0V to 3.3V, and this voltage

is decoded into digital format and stored into the

Output_Current register . The ADC divides 3.3V into 255

levels, so LSB = 3.3V/255 = 12.941mV. Platform

designers should design VIMONx to be 3.3V at ICCMAX.

For exa mple, when load current = 0.5 x ICCMAX, VIMON =

1.65V a nd Output_Current register = 7Fh.

The IMON pin is the output of internal operational a mplifier

and sends out IMON signal. When IMON voltage rises

above 3.3V (100% of VR output current), the VR will update

the bit2 data from 0 to 1 in the Status_1 register . The 1 in

bit2 of Status_1 register will be cleared to 0 only after the

master (usually Intel's VR12/IMVP7 CPU) executes

GetReg comma nd to Status_1 register .

Over Current Protection

The CORE/GFX VR compares a programmable current

limit set point to the voltage from the current sense a mplifier

output for Over Current Protection (OCP). The voltage

applied to OCSETx pin defines the desired peak current

limit threshold ILIMIT :

VOCSET = 48 x ILIMIT x RSENSE (22)

Connect a resistive voltage divider from VCC to GND, with

the joint of the resistive divider connected to OCSET pin

a s shown in Figure 16. For a given ROC2, then

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38 DS8167A-00 January 2012www.richtek.com

Solving (26) and (27) yields ROC1b and ROC2

(28)

OC2

EQU, HOT EQU, COLD EQU, 25

OCSET, 25

RRR (1)R

V(1 )

α× − + −α ×

×−α

(29)

OC1b

EQU, HOT EQU, COLD

R(1)R2 R R

(1 )

α− × +α× −

−α

where

SENSE, HOT 25 HOT

SENSE, COLD 25 COLD

RDCR [1 0.00393 (T 25)]

R DCR [1 0.00393 (T 25)]

α=

×+ × −

=×+ × −

(30)

REQU, T = ROC1a // RNTC, T (31)

Over Voltage Protection (OVP)

The over voltage protection circuit of CORE/GFX VR

monitors the output voltage via the ISENxN pin. The

supported maximum operating VID of VR (V(MAX)) is stored

in the VOUT(MAX) register . Once VISENxN exceeds “V(MAX) +

200mV”, OVP is triggered and latched. V R will try to turn

on low side MOSFETs and turn off high side MOSFETs to

protect CPU. When OVP is triggered by the one of the

VRs, the other V R will enter soft shutdown sequence. A

10μs delay is used in OVP detection circuit to prevent

false trigger .

Negative Voltage Protection (NVP)

During OVP latch state, both CORE/GFX VRs also monitor

ISENxN pin for negative voltage protection. Since the OVP

latch will continuously turn on low side MOSFET of VR,

VR may suffer negative output voltage. Therefore, when

the voltage of ISENxN drops below −0.05V after triggering

OVP, VR will turn of f low side MOSFETs while high side

MOSFETs remain off. The N VP function will be a ctive only

after OVP is triggered.

Under Voltage Protection (UVP)

Both CORE/GFX VR implement U nder V oltage Protection

(UVP). If ISENxN is less than VREFx by 300mV + VOFFSET,

VR will trigger UVP latch. The UVP latch will turn off both

high side and low side MOSFETs. When UVP is triggered

by one of the VRs, the other VR will enter into soft

shutdown sequence. The UVP mechanism is masked

when V Rx_READY = low.

(32)

IN OUT

MIN ON

Ripple(MAX)

I−

=×

where tON is the UGA TE turn on period.

Higher inducta nce induces less ripple current a nd hence

higher efficiency . However, the tradeoff is a slower transient

response of the power stage to load transients. This might

increa se the need for more output ca pacitors, thus driving

up the cost. Find a low-loss inductor having the lowest

possible DC resista nce that fits in the allotted dimensions.

The core must be large enough not to be saturated at the

pea k inductor current.

Output Capacitor Selection

Output capacitors are used to obtain high bandwidth f or

the output voltage beyond the bandwidth of the converter

itself. Usually, the CPU manufacturer recommends a

capacitor configuration. Two different kinds of output

capacitors can be found, bulk capacitors closely located

to the inductors and ceramic output capacitors in close

proximity to the load. Latter ones are for mid-frequency

decoupling with very small ESR and ESL values while the

bulk ca p acitors have to provide enough stored energy to

overcome the low-frequency bandwidth ga p between the

regulator and the CPU.

Layout Considerations

Careful PC board layout is critical to achieving low

switching losses and clean, stable operation. The

switching power stage requires particular attention. If

possible, mount all of the power components on the top

side of the board with their ground terminals flushed

against one another . Follow these guidelines for optimum

PC board layout :

Under Voltage Lock Out (UVLO)

During normal operation, if the voltage at the VCC pin

drops below UVLO falling edge threshold, both VR will

trigger UVLO. The UVLO protection forces all high side

MOSFETs a nd low side MOSFETs off to turn of f.

Inductor Selection

The switching frequency and ripple current determine the

inductor value a s f ollows :

RT8167A

DS8167A-00 January 2012 www.richtek.com

`Keep the high current paths short, especially at the

ground terminals.

`Keep the power traces a nd load connections short. This

is essenti al for high ef ficiency.

`When trade-offs in trace lengths must be made, it's

preferable to allow the inductor charging path to be made

longer than the discharging path.

`Place the current sense component close to the

controller. ISENxP and ISENxN connections for current

limit a nd voltage positioning must be made using Kelvin

sense connections to guarantee the current sense

a ccuracy . The PCB tra ce from the sense nodes should

be parallel to the controller .

`Route high-speed switching nodes away from sensitive

analog areas (COMPx, FBx, ISENxP, ISENxN, etc...)

`Special attention should be paid in placing the DCR

current sensing components. The DCR current sensing

capacitor and resistors must be placed close to the

controller.

`The capacitor connected to the ISEN1N/ISENAN for noise

decoupling is optional a nd it should also be placed close

to the ISEN1N/ISENAN pin.

`The NTC thermistor should be placed physically close

to the inductor for better DCR thermal compensation.

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40 DS8167A-00 January 2012www.richtek.com

Richtek Technology Corporation

5F, No. 20, Taiyuen Street, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should

obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot

assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be

accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

Outline Dimension

Dimension s In Millimeters Dimensions In Inches

Symbol Min Max Min Max

A 0.700 0.800 0.028 0.031

A1 0.000 0.050 0.000 0.002

A3 0.175 0.250 0.007 0.010

b 0.150 0.250 0.006 0.010

D 5.950 6.050 0.234 0.238

D2 4.250 4.350 0.167 0.171

E 5.950 6.050 0.234 0.238

E2 4.250 4.350 0.167 0.171

e 0.400 0.016

L 0.350 0.450

0.014 0.018

W-Type 48L QFN 6x6 Package

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

DETAIL A

Pin #1 ID a nd T ie Bar M ark Options