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April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
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DATA SHEET U17832EE1V0DS00 1
32-bit single-chip micro controller
INTRODUCTION
The V850ES/FG2 are 32-bit single-chip microcontrollers that include the V850ES CPU core and integrate peripheral
functions such as timers/counters, serial interfaces, and an A/D converter. These microcontrollers also incorporate a
CAN (Controller Area Network) as an automo t ive LAN.
In addition to highly real-time responsive, 1-clock-pitch basic instructions, these microcontrollers h ave i nstructions
ideal for digital servo applic ations, such as multiplication instructions using a hardware multiplier, sum-of-products
operation instructions, and bit manipulation instructions. These microcontrollers ca n also realize a real-time control
system that is highly cost effective and can be used in automotive instrumentatio n fields.
FEATURES
- Number of instructions: 83
- Minimum instruction execution time: 50 ns (main clock (fxx) = 20 MHz)
- General-purpose registers: 32 bits × 32
- Power-on clear function
- Low-voltage detection function
- Ring-OSC: 200 kHz (TYP.)
- Internal memory:
- RAM: 6/12/16 KB
- Flash memory: 256/384KB
- Mask ROM: 128/256KB
- Interrupts/exceptions :
- Non-maskable interrupts : 1 source
- Maskable interrupts : 61 sources
- Software exceptions: 2 sources
- Exception trap: 1 source
- I/O lines I/O ports: 84
- Timer/counters:
- 16-bit interval timer M (TMM): 1 ch
- 16-bit timer/event counter P (TMP): 4 ch
- 16-bit timer/event counter Q (TMQ): 2 ch
- Watch timer: 1 ch
- Watchdog timer 2: 1 ch
- Serial interface (SIO):
- Asynchronous serial interface A (UART): 3 ch
- 3-wire variable-length serial interface B (CSIB): 2 ch
- CAN controller: 2 ch
- A/D converter 10-bit resolution: 16 ch
- Clock generator Main clock/subclock operation:
- CPU clock in seven steps (fxx, fxx/2, fxx/4, fxx/8, fxx/16, fxx/32, fxt)
- Clock-through mode/PLL mode selectable
- Internal oscillator: 200 kHz（TYP.）
- Power save function: HALT/IDLE1/IDLE2/software STOP/subclock/sub-IDLE modes
- Package: 100-pin plastic LQFP (fine pitch) (14 × 14)
Part Number Internal ROM Internal RAM CAN I/F
uPD703234 128KB (Mask ROM) 6KB 2 channel
uPD703235 256KB (Mask ROM) 12KB 2 channel
UPD70F3234 128KB (Flash) 6KB 2 channel
uPD70F3235 256KB (Flash) 12KB 2 channel
uPD70F3236 384KB (Flash) 16KB 2 channel
MOS Integrated Circuit
V850ES/FG2
DATA SHEET
V850ES/FG2
DATA SHEET U17832EE1V0DS00
2
Table of Contents
1. Electrical Specifications........................................................................................................................................... 4
1.1 Electrical Specifications of (A)-Grade ................................................................................................................ 4
1.1.1 Absolute maximum ratings.......................................................................................................................... 4
1.1.2 Capacitance ................................................................................................................................................ 8
1.1.3 Operating conditions ................................................................................................................................... 8
1.1.4 Oscillator Characteristics ............................................................................................................................ 9
1.1.5 PLL Characteristics ................................................................................................................................... 11
1.1.6 Ring-OSC Characteristics ......................................................................................................................... 11
1.1.7 Voltage Regulator Characteristics ............................................................................................................. 11
1.1.8 DC Characteristics .................................................................................................................................... 12
1.1.9 Data Retention Characteristics ................................................................................................................. 16
1.1.10 AC Characteristics .................................................................................................................................. 17
1.2 Electrical Specifications of (A1)-Grade ............................................................................................................ 28
1.2.1 Absolute maximum ratings........................................................................................................................ 28
1.2.2 Capacitance .............................................................................................................................................. 32
1.2.3 Operating conditions ................................................................................................................................. 32
1.2.4 Oscillator Characteristics .......................................................................................................................... 33
1.2.5 PLL Characteristics ................................................................................................................................... 35
1.2.6 Ring-OSC Characteristics ......................................................................................................................... 35
1.2.7 Voltage Regulator Characteristics ............................................................................................................. 35
1.2.8 DC Characteristics .................................................................................................................................... 36
1.2.9 Data Retention Characteristics ................................................................................................................. 40
1.2.10 AC Characteristics .................................................................................................................................. 41
1.3 Electrical Specifications of (A2)-Grade ............................................................................................................ 52
1.3.1 Absolute maximum ratings........................................................................................................................ 52
1.3.2 Capacitance .............................................................................................................................................. 56
1.3.3 Operating conditions ................................................................................................................................. 56
1.3.4 Oscillator Characteristics .......................................................................................................................... 57
1.3.5 PLL Characteristics ................................................................................................................................... 59
1.3.6 Ring-OSC Characteristics ......................................................................................................................... 59
1.3.7 Voltage Regulator Characteristics ............................................................................................................. 59
1.3.8 DC Characteristics .................................................................................................................................... 60
1.3.9 Data Retention Characteristics ................................................................................................................. 64
1.3.10 AC Characteristics .................................................................................................................................. 65
2. Injected Current Specification................................................................................................................................ 76
2.1 Injected Current Specification of (A)-Grade ..................................................................................................... 76
2.1.1 Absolute Maximum Ratings ...................................................................................................................... 76
2.1.2 DC Characteristics for overload current .................................................................................................... 76
2.1.3 DC Characteristics for pins influenced by injected current on an adjacent pin .......................................... 77
2.1.4 A/D converter influenced by injected current on an adjacent pin............................................................... 78
2.2 Injected Current Specification of (A1)-Grade ................................................................................................... 79
2.2.1 Absolute Maximum Ratings ...................................................................................................................... 79
2.2.2 DC Characteristics for overload current .................................................................................................... 79
2.2.3 DC Characteristics for pins influenced by injected current on an adjacent pin .......................................... 80
2.2.4 A/D converter influenced by injected current on an adjacent pin............................................................... 81
2.3 Injected Current Specification of (A2)-Grade ................................................................................................... 82
V850ES/FG2
DATA SHEET U17832EE1V0DS00 3
2.3.1 Absolute Maximum Ratings .......................................................................................................................82
2.3.2 DC Characteristics for overload current .....................................................................................................82
2.3.3 DC Characteristics for pins influenced by injected current on an adjacent pin...........................................83
2.3.4 A/D converter influenced by injected current on an adjacent pin ...............................................................84
3. Package Drawings .................................................................................................................................................85
Figure 3-1: Package Drawing .................................................................................................................................85
4. Recommended Soldering Conditions.....................................................................................................................86
Table 4-1: Soldering Conditions..............................................................................................................................86
V850ES/FG2
DATA SHEET U17832EE1V0DS00
4
1. Electrical Specifications
1.1 Electrical Specifications of (A)-Grade
1.1.1 Absolute maximum ratings
Absolute maximum ratings (TA = 25°C): Flash memory products (1/2)
Parameter Symbol Conditions Ratings Unit
VDD VDD = EVDD = BVDD −0.5 to +6.5 V
BVDD VDD = EVDD = BVDD −0.5 to +6.5 V
EVDD VDD = EVDD = BVDD −0.5 to +6.5 V
AVREF0 −0.5 to +6.5 V
VSS VSS = EVSS = BVSS = AVSS −0.5 to +0.5 V
AVSS VSS = EVSS = BVSS = AVSS −0.5 to +0.5 V
BVSS VSS = EVSS = BVSS = AVSS −0.5 to +0.5 V
Supply voltage
EVSS VSS = EVSS = BVSS = AVSS −0.5 to +0.5 V
VI1 P00 to P06, P10, P11, P30 to P39, P40 to P42, P50 to P55,
P90 to P915, RESET, FLMD0
−0.5 to EVDD + 0.5Note V
VI2 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6,
PDL0 to PDL13
−0.5 to BVDD + 0.5Note V
Input voltage
VI3 X1, X2, XT1, XT2 −0.5 to VRO + 0.5Note V
Analog input voltage VIAN P70 to P715 −0.5 to AVREF0 + 0.5 Note V
Note Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage.
Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and betw een VDD or VCC
and GND.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily
for any parameter. That is, the absolute maximum ratings are rated values at which the
product is on the verge of suffering physical damage, and therefore the product must be
used under conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions indicated for DC characteristics and AC characteristics
represent the quality assura n ce range during normal operation .
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
V850ES/FG2
DATA SHEET U17832EE1V0DS00 5
Absolute maximum ratings (TA = 25°C): Flash memory products (2/2)
Parameter Symbol Conditions Ratings Unit
Per pin 4 mA
P00 to P06, P10, P11, P30 to P39,
P40 to P42, P50 to P55, P90 to P915 Total of all pins 50 mA
Per pin 4 mA P70 to P715
Total of all pins 20 mA
Per pin 4 mA
Output current, low IOL
PCM0 to PCM3, PCS0, PCS1, PCT0,
PCT1, PCT4, PCT6, PDL0 to PDL13 Total of all pins 50 mA
Per pin −4 mA
P00 to P06, P10, P11, P30 to P39,
P40 to P42, P50 to P55, P90 to P915 Total of all pins −50 mA
Per pin −4 mA P70 to P715
Total of all pins −20 mA
Per pin −4 mA
Output current, high IOH
PCM0 to PCM3, PCS0, PCS1, PCT0,
PCT1, PCT4, PCT6, PDL0 to PDL13 Total of all pins −50 mA
Normal operating mode −40 to +85 °C
Operating ambient
temperature
TA
Flash programming mode −40 to +85 °C
Storage temperature Tstg −40 to +125 °C
Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and betw een VDD or VCC
and GND.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily
for any parameter. That is, the absolute maximum ratings are rated values at which the
product is on the verge of suffering physical damage, and therefore the product must be
used under conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions indicated for DC characteristics and AC characteristics
represent the quality assura n ce range during normal operation .
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
V850ES/FG2
DATA SHEET U17832EE1V0DS00
6
Absolute maximum ratings (TA = 25°C): Mask ROM products (1/2)
Parameter Symbol Conditions Ratings Unit
VDD VDD = EVDD = BVDD −0.5 to +6.5 V
BVDD VDD = EVDD = BVDD −0.5 to +6.5 V
EVDD VDD = EVDD = BVDD −0.5 to +6.5 V
AVREF0 −0.5 to +6.5 V
VSS VSS = EVSS = BVSS = AVSS −0.5 to +0.5 V
AVSS VSS = EVSS = BVSS = AVSS −0.5 to +0.5 V
BVSS VSS = EVSS = BVSS = AVSS −0.5 to +0.5 V
Supply voltage
EVSS VSS = EVSS = BVSS = AVSS −0.5 to +0.5 V
VI1 P00 to P06, P10, P11, P30 to P39, P40 to P42, P50 to P55,
P90 to P915, RESET, IC
−0.5 to EVDD + 0.5Note V
VI2 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6,
PDL0 to PDL13
−0.5 to BVDD + 0.5Note V
Input voltage
VI3 X1, X2, XT1, XT2 −0.5 to VRO + 0.5Note V
Analog input voltage VIAN P70 to P715 −0.5 to AVREF0 + 0.5 Note V
Note Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage.
Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and betw een VDD or VCC
and GND.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily
for any parameter. That is, the absolute maximum ratings are rated values at which the
product is on the verge of suffering physical damage, and therefore the product must be
used under conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions indicated for DC characteristics and AC characteristics
represent the quality assura n ce range during normal operation .
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
V850ES/FG2
DATA SHEET U17832EE1V0DS00 7
Absolute maximum ratings (TA = 25°C): Mask ROM products (2/2)
Parameter Symbol Conditions Ratings Unit
Per pin 4 mA
P00 to P06, P10, P11, P30 to P39,
P40 to P42, P50 to P55, P90 to P915 Total of all pins 50 mA
Per pin 4 mA P70 to P715
Total of all pins 20 mA
Per pin 4 mA
Output current, low IOL
PCM0 to PCM3, PCS0, PCS1, PCT0,
PCT1, PCT4, PCT6, PDL0 to PDL13 Total of all pins 50 mA
Per pin −4 mA
P00 to P06, P10, P11, P30 to P39,
P40 to P42, P50 to P55, P90 to P915 Total of all pins −50 mA
Per pin −4 mA P70 to P715
Total of all pins −20 mA
Per pin −4 mA
Output current, high IOH
PCM0 to PCM3, PCS0, PCS1, PCT0,
PCT1, PCT4, PCT6, PDL0 to PDL13 Total of all pins −50 mA
Operating ambient
temperature
TA Normal operating mode −40 to +85 °C
Storage temperature Tstg −65 to +150 °C
Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and betw een VDD or VCC
and GND.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily
for any parameter. That is, the absolute maximum ratings are rated values at which the
product is on the verge of suffering physical damage, and therefore the product must be
used under conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions indicated for DC characteristics and AC characteristics
represent the quality assura n ce range during normal operation .
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
V850ES/FG2
DATA SHEET U17832EE1V0DS00
8
1.1.2 Capacitance
(TA = 25°C, VDD = EVDD = AVREF0 = BVDD = AVREF1 = VSS = EVSS = BVSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
I/O capacitance CIO fX = 1 MHz,
Unmeasured pins returned to 0 V.
10 pF
1.1.3 Operating conditions
(TA = −40 to +85°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
REGC Capacity = 4.7
μ
F, at operation with
main clock
4 20 MHz
REGC Capacity = 4.7
μ
F, at operation with
subclock (crystal resonator)
32 35 kHz
Internal system clock
frequency
fCLK
REGC Capacity = 4.7
μ
F, at operation with
subclock (RC resonator)
12.5 Note 27.5 Note kHz
Note The internal system clock frequency is half the oscillation frequency.
V850ES/FG2
DATA SHEET U17832EE1V0DS00 9
1.1.4 Oscillator Characteristics
Main clock oscillator characteristics
(TA = −40 to +85°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V)
Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit
Oscillation frequency
(fX)Note 1
4 5 MHz
After reset release 216/fX s
After STOP mode
release
0.5Note 3 Note 4 ms
Ceramic
resonator
Oscillation
stabilization timeNote 2
After IDLE2 mode
release
0.35 Note 4 ms
Oscillation frequency
(fX)Note 1
4 5 MHz
After reset release 216/fX s
After STOP mode
release
0.5Note 3 Note 4 ms
Crystal
resonator
X2X1
Oscillation
stabilization timeNote 2
After IDLE2 mode
release
350 Note 4
μ
s
Notes 1. Indicates only oscillator characteristics.
2. Time required to stabilize the crystal resonator after reset or STOP mode is released.
3. Time required to stabilize access to the internal flash memory.
4. The value differs depending on the OSTS register settings.
Cautions 1. When using the main clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to a void an adverse effect from wiring cap acitance.
• Keep the wiring length as short as possib le.
• Do not cross the wiring with the other sign al lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main clock is stopped and the device is operating on the subclock, wait until the
oscillation stabilization time has been secured by the program before switching back to the
main clock.
V850ES/FG2
DATA SHEET U17832EE1V0DS00
10
Subclock oscillator characteristics
(TA = −40 to +85°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V)
Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit
Oscillation frequency
(fXT)Note 1
32 32.768 35 kHz
Crystal
resonator
Note 5
XT2
XT1
C2'
C1'
Q
U
R'1
Oscillation
stabilization timeNote 2
10 s
Oscillation frequency
(fXT)Notes1, 4
R = 390 kΩ ±5%Note 3
C = 47 pF ±10%Note 3
25 40 55 kHz
RC
resonator
XT2XT1
Oscillation
stabilization timeNote 2
100
μ
s
Notes 1. Indicates only oscillator characteristics. Refer to 27. 1. 10 AC Characteristics for CPU operating clock.
2. Time required from when VDD reaches oscillation voltage range (MIN.: 3.5 V) to when the crystal
resonator stabilizes.
3. In order to avoid the influence of wiring capacity, shorten wiring as much as possible.
4. RC oscillation frequency is 40 kHz (Typ.). This clock is divided (1/2) internally. In case of RC oscillator,
internal system clock frequency (fXT) is 12.5 kHz (Min.), 20 kHz (Typ.), and 27.5 kHz (Max.).
5. The values of capacitors C1’, C2’ and resistors R’1 depend on the resonator used and must be
specified in cooperation with the manufacturer.
Cautions 1. When using the subclock oscillator, wire as follows in the area enclosed by the broken lines in
the above figures to avoid an adverse effect from wi ring capacitance.
• Keep the wiring length as short as possib le.
• Do not cross the wiring with the other sign al lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. The subclock oscillator is designed as a low-amplitude circuit for reducing current
consumption, and is more prone to malfunction due to noise than the main clock oscillator.
Particular care is therefore required with the wiring method when the subclock is used.
V850ES/FG2
DATA SHEET U17832EE1V0DS00 11
1.1.5 PLL Characteristics
(TA = −40 to +85°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input frequency fx 4 5 MHz
Output frequency fxx 16 20 MHz
Clock time tPLL After VDD reaches MIN.: 3.5 V 800
μ
s
1.1.6 Ring-OSC Characteristics
(TA = −40 to +85°C, VDD = EVDD = BVDD, VSS = EVSS = BVSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Output frequency fr 100 200 400 kHz
1.1.7 Voltage Regulator Characteris tics
(TA = −40 to +85°C, VDD = EVDD = BVDD, VSS = EVSS = BVSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input voltage VDD 3.5 5.5 V
Output voltage VRO 2.5 V
Lock timeNote 1 tREG After VDD reaches MIN.: 3.5 V
Connect C = 4.7
μ
F ± 20% to REGC pin
1 ms
Note 1. The lock time does not have to be considered for devices that have POC.
VDD 3.5 V
VRO
RESET
tREG
V850ES/FG2
DATA SHEET U17832EE1V0DS00
12
1.1.8 DC Characteristics
(1) Input/Output level
(TA = −40 to +85°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VIH1 P30, P34, P38, P41, P98, P911 0.7EVDD EVDD V
VIH2 P00 to P06, P10, P11, P31 to P33, P35, P39,
P40, P42, P50 to P55, P90 to P97, P99, P910,
P912 to P915
0.8EVDD EVDD V
VIH3 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1,
PCT4, PCT6, PDL0 to PDL13
0.7BVDD BVDD V
VIH4 P70 to P715 0.7AVREF0 AVREF0 V
Input voltage, high
VIH5 RESET, FLMD0 0.8EVDD EVDD V
VIL1 P30, P34, P38, P41, P98, P911 EVSS 0.3EVDD V
VIL2 P00 to P06, P10, P11, P31 to P33, P35, P39,
P40, P42, P50 to P55, P90 to P97, P99, P910,
P912 to P915
EVSS 0.2EVDD V
VIL3 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1,
PCT4, PCT6, PDL0 to PDL13
BVSS 0.3BVDD V
VIL4 P70 to P715 AVSS 0.3AVREF0 V
Input voltage, low
VIL5 RESET, FLMD0 EVSS 0.2EVDD V
IOH = −1.0 mA EVDD − 1.0 EVDD V VOH1 P00 to P06, P10, P11,
P30 to P39, P40 to P42,
P50 to P55, P90 to P915
IOH = −0.1 mA EVDD − 0.5 EVDD V
IOH = −1.0 mA BVDD − 1.0 BVDD V VOH2 PCM0 to PCM3, PCS0,
PCS1, PCT0, PCT1, PCT4,
PCT6, PDL0 to PDL13
IOH = −0.1 mA BVDD − 0.5 BVDD V
IOH = −1.0 mA AVREF0 − 1.0 AVREF0 V
Output voltage,
highNote 1
VOH3 P70 to P715
IOH = −0.1 mA AVREF0 − 0.5 AVREF0 V
VOL1 P00 to P06, P10, P11,
P30 to P39, P40 to P42,
P50 to P55, P90 to P915
IOL = 1.0 mA 0 0.4 V
VOL2 PCM0 to PCM3, PCS0,
PCS1, PCT0, PCT1, PCT4,
PCT6, PDL0 to PDL13
IOL = 1.0 mA 0 0.4 V
Output voltage,
lowNote 1
VOL3 P70 to P715 IOL = 1.0 mA 0 0.4 V
Pull-up resistor R1 VI = 0 V 10 30 100 kΩ
Pull-down
resistorNote 2
R2 VI = VDD 10 30 100 kΩ
Notes 1. Total IOH/IOL (Max.) is 20 mA/-20 mA each power supply terminal (EVDD, BVDD and AVREF0).
2. DRST pin only (OCDM0 is the control register).
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
V850ES/FG2
DATA SHEET U17832EE1V0DS00 13
(2) Pin leakage current
(TA = −40 to +85°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Analog pins +0.2 Input leakage current, high ILIH1 VIN = VDD
Other pinsNote 1 +0.5
μ
A
Analog pins −0.2 Input leakage current, low ILIL1 VIN = 0 V
Other pinsNote 1 −0.5
μ
A
Analog pins +0.2 Output leakage current, high ILOH1 VO = VDD
Other pins +0.5
μ
A
Analog pins −0.2 Output leakage current, low ILOL1 VO = 0 V
Other pins −0.5
μ
A
Note 1. For flash memory product, specification of FLMD0 is as follows:
Input leakage current, high: 2
μ
A
Input leakage current, low: −2
μ
A
V850ES/FG2
DATA SHEET U17832EE1V0DS00
14
(3) Supply current
Supply current (V850ES/FG2:
μ
PD70F3236,
μ
PD70F3235,
μ
PD70F3234)
(TA = −40 to +85°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
fXX = 20 MHz
(OSC = 5 MHz),
all peripheral
functions operating
30 45 mA
IDD1 Normal operation
fXX = 20 MHz
(OSC = 5 MHz),
all peripheral
functions stopped
22 mA
fXX = 20 MHz
(OSC = 5 MHz),
all peripheral
functions operating
18 28 mA
IDD2 HALT mode
fXX = 20 MHz
(OSC = 5 MHz),
all peripheral
functions stopped
11 mA
IDD3 IDLE1 mode fXX = 5 MHz
(OSC = 5 MHz),
PLL off
0.6 0.9 mA
IDD4 IDLE2 mode fXX = 5 MHz
(OSC = 5 MHz),
PLL off
0.25 0.7 mA
Subclock operation
modeNotes 2, 3
Crystal resonator
fXT = 32.768 kHz
200 400
μ
A IDD5
Subclock operation
modeNotes 2, 3
RC resonator
fXT = 40 kHz Note 4
200 400
μ
A
Sub-IDLE
modeNotes 2, 3
Crystal resonator
fXT = 32.768 kHz
20 120
μ
A IDD6
Sub-IDLE
modeNotes 2, 3
RC resonator
fXT = 40 kHzNote 4
35 140
μ
A
Stop modeNotes 2, 5 POC stopped,
Ring-OSC stopped
7 50
μ
A
POC operating,
Ring-OSC stopped
10 55
μ
A
POC stopped,
Ring-OSC operating
15 65
μ
A
Flash memory products
supply currentNote 1
IDD7
POC operating,
Ring-OSC operating
18 70
μ
A
Notes 1. Total current of VDD, EVDD, and BVDD (all ports stopped).
The current of AVREF0 and the port buffer current including the current flowing through the on-chip
pull-up/pull-down resistors are not included.
2. When the main OSC is stopped.
3. POC operating, Ring-OSC operating.
4. The RC oscillation frequency is 40 kHz(TYP.). This clock is internally divided by 2.
5. When the sub-OSC is not used.
V850ES/FG2
DATA SHEET U17832EE1V0DS00 15
Supply current (V850ES/FG2:
μ
PD703235,
μ
PD703234)
(TA = −40 to +85°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
fXX = 20 MHz
(OSC = 5 MHz),
all peripheral
functions operating
25 40 mA
IDD1 Normal operation
fXX = 20 MHz
(OSC = 5 MHz),
all peripheral
functions stopped
20 mA
fXX = 20 MHz
(OSC = 5 MHz),
all peripheral
functions operating
14 24 mA
IDD2 HALT mode
fXX = 20 MHz
(OSC = 5 MHz),
all peripheral
functions stopped
9 mA
IDD3 IDLE1 mode fXX = 5 MHz
(OSC = 5 MHz),
PLL off
0.25 0.7 mA
IDD4 IDLE2 mode fXX = 5 MHz
(OSC = 5 MHz),
PLL off
0.2 0.7 mA
IDD5 Subclock operation
modeNotes 2, 3
Crystal resonator
fXT = 32.768 kHz
50 350
μ
A
Sub-IDLE
modeNotes 2, 3
Crystal resonator
fXT = 32.768 kHz
20 120
μ
A IDD6
Sub-IDLE
modeNotes 2, 3
RC resonator
fXT = 40 kHzNote 4
35 140
μ
A
Stop modeNotes 2, 5 POC stopped,
Ring-OSC stopped
7 50
μ
A
POC operating,
Ring-OSC stopped
10 55
μ
A
POC stopped,
Ring-OSC
operating
15 65
μ
A
Mask ROM products supply
currentNote 1
IDD7
POC operating,
Ring-OSC
operating
18 70
μ
A
Notes 1. Total current of VDD, EVDD, and BVDD (all ports stopped).
The current of AVREF0 and the port buffer current including the current flowing through the on-chip
pull-up/pull-down resistors are not included.
2. When the main OSC is stopped.
3. POC operating, Ring-OSC operating.
4. The RC oscillation frequency is 40 kHz(TYP.). This clock is internally divided by 2.
5. When the sub-OSC is not used.
V850ES/FG2
DATA SHEET U17832EE1V0DS00
16
1.1.9 Data Retention Characteristics
STOP Mode (TA = −40 to +85°C, VDD = EVDD = BVDD = 1.9 V to 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention voltage VDDDR In STOP mode 1.9 5.5 V
Data retention current IDDDR VDDDR = 2.0 V 6 450
μ
A
Supply voltage rise time tRVD 1
μ
s
Supply voltage fall time tFVD 1
μ
s
Supply voltage retention time tHVD After STOP mode release 0 ms
STOP release signal input time tDREL After VDD reaches MIN.: 3.5 V 0
μ
s
Data retention input voltage, high VIHDR All input ports 0.9VDDDR VDDDR V
Data retention input voltage, low VILDR All input ports 0 0.1VDDDR V
Caution Shifting to STOP mode and restoring from STOP mode must be performed within the rated
operating range.
tDRELtHVD
tFVD tRVD
STOP release signal inputSTOP mode setting
VDDDR
VIHDR
VIHDR
VILDR
VDD/EVDD/BVDD
RESET (input)
STOP mode release interrupt (NMI, etc.)
(Released by falling edge)
STOP mode release interrupt (NMI, etc.)
(Released by rising edge)
Operating voltage lower limit (Min.)
V850ES/FG2
DATA SHEET U17832EE1V0DS00 17
1.1.10 AC Characteristics
AC Test Input Measurement Points (VDD, AVDD, EVDD, BVDD)
V
DD
V
SS
V
IH (MIN.)
V
IL (MAX.)
V
IH (MIN.)
V
IL (MAX.)
Measurement points
AC Test Output Measurement Poin ts
VOH (MIN.)
VOL (MAX.)
VOH (MIN.)
VOL (MAX.)
Measurement points
Load Conditions
DUT
(Device under
measurement) C
L
= 50 pF
Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load
capacitance of the device to 50 pF or less by inserting a buffer or by some ot her means.
V850ES/FG2
DATA SHEET U17832EE1V0DS00
18
(1) CLKOUT output timing
(TA = −40 to +85°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
Output cycle tCYK 50 ns 80
μ
s
High-level width tWKH tCYK/2 − 15 ns
Low-level width tWKL tCYK/2 − 15 ns
Rise time tKR 15 ns
Fall time tKF 15 ns
Clock Timing
CLKOUT (output)
tCYK
tWKH tWKL
tKR tKF
V850ES/FG2
DATA SHEET U17832EE1V0DS00 19
(2) Basic Operation
(a) Reset, Interrupt timing
(TA = −40 to +85°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
RESET low-level width tWRSL 500 ns
NMI high-level width tWNIH Analog noise elimination 500 ns
NMI low-level width tWNIL Analog noise elimination 500 ns
Analog noise elimination (n = 0 to 7) 500 ns
INTPnNote 1 high-level
width
tWITH
Digital noise elimination (n = 3) Note 2 ns
Analog noise elimination (n = 0 to 7) 500 ns
INTPnNote 1 low-level
width
tWITL
Digital noise elimination (n = 3) Note 2 ns
Notes 1. ADTRG is same spec (P03/INTP0/ADTRG). DRST is same spec (P05/INTP2/DRST).
2. 2Tsamp + 20 or 3Tsamp + 20
Tsamp: Sampling clock for noise elimination
Reset/Interrupt
t
REG
t
WNIH
t
WRSL
V
DD
RESET (input)
NMI (input)
INTPn (input)
t
WNIL
t
WITH
t
WITL
Remark n = 0 to 7
V850ES/FG2
DATA SHEET U17832EE1V0DS00
20
(b) Key return timing
(TA = −40 to +85°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
KRn input high-level width tWKRH 500 ns
KRn input low-level width tWKRL
Analog noise elimination (n = 0 to 7)
500 ns
t
WKRH
KRn (input)
t
WKRL
Remark n = 0 to 7
(c) Timer input timing
(TA = −40 to +85°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
TIn high-level width tTIH Note ns
TIn low-level width tTIL
TIP00, TIP01, TIP10, TIP11, TIP20,
TIP21, TIP30, TIP31,
TIQ00 to TIQ03, TIQ10 to TIQ13 Note ns
Note 2Tsamp + 20 or 3Tsamp + 20
Tsamp: Sampling clock for noise elimination
t
TIH
TIn (input)
t
TIL
Remark TIn: TIP00, TIP01, TIP10 TIP11, TIP20, TIP21, TIP30, TIP31, TIQ00 to TIQ03, TIQ10 to TIQ13
V850ES/FG2
DATA SHEET U17832EE1V0DS00 21
(d) CSIB timing
(i) Master mode
(TA = −40 to +85°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
SCKBn cycle time tKCYn 125 ns
SCKBn high-level width tKHn tKCYn/2 − 15 ns
SCKBn low-level width tKLn tKCYn/2 − 15 ns
SIBn setup time (to SCKBn↑) tSIKn 30 ns
SIBn hold time (from SCKBn↑) tKSIn 25 ns
Output delay time from SCKBn↓ to SOBn tKSOn 25 ns
Remark n = 0, 1
(ii) Slave mode
(TA = −40 to +85°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
SCKBn cycle time tKCYn 200 ns
SCKBn high-level width tKHn 90 ns
SCKBn low-level width tKLn 90 ns
SIBn setup time (to SCKBn↑) tSIKn 50 ns
SIBn hold time (from SCKBn↑) tKSIn 50 ns
Output delay time from SCKBn↓ to SOBn tKSOn 50 ns
Remark n = 0, 1
V850ES/FG2
DATA SHEET U17832EE1V0DS00
22
t
KLn
t
SIKn
t
KSIn
t
KSOn
t
KCYn
t
KHn
SOBn (output)
Input data
Output data
SIBn (input)
SCKBn (I/O)
Hi-Z
Remark n = 0. 1
(e) UART timing
(TA = −40 to +85°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
Communication rate 312.5 kbps
ASCK0 cycle time 10 MHz
V850ES/FG2
DATA SHEET U17832EE1V0DS00 23
(f) CAN timing
(TA = −40 to +85°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
Transfer rate 1 Mbps
Internal delay timeNote 100 ns
Note Internal delay time (tNODE) = Internal transfer delay time (tOUTPUT) + Internal receive delay time (tINPUT)
CAN internal clock Note
CTXDn pin
(Transfer data)
CRXDn pin
(Receive data)
tinput
toutput
Note *CAN internal clock (fCAN): CAN baud rate clock
Remark n = 0, 1
V850ES/FG2
CAN macro
Image figure of internal delay
CRXDn pin
Internal receive delay
Internal transfer delay CTXDn pin
{
{
Remark n = 0, 1
V850ES/FG2
DATA SHEET U17832EE1V0DS00
24
(g) A/D converter
(TA = −40 to +85°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 10 bit
Overall errorNote 4.0 ≤ AVREF0 ≤ 5.5 V ±0.15 ±0.3 %FSR
Conversion time tCONV 3.1 16
μ
s
Analog input voltage VIAN AVSS AVREF0 V
When using A/D converter 5 10 mA AVREF0 current IAREF0
When not using A/D converter 1 10
μ
A
Note Excluding quantization error (±0.05%FSR). Indicates the ratio to the full-scale value (%FSR).
Remark FSR: Full Scale Range
(h) POC circuit characteristics
(TA = −40 to +85°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection voltage VPOC0 3.5 3.7 3.9 V
Power supply startup time tPTH VDD = 0 V → 3.5 V 0.002 ms
Response delay time 1Note 1 tPTHD In case of power on.
After VDD reaches 3.9 V.
3.0 ms
Response delay time 2 Note
2
tPD In case of power off.
After VDD drops 3.5 V.
1 ms
Minimum VDD width tPW 0.2 ms
Notes 1. From detect voltage to release reset signal.
2. From detect voltage to output reset signal.
tPTH tPTHD
VDD
Detection voltage (MAX.)
Detection voltage (TYP.)
Detection voltage (MIN.)
Time
tPW
tPD tPTHD
V850ES/FG2
DATA SHEET U17832EE1V0DS00 25
(i) LVI circuit characteristics
(TA = −40 to +85°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VLVI0 4.2 4.4 4.6 V Detection voltage
VLVI1 4.0 4.2 4.4 V
Response timeNote 1 tLD After VDD reaches VLVI0/VLVI1
(Max.).
After VDD drops VLVI0/VLVI1 (Min.).
0.2 2.0 ms
Minimum VDD width tLW 0.2 ms
Reference voltage stabilization
wait timeNote 2
tLWAIT After VDD reaches 3.5 V.
After LVION bit (LVIM.bit7) =
0 →1
0.1 0.2 ms
Notes 1. The time required to output an interrupt/reset after the detection voltage is detected.
2. Unnecessary when the POC function is used.
t
LWAIT
LVION bit = 0 → 1
V
DD
Detection voltage (MAX.)
Detection voltage (TYP.)
Detection voltage (MIN.)
Time
t
LW
t
LD
t
LD
V850ES/FG2
DATA SHEET U17832EE1V0DS00
26
(j) RAM retention flag characteristics
(TA = −40 to +85°C, VDD = EVDD = BVDD = 1.9 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection voltage VRAMH 1.9 2.0 2.1 V
Supply voltage rise time tRAMHTH VDD = 0 V → 3.5 V 0.002 1,800 ms
Response timeNote tRAMHD After the supply voltage reaches
the detection voltage (MAX.)
0.2 2.0 ms
Minimum VDD width tRAMHW 0.2 ms
Note Time required to set the RAMF bit after the detection voltage is detected.
tRAMHD
VDD
Detection voltage (MAX.)
Detection voltage (TYP.)
Detection voltage (MIN.)
Operating voltage (MIN.)
Time
tRAMHW
tRAMHTH
tRAMHD
V850ES/FG2
DATA SHEET U17832EE1V0DS00 27
(k) Flash memory pro g ramming characteristics
(i) Basic characteristics
(TA = −40 to +85°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Operating frequency fCPU 4 20 MHz
Supply voltage VDD 3.5 5.5 V
Number of writes CWRTNote 100 Times
Input voltage, high VIH FLMD0 0.8EVDD EVDD V
Input voltage, low VIL FLMD0 EVSS 0.2EVDD V
Write time + erase time tIWRT
+ tERASE
Flash: 256 KB (
μ
PD70F3235)
384 KB (
μ
PD70F3236)
T.B.D s
Programming temperature tPRG −40 +85 °C
Note The initial write when the product is shipped, any erase → write set of operations, or any programming
operation is counted as one rewrite.
Example: P: Write, E: Erase
Shipped product → P → E → P → E → P: 3 rewrites
Shipped product → E → P → E → P → E → P: 3 rewrites
(ii) Serial Write Operation Characteristics
(TA = −40 to +85°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
FLMD0 setup time from RESET↑ tRFCF 5000/fX+α s
Count execution time tCOUNT 3 ms
FLMD0 high-level width tCH 10 100
μ
s
FLMD0 low-level width tCL 10 100
μ
s
FLMD rise time tR 50 n s
FLMD fall time tF 50 n s
Note “ ” represents the oscillation stabilization time.
L
VSS
VDD
RESET
FLMD0
FLMD1
VSS
VDD
VSS
VDD
tCOUNT
tRFCF
tCL tFtR
tCH
V850ES/FG2
DATA SHEET U17832EE1V0DS00
28
1.2 Electrical Specifications of (A1)-Grade
1.2.1 Absolute maximum ratings
Absolute Maximum Ratings (TA = 25°C): Flash memory products (1/2)
Parameter Symbol Conditions Ratings Unit
VDD VDD = EVDD = BVDD −0.5 to +6.5 V
BVDD VDD = EVDD = BVDD −0.5 to +6.5 V
EVDD VDD = EVDD = BVDD −0.5 to +6.5 V
AVREF0 −0.5 to +6.5 V
VSS VSS = EVSS = BVSS = AVSS −0.5 to +0.5 V
AVSS VSS = EVSS = BVSS = AVSS −0.5 to +0.5 V
BVSS VSS = EVSS = BVSS = AVSS −0.5 to +0.5 V
Supply voltage
EVSS VSS = EVSS = BVSS = AVSS −0.5 to +0.5 V
VI1 P00 to P06, P10, P11, P30 to P39, P40 to P42, P50 to P55,
P90 to P915, RESET, FLMD0
−0.5 to EVDD + 0.5Note V
VI2 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6,
PDL0 to PDL13
−0.5 to BVDD + 0.5Note V
Input voltage
VI3 X1, X2, XT1, XT2 −0.5 to VRO + 0.5Note V
Analog input voltage VIAN P70 to P715 −0.5 to AVREF0 + 0.5 Note V
Note Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage.
Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and betw een VDD or VCC
and GND.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily
for any parameter. That is, the absolute maximum ratings are rated values at which the
product is on the verge of suffering physical damage, and therefore the product must be
used under conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions indicated for DC characteristics and AC characteristics
represent the quality assura n ce range during normal operation .
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
V850ES/FG2
DATA SHEET U17832EE1V0DS00 29
Absolute maximum ratings (TA = 25°C): Flash memory products (2/2)
Parameter Symbol Conditions Ratings Unit
Per pin 4 mA
P00 to P06, P10, P11, P30 to P39,
P40 to P42, P50 to P55, P90 to P915 Total of all pins 50Note1 mA
Per pin 4 mA P70 to P715
Total of all pins 20Note2 mA
Per pin 4 mA
Output current, low IOL
PCM0 to PCM3, PCS0, PCS1, PCT0,
PCT1, PCT4, PCT6, PDL0 to PDL13 Total of all pins 50Note1 mA
Per pin −4 mA
P00 to P06, P10, P11, P30 to P39,
P40 to P42, P50 to P55, P90 to P915 Total of all pins −50Note1 mA
Per pin −4 mA P70 to P715
Total of all pins −20Note2 mA
Per pin −4 mA
Output current, high IOH
PCM0 to PCM3, PCS0, PCS1, PCT0,
PCT1, PCT4, PCT6, PDL0 to PDL13 Total of all pins −50Note1 mA
Normal operating mode −40 to +110 °C
Operating ambient
temperature
TA
Flash programming mode −40 to +85 °C
Storage temperature Tstg −40 to +125 °C
Notes 1. This value is a value at the time of TA = 25 °C. At the time of TA = 110 °C, This value is 20
mA/−20 mA.
2. This value is a value at the time of TA = 25 °C. At the time of TA = 110 °C, This value is 10
mA/−10 mA.
Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and betw een VDD or VCC
and GND.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily
for any parameter. That is, the absolute maximum ratings are rated values at which the
product is on the verge of suffering physical damage, and therefore the product must be
used under conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions indicated for DC characteristics and AC characteristics
represent the quality assura n ce range during normal operation .
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
V850ES/FG2
DATA SHEET U17832EE1V0DS00
30
Absolute Maximum Ratings (TA = 25°C): Mask ROM products (1/2)
Parameter Symbol Conditions Ratings Unit
VDD VDD = EVDD = BVDD −0.5 to +6.5 V
BVDD VDD = EVDD = BVDD −0.5 to +6.5 V
EVDD VDD = EVDD = BVDD −0.5 to +6.5 V
AVREF0 −0.5 to +6.5 V
VSS VSS = EVSS = BVSS = AVSS −0.5 to +0.5 V
AVSS VSS = EVSS = BVSS = AVSS −0.5 to +0.5 V
BVSS VSS = EVSS = BVSS = AVSS −0.5 to +0.5 V
Supply voltage
EVSS VSS = EVSS = BVSS = AVSS −0.5 to +0.5 V
VI1 P00 to P06, P10, P11, P30 to P39, P40 to P42, P50 to P55,
P90 to P915, RESET, IC
−0.5 to EVDD + 0.5Note V
VI2 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6,
PDL0 to PDL13
−0.5 to BVDD + 0.5Note V
Input voltage
VI3 X1, X2, XT1, XT2 −0.5 to VRO + 0.5Note V
Analog input voltage VIAN P70 to P715 −0.5 to AVREF0 + 0.5 Note V
Note Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage.
Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and betw een VDD or VCC
and GND.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily
for any parameter. That is, the absolute maximum ratings are rated values at which the
product is on the verge of suffering physical damage, and therefore the product must be
used under conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions indicated for DC characteristics and AC characteristics
represent the quality assura n ce range during normal operation .
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
V850ES/FG2
DATA SHEET U17832EE1V0DS00 31
Absolute maximum ratings (TA = 25°C): Mask ROM products (2/2)
Parameter Symbol Conditions Ratings Unit
Per pin 4 mA
P00 to P06, P10, P11, P30 to P39,
P40 to P42, P50 to P55, P90 to P915 Total of all pins 50Note1 mA
Per pin 4 mA P70 to P715
Total of all pins 20Note2 mA
Per pin 4 mA
Output current, low IOL
PCM0 to PCM3, PCS0, PCS1, PCT0,
PCT1, PCT4, PCT6, PDL0 to PDL13 Total of all pins 50 Note1 mA
Per pin −4 mA
P00 to P06, P10, P11, P30 to P39,
P40 to P42, P50 to P55, P90 to P915 Total of all pins −50 Note1 mA
Per pin −4 mA P70 to P715
Total of all pins −20Note2 mA
Per pin −4 mA
Output current, high IOH
PCM0 to PCM3, PCS0, PCS1, PCT0,
PCT1, PCT4, PCT6, PDL0 to PDL13 Total of all pins −50Note1 mA
Operating ambient
temperature
TA −40 to +110 °C
Storage temperature Tstg −65 to +110 °C
Notes 1. This value is a value at the time of TA = 25 °C. At the time of TA = 110 °C, This value is 20
mA/−20 mA.
2. This value is a value at the time of TA = 25 °C. At the time of TA = 110 °C, This value is 10
mA/−10 mA.
Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and betw een VDD or VCC
and GND.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily
for any parameter. That is, the absolute maximum ratings are rated values at which the
product is on the verge of suffering physical damage, and therefore the product must be
used under conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions indicated for DC characteristics and AC characteristics
represent the quality assura n ce range during normal operation .
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
V850ES/FG2
DATA SHEET U17832EE1V0DS00
32
1.2.2 Capacitance
(TA = 25°C, VDD = EVDD = AVREF0 = BVDD = AVREF1 = VSS = EVSS = BVSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
I/O capacitance CIO fX = 1 MHz,
Unmeasured pins returned to 0 V.
10 pF
1.2.3 Operating conditions
(TA = −40 to +110°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = A VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
REGC Capacity = 4.7
μ
F at operation with
main clock
4 20 MHz
Internal system clock
frequency
fCLK
REGC Capacity = 4.7
μ
F at operation with
subclock (RC resonator)
12.5 Note 27.5 Note kHz
Note The internal system clock frequency is half the oscillation frequency.
V850ES/FG2
DATA SHEET U17832EE1V0DS00 33
1.2.4 Oscillator Characteristics
Main clock oscillator characteristics
(TA = −40 to +110°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = A VSS = 0 V)
Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit
Oscillation frequency
(fX)Note 1
4 5 MHz
After reset release 216/fX s
After STOP mode
release
0.5Note 3 Note 4 ms
Ceramic
resonator
Oscillation
stabilization timeNote 2
After IDLE2 mode
release
0.35 Note 4 ms
Oscillation frequency
(fX)Note 1
4 5 MHz
After reset release 216/fX s
After STOP mode
release
0.5Note 3 Note 4 ms
Crystal
resonator
X2X1
Oscillation
stabilization timeNote 2
After IDLE2 mode
release
350 Note 4
μ
s
Notes 1. Indicates only oscillator characteristics.
2. Time required to stabilize the crystal resonator after reset or STOP mode is released.
3. Time required to stabilize access to the internal flash memory.
4. The value differs depending on the OSTS register settings.
Cautions 1. When using the main clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to a void an adverse effect from wiring cap acitance.
• Keep the wiring length as short as possib le.
• Do not cross the wiring with the other sign al lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main clock is stopped and the device is operating on the subclock, wait until the
oscillation stabilization time has been secured by the program before switching back to the
main clock.
V850ES/FG2
DATA SHEET U17832EE1V0DS00
34
Subclock Oscillator Characteristics
(TA = −40 to +110°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V)
Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit
Oscillation frequency
(fXT)Notes1, 4
R = 390 kΩ ±5%Note 3
C = 47 pF ±10%Note 3
25 40 55 kHz
RC
resonator
XT2XT1
Oscillation
stabilization timeNote 2
100
μ
s
Notes 1. Indicates only oscillator characteristics. Refer to 27. 2. 10 AC Characteris tic s for CPU operating clock.
2. Time required from when VDD reaches oscillation voltage range (MIN.: 3.5 V) to when the crystal
resonator stabilizes.
3. In order to avoid the influence of wiring capacity, shorten wiring as much as possible.
4. RC oscillation frequency is 40 kHz (Typ.). This clock is divided (1/2) internally. In case of RC oscillator,
internal system clock frequency (fXT) is 12.5 kHz (Min.), 20 kHz (Typ.), and 27.5 kHz (Max.).
Cautions 1. When using the subclock oscillator, wire as follows in the area enclosed by the broken lines in
the above figures to avoid an adverse effect from wi ring capacitance.
• Keep the wiring length as short as possib le.
• Do not cross the wiring with the other sign al lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. The subclock oscillator is designed as a low-amplitude circuit for reducing current
consumption, and is more prone to malfunction due to noise than the main clock oscillator.
Particular care is therefore required with the wiring method when the subclock is used.
V850ES/FG2
DATA SHEET U17832EE1V0DS00 35
1.2.5 PLL Characteristics
(TA = −40 to +110°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = A VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input frequency fx 4 5 MHz
Output frequency fxx 16 20 MHz
Clock time tPLL After VDD reaches MIN.: 3.5 V 800
μ
s
1.2.6 Ring-OSC Characteristics
(TA = −40 to +110°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Output frequency fr 100 200 400 kHz
1.2.7 Voltage Regulator Characteris tics
(TA = −40 to +110°C, VDD = EVDD = BVDD, VSS = EVSS = BVSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input voltage VDD 3.5 5.5 V
Output voltage VRO 2.5 V
Lock timeNote 1 tREG After VDD reaches MIN.: 3.5 V
Connect C = 4.7
μ
F ± 20% to REGC pin
1 ms
Note 1. The lock time does not have to be considered for devices that have POC.
VDD 3.5 V
VRO
RESET
tREG
V850ES/FG2
DATA SHEET U17832EE1V0DS00
36
1.2.8 DC Characteristics
(1) Input/Output level
(TA = −40 to +110°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = A VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VIH1 P30, P34, P38, P41, P98, P911 0.7EVDD EVDD V
VIH2 P00 to P06, P10, P11, P31 to P33, P35, P39,
P40, P42, P50 to P55, P90 to P97, P99, P910,
P912 to P915
0.8EVDD EVDD V
VIH3 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1,
PCT4, PCT6, PDL0 to PDL13
0.7BVDD BVDD V
VIH4 P70 to P715 0.7AVREF0 AVREF0 V
Input voltage, high
VIH5 RESET, FLMD0 0.8EVDD EVDD V
VIL1 P30, P34, P38, P41, P98, P911 EVSS 0.3EVDD V
VIL2 P00 to P06, P10, P11, P31 to P33, P35, P39,
P40, P42, P50 to P55, P90 to P97, P99, P910,
P912 to P915
EVSS 0.2EVDD V
VIL3 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1,
PCT4, PCT6, PDL0 to PDL13
BVSS 0.3BVDD V
VIL4 P70 to P715 AVSS 0.3AVREF0 V
Input voltage, low
VIL5 RESET, FLMD0 EVSS 0.2EVDD V
IOH = −1.0 mA EVDD − 1.0 EVDD V VOH1 P00 to P06, P10, P11,
P30 to P39, P40 to P42,
P50 to P55, P90 to P915
IOH = −0.1 mA EVDD − 0.5 EVDD V
IOH = −1.0 mA BVDD − 1.0 BVDD V VOH2 PCM0 to PCM3, PCS0,
PCS1, PCT0, PCT1, PCT4,
PCT6, PDL0 to PDL13
IOH = −0.1 mA BVDD − 0.5 BVDD V
IOH = −1.0 mA AVREF0 − 1.0 AVREF0 V
Output voltage,
highNote 1
VOH3 P70 to P715
IOH = −0.1 mA AVREF0 − 0.5 AVREF0 V
VOL1 P00 to P06, P10, P11,
P30 to P39, P40 to P42,
P50 to P55, P90 to P915
IOL = 1.0 mA 0 0.4 V
VOL2 PCM0 to PCM3, PCS0,
PCS1, PCT0, PCT1, PCT4,
PCT6, PDL0 to PDL13
IOL = 1.0 mA 0 0.4 V
Output voltage,
lowNote 1
VOL3 P70 to P715 IOL = 1.0 mA 0 0.4 V
Pull-up resistor R1 VI = 0 V 10 30 100 kΩ
Pull-down
resistorNote 2
R2 VI = VDD 10 30 100 kΩ
Notes 1. Total IOH/IOL (Max.) is 20 mA/-20 mA each power supply terminal (EVDD, BVDD and AVREF0).
2. DRST pin only (OCDM0 is the control register).
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
V850ES/FG2
DATA SHEET U17832EE1V0DS00 37
(2) Pin leakage current
(TA = −40 to +110°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = A VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Analog pins +0.3 Input leakage current, high ILIH1 VIN = VDD
Other pinsNote 1 +2.0
μ
A
Analog pins −0.3 Input leakage current, low ILIL1 VIN = 0 V
Other pinsNote 1 −2.0
μ
A
Analog pins +0.3 Output leakage current, high ILOH1 VO = VDD
Other pins +2.0
μ
A
Analog pins −0.2 Output leakage current, low ILOL1 VO = 0 V
Other pins −2.0
μ
A
Note 1. For flash memory product, specification of FLMD0 is as follows:
Input leakage current, high: 4
μ
A
Input leakage current, low: −4
μ
A
V850ES/FG2
DATA SHEET U17832EE1V0DS00
38
(3) Supply current
Supply current (V850ES/FG2:
μ
PD70F3236,
μ
PD70F3235,
μ
PD70F3234)
(TA = −40 to +110°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = A VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
fXX = 20 MHz
(OSC = 5 MHz),
all peripheral
functions operating
30 45 mA
IDD1 Normal operation
fXX = 20 MHz
(OSC = 5 MHz),
all peripheral
functions stopped
22 mA
fXX = 20 MHz
(OSC = 5 MHz),
all peripheral
functions operating
18 30 mA
IDD2 HALT mode
fXX = 20 MHz
(OSC = 5 MHz),
all peripheral
functions stopped
11 mA
IDD3 IDLE1 mode fXX = 5 MHz
(OSC = 5 MHz),
PLL off
0.6 1.2 mA
IDD4 IDLE2 mode fXX = 5 MHz
(OSC = 5 MHz),
PLL off
0.25 0.9 mA
IDD5 Subclock operation
modeNotes 2, 3
RC resonator
fXT = 40 kHz Note 4
200 600
μ
A
IDD6 Sub-IDLE
modeNotes 2, 3
RC resonator
fXT = 40 kHzNote 4
35 340
μ
A
Stop modeNotes 2, 5 POC stopped,
Ring-OSC stopped
7 250
μ
A
POC operating,
Ring-OSC stopped
10 255
μ
A
POC stopped,
Ring-OSC
operating
15 265
μ
A
Flash memory products
supply currentNote 1
IDD7
POC operating,
Ring-OSC
operating
18 270
μ
A
Notes 1. Total current of VDD, EVDD, and BVDD (all ports stopped).
The current of AVREF0 and the port buffer current including the current flowing through the on-chip
pull-up/pull-down resistors are not included.
2. When the main OSC is stopped.
3. POC operating, Ring-OSC operating.
4. The RC oscillation frequency is 40 kHz (TYP.). This clock is internally divided by 2.
5. When the sub-OSC is not used.
V850ES/FG2
DATA SHEET U17832EE1V0DS00 39
Supply current (V850ES/FG2:
μ
PD703235,
μ
PD703234)
(TA = −40 to +110°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = A VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
fXX = 20 MHz
(OSC = 5 MHz),
all peripheral
functions operating
25 40 mA
IDD1 Normal operation
fXX = 20 MHz
(OSC = 5 MHz),
all peripheral
functions stopped
20 mA
fXX = 20 MHz
(OSC = 5 MHz),
all peripheral
functions operating
14 26 mA
IDD2 HALT mode
fXX = 20 MHz
(OSC = 5 MHz),
all peripheral
functions stopped
9 mA
IDD3 IDLE1 mode fXX = 5 MHz
(OSC = 5 MHz),
PLL off
0.25 0.9 mA
IDD4 IDLE2 mode fXX = 5 MHz
(OSC = 5 MHz),
PLL off
0.2 0.9 mA
IDD5 Subclock operation
modeNotes 2, 3
RC resonator
fXT = 40 kHz Note 4
50 550
μ
A
IDD6 Sub-IDLE
modeNotes 2, 3
RC resonator
fXT = 40 kHzNote 4
35 340
μ
A
Stop modeNotes 2, 5 POC stopped,
Ring-OSC stopped
7 250
μ
A
POC operating,
Ring-OSC stopped
10 255
μ
A
POC stopped,
Ring-OSC
operating
15 265
μ
A
Mask ROM products supply
currentNote 1
IDD7
POC operating,
Ring-OSC
operating
18 270
μ
A
Notes 1. Total current of VDD, EVDD, and BVDD (all ports stopped).
The current of AVREF0 and the port buffer current including the current flowing through the on-chip
pull-up/pull-down resistors are not included.
2. When the main OSC is stopped.
3. POC operating, Ring-OSC operating.
4. The RC oscillation frequency is 40 kHz(TYP.). This clock is internally divided by 2.
5. When the sub-OSC is not used.
V850ES/FG2
DATA SHEET U17832EE1V0DS00
40
1.2.9 Data Retention Characteristics
STOP Mode (TA = −40 to +110°C, VDD = EVDD = BVDD = 1.9 V to 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention voltage VDDDR In STOP mode 1.9 5.5 V
Data retention current IDDDR VDDDR = 2.0 V 10 230
μ
A
Supply voltage rise time tRVD 1
μ
s
Supply voltage fall time tFVD 1
μ
s
Supply voltage retention time tHVD After STOP mode release 0 ms
STOP release signal input time tDREL After VDD reaches MIN.: 3.5 V 0
μ
s
Data retention input voltage, high VIHDR All input ports 0.9VDDDR VDDDR V
Data retention input voltage, low VILDR All input ports 0 0.1VDDDR V
Caution Shifting to STOP mode and restoring from STOP mode must be performed within the rated
operating range.
tDRELtHVD
tFVD tRVD
STOP release signal inputSTOP mode setting
VDDDR
VIHDR
VIHDR
VILDR
VDD/EVDD/BVDD
RESET (input)
STOP mode release interrupt (NMI, etc.)
(Released by falling edge)
STOP mode release interrupt (NMI, etc.)
(Released by rising edge)
Operating voltage lower limit (Min.)
V850ES/FG2
DATA SHEET U17832EE1V0DS00 41
1.2.10 AC Characteristics
AC Test Input Measurement Points (VDD, AVDD, EVDD, BVDD)
V
DD
V
SS
V
IH (MIN.)
V
IL (MAX.)
V
IH (MIN.)
V
IL (MAX.)
Measurement points
AC Test Output Measurement Poin ts
VOH (MIN.)
VOL (MAX.)
VOH (MIN.)
VOL (MAX.)
Measurement points
Load Conditions
DUT
(Device under
measurement) C
L
= 50 pF
Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load
capacitance of the device to 50 pF or less by inserting a buffer or by some ot her means.
V850ES/FG2
DATA SHEET U17832EE1V0DS00
42
(1) CLKOUT output timing
(TA = −40 to +110°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AV REF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
Output cycle tCYK 50 ns 80
μ
s
High-level width tWKH tCYK/2 − 15 ns
Low-level width tWKL tCYK/2 − 15 ns
Rise time tKR 15 ns
Fall time tKF 15 ns
Clock Timing
CLKOUT (output)
tCYK
tWKH tWKL
tKR tKF
V850ES/FG2
DATA SHEET U17832EE1V0DS00 43
(2) Basic Operation
(a) Reset, Interrupt timing
(TA = −40 to +110°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AV REF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
RESET low-level width tWRSL 500 ns
NMI high-level width tWNIH Analog noise elimination 500 ns
NMI low-level width tWNIL Analog noise elimination 500 ns
Analog noise elimination (n = 0 to 7) 500 ns
INTPnNote 1 high-level
width
tWITH
Digital noise elimination (n = 3) Note 2 ns
Analog noise elimination (n = 0 to 7) 1 ns
INTPnNote 1 low-level
width
tWITL
Digital noise elimination (n = 3) Note 2 ns
Notes 1. ADTRG is same spec (P03/INTP0/ADTRG). DRST is same spec (P05/INTP2/DRST).
2. 2Tsamp + 20 or 3Tsamp + 20
Tsamp: Sampling clock for noise elimination
Reset/Interrupt
t
REG
t
WNIH
t
WRSL
V
DD
RESET (input)
NMI (input)
INTPn (input)
t
WNIL
t
WITH
t
WITL
Remark n = 0 to 7
V850ES/FG2
DATA SHEET U17832EE1V0DS00
44
(b) Key return timing
(TA = −40 to +110°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
KRn input high-level width tWKRH 500 ns
KRn input low-level width tWKRL
Analog noise elimination (n = 0 to 7)
500 ns
t
WKRH
KRn (input)
t
WKRL
Remark n = 0 to 7
(c) Timer input timing
(TA = −40 to +110°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
TIn high-level width tTIH Note ns
TIn low-level width tTIL
TIP00, TIP01, TIP10, TIP11, TIP20,
TIP21, TIP30, TIP31,
TIQ00 to TIQ03, TIQ10 to TIQ13 Note ns
Note 2Tsamp + 20 or 3Tsamp + 20
Tsamp: Sampling clock for noise elimination
t
TIH
TIn (input)
t
TIL
Remark TIn: TIP00, TIP01, TIP10 TIP11, TIP20, TIP21, TIP30, TIP31, TIQ00 to TIQ03, TIQ10 to TIQ13
V850ES/FG2
DATA SHEET U17832EE1V0DS00 45
(d) CSIB timing
(i) Master mode
(TA = −40 to +110°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
SCKBn cycle time tKCYn 125 ns
SCKBn high-level width tKHn tKCYn/2 − 15 ns
SCKBn low-level width tKLn tKCYn/2 − 15 ns
SIBn setup time (to SCKBn↑) tSIKn 30 ns
SIBn hold time (from SCKBn↑) tKSIn 25 ns
Output delay time from SCKBn↓ to SOBn tKSOn 25 ns
Remark n = 0, 1
(ii) Slave mode
(TA = −40 to +110°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
SCKBn cycle time tKCYn 200 ns
SCKBn high-level width tKHn 90 ns
SCKBn low-level width tKLn 90 ns
SIBn setup time (to SCKBn↑) tSIKn 50 ns
SIBn hold time (from SCKBn↑) tKSIn 50 ns
Output delay time from SCKBn↓ to SOBn tKSOn 50 ns
Remark n = 0, 1
V850ES/FG2
DATA SHEET U17832EE1V0DS00
46
t
KLn
t
SIKn
t
KSIn
t
KSOn
t
KCYn
t
KHn
SOBn (output)
Input data
Output data
SIBn (input)
SCKBn (I/O)
Hi-Z
Remark n = 0, 1
(e) UART timing
(TA = −40 to +110°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
Communication rate 312.5 kbps
ASCK0 cycle time 10 MHz
V850ES/FG2
DATA SHEET U17832EE1V0DS00 47
(f) CAN timing
(TA = −40 to +110°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AV REF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
Transfer rate 1 Mbps
Internal delay timeNote 100 ns
Note Internal delay time (tNODE) = Internal transfer delay time (tOUTPUT) + Internal receive delay time (tINPUT)
CAN internal clock Note
CTXDn pin
(Transfer data)
CRXDn pin
(Receive data)
tinput
toutput
Note *CAN internal clock (fCAN): CAN baud rate clock
Remark n = 0, 1
V850ES/FG2
CAN macro
Image figure of internal delay
CRXDn pin
Internal receive delay
Internal transfer delay CTXDn pin
{
{
Remark n = 0, 1
V850ES/FG2
DATA SHEET U17832EE1V0DS00
48
(g) A/D converter
(TA = −40 to +110°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 10 bit
Overall errorNote 4.0 ≤ AVREF0 ≤ 5.5 V ±0.15 ±0.3 %FSR
Conversion time tCONV 3.1 16
μ
s
Analog input voltage VIAN AVSS AVREF0 V
When using A/D converter 5 10 mA AVREF0 current IAREF0
When not using A/D converter 1 10
μ
A
Note Excluding quantization error (±0.05%FSR). Indicates the ratio to the full-scale value (%FSR).
Remark FSR: Full Scale Range
(h) POC circuit characteristics
(TA = −40 to +110°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection voltage VPOC0 3.5 3.7 3.9 V
Power supply startup time tPTH VDD = 0 V → 3.5 V 0.002 ms
Response delay time 1Note 1 tPTHD In case of power on.
After VDD reaches 3.9 V.
3.0 ms
Response delay time 2 Note 2 tPD In case of power off.
After VDD drops 3.5 V.
1 ms
Minimum VDD width tPW 0.2 ms
Notes 1. From detect voltage to release reset signal.
2. From detect voltage to output reset signal.
tPTH tPTHD
VDD
Detection voltage (MAX.)
Detection voltage (TYP.)
Detection voltage (MIN.)
Time
tPW
tPD tPTHD
V850ES/FG2
DATA SHEET U17832EE1V0DS00 49
(i) LVI circuit characteristics
(TA = −40 to +110°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VLVI0 4.2 4.4 4.6 V Detection voltage
VLVI1 4.0 4.2 4.4 V
Response timeNote 1 tLD After VDD reaches VLVI0/VLVI1
(Max.).
After VDD drops VLVI0/VLVI1 (Min.).
0.2 2.0 ms
Minimum VDD width tLW 0.2 ms
Reference voltage stabilization
wait timeNote 2
tLWAIT After VDD reaches 3.5 V.
After LVION bit (LVIM.bit7) =
0 →1
0.1 0.2 ms
Notes 1. The time required to output an interrupt/reset after the detection voltage is detected.
2. Unnecessary when the POC function is used.
t
LWAIT
LVION bit = 0 → 1
V
DD
Detection voltage (MAX.)
Detection voltage (TYP.)
Detection voltage (MIN.)
Time
t
LW
t
LD
t
LD
V850ES/FG2
DATA SHEET U17832EE1V0DS00
50
(j) RAM retention flag characteristics
(TA = −40 to +110°C, VDD = EVDD = BVDD = 1.9 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection voltage VRAMH 1.9 2.0 2.1 V
Supply voltage rise time tRAMHTH VDD = 0 V → 3.5 V 0.002 1,800 ms
Response timeNote tRAMHD After the supply voltage reaches
the detection voltage (MAX.)
0.2 2.0 ms
Minimum VDD width tRAMHW 0.2 ms
Note Time required to set the RAMF bit after the detection voltage is detected.
tRAMHD
VDD
Detection voltage (MAX.)
Detection voltage (TYP.)
Detection voltage (MIN.)
Operating voltage (MIN.)
Time
tRAMHW
tRAMHTH
tRAMHD
V850ES/FG2
DATA SHEET U17832EE1V0DS00 51
(k) Flash memory pro g ramming characteristics
(i) Basic characteristics
(TA = −40 to +85°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Operating frequency fCPU 4 20 MHz
Supply voltage VDD 3.5 5.5 V
Number of writes CWRTNote 100 Times
Input voltage, high VIH FLMD0 0.8EVDD EVDD V
Input voltage, low VIL FLMD0 EVSS 0.2EVDD V
Write time + erase time tIWRT
+ tERASE
Flash: 256 KB (
μ
PD70F3235)
384 KB (
μ
PD70F3236)
T.B.D s
Programming temperature tPRG −40 +85 °C
Note The initial write when the product is shipped, any erase → write set of operations, or any programming
operation is counted as one rewrite.
Example: P: Write, E: Erase
Shipped product → P → E → P → E → P: 3 rewrites
Shipped product → E → P → E → P → E → P: 3 rewrites
(ii) Serial Write Operation Characteristics
(TA = −40 to +85°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
FLMD0 setup time from RESET↑ tRFCF 5000/fx+α s
Count execution time tCOUNT 3 ms
FLMD0 high-level width tCH 10 100
μ
s
FLMD0 low-level width tCL 10 100
μ
s
FLMD rise time tR 50 n s
FLMD fall time tF 50 n s
Note “ ” represents the oscillation stabilization time.
L
VSS
VDD
RESET
FLMD0
FLMD1
VSS
VDD
VSS
VDD
tCOUNT
tRFCF
tCL tFtR
tCH
V850ES/FG2
DATA SHEET U17832EE1V0DS00
52
1.3 Electrical Specifications of (A2)-Grade
1.3.1 Absolute maximum ratings
Absolute Maximum Ratings (TA = 25°C): Flash memory products (1/2)
Parameter Symbol Conditions Ratings Unit
VDD VDD = EVDD = BVDD −0.5 to +6.5 V
BVDD VDD = EVDD = BVDD −0.5 to +6.5 V
EVDD VDD = EVDD = BVDD −0.5 to +6.5 V
AVREF0 −0.5 to +6.5 V
VSS VSS = EVSS = BVSS = AVSS −0.5 to +0.5 V
AVSS VSS = EVSS = BVSS = AVSS −0.5 to +0.5 V
BVSS VSS = EVSS = BVSS = AVSS −0.5 to +0.5 V
Supply voltage
EVSS VSS = EVSS = BVSS = AVSS −0.5 to +0.5 V
VI1 P00 to P06, P10, P11, P30 to P39, P40 to P42, P50 to P55,
P90 to P915, RESET, FLMD0
−0.5 to EVDD + 0.5Note V
VI2 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6,
PDL0 to PDL13
−0.5 to BVDD + 0.5Note V
Input voltage
VI3 X1, X2, XT1, XT2 −0.5 to VRO + 0.5Note V
Analog input voltage VIAN P70 to P715 −0.5 to AVREF0 + 0.5 Note V
Note Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage.
Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and betw een VDD or VCC
and GND.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily
for any parameter. That is, the absolute maximum ratings are rated values at which the
product is on the verge of suffering physical damage, and therefore the product must be
used under conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions indicated for DC characteristics and AC characteristics
represent the quality assura n ce range during normal operation .
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
V850ES/FG2
DATA SHEET U17832EE1V0DS00 53
Absolute maximum ratings (TA = 25°C): Flash memory products (2/2)
Parameter Symbol Conditions Ratings Unit
Per pin 4 mA
P00 to P06, P10, P11, P30 to P39,
P40 to P42, P50 to P55, P90 to P915 Total of all pins 50Note1 mA
Per pin 4 mA P70 to P715
Total of all pins 20Note2 mA
Per pin 4 mA
Output current, low IOL
PCM0 to PCM3, PCS0, PCS1, PCT0,
PCT1, PCT4, PCT6, PDL0 to PDL13 Total of all pins 50Note1 mA
Per pin −4 mA
P00 to P06, P10, P11, P30 to P39,
P40 to P42, P50 to P55, P90 to P915 Total of all pins −50Note1 mA
Per pin −4 mA P70 to P715
Total of all pins −20Note2 mA
Per pin −4 mA
Output current, high IOH
PCM0 to PCM3, PCS0, PCS1, PCT0,
PCT1, PCT4, PCT6, PDL0 to PDL13 Total of all pins −50Note1 mA
Normal operating mode −40 to +125 °C
Operating ambient
temperature
TA
Flash programming mode −40 to +85 °C
Storage temperature Tstg −40 to +125 °C
Notes 1. This value is a value at the time of TA = 25 °C. At the time of TA = 125 °C, This value is 20
mA/−20 mA.
2. This value is a value at the time of TA = 25 °C. At the time of TA = 125 °C, This value is 10
mA/−10 mA.
Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and betw een VDD or VCC
and GND.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily
for any parameter. That is, the absolute maximum ratings are rated values at which the
product is on the verge of suffering physical damage, and therefore the product must be
used under conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions indicated for DC characteristics and AC characteristics
represent the quality assura n ce range during normal operation .
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
V850ES/FG2
DATA SHEET U17832EE1V0DS00
54
Absolute Maximum Ratings (TA = 25°C): Mask ROM products (1/2)
Parameter Symbol Conditions Ratings Unit
VDD VDD = EVDD = BVDD −0.5 to +6.5 V
BVDD VDD = EVDD = BVDD −0.5 to +6.5 V
EVDD VDD = EVDD = BVDD −0.5 to +6.5 V
AVREF0 −0.5 to +6.5 V
VSS VSS = EVSS = BVSS = AVSS −0.5 to +0.5 V
AVSS VSS = EVSS = BVSS = AVSS −0.5 to +0.5 V
BVSS VSS = EVSS = BVSS = AVSS −0.5 to +0.5 V
Supply voltage
EVSS VSS = EVSS = BVSS = AVSS −0.5 to +0.5 V
VI1 P00 to P06, P10, P11, P30 to P39, P40 to P42, P50 to P55,
P90 to P915, RESET, IC
−0.5 to EVDD + 0.5Note V
VI2 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1, PCT4, PCT6,
PDL0 to PDL13
−0.5 to BVDD + 0.5Note V
Input voltage
VI3 X1, X2, XT1, XT2 −0.5 to VRO + 0.5Note V
Analog input voltage VIAN P70 to P715 −0.5 to AVREF0 + 0.5 Note V
Note Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage.
Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and betw een VDD or VCC
and GND.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily
for any parameter. That is, the absolute maximum ratings are rated values at which the
product is on the verge of suffering physical damage, and therefore the product must be
used under conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions indicated for DC characteristics and AC characteristics
represent the quality assura n ce range during normal operation .
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
V850ES/FG2
DATA SHEET U17832EE1V0DS00 55
Absolute maximum ratings (TA = 25°C): Mask ROM products (2/2)
Parameter Symbol Conditions Ratings Unit
Per pin 4 mA
P00 to P06, P10, P11, P30 to P39,
P40 to P42, P50 to P55, P90 to P915 Total of all pins 50Note1 mA
Per pin 4 mA P70 to P715
Total of all pins 20Note2 mA
Per pin 4 mA
Output current, low IOL
PCM0 to PCM3, PCS0, PCS1, PCT0,
PCT1, PCT4, PCT6, PDL0 to PDL13 Total of all pins 50 Note1 mA
Per pin −4 mA
P00 to P06, P10, P11, P30 to P39,
P40 to P42, P50 to P55, P90 to P915 Total of all pins −50 Note1 mA
Per pin −4 mA P70 to P715
Total of all pins −20Note2 mA
Per pin −4 mA
Output current, high IOH
PCM0 to PCM3, PCS0, PCS1, PCT0,
PCT1, PCT4, PCT6, PDL0 to PDL13 Total of all pins −50Note1 mA
Operating ambient
temperature
TA −40 to +125 °C
Storage temperature Tstg −65 to +150 °C
Notes 1. This value is a value at the time of TA = 25 °C. At the time of TA = 125 °C, This value is 20
mA/−20 mA.
2. This value is a value at the time of TA = 25 °C. At the time of TA = 125 °C, This value is 10
mA/−10 mA.
Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and betw een VDD or VCC
and GND.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily
for any parameter. That is, the absolute maximum ratings are rated values at which the
product is on the verge of suffering physical damage, and therefore the product must be
used under conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions indicated for DC characteristics and AC characteristics
represent the quality assura n ce range during normal operation .
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
V850ES/FG2
DATA SHEET U17832EE1V0DS00
56
1.3.2 Capacitance
(TA = 25°C, VDD = EVDD = AVREF0 = BVDD = AVREF1 = VSS = EVSS = BVSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
I/O capacitance CIO fX = 1 MHz,
Unmeasured pins returned to 0 V.
10 pF
1.3.3 Operating conditions
(TA = −40 to +125°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = A VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
REGC Capacity = 4.7
μ
F, at operation with
main clock
4 20 MHz
Internal system clock
frequency
fCLK
REGC Capacity = 4.7
μ
F, at operation with
subclock (RC resonator)
12.5Note 27.5Note kHz
Note The internal system clock frequency is half the oscillation frequency.
V850ES/FG2
DATA SHEET U17832EE1V0DS00 57
1.3.4 Oscillator Characteristics
Main clock oscillator characteristics
(TA = −40 to +125°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = A VSS = 0 V)
Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit
Oscillation frequency
(fX)Note 1
4 5 MHz
After reset release 216/fX s
After STOP mode
release
0.5Note 3 Note 4 ms
Ceramic
resonator
Oscillation
stabilization timeNote 2
After IDLE2 mode
release
0.35 Note 4 ms
Oscillation frequency
(fX)Note 1
4 5 MHz
After reset release 216/fX s
After STOP mode
release
0.5Note 3 Note 4 ms
Crystal
resonator
X2X1
Oscillation
stabilization timeNote 2
After IDLE2 mode
release
350 Note 4
μ
s
Notes 1. Indicates only oscillator characteristics.
2. Time required to stabilize the crystal resonator after reset or STOP mode is released.
3. Time required to stabilize access to the internal flash memory.
4. The value differs depending on the OSTS register settings.
Cautions 1. When using the main clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to a void an adverse effect from wiring cap acitance.
• Keep the wiring length as short as possib le.
• Do not cross the wiring with the other sign al lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main clock is stopped and the device is operating on the subclock, wait until the
oscillation stabilization time has been secured by the program before switching back to the
main clock.
V850ES/FG2
DATA SHEET U17832EE1V0DS00
58
Subclock Oscillator Characteristics
(TA = −40 to +125°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V)
Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit
Oscillation frequency
(fXT)Notes1, 4
R = 390 kΩ ±5%Note 3
C = 47 pF ±10%Note 3
25 40 55 kHz
RC
resonator
XT2XT1
Oscillation
stabilization timeNote 2
100
μ
s
Notes 1. Indicates only oscillator characteristics. Refer to 27. 3. 10 AC Characteristics for CPU operating clock.
2. Time required from when VDD reaches oscillation voltage range (MIN.: 3.5 V) to when the crystal
resonator stabilizes.
3. In order to avoid the influence of wiring capacity, shorten wiring as much as possible.
4. RC oscillation frequency is 40 kHz (Typ.). This clock is divided (1/2) internally. In case of RC oscillator,
internal system clock frequency (fXT) is 12.5 kHz (Min.), 20 kHz (Typ.), and 27.5 kHz (Max.).
Cautions 1. When using the subclock oscillator, wire as follows in the area enclosed by the broken lines in
the above figures to avoid an adverse effect from wi ring capacitance.
• Keep the wiring length as short as possib le.
• Do not cross the wiring with the other sign al lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. The subclock oscillator is designed as a low-amplitude circuit for reducing current
consumption, and is more prone to malfunction due to noise than the main clock oscillator.
Particular care is therefore required with the wiring method when the subclock is used.
V850ES/FG2
DATA SHEET U17832EE1V0DS00 59
1.3.5 PLL Characteristics
(TA = −40 to +125°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = A VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input frequency fx 4 5 MHz
Output frequency fxx 16 20 MHz
Clock time tPLL After VDD reaches MIN.: 3.5 V 800
μ
s
1.3.6 Ring-OSC Characteristics
(TA = −40 to +125°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Output frequency fr 100 200 400 kHz
1.3.7 Voltage Regulator Characteris tics
(TA = −40 to +125°C, VDD = EVDD = BVDD, VSS = EVSS = BVSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input voltage VDD 3.5 5.5 V
Output voltage VRO 2.5 V
Lock timeNote 1 tREG After VDD reaches MIN.: 3.5 V
Connect C = 4.7 mF ± 20% to REGC pin
1 ms
Note 1. The lock time does not have to be considered for devices that have POC.
VDD 3.5 V
VRO
RESET
tREG
V850ES/FG2
DATA SHEET U17832EE1V0DS00
60
1.3.8 DC Characteristics
(1) Input/Output level
(TA = −40 to +125°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = A VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VIH1 P30, P34, P38, P41, P98, P911 0.7EVDD EVDD V
VIH2 P00 to P06, P10, P11, P31 to P33, P35, P39,
P40, P42, P50 to P55, P90 to P97, P99, P910,
P912 to P915
0.8EVDD EVDD V
VIH3 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1,
PCT4, PCT6, PDL0 to PDL13
0.7BVDD BVDD V
VIH4 P70 to P715 0.7AVREF0 AVREF0 V
Input voltage, high
VIH5 RESET, FLMD0 0.8EVDD EVDD V
VIL1 P30, P34, P38, P41, P98, P911 EVSS 0.3EVDD V
VIL2 P00 to P06, P10, P11, P31 to P33, P35, P39,
P40, P42, P50 to P55, P90 to P97, P99, P910,
P912 to P915
EVSS 0.2EVDD V
VIL3 PCM0 to PCM3, PCS0, PCS1, PCT0, PCT1,
PCT4, PCT6, PDL0 to PDL13
BVSS 0.3BVDD V
VIL4 P70 to P715 AVSS 0.3AVREF0 V
Input voltage, low
VIL5 RESET, FLMD0 EVSS 0.2EVDD V
IOH = −1.0 mA EVDD − 1.0 EVDD V VOH1 P00 to P06, P10, P11,
P30 to P39, P40 to P42,
P50 to P55, P90 to P915
IOH = −0.1 mA EVDD − 0.5 EVDD V
IOH = −1.0 mA BVDD − 1.0 BVDD V VOH2 PCM0 to PCM3, PCS0,
PCS1, PCT0, PCT1, PCT4,
PCT6, PDL0 to PDL13
IOH = −0.1 mA BVDD − 0.5 BVDD V
IOH = −1.0 mA AVREF0 − 1.0 AVREF0 V
Output voltage,
highNote 1
VOH3 P70 to P715
IOH = −0.1 mA AVREF0 − 0.5 AVREF0 V
VOL1 P00 to P06, P10, P11,
P30 to P39, P40 to P42,
P50 to P55, P90 to P915
IOL = 1.0 mA 0 0.4 V
VOL2 PCM0 to PCM3, PCS0,
PCS1, PCT0, PCT1, PCT4,
PCT6, PDL0 to PDL13
IOL = 1.0 mA 0 0.4 V
Output voltage,
lowNote 1
VOL3 P70 to P715 IOL = 1.0 mA 0 0.4 V
Pull-up resistor R1 VI = 0 V 10 30 100 kΩ
Pull-down
resistorNote 2
R2 VI = VDD 10 30 100 kΩ
Notes 1. Total IOH/IOL (Max.) of EVDD is 20 mA/-20 mA.
Total IOH/IOL (Max.) of AVREF0 is 10 mA/-10 mA.
2. DRST pin only (OCDM0 is the control register).
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
V850ES/FG2
DATA SHEET U17832EE1V0DS00 61
(2) Pin leakage current
(TA = −40 to +125°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = A VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Analog pins +1.0 Input leakage current, high ILIH1 VIN = VDD
Other pins +5.0
μ
A
Analog pins −1.0 Input leakage current, low ILIL1 VIN = 0 V
Other pins −5.0
μ
A
Analog pins +1.0 Output leakage current, high ILOH1 VO = VDD
Other pins +5.0
μ
A
Analog pins −1.0 Output leakage current, low ILOL1 VO = 0 V
Other pins −5.0
μ
A
V850ES/FG2
DATA SHEET U17832EE1V0DS00
62
(3) Supply current
Supply current (V850ES/FG:
μ
PD70F3236,
μ
PD70F3235,
μ
PD70F3234)
(TA = −40 to +125°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
fXX = 20 MHz
(OSC = 5 MHz),
all peripheral
functions operating
30 45 mA
IDD1 Normal operation,
fXX = 20 MHz
(OSC = 5 MHz),
all peripheral
functions stopped
22 mA
fXX = 20 MHz
(OSC = 5 MHz),
all peripheral
functions operating
18 30 mA
IDD2 HALT mode
fXX = 20 MHz
(OSC = 5 MHz),
all peripheral
functions stopped
11 mA
IDD3 IDLE1 mode fXX = 5 MHz
(OSC = 5 MHz),
PLL off
0.6 1.5 mA
IDD4 IDLE2 mode fXX = 5 MHz
(OSC = 5 MHz),
PLL off
0.25 1.15 mA
IDD5 Subclock operation
modeNotes 2, 3
RC resonator
fXT = 40 kHz Note 4
200 850
μ
A
IDD6 Sub-IDLE
modeNotes 2, 3
RC resonator
fXT = 40 kHzNote 4
35 590
μ
A
Stop modeNotes 2, 5 POC stopped,
Ring-OSC stopped
7 500
μ
A
POC operating,
Ring-OSC stopped
10 505
μ
A
POC stopped,
Ring-OSC
operating
15 515
μ
A
Flash memory products
supply currentNote 1
IDD7
POC operating,
Ring-OSC
operating
18 520
μ
A
Notes 1. Total current of VDD, EVDD, and BVDD (all ports stopped).
The current of AVREF0 and the port buffer current including the current flowing through the on-chip
pull-up/pull-down resistors are not included.
2. When the main OSC is stopped.
3. POC operating, Ring-OSC operating.
4. The RC oscillation frequency is 40 kHz(TYP.). This clock is internally divided by 2.
5. When the sub-OSC is not used.
V850ES/FG2
DATA SHEET U17832EE1V0DS00 63
Supply current (V850ES/FG2:
μ
PD703235,
μ
PD703234)
(TA = −40 to +125°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = A VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
fXX = 20 MHz
(OSC = 5 MHz),
all peripheral
functions operating
25 40 mA
IDD1 Normal operation,
fXX = 20 MHz
(OSC = 5 MHz),
all peripheral
functions stopped
20 mA
fXX = 20 MHz
(OSC = 5 MHz),
all peripheral
functions operating
14 26 mA
IDD2 HALT mode
fXX = 20 MHz
(OSC = 5 MHz),
all peripheral
functions stopped
9 mA
IDD3 IDLE1 mode fXX = 5 MHz
(OSC = 5 MHz),
PLL off
0.25 1.15 mA
IDD4 IDLE2 mode fXX = 5 MHz
(OSC = 5 MHz),
PLL off
0.2 1.15 mA
IDD5 Subclock operation
modeNotes 2, 3
RC resonator
fXT = 40 kHz Note 4
50 800
μ
A
IDD6 Sub-IDLE
modeNotes 2, 3
RC resonator
fXT = 40 kHzNote 4
35 590
μ
A
Stop modeNotes 2, 5 POC stopped,
Ring-OSC stopped
7 500
μ
A
POC operating,
Ring-OSC stopped
10 505
μ
A
POC stopped,
Ring-OSC
operating
15 515
μ
A
Mask ROM products supply
currentNote 1
IDD7
POC operating,
Ring-OSC
operating
18 520
μ
A
Notes 1. Total current of VDD, EVDD, and BVDD (all ports stopped).
The current of AVREF0 and the port buffer current including the current flowing through the on-chip
pull-up/pull-down resistors are not included.
2. When the main OSC is stopped.
3. POC operating, Ring-OSC operating.
4. The RC oscillation frequency is 40 kHz (TYP.). This clock is internally divided by 2.
5. When the sub-OSC is not used.
V850ES/FG2
DATA SHEET U17832EE1V0DS00
64
1.3.9 Data Retention Characteristics
STOP Mode (TA = −40 to +125°C, VDD = EVDD = BVDD =1.9 V to 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention voltage VDDDR In STOP mode 1.9 5.5 V
Data retention current IDDDR VDDDR = 2.0 V 6 450
μ
A
Supply voltage rise time tRVD 1
μ
s
Supply voltage fall time tFVD 1
μ
s
Supply voltage retention time tHVD After STOP mode release 0 ms
STOP release signal input time tDREL After VDD reaches MIN.: 3.5 V 0
μ
s
Data retention input voltage, high VIHDR All input ports 0.9VDDDR VDDDR V
Data retention input voltage, low VILDR All input ports 0 0.1VDDDR V
Caution Shifting to STOP mode and restoring from STOP mode must be performed within the rated
operating range.
tDRELtHVD
tFVD tRVD
STOP release signal inputSTOP mode setting
VDDDR
VIHDR
VIHDR
VILDR
VDD/EVDD/BVDD
RESET (input)
STOP mode release interrupt (NMI, etc.)
(Released by falling edge)
STOP mode release interrupt (NMI, etc.)
(Released by rising edge)
Operating voltage lower limit (Min.)
V850ES/FG2
DATA SHEET U17832EE1V0DS00 65
1.3.10 AC Characteristics
AC Test Input Measurement Points (VDD, AVDD, EVDD, BVDD)
V
DD
V
SS
V
IH (MIN.)
V
IL (MAX.)
V
IH (MIN.)
V
IL (MAX.)
Measurement points
AC Test Output Measurement Poin ts
VOH (MIN.)
VOL (MAX.)
VOH (MIN.)
VOL (MAX.)
Measurement points
Load Conditions
DUT
(Device under
measurement) C
L
= 50 pF
Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load
capacitance of the device to 50 pF or less by inserting a buffer or by some ot her means.
V850ES/FG2
DATA SHEET U17832EE1V0DS00
66
(1) CLKOUT output timing
(TA = −40 to +125°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AV REF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
Output cycle tCYK 50 ns 80
μ
s
High-level width tWKH tCYK/2 − 15 ns
Low-level width tWKL tCYK/2 − 15 ns
Rise time tKR 15 ns
Fall time tKF 15 ns
Clock Timing
CLKOUT (output)
tCYK
tWKH tWKL
tKR tKF
V850ES/FG2
DATA SHEET U17832EE1V0DS00 67
(2) Basic Operation
(a) Reset, Interrupt timing
(TA = −40 to +125°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AV REF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
RESET low-level width tWRSL 500 ns
NMI high-level width tWNIH Analog noise elimination 500 ns
NMI low-level width tWNIL Analog noise elimination 500 ns
Analog noise elimination (n = 0 to 7) 500 ns
INTPnNote 1 high-level
width
tWITH
Digital noise elimination (n = 3) Note 2 ns
Analog noise elimination (n = 0 to 7) 1 ns
INTPnNote 1 low-level
width
tWITL
Digital noise elimination (n = 3) Note 2 ns
Notes 1. ADTRG is same spec (P03/INTP0/ADTRG). DRST is same spec (P05/INTP2/DRST).
2. 2Tsamp + 20 or 3Tsamp + 20
Tsamp: Sampling clock for noise elimination
Reset/Interrupt
t
REG
t
WNIH
t
WRSL
V
DD
RESET (input)
NMI (input)
INTPn (input)
t
WNIL
t
WITH
t
WITL
Remark n = 0 to 7
V850ES/FG2
DATA SHEET U17832EE1V0DS00
68
(b) Key return timing
(TA = −40 to +125°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
KRn input high-level width tWKRH 500 ns
KRn input low-level width tWKRL
Analog noise elimination (n = 0 to 7)
500 ns
t
WKRH
KRn (input)
t
WKRL
Remark n = 0 to 7
(c) Timer input timing
(TA = −40 to +125°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
TIn high-level width tTIH Note ns
TIn low-level width tTIL
TIP00, TIP01, TIP10, TIP11, TIP20,
TIP21, TIP30, TIP31,
TIQ00 to TIQ03, TIQ10 to TIQ13 Note ns
Note 2Tsamp + 20 or 3Tsamp + 20
Tsamp: Sampling clock for noise elimination
t
TIH
TIn (input)
t
TIL
Remark TIn: TIP00, TIP01, TIP10 TIP11, TIP20, TIP21, TIP30, TIP31, TIQ00 to TIQ03, TIQ10 to TIQ13
V850ES/FG2
DATA SHEET U17832EE1V0DS00 69
(d) CSIB timing
(i) Master mode
(TA = −40 to +125°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
SCKBn cycle time tKCYn 125 ns
SCKBn high-level width tKHn tKCYn/2 − 15 ns
SCKBn low-level width tKLn tKCYn/2 − 15 ns
SIBn setup time (to SCKBn↑) tSIKn 30 ns
SIBn hold time (from SCKBn↑) tKSIn 25 ns
Output delay time from SCKBn↓ to SOBn tKSOn 25 ns
Remark n = 0, 1
(ii) Slave mode
(TA = −40 to +125°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
SCKBn cycle time tKCYn 200 ns
SCKBn high-level width tKHn 90 ns
SCKBn low-level width tKLn 90 ns
SIBn setup time (to SCKBn↑) tSIKn 50 ns
SIBn hold time (from SCKBn↑) tKSIn 50 ns
Output delay time from SCKBn↓ to SOBn tKSOn 50 ns
Remark n = 0, 1
V850ES/FG2
DATA SHEET U17832EE1V0DS00
70
t
KLn
t
SIKn
t
KSIn
t
KSOn
t
KCYn
t
KHn
SOBn (output)
Input data
Output data
SIBn (input)
SCKBn (I/O)
Hi-Z
Remark n = 0, 1
(e) UART timing
(TA = −40 to +125°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
Communication rate 312.5 kbps
ASCK0 cycle time 10 MHz
V850ES/FG2
DATA SHEET U17832EE1V0DS00 71
(f) CAN timing
(TA = −40 to +125°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AV REF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
Transfer rate 1 Mbps
Internal delay timeNote 100 ns
Note Internal delay time (tNODE) = Internal transfer delay time (tOUTPUT) + Internal receive delay time (tINPUT)
CAN internal clock Note
CTXDn pin
(Transfer data)
CRXDn pin
(Receive data)
tinput
toutput
Note *CAN internal clock (fCAN): CAN baud rate clock
Remark n = 0, 1
V850ES/FG2
CAN macro
Image figure of internal delay
CRXDn pin
Internal receive delay
Internal transfer delay CTXDn pin
{
{
Remark n = 0, 1
V850ES/FG2
DATA SHEET U17832EE1V0DS00
72
(g) A/D converter
(TA = −40 to +125°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 10 bit
Overall errorNote 4.0 ≤ AVREF0 ≤ 5.5 V ±0.15 ±0.35 %FSR
Conversion time tCONV 3.1 16
μ
s
Analog input voltage VIAN AVSS AVREF0 V
When using A/D converter 5 10 mA AVREF0 current IAREF0
When not using A/D converter 1 10
μ
A
Note Excluding quantization error (±0.05%FSR). Indicates the ratio to the full-scale value (%FSR).
Remark FSR: Full Scale Range
(h) POC circuit characteristics
(TA = −40 to +125°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection voltage VPOC0 3.5 3.7 3.9 V
Power supply startup time tPTH VDD = 0 V → 3.5 V 0.002 ms
Response delay time 1Note
1
tPTHD In case of power on.
After VDD reaches 3.9 V.
3.0 ms
Response delay time 2 Note
2
tPD In case of power off.
After VDD drops 3.5 V.
1 ms
Minimum VDD width tPW 0.2 ms
Notes 1. From detect voltage to release reset signal.
2. From detect voltage to output reset signal.
tPTH tPTHD
VDD
Detection voltage (MAX.)
Detection voltage (TYP.)
Detection voltage (MIN.)
Time
tPW
tPD tPTHD
V850ES/FG2
DATA SHEET U17832EE1V0DS00 73
(i) LVI circuit characteristics
(TA = −40 to +125°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VLVI0 4.2 4.4 4.6 V Detection voltage
VLVI1 4.0 4.2 4.4 V
Response timeNote 1 tLD After VDD reaches VLVI0/VLVI1
(Max.).
After VDD drops VLVI0/VLVI1 (Min.).
0.2 2.0 ms
Minimum VDD width tLW 0.2 ms
Reference voltage stabilization
wait timeNote 2
tLWAIT After VDD reaches 3.5 V.
After LVION bit (LVIM.bit7) =
0 →1
0.1 0.2 ms
Notes 1. The time required to output an interrupt/reset after the detection voltage is detected.
2. Unnecessary when the POC function is used.
t
LWAIT
LVION bit = 0 → 1
V
DD
Detection voltage (MAX.)
Detection voltage (TYP.)
Detection voltage (MIN.)
Time
t
LW
t
LD
t
LD
V850ES/FG2
DATA SHEET U17832EE1V0DS00
74
(j) RAM retention flag characteristics
(TA = −40 to +125°C, VDD = EVDD = BVDD = 1.9 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection voltage VRAMH 1.9 2.0 2.1 V
Supply voltage rise time tRAMHTH VDD = 0 V → 3.5 V 0.002 1,800 ms
Response timeNote tRAMHD After the supply voltage reaches
the detection voltage (MAX.)
0.2 2.0 ms
Minimum VDD width tRAMHW 0.2 ms
Note Time required to set the RAMF bit after the detection voltage is detected.
tRAMHD
VDD
Detection voltage (MAX.)
Detection voltage (TYP.)
Detection voltage (MIN.)
Operating voltage (MIN.)
Time
tRAMHW
tRAMHTH
tRAMHD
V850ES/FG2
DATA SHEET U17832EE1V0DS00 75
(k) Flash memory pro g ramming characteristics
(i) Basic characteristics
(TA = −40 to +85°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Operating frequency fCPU 4 20 MHz
Supply voltage VDD 3.5 5.5 V
Number of writes CWRTNote 100 Times
Input voltage, high VIH FLMD0 0.8EVDD EVDD V
Input voltage, low VIL FLMD0 EVSS 0.2EVSS V
Write time + erase time tIWRT
+ tERASE
Flash: 256 KB (
μ
PD70F3235)
384 KB (
μ
PD70F3236)
T.B.D s
Programming temperature tPRG −40 +85 °C
Note The initial write when the product is shipped, any erase → write set of operations, or any programming
operation is counted as one rewrite.
Example: P: Write, E: Erase
Shipped product → P → E → P → E → P: 3 rewrites
Shipped product → E → P → E → P → E → P: 3 rewrites
(ii) Serial Write Operation Characteristics
(TA = −40 to +85°C, VDD = EVDD = BVDD = 3.5 V to 5.5 V, 4.0 V ≤ AVREF0 ≤ 5.5 V, VSS = EVSS = BVSS = AVSS = 0 V,
CL = 50 pF)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
FLMD0 setup time from RESET↑ tRFCF 5000/fX+α s
Count execution time tCOUNT 3 ms
FLMD0 high-level width tCH 10 100
μ
s
FLMD0 low-level width tCL 10 100
μ
s
FLMD rise time tR 50 n s
FLMD fall time tF 50 n s
Note “ ” represents the oscillation stabilization time.
L
VSS
VDD
RESET
FLMD0
FLMD1
VSS
VDD
VSS
VDD
tCOUNT
tRFCF
tCL tFtR
tCH
V850ES/FG2
DATA SHEET U17832EE1V0DS00
76
2. Injected Current Specification
2.1 Injected Current Specification of (A)-Grade
2.1.1 Absolute Maximum Ratings
( Ta = +25 °C )
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Pos. Overload Current IINJPM Digital input pins Per pin 4 mA
VIN > VDD Total 50 mA
Analog input pins Per pin 4 mA
Total 20 mA
Neg. Overload Current IINJNM Digital input pins Per pin -4 mA
VIN < VSS Total -50 mA
Analog input pins Per pin -4 mA
Total -20 mA
Caution: Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter.
Remark: Analog input pins are pins of Port7 and Port12. Digital input pins are pins except analog input pins.
2.1.2 DC Characteristics for overload current
( Ta = -40 to +85 °C, VDD=EVDD=BVDD= 3.5V to 5.5V, AVREF0= 4.0V to 5.5V, VSS=EVSS=BVSS=AVSS=0V )
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Pos. Overload Current IINJP Digital input pins Per pin 2 mA
VIN > VDD Total 16 mA
Analog input pins Per pin 0.5 mA
Tot a l 2 mA
Neg. Overload Current IINJN Digital input pins Note1 Per pin -0.3 mA
VIN < VSS To tal -2.4 mA
Analog input pins Per pin -0.3 mA
Tot al -1.2 mA
Remark(s):
1. Analog input pins are pins of Port7 and Port12. Digital input pins are pins except analog input pins.
2. These specifications are not tested in outgoing inspection, but specified based on the device
characterization.
3. Refer to the next pages for Input leakage current and A/D characteristics.
Note(s):
1. In case of using Sub clock, an adjacent pin of XT2 pin is the following specification.
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Neg. Overload Current IINJN an adjacent pin Per pin -0.1 mA
VIN < VSS of XT2 pin Note2
Note(s):
2. An adjacent pin of XT2 pin is as follows:
V850ES/FE2: P00 pin, V850ES/FF2: P05 pin, V850ES/FG2: P02 pin, V850ES/FJ2: P02 pin
V850ES/FG2
DATA SHEET U17832EE1V0DS00 77
2.1.3 DC Characteristics for pins influenced by injected curren t on a n adjacent pin
( Ta = -40 to +85 °C, VDD=EVDD=BVDD= 3.5V to 5.5V, AVREF0= 4.0V to 5.5V, VSS=EVSS=BVSS=AVSS=0V )
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input leakage current ILIH V
I = VDD Digital input pins
High
IINJP : 2mA(per pin), 4mA(total) - 0.5 uA
Analog input pins
IINJP : 0.5mA(per pin), 1mA(total) - 0.2 uA
Input leakage current ILIL V
I = 0 Digital input pins
Low
IINJN : -0.3mA(per pin), -0.6mA(total) 5 40 uA
IINJN : -0.1mA(per pin), -0.2mA(total) 1 10 uA
Analog input pins
IINJN : -0.3mA(per pin), -0.6mA(total) 5 40 uA
IINJN : -0.1mA(per pin), -0.2mA(total) 1 10 uA
Remark(s):
1. Analog input pins are pins of Port7 and Port12. Digital input pins are pins except analog input pins.
2. These specifications are not tested in outgoing inspection, but specified based on the device
characterization.
3. Measurement conditions are shown in Figure 1.
4. TYP. is the value of Ta=+25 °C.
V850ES/FG2
DATA SHEET U17832EE1V0DS00
78
2.1.4 A/D converter influenced by injected current on an adjacent pin
( Ta = -40 to +85 °C, VDD=EVDD=BVDD= 3.5V to 5.5V, AVREF0= 4.0V to 5.5V, VSS=EVSS=BVSS=AVSS=0V )
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Degradation of IINJP : 0.5mA(per pin), 1mA(total) +/- 0.10 %FSR
Overall error Note1
IINJN : -0.3mA(per pin), -0.6mA(total) +/- 0.25 %FSR
Remark(s):
1. These specifications are not tested in outgoing inspection, but specified based on the device
characterization.
2. Measurement conditions are shown in Figure 1.
Note(s):
This value is the degradation by injected current on an adjacent pin. Therefore, this value is added to
the specification of A/D converter’s overall error defined separately as the electrical specifications.
Caution(s):
When there is a leakage current, the effect on the ADC accuracy depends on the external analog source
impedance.
Example) Conditions: AVREF0 = 5.0V, external analog source impedance = 10K ohm
If there is a leakage current of 10uA by injected current, the effect on the ADC accuracy is
10(uA) x 10K(ohm) / 5(V) = 2 %FSR
Figure 1
Injected
current
DUT
( dev ice un der te st )
Injected
current
Measurement
V850ES/FG2
DATA SHEET U17832EE1V0DS00 79
2.2 Injected Current Specification of (A1)-Grade
2.2.1 Absolute Maximum Ratings
( Ta = +25 °C )
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Pos. Overload Current IINJPM Digital input pins Per pin 4 mA
VIN > VDD Total 50 mA
Analog input pins Per pin 4 mA
Total 20 mA
Neg. Overload Current IINJNM Digital input pins Per pin -4 mA
VIN < VSS Total -50 mA
Analog input pins Per pin -4 mA
Total -20 mA
Caution: Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter.
Remark: Analog input pins are pins of Port7 and Port12. Digital input pins are pins except analog input pins.
2.2.2 DC Characteristics for overload current
( Ta = -40 to +110 °C, VDD=EVDD=BVDD= 3.5V to 5.5V, AVREF0= 4.0V to 5.5V, VSS=EVSS=BVSS=AVSS=0V )
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Pos. Overload Current IINJP Digital input pins Per pin 2 mA
VIN > VDD Total 16 mA
Analog input pins Per pin 0.5 mA
Tot a l 2 mA
Neg. Overload Current IINJN Digital input pins Note1 Per pin -0.3 mA
VIN < VSS Tot al -2.4 mA
Analog input pins Per pin -0.3 mA
Tot al -1.2 mA
Remark(s):
1. Analog input pins are pins of Port7 and Port12. Digital input pins are pins except analog input pins.
2. These specifications are not tested in outgoing inspection, but specified based on the device
characterization.
3. Refer to the next pages for Input leakage current and A/D characteristics.
Note(s):
1. In case of using Sub clock, an adjacent pin of XT2 pin is the following specification.
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Neg. Overload Current IINJN an adjacent pin Per pin -0.1 mA
VIN < VSS of XT2 pin Note2
Note(s):
2. An adjacent pin of XT2 pin is as follows.
V850ES/FE2: P00 pin, V850ES/FF2: P05 pin, V850ES/FG2: P02 pin, V850ES/FJ2: P02 pin
V850ES/FG2
DATA SHEET U17832EE1V0DS00
80
2.2.3 DC Characteristics for pins influenced by injected curren t on a n adjacent pin
( Ta = -40 to +110 °C, VDD=EVDD=BVDD= 3.5V to 5.5V, AVREF0= 4.0V to 5.5V, VSS=EVSS=BVSS=AVSS=0V )
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input leakage current ILIH V
I = VDD Digital input pins
High
IINJP : 2mA(per pin), 4mA(total) - 2 uA
Analog input pins
IINJP : 0.5mA(per pin), 1mA(total) - 2 uA
Input leakage current ILIL V
I = 0 Digital input pins
Low
IINJN : -0.3mA(per pin), -0.6mA(total) 5 60 uA
IINJN : -0.1mA(per pin), -0.2mA(total) 1 15 uA
Analog input pins
IINJN : -0.3mA(per pin), -0.6mA(total) 5 60 uA
IINJN : -0.1mA(per pin), -0.2mA(total) 1 15 uA
Remark(s):
1. Analog input pins are pins of Port7 and Port12. Digital input pins are pins except analog input pins.
2. These specifications are not tested in outgoing inspection, but specified based on the device
characterization.
3. Measurement conditions are shown in Figure 2.
4. TYP. is the value of Ta=+25 °C.
V850ES/FG2
DATA SHEET U17832EE1V0DS00 81
2.2.4 A/D converter influenced by injected current on an adjacent pin
( Ta = -40 to +110 °C, VDD=EVDD=BVDD= 3.5V to 5.5V, AVREF0= 4.0V to 5.5V, VSS=EVSS=BVSS=AVSS=0V )
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Degradation of IINJP : 0.5mA(per pin), 1mA(total) +/- 0.10 %FSR
Overall error Note1
IINJN : -0.3mA(per pin), -0.6mA(total) +/- 0.25 %FSR
Remark(s):
1. These specifications are not tested in outgoing inspection, but specified based on the device
characterization.
2. Measurement conditions are shown in Figure 2.
Note(s):
This value is the degradation by injected current on an adjacent pin. Therefore, this value is added to
the specification of A/D converter’s overall error defined separately as the electrical specifications.
Caution(s):
When there is a leakage current, the effect on the ADC accuracy depends on the external analog source
impedance.
Example) Conditions: AVREF0 = 5.0V, external analog source impedance = 10K ohm
If there is a leakage current of 10uA by injected current, the effect on the ADC accuracy is
10(uA) x 10K(ohm) / 5(V) = 2 %FSR
Figure 2
Injected
current
DUT
( dev ice un der te st )
Injected
current
Measurement
V850ES/FG2
DATA SHEET U17832EE1V0DS00
82
2.3 Injected Current Specification of (A2)-Grade
2.3.1 Absolute Maximum Ratings
( Ta = +25 °C )
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Pos. Overload Current IINJPM Digital input pins Per pin 4 mA
VIN > VDD Total 50 mA
Analog input pins Per pin 4 mA
Total 20 mA
Neg. Overload Current IINJNM Digital input pins Per pin -4 mA
VIN < VSS Total -50 mA
Analog input pins Per pin -4 mA
Total -20 mA
Caution: Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter.
Remark: Analog input pins are pins of Port7 and Port12. Digital input pins are pins except analog input pins.
2.3.2 DC Characteristics for overload current
( Ta = -40 to +125 °C, VDD=EVDD=BVDD= 3.5V to 5.5V, AVREF0= 4.0V to 5.5V, VSS=EVSS=BVSS=AVSS=0V )
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Pos. Overload Current IINJP Digital input pins Per pin 2 mA
VIN > VDD Total 16 mA
Analog input pins Per pin 0.5 mA
Tot a l 2 mA
Neg. Overload Current IINJN Digital input pins Note1 Per pin -0.3 mA
VIN < VSS Tot al -2.4 mA
Analog input pins Per pin -0.3 mA
Tot al -1.2 mA
Remark(s):
1. Analog input pins are pins of Port7 and Port12. Digital input pins are pins except analog input pins.
2. These specifications are not tested in outgoing inspection, but specified based on the device
characterization.
3. Refer to the next pages for Input leakage current and A/D characteristics.
Note(s):
1. In case of using Sub clock, an adjacent pin of XT2 pin is the following specification.
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Neg. Overload Current IINJN an adjacent pin Per pin -0.1 mA
VIN < VSS of XT2 pin Note2
Note(s):
2. An adjacent pin of XT2 pin is as follows.
V850ES/FE2: P00 pin, V850ES/FF2: P05 pin, V850ES/FG2: P02 pin, V850ES/FJ2: P02 pin
V850ES/FG2
DATA SHEET U17832EE1V0DS00 83
2.3.3 DC Characteristics for pins influenced by injected curren t on a n adjacent pin
( Ta = -40 to +125 °C, VDD=EVDD=BVDD= 3.5V to 5.5V, AVREF0= 4.0V to 5.5V, VSS=EVSS=BVSS=AVSS=0V )
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input leakage current ILIH V
I = VDD Digital input pins
High
IINJP : 2mA(per pin), 4mA(total) - 5 uA
Analog input pins
IINJP : 0.5mA(per pin), 1mA(total) - 3 uA
Input leakage current ILIL V
I = 0 Digital input pins
Low
IINJN : -0.3mA(per pin), -0.6mA(total) 5 60 uA
IINJN : -0.1mA(per pin), -0.2mA(total) 1 15 uA
Analog input pins
IINJN : -0.3mA(per pin), -0.6mA(total) 5 60 uA
IINJN : -0.1mA(per pin), -0.2mA(total) 1 15 uA
Remark(s):
1. Analog input pins are pins of Port7 and Port12. Digital input pins are pins except analog input pins.
2. These specifications are not tested in outgoing inspection, but specified based on the device
characterization.
3. Measurement conditions are shown in Figure 3.
4. TYP. is the value of Ta=+25 °C.
V850ES/FG2
DATA SHEET U17832EE1V0DS00
84
2.3.4 A/D converter influenced by injected current on an adjacent pin
( Ta = -40 to +125 °C, VDD=EVDD=BVDD= 3.5V to 5.5V, AVREF0= 4.0V to 5.5V, VSS=EVSS=BVSS=AVSS=0V )
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Degradation of IINJP : 0.5mA(per pin), 1mA(total) +/- 0.10 %FSR
Overall error Note1
IINJN : -0.3mA(per pin), -0.6mA(total) +/- 0.25 %FSR
Remark(s):
1. These specifications are not tested in outgoing inspection, but specified based on the device
characterization.
2. Measurement conditions are shown in Figure 3.
Note(s):
This value is the degradation by injected current on an adjacent pin. Therefore, this value is added to
the specification of A/D converter’s overall error defined separately as the electrical specifications.
Caution(s):
When there is a leakage current, the effect on the ADC accuracy depends on the external analog source
impedance.
Example) Conditions: AVREF0 = 5.0V, external analog source impedance = 10K ohm
If there is a leakage current of 10uA by injected current, the effect on the ADC accuracy is
10(uA) x 10K(ohm) / 5(V) = 2 %FSR
Figure 3
Injected
current
DUT
( dev ice un der te st )
Injected
current
Measurement
V850ES/FG2
DATA SHEET U17832EE1V0DS00 85
3. Package Drawings
Figure 3-1: Package Drawing
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
NOTE
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
D
G
16.00±0.20
14.00±0.20
0.50 (T.P.)
1.00
J
16.00±0.20
K
C 14.00±0.20
I 0.08
1.00±0.20
L0.50±0.20
F 1.00
N
P
Q
0.08
1.40±0.05
0.10±0.05
S100GC-50-8EU, 8EA-2
S 1.60 MAX.
H 0.22+0.05
−0.04
M 0.17+0.03
−0.07
R3°+7°
−3°
125
26
50
100
76
75 51
S
SN
J
detail of lead end
C D
A
B
R
K
M
L
P
I
S
Q
G
F
M
H
V850ES/FG2
DATA SHEET U17832EE1V0DS00
86
4. Recommended Soldering Conditions
Table 4-1: Soldering Conditions
(1) µPD70F3236MxGC(Ax)-8EA, µPD70F3235MxGC(Ax)-8EA, µPD70F3234MxGC(Ax)-8EA
Soldering Method Soldering Condition Symbol of Recommended Soldering
Condition
Infrared Reflow Package Peak Temperature: 235°C
Time: 30 seconds max. (210°C min.)
Count: 3 max
Exposure Limit: 7 daysNote
IR35-207-3
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
After that, prebaking is necessary at 125 °C for 20 to 72 hours.
