CYV270M0101EQ
Adaptive Video Cable Equalizer
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-06830 Rev. *B Revised October 25, 2007
Features
■Adaptive cable equalization
■SMPTE 259M compliant
■Supports DVB-ASI at 270 Mbps
■Multi standard operation fro m 14 3 Mbps to 360 Mbps
■Cable length indicator for SD-SDI data rates
■Maximum cable length adju s tment for SD-SDI data rates
■Carrier detect and mute functionality for SD-SDI data rates
■Equalizer bypass mode
■Seamless connection with HOTLink II™ family and HOTLink®
receiver
■Equalizes up to 350m of Canare L-5C FB and Belden 1694A
coaxial cable at 270 Mbps
■Low power 160 mW at 3.3V
■Single 3.3V supply
■16-pin SOIC
■0.18 μm CMOS technology
■Pb-free and RoHS compliant
■Uses Cypress CLEANLink™ technology
■Pin compatible to existing equalizer devices
Functional Description
The CYV270M0101EQ is an adaptive video cable equalizer
designed to equalize and restore signals received over 75Ω
coaxial cable. The equalizer meets SMPTE 259M data rates and
is optimized for performance at 270 Mbps. The
CYV270M0101EQ is optimized to equalize up to 350m of
Canare L-5CFB and Belde n 1694A coaxial cable at 270 Mbps.
The CYV270M0101EQ connects seamlessly to the HOTLink II
family of transceivers and HOTLink receivers.
The CYV270M0101EQ has DC restoration for compensation of
the DC content of the SMPTE pathological patterns. A cable
length indicator (CLI) provides an indication of the cable leng th
equalized at SD-SDI data rates. The maximum cable length
adjust (MCLADJ) sets the approximate maximum cable length to
equalize. The CYV270M0101EQ differential serial outputs
(SDO, SDO) mute when the approximate cable length set by
MCLADJ is reached. CD/MUTE is a bidirectional pin that
provides an indication of the signal present at the equalizer
inputs. It also controls muting the outputs of the equalizer.
Power consumption is typically 160 mW at 3.3V.
Serial Links
Copper Cable
CYV270M0101EQ
Connections
Equalizer System Connection Diagram
Cable
Driver
HOTLink II
Serializer
HOTLink II
Deserializer
Adaptive
Cable
Equalizer
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CYV270M0101EQ
Document Number: 001-06830 Rev. *B Page 2 of 10
Pinouts
Figure 1. Pin Diagram - 16 Pin SOIC (Top View)
Equalizer Block Diagram
CYV270M 0101 EQ Adaptive Video Cable Equalizer Block Diagram
CYV 27 0M010 1 E Q A da p tive Vide o C ab le E qua lize r Bloc k D iag ram
Differential Output
Cable Len gth An alog
Adjustor an d Mute
Threshold Bloc k
Carrier Detect an d
Mute Contro l B lo ck
DC Restore
Equalizer
MUTE
BYPASS
SDO, SDO
SDI, S D I
MCLADJ CD
2
3
4
5
6
7
8
15
14
13
12
11
10
9
16
CYV270M0101EQ
VCC
GND
SDO
SDO
GND
MCLADJ
BYPASS
CD/MUTE
VCC
GND
SDI
SDI
GND
AGC+
AGC-
CLI
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CYV270M0101EQ
Document Number: 001-06830 Rev. *B Page 3 of 10
Table 1. Pin Descriptions - CYV270M0101EQ Single Channel Cable Equalizer
Name IO Characteristics Signal Description
Control Signals
CLI Analog Output Cable Length Indicator. CLI provides an analog voltage proportional to the equalized
cable length.
CD/MUTE LVTTL IO Carrier Detect/Mute Indicator.
Output:
When the incoming d ata stream is present and the cable length does not exceed that set
by MCLADJ, the CD/MUTE outputs a voltage less than 0.8V.
When the incoming data stream is not present or the cable length exceeds that set by
MCLADJ, the CD/MUTE outputs a voltage greater than 2.8V.
Input:
When the CD/MUTE pin is set LOW, the equalizer’s differential serial outputs are not muted.
When the CD/MUTE pin is set HIGH, the equalizer’s differential serial outputs are muted.
MCLADJ Analog Input Maximum Cable Length Adjust. The maximum equalized cable length is set by the
voltage applied to the MCLADJ input. When the maximum cable length se t by MCLADJ is
reached, CD is driven high and the differential output is muted.
If MCLADJ functionality is not needed, this pin should be l eft floating or tied to ground to
allow maximum equaliz ed cable length.
BYPASS LVTTL Input Equalizer Bypass. When BYPASS is set HIGH, the signal presented at the equalizer’s
differential serial inputs (SDI, SDI) is routed to the equalizer’s differential serial outputs
(SDO, SDO) without equalizing.
When BYPASS is set LOW, the incoming video data stream is equalized and presented at
the equalizer‘s serial differential outputs (SDO, SDO).
In equalizer bypass mode, CD/MUTE is not functional.
AGC± Analog Automatic Gain Control. Place a capacitor of 1 μF between the AGC± pins.
SDO, SDO Differential
Output Differential Serial Outputs. The equalized serial video data stream is presented at the
SDO/SDO differential serial CML output.
SDI, SDI Differential
Input Differential Serial Input s. SDI/SDI accepts either a single-ended or differential serial video
data stream over 75Ω coaxial cable.
Power
VCC Power +3.3V Power.
GND Gnd Connect to Ground.
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CYV270M0101EQ
Document Number: 001-06830 Rev. *B Page 4 of 10
Equalizer Operation
The CYV270M0101EQ is an adaptive video cable equalizer
designed to equalize standard definition (SD) serial digital
interface (SDI) video data streams. The CYV270M0101EQ
equalizer is optimized to equalize up to 350m of Canare L-5CFB
and Belden 1694A cable at 270 Mbps. The device contains one
power supply and typically consumes 160 mW power at 3.3V.
The adaptive equalizer meets the SMPTE 259M and DVB-ASI
video standards. It meets all pathological requirements for
SMPTE 259M as defined by RP178. The CYV270M0101EQ
Video Cable Equalizer is auto adaptive from 143 Mbps to 360
Mbps.
The CYV270M0101EQ equalizer has variable gain and multiple
equalization stages that reverse the effects of the cable. This
equalization is achieved by separate regulation of the lower and
higher frequency components in the signal to give a clean output
eye diagram. The CYV270M0101EQ has DC restoration to
compensate the DC content of the SMPTE pathological patterns.
SDI, SDI
The CYV270M0101EQ accepts single-ended or differential
serial video data streams over 75Ω coaxial cable. It is recom-
mended to AC couple the SDI and SDI inputs as they are inte r-
nally biased to 1.2V.
SDO, SDO
The CYV270M0101EQ has differential serial output interface
drivers that use current mode logic [CML] drivers to provide
source matching for the transmission line. These outputs are
either AC coupled or DC coupled to the HOTLink II SerDes
device.
CLI
Cable Length Indicator (CLI) is an analog output that gives an
output voltage proportional to the equalized cable length. CLI
gives an approximation of the length of cable at the differential
serial inputs (SDI, SDI). CLI works at standard definition (SD)
data rates. The graph in Figure 3 on page 7 illustrates the CLI
output voltage at various Belden 1694A cable lengths. With an
increase in cable length, CLI output voltage decreases.
MCLADJ
Maximum Cable Length Adjust (MCLADJ) sets the approximate
maximum amount of cable to be equalized.
If the MCLADJ voltage is greater than the CLI output voltage, CD
is driven high and the equalizer serial differential outputs (SDO,
SDO) are muted. If the MCLADJ voltage is less than CLI voltage,
then the equalizer’s differential serial outputs (SDO, SDO) are
not muted and the incoming data stream is equalized. The graph
in Figure 2 on page 7 illustrates the voltage required at MCLADJ
input to equalize various Belden 1694A cable lengths for SD data
rates. If MCLADJ functionality is not required, this pin should be
left floating or tied to ground to allow maximum equalized cable
length.
CD/MUTE
Carrier Detect/MUTE (CD/MUTE) is a bidirectional pin that
provides an indication of the signal present at the equalizer’s
input, or it controls the muting of the equalizer’s output.
If CD/MUTE is used as an output and the incoming data stream
is not present or the cable length exceeds th at set by MCLADJ,
the voltage at the CD/MUTE output is greater than 2.8V. If
CD/MUTE is used as an output, the incoming data stream is
present and the cable length does not exceed that set by
MCLADJ, then the voltage at the CD/MUTE outpu t is less than
0.8V.
If CD/MUTE is used as an input, and set LOW, the equalizer
serial outputs are not muted. If the CD/MUTE is used as an input
and is set HIGH, then the equalizer serial outputs are muted.
When an invalid signal or a signal transmitted with a launch
amplitude of less than 500 mV at SD data rates is received, the
equalizer’s serial outputs are muted and the MCLADJ setting is
overwritten.
BYPASS
The CYV270M0101EQ has a bypass mode that allows the user
to bypass the equalizer’s equalization and DC restoration
functions. When the Bypass mode is tied to VCC, the signal
presented at the equalizer ’s differential serial inputs (SDI, SDI)
is routed to the equalizer’s differential serial outputs (SDO, SDO)
without performing equalization.
When BYPASS is tied to GND, the incoming video data stream
is equalized and presented at the equalizer‘s differential serial
outputs (SDO, SDO).
In equalizer bypass mode, CD/MUTE is not functional.
AGC
Place a capacitor of 1 μF between the AGC± pins of the
CYV270M0101EQ equalizer.
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CYV270M0101EQ
Document Number: 001-06830 Rev. *B Page 5 of 10
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage Temperature.................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............ ................................ –55°C to +125°C
Supply Voltage to Ground Potential................–0.5V to +3.8V
DC Voltage Applied to Outputs
in High Z State....... ... .. ................. ... ... ....–0.5V to VCC + 0.5V
DC Input Voltage ........ ... ................. ... ... ...–0.5V to V CC+0.5V
Electro Static Discharge (ESD) HBM.......................> 2000 V
(JEDEC EIA/JESD-A114A)
Latch Up Current.............. ... ................. ................. .> 200 mA
Power Up Requirements
The CYV270M0101EQ contains one power supply. Th e voltage
on any input or IO pin must not exceed the power pin during
power up.
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C +3.3V ±5%
Notes
1. Production test.
2. Calculated results from production test.
3. Not tested. Based on characterization .
DC Electrical Characteristics
Parameter Description Test Conditions Min Typ Max Unit
VCC Supply Voltage[1] –3.135 3.3 3.465 V
PDPower Consumption[2] –125 160 190 mW
ISSupply Current[1] –38 48 60 mA
VCMOUT Output Common Mode Voltage[1] Load = 50Ω– VCC – ΔVSDO/2
= 2.9 – V
VCMIN Input Common Mode Voltage[1]
(Bypass = High) – 1 1.4 V
Input Common Mode Voltage[1]
(Bypass = Low) – 0 2.9 V
–CLI DC Vo ltage (0m)[1] –2.2 2.65 2.95 V
–CLI DC Vo ltage (No Signal) [1] –1.5 1.9 2.3 V
–Floating MCLADJ DC Voltage[1] –1.3 V
–MCLADJ Range[3] –0.4 0.72 1.02 V
VCD/MUTE(OH) CD/MUTE Output Voltage[1] Carrier Not Present 2.8 – – V
VCD/MUTE(OL) Carrier Present – – 0.8 V
VCD/MUTE CD/MUTE Input Voltage Required to
Force Outputs to Mute[1] Min to Mute 2.5 – – V
VCD/MUTE CD/MUTE Input Voltage Required to
Force Active[1] Max to Activate – – 1 V
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CYV270M0101EQ
Document Number: 001-06830 Rev. *B Page 6 of 10
AC Electrical Characteristics
Parameter Description Test Conditions Min Typ Max Unit
–Serial Input Data Rate[1] –143 –360 Mbps
VSDI Input Voltage Swing Single-ended, at the transmitter ,
SD data rate 500[5] 1200 mV
ΔVSDO Output Voltage Swing[1] Differentialp-p, 50Ω load 450 700 950 mV
–Output Jitter for Various Cable
Lengths and Data Rates 270 Mbps
Belden 1694A: 0-350m
Canare L-5CFB: 0-350m
800 mV transmit amplitude
Equalizer pathological pattern
–0.2[1] –UI
–Output Rise/Fall Time[3, 4] 20% - 80% 80 120 350 ps
–Mismatch in Rise/Fall T ime[3, 4] – – – 30 ps
–Duty Cycle Distortion[3, 4] SD Color Bar Pattern –0.03 –UI
–Overshoot[3, 4] – – – 10 %
–Input Return Loss[3, 4] –-15 – – dB
–Input Resistance[3] Single-ended –2.5 – kΩ
–Input Capacitance[3] Single-ended – 1 – pF
–Output Resistance[3] Single-ended –50 –Ω
Notes
4. Not tested. Guarant eed by design simulations.
5. Based on characterization across temperature and voltage with 350m of Belden 1694A cable, transmitting SMPTE Equalizer Pathological Test Pattern.
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CYV270M0101EQ
Document Number: 001-06830 Rev. *B Page 7 of 10
Typical Performance Graphs
(Unless otherwise stated, VCC = 3.3V, TA = 25°C)
Figure 2. MCLADJ Input Voltage vs. Belden 1694A Cable Length at SD-SDI Data Rate
Figure 3. CLI Output Voltage vs. Belden 1694A Cable Length at SD-SDI Data Rate
CABLE LENGTH (m )
VOLTAGE (V)
1.7
1.8
1.9
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
0 50 100 150 200 250 300 350
CABLE LENGT H (m)
VOLTAGE (V)
1.7
1.8
1.9
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
0 50 100 150 200 250 300 350
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CYV270M0101EQ
Document Number: 001-06830 Rev. *B Page 8 of 10
Typical Application Circuit
Figure 4. Interfacing CYV270M0101EQ to the HOTLink II SerDes
CLI
1
VCC
2
VEE
3
SDI
4
SDI
5
VEE
6
AGC+
7
AGC
−
8
BYPASS
9
MCLADJ
10
VEE
11
SDO
12
SDO
13
VEE
14
VCC
15
16
CYV270M0101EQ
+3.3V
+3.3V
0.01 μF0. 01 μF
+1 μF
RXLE
SDASEL
LPEN
INSEL
IN1+
IN1
−
FRAMCHAR
RFEN
RFMODE
DECMODE
RXCKSEL
RXMODE
RXRATE
RXCLKC+
RXCLK
−
RXCLK+
RXST0
RXST1
RXST2
RXOP
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
LFI
CYV15G0101DXB
BNC JACK
6.4 n H
1 μF
C10
C11
C12
C15
C16
R15 R14
R16
L2
75Ω
Z0
Z0
2 Z0
R18
C L I
75 Ω
75 Ω
37.4 Ω
C D / M U T E
M C L A D J
CD/MUTE
1 μF
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CYV270M0101EQ
Document Number: 001-06830 Rev. *B Page 9 of 10
Ordering Information
Ordering Code Package Name Package Type Operating
Range
CYV270M0101EQ-SXC SZ16.15 Pb-Free 16-Pin 150 Mil SOIC 0 to 70°C
Package Dimensions Figur e 5. 16-Pin (150 Mil) SOIC S16.15
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Document Number: 001-06830 Rev. *B Revised October 25, 2007 Page 10 of 10
PSoC Designer™, Programmable System-on-Chip™, an d PS oC Exp re ss™ are tra demarks a nd PSo C® is a registe red t rade mark of Cypress S emi conductor Corp. All o the r tr a dem a rks o r re gi ster e d
trademar ks refere nced herei n are prop erty of the respe ctive corp orations. Purchas e of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the
Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard S pecification as defined by Philips. HOTLink is a registered trademark and
HOTLink II is a trademark of Cypress Semiconductor. All other trademarks or registered trademarks referenced herein are property of the respective corporations. All products and company names
mentioned in this document may be the trademarks of their respective holders.
CYV270M0101EQ
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products a re not warranted no r intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Further more, Cypr ess does not author ize its produc ts for use as critic al
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protectio n (United States and fore ign),
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and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee pr oduct to be used only in conjunction with a Cyp ress
integrated circui t as specified in the applicab le agreement. Any r eproduction, mod ification, translati on, compilatio n, or represent ation of this Sour ce Code except a s specified abo ve is prohibit ed without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described h erein. Cypres s does not
assume any liabil ity ar ising ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypress d oes not a uthor ize its p roducts fo r use as critical componen ts in life-su pport systems whe re
a malfuncti on or failure may reason ably be expected to res ult in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document History Page
Document Title: CYV270M0101EQ Adaptive Video Cable Equalizer
Document Number: 001-06830
Rev. Ecn No. Issue
Date Orig. Of
Change Description Of Change
** 427547 SEE ECN BCD New preliminary datasheet
*A 663916 SEE ECN FRE Updated AC and DC parameters. Changed datasheet status from
preliminary to final
*B 1396423 SEE ECN UKK/AESA Updated AC and DC electrical characteristics and pin description of
CD/MUTE and MCLADJ
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