PC745B and PC755B PowerPC microprocessors are high-performance, low-power, 32 -bit implementations of the
PowerPC Reduced Instruction Set Computer (RISC) architecture, specially enhanced for embedded applications. The
PC755B and PC745B microprocessors differ only in that the PC755B features an enhanced, dedicated L2-cache
interface with on-chip L2 -tags. Both are software compatible with the PowerPC603e microprocessor family and the
PC745B is pin-compatible as well. Both PC745B and PC755B are fully JTAG compliant.
PC745B and PC755B Main Features
nSix independent execution units
-2 Integer Units sharing 32 General Purpose Registers
-Floating Point Unit using a 32-entry FPR file
-Branch Processing Unit : 4 instructions fetched per clock
-Load/Store Unit
-System Register Unit
nCache and MMU support
-32-Kbytes, physically addressed, Instruction and Data caches
-8-way set associative Instruction and Data caches
-Dedicated L2-cache with on-chip L2 tags (PC755B only)
-Separate Instruction and Data MMUs
-Virtual memory support up to 4 Petabytes (252)
-Real memory support up to 4 Gigabytes (232)
-128-entry instruction and data TLBs
PC745B/PC755BFS -Rev.1 –01/11
PC745B AND PC755B PowerPCTM Microprocessors
Fact Sheet
Completion
Unit Dispatch
Unit
Branch
Unit
Integer
Unit
Gen
Reg
File
Load/
Store
Unit
I MMU
D MMU
Data Cache Inst. Cache
Bus Interface Unit
System Bus
32bit
Address
Gen
Re-
name
32/64bit
Data
Floating
Point
Unit
FPU
Reg
File
L2 Data Bus
L2 Cache
Port (755 only)
L2
tags
BP123 -38521 Saint-Egrève Cedex -France -Tel: +33 (0)4 76 58 30 00 -Fax: +33 (0)4 76 58 34 80
•Bus Interface
-Compatible with 60x processor interface
-32-bit address bus
-64-bit data bus, 32-bit mode selectable
-13 Bus-to-Core frequency multipliers
-Selectable interface voltages
•Power Management
-Low-power design
-Selectable 1.8V/2.0V interface voltage
-3 static power saving modes : doze, nap and sleep
-Dynamic power management
-Integrated thermal management unit
•Packaging
-255 Flip-Chip PBGA (PC745B)
-360 Flip-Chip PBGA (PC755B)
-255 and 360 CBGA available upon request
•Screening
-FC-PBGA upscreeningbased upon
ATMEL-Grenoble standards
-Full Military temperature range (Tj= -55°C, + 125°C)
-Industrial temperature range (Tj= -40°C, +110°C)
For additional information:
contact your local ATMEL-Grenoble representative
or visit our web site at http://www.atmel-grenoble.com
You may also contact the PowerPC technical hotline at std.hotline@atmel-grenoble.com
The PowerPC and PowerPC603e names and the PowerPC logotype are trademarks of
International Business Machines Corporation, used under license therefrom.
CPU
Summary
PC745B
300 - 350 MHz PC755B
300 - 400 MHz
Die Revision 2.7 = D 2.7 = D
300 MHz 300 MHz
350 MHz 350 MHz
CPU Speeds -
Internal 400 MHz
CPU Bus Dividers 2x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x,
6x, 6.5x, 7x, 7.5x, 8x, 10x 2x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x,
6x, 6.5x, 7x, 7.5x, 8x, 10x
Bus Interface 32-bit address, 32/64-bit data 32-bit address, 32/64-bit data
Instructions per
Clock 3 (2+Branch) 3 (2+Branch)
L1 Cache 32-KB Instruction and Data 32-KB Instruction and Data
L2 Cache -256KB, 512KB, 1MB
Core-to-L2
Frequency Divisions -1:1, 1.5:1, 2:1, 2.5:1, 3:1
Typ/Max Power
Dissipation 4.0W/5.7W @ 350 MHz 4.4W/6.4W @ 400 MHz
Die Size 51 mm251 mm2
255-pin Flip-Chip PBGA 360-pin Flip-Chip PBGA
Package Ceramic Package if
Identifications Ceramic Package if
Identifications
Process 0.22µ CMOS, 5LM 0.22µ CMOS, 5LM
1.8/2.0 or 3.3V I/O 1.8/2.0 or 3.3V I/OVoltage 2.0V internal 2.0V internal
SPECint95
(estimated) 15.7 @ 350 MHz 18.1 @ 400MHz
SPECfp95
(estimated) 11.6 @ 350 MHz 12.3 @ 400MHz
Other Performance 641 MIPS @ 350 MHz 733 MIPS @ 400MHz
Status Active Active
Samples Now Now
Production Now Now
Integer (2) Integer (2)
Floating Point Unit Floating Point Unit
Branch Unit Branch Unit
Load/Store Unit Load/Store Unit
Execution Units
System Register System Register
Screening level:
U: UpscreeningTest
PC755B ZF U300 x
Type
(PCX755B if prototype)
M
Temperature range : Tj
M: -55, +125°C
V: -40, +110°C
Package:
ZF: FC-PBGA
Bus divider
(to be confirmed)
L: Any valid PLL configuration
Revision level
Max internal processor speed
300: 300 MHz
350: 350 MHz
400: 400 MHz, TBC
L
D: Rev. 2.7
E: Rev 2.8
