1
IPB017N10N5LF
Rev.2.1,2017-02-16Final Data Sheet
1
7
tab
D²-PAK7pin
Drain
Pin 4, tab
Gate
Pin 1
Source
Pin 2,3,5,6,7
MOSFET
OptiMOSTM5LinearFET,100V
Features
•Idealforhot-swapande-fuseapplications
•Verylowon-resistanceRDS(on)
•WidesafeoperatingareaSOA
•N-channel,normallevel
•100%avalanchetested
•Pb-freeplating;RoHScompliant
•QualifiedaccordingtoJEDEC1)fortargetapplications
•Halogen-freeaccordingtoIEC61249-2-21
Table1KeyPerformanceParameters
Parameter Value Unit
VDS 100 V
RDS(on),max 1.7 mΩ
ID(siliconlimited) 314 A
ID(packagelimited) 180 A
Ipulse(VDS=56V,tp=10
ms) 10.2 A
Type/OrderingCode Package Marking RelatedLinks
IPB017N10N5LF PG-TO 263-7 017N10LF -
1) J-STD20 and JESD22
2
OptiMOSTM5LinearFET,100V
IPB017N10N5LF
Rev.2.1,2017-02-16Final Data Sheet
TableofContents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
OptiMOSTM5LinearFET,100V
IPB017N10N5LF
Rev.2.1,2017-02-16Final Data Sheet
1Maximumratings
atTA=25°C,unlessotherwisespecified
Table2Maximumratings
Values
Min. Typ. Max.
Parameter Symbol Unit Note/TestCondition
Continuous drain current ID
-
-
-
-
-
-
180
180
31
A
VGS=10V,TC=25°C
VGS=10V,TC=100°C
VGS=10V,TC=25°C,RthJA=40K/W1)
Pulsed drain current2) ID,pulse - - 720 A TC=25°C
Avalanche energy, single pulse3) EAS - - 979 mJ ID=100A,RGS=25Ω
Gate source voltage VGS -20 - 20 V -
Power dissipation Ptot - - 313 W TC=25°C
Operating and storage temperature Tj,Tstg -55 - 150 °C IEC climatic category;
DIN IEC 68-1: 55/150/56
2Thermalcharacteristics
Table3Thermalcharacteristics
Values
Min. Typ. Max.
Parameter Symbol Unit Note/TestCondition
Thermal resistance, junction - case RthJC - 0.25 0.4 K/W -
Device on PCB,
minimal footprint RthJA - - 62 K/W -
Device on PCB,
6 cm² cooling area1) RthJA - - 40 K/W -
1) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
2) See Diagram 3 for more detailed information
3) See Diagram 13 for more detailed information
4
OptiMOSTM5LinearFET,100V
IPB017N10N5LF
Rev.2.1,2017-02-16Final Data Sheet
3Electricalcharacteristics
Table4Staticcharacteristics
Values
Min. Typ. Max.
Parameter Symbol Unit Note/TestCondition
Drain-source breakdown voltage V(BR)DSS 100 - - V VGS=0V,ID=1mA
Gate threshold voltage VGS(th) 2.5 3.3 4.1 V VDS=VGS,ID=270µA
Zero gate voltage drain current IDSS -
-
1
10
10
100 µA VDS=100V,VGS=0V,Tj=25°C
VDS=100V,VGS=0V,Tj=125°C
Gate-source leakage current IGSS -
-
2
-2
5
-5 µA VGS=20V,VDS=0V
VGS=-10V,VDS=0V
Drain-source on-state resistance RDS(on) - 1.5 1.7 mΩVGS=10V,ID=100A
Gate resistance1) RG- 44 66 Ω-
Transconductance gfs 32 63 - S |VDS|>2|ID|RDS(on)max,ID=100A
Table5Dynamiccharacteristics1)
Values
Min. Typ. Max.
Parameter Symbol Unit Note/TestCondition
Input capacitance Ciss - 650 840 pF VGS=0V,VDS=50V,f=1MHz
Output capacitance Coss - 1900 2500 pF VGS=0V,VDS=50V,f=1MHz
Reverse transfer capacitance Crss - 25 - pF VGS=0V,VDS=50V,f=1MHz
Turn-on delay time td(on) - 7 - ns VDD=50V,VGS=10V,ID=50A,
RG,ext=1.7Ω
Rise time tr- 28 - ns VDD=50V,VGS=10V,ID=50A,
RG,ext=1.7Ω
Turn-off delay time td(off) - 128 - ns VDD=50V,VGS=10V,ID=50A,
RG,ext=1.7Ω
Fall time tf- 82 - ns VDD=50V,VGS=10V,ID=50A,
RG,ext=1.7Ω
Table6Gatechargecharacteristics2)
Values
Min. Typ. Max.
Parameter Symbol Unit Note/TestCondition
Gate to source charge Qgs - 4.4 - nC VDD=50V,ID=180A,VGS=0to10V
Gate to drain charge1) Qgd - 141 - nC VDD=50V,ID=180A,VGS=0to10V
Gate charge total1) Qg- 195 - nC VDD=50V,ID=180A,VGS=0to10V
Gate plateau voltage Vplateau - 7.1 - V VDD=50V,ID=180A,VGS=0to10V
Output charge1) Qoss - 209 - nC VDD=50V,VGS=0V
1) Defined by design. Not subject to production test.
2) See ″Gate charge waveforms″ for parameter definition
5
OptiMOSTM5LinearFET,100V
IPB017N10N5LF
Rev.2.1,2017-02-16Final Data Sheet
Table7Reversediode
Values
Min. Typ. Max.
Parameter Symbol Unit Note/TestCondition
Diode continuous forward current IS- - 180 A TC=25°C
Diode pulse current IS,pulse - - 720 A TC=25°C
Diode forward voltage VSD - 0.86 1.2 V VGS=0V,IF=100A,Tj=25°C
Reverse recovery time1) trr - 62 - ns VR=50V,IF=50A,diF/dt=100A/µs
Reverse recovery charge1) Qrr - 113 - nC VR=50V,IF=50A,diF/dt=100A/µs
1) Defined by design. Not subject to production test.
6
OptiMOSTM5LinearFET,100V
IPB017N10N5LF
Rev.2.1,2017-02-16Final Data Sheet
4Electricalcharacteristicsdiagrams
Diagram1:Powerdissipation
TC[°C]
Ptot[W]
0 25 50 75 100 125 150 175
0
50
100
150
200
250
300
350
Ptot=f(TC)
Diagram2:Draincurrent
TC[°C]
ID[A]
0 25 50 75 100 125 150 175
0
40
80
120
160
200
240
280
320
360
limited by package
limited by silicon
ID=f(TC);VGS≥10V
Diagram3:Safeoperatingarea
VDS[V]
ID[A]
10-1 100101102103
100
101
102
103
1 µs
10 µs
100 µs
1 ms
10 ms
DC
ID=f(VDS);TC=25°C;D=0;parameter:tp
Diagram4:Max.transientthermalimpedance
tp[s]
ZthJC[K/W]
10-6 10-5 10-4 10-3 10-2 10-1 100
10-3
10-2
10-1
100
0.5
0.2
0.1
0.05
0.02
0.01
single pulse
ZthJC=f(tp);parameter:D=tp/T
7
OptiMOSTM5LinearFET,100V
IPB017N10N5LF
Rev.2.1,2017-02-16Final Data Sheet
Diagram5:Typ.outputcharacteristics
VDS[V]
ID[A]
012345
0
20
40
60
80
100
120
8 V
10 V
6 V
5.5 V
5 V
4.5 V
ID=f(VDS);Tj=25°C,tp=30µs;parameter:VGS
Diagram6:Typ.drain-sourceonresistance
ID[A]
RDS(on)[mΩ]
0 20 40 60 80 100 120
0.0
0.5
1.0
1.5
2.0
8 V
10 V
RDS(on)=f(ID);Tj=25°C;parameter:VGS
Diagram7:Typ.transfercharacteristics
VGS[V]
ID[A]
01234567
0
20
40
60
80
100
120
150 °C
25 °C
ID=f(VGS);VDS=10V;parameter:Tj
Diagram8:Typ.forwardtransconductance
ID[A]
gfs[S]
0 20 40 60 80 100 120
0
10
20
30
40
50
60
70
80
gfs=f(ID);Tj=25°C
8
OptiMOSTM5LinearFET,100V
IPB017N10N5LF
Rev.2.1,2017-02-16Final Data Sheet
Diagram9:Normalizeddrain-sourceon-stateresistance
Tj[°C]
RDS(on),normalizedto25°C
-80 -40 0 40 80 120 160
0.0
0.4
0.8
1.2
1.6
2.0
RDS(on)=f(Tj),ID=100A,VGS=10V
Diagram10:Typ.gatethresholdvoltage
Tj[°C]
VGS(th)[V]
-60 -20 20 60 100 140 180
0
1
2
3
4
2700 µA
270 µA
VGS(th)=f(Tj);VGS=VDS
Diagram11:Typ.capacitances
VDS[V]
C[pF]
0 20 40 60 80 100
101
102
103
104
Coss
Ciss
Crss
C=f(VDS);VGS=0V;f=1MHz
Diagram12:Forwardcharacteristicsofreversediode
VSD[V]
IF[A]
0.0 0.5 1.0 1.5 2.0 2.5
100
101
102
103
25 °C
25 °C, max
150 °C
150 °C, max
IF=f(VSD);parameter:Tj
9
OptiMOSTM5LinearFET,100V
IPB017N10N5LF
Rev.2.1,2017-02-16Final Data Sheet
Diagram13:Avalanchecharacteristics
tAV[µs]
IAV[A]
100101102103
100
101
102
103
25 °C
100 °C
125 °C
IAS=f(tAV);RGS=25Ω;parameter:Tj(start)
Diagram14:Typ.gatecharge
Qgate[nC]
VGS[V]
0 50 100 150 200 250
0
2
4
6
8
10
12
50 V
80 V
20 V
VGS=f(Qgate);ID=180Apulsed,resistiveload;parameter:VDD
Diagram15:Drain-sourcebreakdownvoltage
Tj[°C]
VBR(DSS)[V]
-60 -20 20 60 100 140 180
95
100
105
110
VBR(DSS)=f(Tj);ID=1mA
Gate charge waveforms
10
OptiMOSTM5LinearFET,100V
IPB017N10N5LF
Rev.2.1,2017-02-16Final Data Sheet
5PackageOutlines
Figure1OutlinePG-TO263-7,dimensionsinmm/inches
11
OptiMOSTM5LinearFET,100V
IPB017N10N5LF
Rev.2.1,2017-02-16Final Data Sheet
RevisionHistory
IPB017N10N5LF
Revision:2017-02-16,Rev.2.1
Previous Revision
Revision Date Subjects (major changes since last revision)
2.0 2016-12-15 Release of final version
2.1 2017-02-16 Update technology heading
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TrademarksupdatedAugust2015
OtherTrademarks
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