W25Z040A Cj) fll Winbond s Electronics Carp. 128K x 36 PIPELINED ZWS SRAM GENERAL DESCRIPTION The W257040A is a high-speed, low-power, Zero-Wait-State (7WS) Synchronous Pipelined CMOS Static RAM organized as 131,072 x 36 bits. A built-in two-bit burst address counter supports both Linear and Interleaved burst mode. The mode to be executed is controlled by the LBO pin. A snooze mode can reduce the power dissipation. The ZWS SRAM is optimized for 100 percent bus utilization by eliminating wait states when transitioning from read to write, or vice versa. All addresses, data inputs, clock enable (CLKE), write enable (WE ), byte-write enables (BW [4:1]) and chip enables (CE1, CE2 and CE3 for easy depth expansion) are synchronously sampled with by a positive-edge-triggered clock (CLK). Asynchronous inputs include the output enable (OE ), clock (CLK) and snooze (ZZ). To provide 100 percent use of the data bus, the pipelined ZWS SRAM uses the two-stage write address registers. For example, when the address and control signals are applied to the SRAM in clock cycle one, the data associated with the address occurs two cycles later, or the clack cycle three. The W25Z040A operates on a single 3.3V power supply, with all inouts and outputs compatible with the LVTTL interface. Based on the bus efficiency, the device is ideal for high bandwidth application systems. FEATURES Synchronous operation Asynchronous output enable High-speed access time: 3.8/4.2/4.5/5 nS Zero wait states between read/write cycles Single +3.3V power supply Supports snooze mode (low-power state) * Individual byte write capability Internal burst counter supports Interleaved 3.3V LVTTL compatible I/O burst mode & linear burst mode * Clock-controlled and registered input Packaged in 100-pin TQFP BLOCK DIAGRAM AO Po K ey Wiite K eH Write ANB Add _ Data Data Re A Reg Reg pat 4 Fs #0 Kt AO, Al Mux Burst LBO Counter |? me ~ 128K X 38 Mux | Output , Output wr . . Core Cell ~ | Reg Butier ew V/O[36: 1] Write 1 Write _ _ Lge) Ait pe) Add ~ - Reg Reg i GLK K ADVWLD, WE, BW[4:1] te _ Read/Write Gontrol CLKE }-_ Kt 4 cet < } GES K Publication Release Date: April 1999 -_]- Revision A24 fetthey, Ps WV y cP EES, imbond Electronics Corp. W25Z040A SRR TITIES PIN CONFIGURATION vois LI yoro [TI vo21 [J voD@ [I vsso L__] yore? [I yoe3 [| voe4 vores vsso CO] vong [| yore J yo27 __y FT L__] vob [7] voDp C4 vss [__] vores voe9 vopg SSQ L__] vos0 [| vos [7] yose [| O33 (| ysso [| vope L_] yo34 [J voss [J yose [7] eonan hon =\ Naa 13 14 15 16 ooo Om oo I oo +ma7 so J mo oof *sEo~ aef go> sof so~ aof]-ga> hoo amoa =o oo oo co on ACO 100-pin TQFP MO-136 oof ms a mArC oO oo fj] mo~ aap ]ore<0> aaPoz eafnoz nap] o> of o> oo a 77 76 75 74 73 #2 7 70 69 68 G7 66 65 64 63 62 6 59 58 o7 56 55 54 53 52 51 a J vars 7 van? ens |; DDG Pd) SSQ: vars Po) CH J vans verte |) SSQ 1] vopa Po) 1 eno 1 vss |) DD - 1 oD [1 zz [7 vo9 P 7) vos |; DDG fd) SSQ Po) OF P) vos [7 vos P voa [_] vssa [7] vope [1 vO3 [7 woe 7 01 our = t ap pNe > oo 09 o> Jae roe Lae +>] aprpl Ine <nal pow <mun LDL Jow aa<fL fof go<CL_j-F <HnD_Jra <nDD Jus cotpCL Jan +-+pL for yop fos op CNS Bop pos oa+p (Je a+, CL foamAthy @ Winbond SOR Electronics Corn, SIRES I SIDS IIIS IIIS II IIIS PIN DESCRIPTION W25Z040A SYMBOL TYPE DESCRIPTION A0-A16 Input, Synchronous Host Address (01-036 VO, Synchronous Data Inputs/Outputs CLK Input, Clock Processor Host Bus Clock CLKE Input, Synchronous Clock Enable CE1, CE2, CE3 | Input, Synchronous Chip Enables WE Input, Synchronous Write Enable from System Controller BW1-BW4 Input, Synchronous | Host Bus Byte Enables used with WE OE Input, Asynchronous | Output Enable Input ADV/LD Input, Synchronous Internal Burst Address Counter Advance(Sampled High} / Load External Address (Sampled Low) 22 Input, Asynchronous | Snooze Pin for Low-power State, internally pulled low FT Input, Static This pin should be connected to VDD or unconnected to meet the specification in pipelined mode operation. LBO Input, Static Lower Adcress Burst Order Gonnected to VSS: Device operates in linear mode. Connected to VDD or unconnected: Device is in non- linear mode. VDDQ (O Power Supply Vssa VO Ground VDD Power Supply Vss Ground RSV Reserved Pin, Don't Use These Pins NG No Connection Publication Release Date: April 1999 -3- Revision A2W25Z040A Winbond fetthey, SPIRIT, FUNCTIONAL DESCRIPTION Read Operation The address is registered on the rising edge of CLK and the associated output data will be valid atter two cycles later. Write Operation During the write operation, the input data follows the address by two cycles later. The new incoming address and data are transferred into a two-stage write buffer while the residing address which are received two write cycles earlier are used for actual write operation. Data stored in these two-stage write data registers are used for first two write cycles following the read or unselected cycle. A subsequent read which matches the address in either write butfer allows the corresponding butter data to be passed directly to output register. Truth Table CYCLE cartel zz | CEi | ce2 | CEs | CLKE|ADWLD| WE | BwWx | DATA | NOTES Unselected No 0 1 x x 0 0 x x Hi-Z Unselected No 0 X 0 Xx 0 0 Xx Xx Hi-Z Unselected No 0 Xx x 1 0 0 x x Hi-Z Begin Read External 0 0 1 0 0 0 1 x D-Out 3 Continue Read Next 0 X x Xx 0 1 Xx Xx D-Out 3 Begin Write External 0 0 1 0 0 0 0 0 D-In Begin Write None 0 0 1 0 0 0 0 1 Hi-Z 4 /NOP Continue Write Next 0 Xx x 0 1 x 0 D-In Continue Write Next 0 X x x 0 1 x 1 Hi-Z 4 /NOP Stall Current 0 X Xx Xx 1 X Xx Xx - 5 Snooze None 1 Xx x x x x x x Hi-Z Notes: 1. For a detailed definition of read/write, see the Write Table below. 2. An"X" means don't care, "1" means logic high, and "0" means logic low. 3. The OE pin enables the data output and is not sampled with the clock. All signals of the SRAM are sampled synchronously with the bus clock except for the OE pin. 4, NOP can be seen as No Operation. 5. If clack enable sampled high occurs during READ cycle, the bus will remain active (valid data). If clock enable sampled high occurs during WRITE cycle the bus will remain in high-2 state.W25Z040A Winbond Electronics Corn, SITIES IIIS IIS IPSS OI III IIS Write Table READ/WRITE FUNCTION WE Bw4 BW3 BWwe2 BW1 Read 1 xX X x x Write/NOP 0 1 1 1 1 Write byte 1 /O1-l/O9 0 1 1 1 0 Write byte 2 1/010-1/018 0 1 1 0 1 Write byte 2, byte 1 0 1 1 0 0 Write byte 3 1/019-l/O27 0 1 0 1 1 Write byte 3, byte 1 0 1 0 1 0 Write byte 3, byte 2 0 1 0 0 1 Write byte 3, byte 2, byte 1 0 1 0 0 0 Write byte 4 1/028-I/O36 0 0 1 1 1 Write byte 4, byte 1 0 0 1 1 0 Write byte 4, byte 2 0 0 1 0 1 Write byte 4, byte 2, byte 1 0 0 1 0 0 Write byte 4, byte 3 0 0 0 1 1 Write byte 4, byte 3, byte 1 0 0 0 1 0 Write byte 4, byte 3, byte 2 0 0 0 0 1 Write all bytes I/01-l/O36 0 0 0 0 0 Read-Write-Read Operation There is no wait state to be asserted for a read-write-read operation. i.e. there is no extra dead bus cycle for read-write or write-read recovering and the bus utilization is 100%. Publication Release Date: April 1999 -5- Revision A2an G Winbond NE Flectronics Corn. W25Z040A SRR TITIES ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNIT Core Supply Voltage to Vss -0.5 to 4.6 Vv QO Supply Voltage to Vss -0.510 4.6 V Input/Output te VSs@ Potential Vssq -0.5 to Vana +0.5 Vv Allowable Power Dissipation 1.5 WwW Storage Temperature -65 to 150 G Operating Temperature 0 to +70 C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. OPERATING CHARACTERISTICS (VDD/VDDO = 3.3V+ 5%, Vss/Vssa = OV, TA =0 to 70 Cc) PARAMETER SYM. TEST CONDITIONS MIN. | TYP. MAX. | UNIT Input Low Voltage VIL - -0.5 - +0.8 Vv Input High Voltage VIH - +2.0 - Vpb +0.3 V Input Leakage Current | ILI VIN = Vsse to VDDQ -1 - +1 LA Output Leakage ILo Vio = Vsso to Voba, and data -1 - +1 nA Current VO pins in high-Z state defined in truth table Output Low Voltage VOL loL = +8.0 mA - - 0.4 Vv Output High Voltage VoH | IOH =-4.0 mA 2.4 - - Vv Operating Current IDD All inputs 2 VIH or $ VIL, -3A - - 420 mA Teyc2 min., /O=0mA | -4 - - 370 mA -4A - - 330 mA 5 - - 300 mA Standby Current IsBi Device unselected, 7Z < VSS + 0.2, - - 10 mA All inputs < VSS + 0.2 or > VDD -0.2, and static /O =O mA, CLK frequency = 0 Standby Current IsB2 | Device unselected, - - 25 mA ZZ = VIL, All inputs = VIL or = VIH, O = 0 mA, GLK frequency = 0 77 Mode Current Izz ZZ > VIH, All inputs < VIL or > VIH, - - 10 mA /O=0 mA Note: Typical characteristics are measured at VDD = 3.3V, TA= 25 C. Publication Release Date: April 1999 Revision A2W25Z040A Athy G, Winbond CAPACITANCE (VDD = 3.3V, TA = 25 C, Freq. = 1 MHz) PARAMETER SYM. CONDITIONS MAX. UNIT Address Input Capacitance CADD VIN = OV 3.5 pF Clock & Control Input Capacitance CCLK VCLK = OV 4 pF Input/Output Capacitance Co Vio = OV 5 pF Note: These parameters are sampled but not 100% tested. AC TEST CONDITIONS PARAMETER CONDITIONS Input Pulse Levels OV to 3V Input Rise and Fall Times 1ns Input and Output Timing Reference Level 1.5V Output Load CL = 30 pF, IOH/IOL = -4 mMA/8 mA AC TEST LOADS AND WAVEFORM RL =50 ohm Ri 320 ohm VL = 1.5V 33V OUTPUT ? OUTPUT ) T 5 pF Be ohm Zo = 50 ohm 30 pF = Including = Including Jig and = Jig and Scope Scope (For Tkyz, Tez, Touz, ToLz, measurement) f 10% 10% ov a 1.0nS 1.0nSThE, Winbond ett AC TIMING CHARACTERISTICS (VDD/VDDQ = 3.3V+ 5%, Vss/Vsso = OV, TA = 0 to 70 C, all timings measured in pipelined mode) W25Z040A SOP I III III TTI, PARAMETER SYM. | W25Z040A W25Z040A W25Z040A W25Z040A UNIT | NOTES 3A -4 -4A -5 MIN. | MAX. | MIN. | MAX. | MIN. | MAX. | MIN. | MAX. Clock Cycle Time Teve 6.7 75 8.5 10.0 ns Clock High Pulse Width TKH 2.5 3.0 3.0 3.5 ns Clock Low Pulse Width TKL 2.5 3.0 3.0 3.5 ns Input Setup Time Ts 1.5 15 2.0 2.0 ns Input Hold Time TH 0.5 a5 0.5 0.5 ns Clock Access Time TKQ - 3.8 42 45 5.0 ns Output Hold from Clock High TKX 1.5 15 1.5 15 ns Clock High to Output Low-2 TKLZ 1.5 15 1.5 15 ns 1 Clock High to Output High-Z TKHZ - 3.0 3.5 3.5 3.5 ns 1 Output Enable to Output Valid TOE - 3.8 4.2 45 5.0 ns Output Enable to Output Low-Z Toz 0 0 0 0 ns 1 Output Disable to Output High-Z TOHZ - 3.0 3.5 3.5 3.5 ns 1 22 Standby Time Tzzs - 2 2 2 2 Cycle 22 Recover Time TzZR - 20 20 20 20 ns 4 Notes: 1. These parameters are sampled but not 100% tested. 2. In the ZZ mode, the SRAM will enter a low-power state. In this mode, data retention is guaranteed and the clock is active. 3. Configuration signals LBO and FT are static and should not be changed during operation. 4. Write cycle should not be given for at least 20 nS while the SRAM is transitioning out of ZZ made. Publication Release Date: April 1999 Revision A2W25Z040A Winbond fetthey, PIII ITT TIMING WAVEFORMS Read/Write Cycle Timing Read Read Write Write Read Write Read o& I\S\SI\P\ DV DVD, A A Ts |TH | ba al | ame A - A. Ts Tu | pat | A[16:0] N Xn N+2 ~T Ts | TH | | sat tye _ Wee Ts (TH io al BWI4:1] | E 7 BS a) T, Ta OE wo loz Tkx VO[36:1] Qn -i0-W25Z040A - Fs . , Binbond uk NctEEH 6 Flectronics Corn. _A ERED PPI II Timing Waveforms, continued Burst Read/Write Cycle Timing * WEED DDD ze = KX Ts! TH I | ToE | la | VO[36:1] = Qn ane YX Qn+2 Tow | | | 1 | m+1 Publication Release Date: April 1999 -il- Revision A2W25Z040A - Fs . , Binbond uk NctEEH 6 Flectronics Corn. _A ERED PPI II Timing Waveforms, continued Stall NOP and Unselect Cycle Timing 1 DID DPDDPDLDY BWI4:1] BS Ay ee ee enW25Z040A an G Winbond NE Flectronics Corn. SRR TITIES ORDERING INFORMATION PART NO. ACCESS | OPERATING| STANDBY PACKAGE TIME (nS) CURRENT | CURRENT MAX. (mA) | MAX. (mA) W252Z040AD-3A 3.8 420 25 100-pin TQFP W25Z040AD-4 4.2 3/0 25 100-pin TQFP W257040AD-4A4 45 330 25 100-pin TQFP W257040AD-5 5.0 300 25 100-pin TQFP Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. _]4-W25Z040A ett, & Winbond SEE Flentronics Corp. SRR TITIES PACKAGE DIMENSIONS 100-pin TQFP Dirnension in inches Dimension in mm Symbol Min. |Nom.| Max.| Min. |Nom.| Max A ]|/ f J {[ Ali 0.002) 0.004) 0.006] 0.05 | 0.10 | 0.15 Az 0.053 | 0.055 | 0.057 | 1035 )1.40 [145 b 0.009 |0.013 |0.015 | 022 |0.32 |038 c 0.004 |0.006 | 0.008] 0.10 |0.15 |o.20 D 0.547 0.551 | 0.555 |13.90 | 14.00 |14.10 E 0.769 | 0.787 | 0.781 |19.90 | 20.00 | 20.10 [al 0,020 [0.026 | 0.032 | 0.498) 0.65 | 0.802 Ho 0.626 | 0.630 | 0.634 115.90 | 16.00 | 16.10 He 0.862 | 0.866 | 0.870 | 21.90 | 22.00 | 22.10 L 0.018 | 0.024] 0.030 | 045 | 0.60 | 0.75 Li jooso] | ]r00] _ {0.083 | [0.08 9 o | }7" {oo | / 7 Notes 1. Dimensions D & E do not include interlead flash 2. Dimension b does not include dambar protrusionintrusion. 3. Controlling dimension: Millimeters os 4. General appearance spec. should be based on final visual inspection spec. \ See Det E Ay Seating Plane Publication Release Date: April 1999 -i5- Revision A2G Winbond VERSION HISTORY W25Z040A KEELES Flentronic rr + Electronics Corn, SIPS SII S IIIS IO SII III II OSI IIII SII SID IIIIOI SII III IIOSII IID DIISOIIIIIOPI IID IMI IIE SII INDIE ESIIIEDIII SID IIIIOR SII OIID IIE SII IID HIIIOIIIIIOWB SID OMIIIIESII SIP IIEESIISIDOIIIIPISIIOR ISIS OSIIIEESIISIN VERSION DATE PAGE DESCRIPTION Al Mar. 1998 Initial Issued A2 Apr. 1999 1, 4, 6,7, 9, 14 Change speed bin from 133 to 150 MHz Cancel packaged in 100-pin QFP 3 DC functional pins (LBO, FT ) connect to VSs or VDD 10~13 Marks the detail specifications in the waveforms aftn, (, Winbond MEK Electronics Corp. Meacdquartars No. 4.0 af Taipel Ohice hestion Fla ih Aiip Asem ainboria. cai VYoine & Fasg-onednand: aac. MiSs Winbond Electroanios (M80 Lig. Ry, BS ne Sig PRP SFOOS werig East 3id., Winbond Fhectronigs Nerth &imericg Oar. Winbond Memory Lab. Winbond Microslectronics Gorm, Winkord Systems Lats, BT2F HL Sarat Steaet, Sar dose, RAUL OER UUM UR EL EOL OSES REUSE LURE O RAE OS LER CAR AL ERESE LURE ARLES ARES SRELERESELL UREA ES RESELLERS URAL ELLER MELEE CLONAL EARLS, Sate Ad date and apatioatitons are sedbhent bo ata nae MATION Modine -16-