Page 1 of 15
Document No. 70-0245-05 │www. pse mi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
The PE 43 703 is a HaR P™-enhanced, high linearity, 7-bit RF
Digital Step Attenuator (DSA). This highly versatile DSA
covers a 31.75 dB attenuation range in 0.25 dB, 0.5 dB, or 1.0
dB steps. The customer can choose which step size and
associated specifications are best suited for their application.
The Peregri ne 5 0Ω RF DSA provides multiple CMOS control
interfaces and an optional external Vss feature. It maintains
high attenuation accuracy over frequency and temperature and
exhibits very low insertion loss and low power consumption.
Performance does not change with VDD due to on-board
regulator. This next generation Peregrine DSA is available in a
5x5 mm 32-lead QFN footprint.
The PE43703 is manufactured on Peregrine’s UltraCMOS™
pro c ess, a patented variation of silicon -on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the eco nom y an d i nte gr ation of co nventi on al
CMOS.
Pro duct Specificat ion
50 Ω RF Di gital Attenuator
7-bit, 31.75 dB, 9 kHz - 6000 MHz
VssEXT option
Product Description
Figure 2. Functional Schematic Dia gram
PE43703
Features
• HaRP ™-enha nced UltraCMOS™ device
• Attenuati on op ti o ns: 0.2 5 dB, 0.5 dB , or
1.0 dB steps to 31.75 dB
• 0.2 5 dB m on oto nici ty for ≤ 4. 0 GHz
• 0.5 dB monotonicity for ≤ 5.0 GHz
• 1 dB monotonicity for ≤ 6.0 GHz
• Hi gh Li ne ar it y: Typical + 5 9 dBm IIP3
• Excellent low-frequency performance
• Optional External Vss Control (VssEXT)
• 3.3 V or 5.0 V Power Supply Voltage
• Fast swit ch sett ling time
• Programming Modes:
• Direct Parallel
• Latche d Par allel
• Serial-Addressable: Program up to
eight addresses 000 - 111
• High-attenuation state @ power-up (PUP)
• CMOS Compatible
• No DC b locking capacitors required
Fig ur e 1. Pa ck ag e Typ e
32-l e ad 5x 5x 0. 85 mm QFN Packag e
Control Logic Interface
RF Input RF Output
Switched Attenuator Array
Serial In
LE
CLK
A0 A1 A2
Parallel Control
7
P/S Vss
EXT
(optional)
Product Specification
PE43703
Page 2 of 15
©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0245-05 │ UltraCMOS™ RFIC Solutions
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0
Atte nuation Setting (dB)
Attenuation Error (dB)
200 MHz 900 MHz 1800 MHz
2200 MHz 3000 MHz 4000 MHz
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
0 1000 2000 3000 4000
Frequency (MHz)
Attenuation Error (dB
)
0.25dB State 0.5dB State 1dB State 2dB State
4dB State 8dB State 16dB State 31.75dB State
-0.25
0.00
0.25
0.50
0 4 8 121620242832
Attenuation Setting (dB)
Step Attenuation (dB)
200 MHz 900 MHz 1800 MHz 2200 MHz 3000 MHz
5 1015202530035
5
10
15
20
25
30
0
35
Attenuation State
Attenuation dB
0.25-dB PE43701 Attenuation
900 MHz
1800 MHz
2200 MHz
3000 MHz
Table 1. Electrical Specifications: 0.25 dB steps @ +25°C, VDD = 3.3 V or 5.0 V, VssEXT = -2.7 V or GND
Notes: 1. Please note Maximum Operating Pin (50Ω) of +23dBm as shown in Table 5.
2. To prevent negative voltage generato r spur s, supply –2.7 volts to VssEXT.
Parameter Test Condit ions Frequency Min Typical Max Units
Frequency Range 9 kHz 4000 MHz
Attenuation Range 0.25 dB Step 0 – 31.75 dB
Insertion Loss 9 kH z ≤ 4 GH z 1.9 2.4 dB
Attenuation Error 0 dB - 7.75 dB Atten uatio n se tt i ngs
8 dB - 31.75 dB Attenuation settings
0 dB - 31.75 dB Attenuation settings
9 kH z < 3 G Hz
9 kH z < 3 G Hz
3 GHz < 4 GHz
±(0.2+1.5%)
±(0.15+4%)
±(0.25+4.5%)
dB
dB
dB
Return Loss 9 kHz - 4 GHz 18 dB
Relative Phase All States 9 kHz - 4 GHz 33 deg
P1dB (note 1) Input 20 MHz - 4 GHz 30 32 dBm
IIP3 Two tones at +18 dBm, 20 MHz spacing 20 MHz - 4 GHz 59 dBm
Typical Spurious Value2 VssEXT grounded 1 MHz -110 dBm
Video Feed Through 10 mVpp
Switching Time 50% DC CTRL to 10% / 90% RF 650 ns
RF Trise/Tfall 10% / 90% RF 400 ns
Sett ling Time RF settled to within 0.05 dB of final value.
RBW = 5 MHz, Averaging ON. 4 25 µs
*Monotonicity is held so long as Step-Attenuation does not cross below -0.25
Figure 3. 0.25 dB Step Attenuati on*
Performance Plots, 0.25 dB step
Figure 4. 0.25 dB Step, Actual vs. Ideal Attenuation
Figure 5. 0.25 dB Major State Bit Error Figure 6. 0.25 dB Attenuation Error
Ideal Attenuat ion (dB)
Actual Attenuation (dB)
Product Specification
PE43703
Page 3 of 15
Document No. 70-0245-05 │www. pse mi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
-0.500
0.000
0.500
1.000
0 4 8 121620242832
Attenuation Setting (dB)
Step Attenuation (dB)
200 MHz 900 MHz 1800 MHz 2200 MHz
3000 MHz 4000 MHz 5000 MHz
900 MHz
2200 MHz
3800 MHz
5000 MHz
5 1015202530035
5
10
15
20
25
30
0
35
Attenuation State
Attenuation dB
0.5-dB PE43703 Attenuation
Table 2. Electrical Specifications: 0.5 dB steps @ +25°C, VDD = 3.3 V or 5.0 V, VssEXT = -2.7 V or GND
Figure 7. 0.5 dB Step Attenuation*
Performance Plots, 0.5 dB step
Parameter Test Conditions Frequency Min Typical Max Units
Frequency Range 9 kHz 5000 MHz
Attenuation Range 0.5 dB Step 0 – 31.5 dB
Insertion Loss 9 kHz ≤ 5 GHz 2.0 2.6 dB
Attenuation Error 0 d B - 31 .5 dB A tten uat ion se ttings
0 dB - 16.5 dB Atten uatio n se tt i ngs
17 dB - 31.5 dB Attenuation settings
9 kH z < 4 G Hz
4 ≤ 5 G Hz
4 ≤ 5 G Hz
±(0.25+4.5%)
±(0.3+5%)
±(1.3+0%)
dB
dB
dB
Return Loss 9 kHz - 5 GHz 18 dB
Relative Phase All States 9 kHz - 5 GHz 56 deg
P1dB (note 1) Input 20 MHz - 5 GHz 30 32 dBm
IIP3 Two tones at +18 dBm, 20 MHz spacing 20 MHz - 5 GHz 57 dBm
Typical Spurious Value2 VssEXT grounded 1 MHz -110 dBm
Video Feed Through 10 mVpp
Switching Time 50% DC CTRL to 10% / 90% RF 650 ns
RF Trise/Tfall 10% / 90% RF 400 ns
Sett ling Time RF settled to within 0.05 dB of final value.
RBW = 5 MHz, Averaging ON. 4 25 µs
*Monotonicit y is held so l ong as Step-Atten uation does not cross below -0.5
Figure 8. 0.5 dB Step, Actual vs. Ideal Attenuation
Fig ure 9. 0.5 dB Majo r St at e Bit Er ro r Figure 10. 0.5 dB Attenuation Error
Ideal Attenuat ion (dB)
Actual Attenuation (dB)
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
0 1000 2000 3000 4000 5000
Frequency (MHz)
Attenuation Error (dB)
0.5dB State 1dB State 2dB State 4dB State
8dB State 16dB Stat e 31.5dB St ate
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0
Attenuation Setting (dB)
Attenuation Error (dB)
200 MHz 900 MHz 1800 MHz 2200 MHz
3000 MHz 4000 MHz 5000 MHz
Notes: 1. Please note Maximum Operating Pin (50Ω) of +23dBm as shown in Table 5.
2. To prevent negative voltage generato r spur s, supply –2.7 volts to VssEXT.
Product Specification
PE43703
Page 4 of 15
©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0245-05 │ UltraCMOS™ RFIC Solutions
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
0 4 8 121620242832
Attenuation Setting (dB)
Attenuation Error (dB
)
200 MHz 900 MHz 1800 MHz 2200 MHz
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
0 1000 2000 3000 4000 5000 6000
Frequency (MHz)
Bit Error (dB)
1dB State 2dB State 4dB State
8dB State 16dB State 31dB State
-1
-0.5
0
0.5
1
0 4 8 12 16 20 24 28 32
Attenuation Setting (dB)
Step Attenuation (dB)
200 MHz 900 MHz 1800 MHz 2200 MHz
3000 MHz 4000 MHz 5000 MHz 6000 MHz
900 MHz
2200 MHz
3800 MHz
5800 MHz
5 1015202530035
5
10
15
20
25
30
0
35
Attenuation State
Attenuation dB
1-dB PE43703 Attenuation
Table 3. Electrical Specifications: 1 dB steps @ +25°C, VDD = 3.3 V or 5.0 V, Vss EXT = -2.7 V or GND
Performance Plots, 1 dB step
Parameter Test Conditions Frequency Min Typical Max Units
Frequency range 9 kHz 6000 MHz
Attenuation Range 1 dB Step 0 - 31 dB
Insertion Loss 9 kH z ≤ 6 GHz 2.3 2.8 dB
Attenuation Error
0 dB - 31 dB Attenuation settings
0 dB - 12 dB Attenuation settings
13 dB - 31 dB Attenuation setting
0 dB - 31 dB Attenuation settings
9 kHz – 4 GHz
4 GHz ≤ 6 GHz
4 GHz ≤ 6 GHz
4 GHz ≤ 6 GHz
±(0.25+4.5%)
+0.4+8%
+1.4+0%
-0.2-3%
dB
dB
dB
dB
Return Loss 9 kHz - 6 GHz 18 dB
Relative Phase All States 9 kHz - 6 GHz 74 deg
P1dB (note 1) Input 20 MHz - 6 GHz 30 32 dBm
IIP3 Two tones at +18 dBm, 20 MHz spacing 20 MHz - 6 GHz 53 dBm
Typical Spurious Value2 VssEXT grounded 1 MHz -110 dBm
Video Feed Through 10 mVpp
Switching Time 50% DC CTRL to 10% / 90% RF 650 ns
RF Trise/Tfall 10% / 90% RF 400 ns
Sett ling Time RF settled to within 0.05 dB of final value.
RBW = 5 MHz, Averaging ON. 4 25 µs
*Monotoni c ity is held so long as St ep-A ttenuatio n not cross bel ow -1
Figure 12. 1 dB Step, Actual vs. Ideal Attenuation Figure 11. 1 dB Step Attenua tion
Figure 13. 1 dB Major State Bit Error Figure 14. 1 dB Attenuati on Error
Ideal Attenuat ion (dB)
Actual Attenuation (dB)
Notes: 1. Please note Maximum Operating Pin (50Ω) of +23dBm as shown in Table 5.
2. To prevent negative voltage generato r spur s, supply –2.7 volts to VssEXT.
Product Specification
PE43703
Page 5 of 15
Document No. 70-0245-05 │www. pse mi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
0123456789
Frequency (GHz)
Return Loss (dB)
-40C 25C 85C
-40
-35
-30
-25
-20
-15
-10
-5
0
0123456789
Frequency (GHz)
Return Loss (dB)
-40C 25C 85C
-60
-50
-40
-30
-20
-10
0
01234567 89
Frequency (GHz)
Return Loss (dB)
0dB 0.25dB 0.5dB 1dB 2dB
4dB 8dB 16dB 31.75dB
-5
-4.5
-4
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
0
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0
Frequency (GHz)
Insertion Loss (dB)
-40C +25C +85C
-70
-60
-50
-40
-30
-20
-10
0
0123456789
Frequency (GHz)
Return Loss (dB)
0dB 0.25dB 0.5dB 1dB 2dB
4dB 8dB 16dB 31.75dB
-1. 5
-1. 0
-0. 5
0.0
0.5
1.0
1.5
0 4 8 121620242832
Attenuation Setting (dB)
Attenuation Error (dB)
3000 MHz 4000 MHz 5000 MHz 6000 MH
z
Figure 15. 1 dB Attenuation Error (continued) Figure 16. Inserti on Loss @ Temperature
Performance Plots, 1 dB step (continue d)
Figure 17. Input Return Loss (+25C) Figure 18. Output Return Loss (+25C)
Figure 19. Input Return Loss @ Te mperature for
16 dB State Figure 20. Output Return Loss @ Temperature
for 16 dB State
Product Specification
PE43703
Page 6 of 15
©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0245-05 │ UltraCMOS™ RFIC Solutions
30
35
40
45
50
55
60
65
70
0 1000 2000 3000 4000 5000 6000 7000
Frequency (MHz)
Input IP3 (dBm)
0dB 0.25dB 0.5dB 1dB 2dB
4dB 8dB 16dB 31.75dB
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
0 4 8 121620242832
Attenuation Setting (dB)
At tenuation Error (dB)
+25C -40C +85C
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
0 4 8 121620242832
Attenuation Setting (dB)
Attenuation Error (dB)
+25C -40C +85C
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0
Attenuation Setting (dB)
Attenuation Error (dB)
+25 C -40C +85C
0.00
5.00
10.00
15.00
20.00
25.00
30.00
35.00
-40 -20 0 20 40 60 80
Temperature (Deg C)
Phase (Deg)
900 MHz 1800 MHz 3000 MHz
0
20
40
60
80
100
120
012345678
Frequency (GHz)
Relative Phase Error (Deg)
0dB 0.25dB 0.5dB 1dB 2dB
4dB 8dB 16dB 31.75dB
Figure 21. Relative Phase Error Figure 22. Relative Phase Error vs.
Temperature for 31.75 dB State
Performance Plots (continued)
Figure 23. Attenuation Error @ 900 MHz Figure 24. Attenuation Error @ 180 0 MHz
Figure 25. Attenuation Error @ 3000 MHz Figure 26. Input IP3 vs . Frequency
Product Specification
PE43703
Page 7 of 15
Document No. 70-0245-05 │www. pse mi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Electrostatic Discharge (ESD) Precautions
When handling t his Ultr aCM OS™ device, obs er v e the
same pr ec autions t hat you would us e with other ESD-
sensit ive devices . Alt hough this devic e contains
circ uitry to protect it from dam age due to ES D,
precautions should be taken t o av oid ex c eeding the
specif ied rating.
Expose d Solder Pad Connection
The exposed solder pad on the bottom of t he pac k age
must be grounded f or pr oper dev ic e oper ation.
Figure 27. Pin Configurati on (Top View)
Latc h-Up Avoidance
Unlike conventional CMO S devices, UltraCMOS™
devices ar e im m une to latc h- up.
Swi tc hing Frequency
The PE 43703 has a maxim um 25 kHz switc hing r ate
when Vss EXT is grounded. Switching rate is defined to
be the speed at which the DSA can be t oggled ac r os s
att enuation states.
Pin No. Pin Name Description
1 N/C No Connect
2 VDD Power supply pin
3 P/S Seri al/ P ar alle l mo de sel ec t
4 A0 Address Bit A0 connection
5 GND Ground
6 GND Ground
7 RF1 RF1 port
8 - 17 GND Ground
18 RF2 RF2 port
19 GND Ground
20 VssEXT External Vss Control
21 A2 Address Bit A2 connection
22 A1 Address Bit A1 connection
23 LE Seri al in terfac e Latc h E n ab le in pu t
24 CLK Serial interface Clock input
25 S I Seri al in t er f ac e Dat a in put
26 C16 (D6) Parallel control bit, 16 dB
27 C8 (D5) Parallel control bit, 8 dB
28 C4 (D4) Parallel control bit, 4 dB
29 C2 (D3) Parallel control bit, 2 dB
30 C1 (D2) Parallel control bit, 1 dB
31 C0.5 (D1) Parallel control bit, 0.5 dB
32 C0.25 (D0) Parallel control bit, 0.25 dB
Pad dl e GN D Ground for pr op er op er a tion
8
7
6
5
4
3
2
124
23
22
21
20
19
18
17
32 31 30 29 28 27 26 25
161514131211109
Exposed
Solder pad
NC
VDD
P/S
A0
GND
GND
RF1
GND
GND
GND
GND
GND
GND
GND
GND
GND
CLK
LE
A1
A2
VssEXT
GND
RF2
GND
C0.25
C0.5
C1
C2
C4
C8
C16
SI
Optional External Vss Control (VssEXT)
For pr oper oper ation, the VssEXT cont rol must be
grounded or at the V s s volt age s pec ified in the
Operating Ranges table. When the VssEXT contr ol pin
on the package is grounded the swit c h FET’s ar e
biased with an internal low spur negative voltage
generator. For applications t hat requir e the lowest
possible s pur per formanc e, VssEXT can be applied to
bypass the inter nal negative voltage generat or to
eliminate the spurs.
Table 4 . Pin Descriptions
Moist u re Sen sit i vit y L evel
The Moisture Sensitivity Level rating for the PE43703 in
the 5x5 QFN package is MSL1.
Note: Ground C0.25, C0.5, C1 C2, C4, C8, C16 if not in use.
Product Specification
PE43703
Page 8 of 15
©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0245-05 │ UltraCMOS™ RFIC Solutions
0.0
5.0
10.0
15.0
20.0
25.0
30.0
1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08 1.0E+09
Hz
Pin dBm
Note: 1. Applied only when external VSS power supply used. Pin 20
must be grounded when using internal Vss supply
Table 5. Opera ti ng Ranges Table 6. Absolute Max imum Rati ngs
Parameter Min Typ Max Units
VDD 3.3 V Power Supply
Voltage 3.0 3.3 3.6 V
VDD 5.0 V Power Supply
Voltage 4.5 5.0 5.5 V
VssEXT Negative Power Supply
Voltage1 -3.0 -2.7 -2.4 V
IDD Power Supply Current 70 350 µA
Digital Input High 2.6 5.5 V
PIN Input power ( 50Ω):
9 kHz ≤ 20 MHz
20 MHz ≤ 6 GHz
See fi g. 28
+23
dBm
dBm
TOP Opera ti ng te m perat u re
range -40 25 85 °C
Digital Input Low 0 1 V
Digital Input Leakage 15 µA
Symbol Parameter/Conditions Min Max Units
VDD Power supply voltage -0.3 6.0 V
VssEXT Vss External Negative Power
Supply Voltage (optional) -4.0 0.3 V
VI Voltage on any Digital input -0.3 5.8 V
TST Storage temperature range -65 150 °C
VESD ESD voltage ( HBM)1
ESD voltage ( M achine Mod el) 500
100 V
V
PIN Input power (50Ω)
9 kHz ≤ 20 MHz
20 MHz ≤ 6 GHz
See fig. 28
+23
dBm
dBm
Figure 28. Maximum Power Ha ndling Capability: Z0 = 50 Ω
Exceeding absolute m ax im um r atings may cause
permanent damage. Operation should be res tricted to
the limits in t he Operating Ranges t able. Operat ion
between operating range m ax im um and abs olute
maxim um for extended periods m ay r educ e r eliability.
Note : 1. H u ma n B ody M od el (H BM, MIL_STD 88 3 Meth od 301 5. 7)
Product Specification
PE43703
Page 9 of 15
Document No. 70-0245-05 │www. pse mi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Table 8. Latch and Clock Specifications
Latch Enable Function
0 Shift Register Clocked
↑ Contents of shift register
trans f er r ed t o at te nuato r cor e
Shift Clock
↑
X
Attenuation Wor d
D7 D6 D5 D4 D3 D2 D1 D0
(LSB)
L L L L L L L L Reference I.L.
L L L L L L L H 0.25 dB
L L L L L H L L 1 dB
L L L L H L L L 2 dB
L L L H L L L L 4 dB
L L H L L L L L 8 dB
L H L L L L L L 16 dB
L H H H H H H H 31.75 dB
Attenuation
Setting
RF1-RF2
L L L L L L H L 0.5 dB
Table 11. Serial Attenua tion Word Truth Ta ble
Address Word Address
Setting
A7
(MSB) A6 A5 A4 A3 A2 A1 A0
X X X X X L L L 000
X X X X X L L H 001
X X X X X L H L 010
X X X X X L H H 011
X X X X X H L L 100
X X X X X H L H 101
X X X X X H H L 110
X X X X X H H H 111
Table 10. Serial Address Word Truth Table Table 7. Control Voltage
State Bias Condition
Low 0 to +1.0 Vdc at 2 µA (typ)
High +2.6 to +5 Vdc at 10 µA (typ)
Parallel Control Setting Attenuation
Setting
RF1-RF2
D6 D5 D4 D3 D2 D1 D0
L L L L L L L Reference I.L.
L L L L L L H 0.25 dB
L L L L L H L 0.5 dB
L L L L H L L 1 dB
L L L H L L L 2 dB
L L H L L L L 4 dB
L H L L L L L 8 dB
H L L L L L L 16 dB
H H H H H H H 31.75 dB
Table 9. Parallel Truth Table
Table 12. Serial-Addressable Register Map
Q15 Q14 Q13 Q12 Q11 Q10
A7 A6 A5 A4 A3 A2
Q9 Q8 Q7 Q6 Q5 Q4
A1 A0 D7 D6 D5 D4
Q3 Q2 Q1 Q0
D3 D2 D1 D0
Address Word Attenuation Word
LSB (first in)
MSB (last in)
Bits can either be set to logic high or logic low
Attenuation Word is derived directly from the attenuation value. For example, to program the 18.25 dB state
at addr es s 3:
Address word: XXXXX011
Attenuation Word: Multiply by 4 and convert to binary → 4 * 18 .25 dB → 73 → 01001001
Serial Input: XXXXX01101001001
D7 must be set to lo gic low
Product Specification
PE43703
Page 10 of 15
©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0245-05 │ UltraCMOS™ RFIC Solutions
Programming Options
Parallel/Serial Selection
Either a parallel or serial-addressable interface can
be used to control the PE43703. The P/S b it
provides this se lectio n, with P/S=LOW selecting the
parallel interface and P/S=HIGH selecting the serial-
addressable interface.
Parallel Mode Interface
The parallel interface consists of seven CMOS-
compatible control lines that select the desired
attenuation state, as shown in T abl e 9.
The parallel interface timing requirements are
defined by Fig. 30 (Parallel Interface Timing
Diagram), Table 9 (Parallel Interface AC
Characteristics), and switching speed (Table 1).
For latched-parallel programming the Latch Enable
(LE) should be held LOW while changing attenuation
state control values, then pulse LE HIGH to LOW
(per Fig. 30) to latch new attenuation state into
device.
For direct parallel programming, the Latch Enable
(LE) line should be pulled HIGH. Changing
at tenuation state control v alues will change devic e
state to new attenuation. Direct mode is ideal for
manual control of the device (using hardwire,
switches, or jumpers).
Serial-Addressable Interface
The serial-addressable interface is a 16-bit serial-in,
parallel-out shift register buffered by a transparent
latch. The 16-bits make up two words comprised of
8-bits each. The first word is the Attenuation Word,
which controls the state of the DSA. The second
word is the Address Word, which is compared to the
static (or programmed) logical states of the A0, A1
and A2 digital inputs. If there is an address match,
the DSA changes state; otherwise its current state
will rema in un ch anged. Fig. 29 illustrates an
example timing diagram for programming a state. It
is required that all parallel control inputs be
grounded when the DSA is used in serial-
addressable mode.
The serial-addressable interface is controlled using
three CMOS-compatible signals: Serial-In (SI),
Clock (CLK), and Latch Enable (LE). The SI and
CLK inputs allow data to be serially entered into the
shift register. Serial data is clocked in LSB first,
beginning with the Attenuation Word.
The shift register must be loaded while LE is held
LOW to prevent the attenuator value from changing
as data is entered. The LE input should then be
toggled HIGH and brought LOW again, latching the
new data into the DSA. Address Word and
Attenuation Word truth tables are listed in Table 10
& Table 11, respectively. A programming example of
the serial-addressable register is illust rated in Table
12. The serial-addressable timing diagram is
illustrated in Fig. 29.
Power-up Control Settings
The PE43 703 will always init ialize t o the maximum
attenuation setting (31.75 dB) on power-up for both
the serial-addressable and latched-parallel modes of
operation and will remain in this s etting unt il the user
latches in the next programming word. In direct-
parallel mode, the DSA can be preset to any state
within the 31.75 dB range by pre-setting the parallel
control pins prior to power-up. In this mode, there is
a 400-µs delay between the time the DSA is
powered-up to the time the desired state is
set. During this power-up delay, the device
attenuates to the maximum attenuation setting
(31.75 dB) before defaulting to the user defined
state. If the control pins are left floating in this mode
during power-up, th e device will default to t he
minimum attenuation setting (insertion loss state).
Dynamic operation between serial-addressable and
parallel programming modes is possible.
If the DSA powers up in serial-addressable mode (P/
S = HIGH), all the parallel control inputs DI[6:0] must
be set to logic low. Prior to toggling to parallel mode,
the DSA must be programmed serially to ensure
D[7 ] is set to logic low.
If the DSA powers up in either latched or direct-
parallel mode, all parallel pins DI[6:0] must be set to
logic low prior to toggling to serial-addressable mode
(P/S = HIGH), and held low until the DSA has been
programmed serially to ensure bit D[7] is set to logic
low.
The sequencing is only required once on power-
up. Once completed, the DSA may be toggled
between serial-addressable and parallel
programming modes at will.
Product Specification
PE43703
Page 11 of 15
Document No. 70-0245-05 │www. pse mi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
VDD = 3. 3 or 5.0 V, -40° C < TA < 85° C, unless otherwise specified VDD = 3. 3 or 5.0 V, -40° C < TA < 85° C, unless otherwise specified
Figure 29. Serial-Addressable Timing Diagram
Figure 30. Latched-Parallel/Direc t-Parallel Timing Diagram
Symbol Parameter Min Max Unit
FCLK Serial clock frequency - 10 MHz
TCLKH Serial clock HIGH time 30 - ns
TCLKL Serial clock LOW time 30 - ns
TLESU Last serial clock rising edge
setup time to Latch Enable
rising edge 10 - ns
TLEPW Latch E na bl e min. pu ls e wi dt h 30 - ns
TSISU Seri al data set up time 10 - ns
TSIH Serial data hold time 10 - ns
TDISU Parall el da t a set up ti me 10 0 - ns
TDIH Parallel data hold time 100 - ns
TASU Address setup time 100 - ns
TAH Address hold time 100 - ns
TPSSU Parallel/Serial setup time 100 - ns
TPSH Parallel/Serial hold time 100 - ns
TPD Digital register delay (internal) - 10 ns
Symbol Parameter Min Max Unit
TLEPW Latch Enable minimum
pulse width 30 - ns
TDISU Para llel da ta set up time 10 0 - ns
TDIH Parallel data hold time 100 - ns
TPSSU Parallel/Serial setup time 100 - ns
TPSIH Parallel/Serial hold time 100 - ns
TPD Digital register delay
(internal) - 10 ns
TDIPD Digital register delay
(internal, direct mode only) - 5 ns
VALID
T
DISU
T
DIH
DI[6:0]
LE
P/S
T
PSSU
T
PSH
T
LEPW
VALID
DO[6:0]
T
DIPD
T
PD
Table 14. Paral lel and Direct Inte rface
AC Characteristics
Table 1 3. Ser ial- A dd r essabl e In ter face
AC Characteristics
A[2]A[1]A[0]
T
SISU
T
CLKL
T
LEPW
T
SIH
T
CLKH
SI
CLK
LE
P/S
T
LESU
T
PSSU
T
PSIH
VALID
T
ASU
ADD[2:0]
T
AIH
DO[6:0]
VALID
DI[6:0]
T
PD
T
DISU
T
DIH
D[6]D[5]D[4]D[3]D[2]D[1]D[0] D[7]
D[7] must be set to logic low
Bits can either be set to logic high or logic low
Product Specification
PE43703
Page 12 of 15
©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0245-05 │ UltraCMOS™ RFIC Solutions
Evaluation Kit
The Di gi tal Att en ua t or E val u ation Kit bo ar d w as
designed to ease cus t om er eval u ation of th e
PE43703 Digital Step Attenuator.
Direct-Parallel Programming Procedure
For automated direct-parallel programming,
connect the test harness provided with the EVK
from the parallel port of the PC to the J1 & Serial
header pin and set the D0-D6 SP3T switches to the
‘MIDDL E’ toggle position. Position the Parallel/
Serial (P/S) se lect switch to the Pa rallel (or left)
position. The evaluation software is written to
operate the DSA in either Parallel or Serial-
Addressable Mode. Ensure that the software is set
to program in Direct-Parallel mode. Using the
software, enable or disable each setting to the
desired attenuation state. The software
automatically programs the DSA each time an
attenuation state is enabled or disabled.
For manual direct-parallel programming,
disconnect the test harness provided with the EVK
from the J1 and Serial header pins. Position the
Pa rallel/S erial (P/ S) select swit ch to the Para llel (or
left) posi tio n. Th e LE pin on th e Ser ial he ad er mu st
be tied to VDD. Switches D0-D6 are SP3T switches
whi ch en abl e t he user to m anuall y pr o gr am the
parallel bits. When any input D0-D6 is toggled
‘UP’, logic high is presented to the parallel input.
When toggled ‘DOWN’, logic low is presented to
the paralle l input. Setting D0-D6 to the ‘MIDDLE’
toggle position presents an OPEN, which forces an
on-chip logic low. Table 9 depicts the parallel
programming truth table and Fi g. 30 illustrates the
parallel programming timing diagram.
Latc he d- P ar al l el Program m i ng Pr oc edure
For automated latched-parallel programming, the
procedure is identical to the direct-parallel method.
The user only must ensure that Latched-Parallel is
selected in the software .
For manual latched-parallel programming, the
procedure is identical to direct-parallel except now
the LE pin on the Serial header must be logic low
as the parallel bits are applied. The user must then
pulse LE from 0V to VDD and back to 0V to latch the
programming word into the DSA. LE must be logic
low prior to pr ogramm i ng th e nex t wor d .
Figure 31. Evaluati on Board Layout
Peregr ine S pec ificat ion 101- 0312
Seri al - A ddr essable Program m ing Pr oced ur e
Po sition the Parallel/Serial (P/S) select switch to
the Serial (or right) position. Prior to
programming, the user must define an address
setting using the ADD header pin. Jump the
mi ddl e pins o n the AD D hea der A0-A2 ( or lower )
row of pins to set logic high, or jump the middle
pins to the upper row of pins to set logic low. If
the ADD pi ns are l eft op e n, the n 000 be come the
default address. The evaluation software is
written to operate the DSA in either Parallel or
Serial-Addressable Mode. Ensure that the
software is set to program in Serial-Addressable
mode. Using the software, enable or disable each
setting to the desired attenuation state. The
software automatically programs the DSA each
time an attenuation state is enabled or disabled.
Not e : Refe rence Fig. 32 for Evaluat ion Board Schemat ic
Product Specification
PE43703
Page 13 of 15
Document No. 70-0245-05 │www. pse mi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Figure 33. Package Drawing
QFN 5x5 mm
A MAX 0.900
NOM 0.850
MIN 0.800
Figure 32. Evaluation Board Schematic
Peregr ine S pec ificat ion 102- 0381
Note: Capacitors C1-C8, C13, & C14 may be omitted.
Product Specification
PE43703
Page 14 of 15
©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0245-05 │ UltraCMOS™ RFIC Solutions
Table 15. Ordering Information
Figure 34. Tape and Reel Draw ing
Orde r Code Part Marking Des cription Package Shi pping Method
PE43703MLI 43703 PE43703 G - 32QFN 5x5mm-75A Green 32-lead 5x5mm QFN Bulk or tape cut from reel
PE43703MLI-Z 43703 PE43703 G – 32QFN 5x5mm-3000C Green 32-lead 5x5mm QFN 3000 units / T&R
EK43703-01 43703 PE43703 G – 32QFN 5x5mm-EK Evaluation Kit 1 / Box
Figure 35. Marking Specifications
43703
YYWW
ZZZZZ
YYWW = Date Code
ZZZZZ = Last five digits of Lot Number
Device Orientation in Tape
Top of
Device
Pin 1
Tape Feed Dire c t ion
Product Specification
PE43703
Page 15 of 15
Document No. 70-0245-05 │www. pse mi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Sales Offices
The Americas
Peregrine Semiconductor Corporation
9380 Car r oll Par k Drive
San Diego, CA 92121
Tel: 858-731- 9400
Fax: 858-731-9499
Europe
Peregrine Semiconductor Europe
Bâtiment Maine
13-15 rue des Q uatre Vents
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Tel: +33-1- 4741-9173
Fax : +33-1 -4741 -917 3
For a list of r epresentatives in your area, please ref er to our Web site at: www.psem i.com
Data Sheet Identification
Advance Information
The product is in a format ive or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.
Preliminary Specification
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the r ight
to change specificat ions at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data . In the event Peregrine
dec ide s to cha nge the spe c ific a tions, Pereg rine will not ify
customer s of t he intended changes by issuing a CNF
(Customer Notification Form).
The inform ation in t his dat a sheet is believed to be reliable.
Howeve r, Peregrine assum es no liability f or th e use of this
information. Use shall be entirely at t he user’s own r isk.
No pat ent rights or licenses to any circuits described in this
data sheet are im plied or granted t o any third party.
Peregrine’s products are not designed or intended f or use in
devices or system s intended for sur gical im plant, or in other
applications intended to support or sustain life, or in any
application in which t he failur e of the Peregrine product could
create a situation in which personal injur y or death might occur.
Peregr ine assum es no liability for damages, including
consequential or incident al damages, arising out of the use of
its product s in such applicat ions.
The Per egr ine name, logo, and UTSi are register ed t r ademarks
and Ultr aCMOS, HaRP, MultiSwitch and DuNE are tr ademarks
of Peregr ine Semiconductor Corp.
High-Reliability and Defense Products
Americas
San Diego, CA, USA
Phone: 858-731-9475
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