LTC3115-1
1
Rev. C
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TYPICAL APPLICATION
FEATURES DESCRIPTION
40V, 2A Synchronous
Buck-Boost DC/DC
Converter
The LTC
®
3115-1 is a high voltage monolithic synchronous
buck-boost DC/DC converter. Its wide 2.7V to 40V input
and output voltage ranges make it well suited to a wide
variety of automotive and industrial applications. A propri-
etary low noise switching algorithm optimizes efficiency
with input voltages that are above, below or even equal
to the output voltage and ensures seamless transitions
between operational modes.
Programmable frequency PWM mode operation pro-
vides low noise, high efficiency operation and the ability
to synchronize switching to an external clock. Switching
frequencies up to 2MHz are supported to allow use of
small value inductors for miniaturization of the appli-
cation circuit. Pin selectable Burst Mode operation
reduces standby current and improves light load effi-
ciency which, combined with a 3µA shutdown current,
make the LTC3115-1 ideally suited for battery-powered
applications. Additional features include output discon-
nect in shutdown, short-circuit protection and inter-
nal soft-start. The LTC3115-1 is available in thermally
enhanced 16-lead 4mm × 5mm × 0.75mm DFN and
20-lead TSSOP packages.
Efficiency vs VIN
APPLICATIONS
n Wide VIN Range: 2.7V to 40V
n Wide VOUT Range: 2.7V to 40V
n 1A Output Current for VIN ≥ 3.6V, VOUT = 5V
n 2A Output Current in Step-Down Operation
for VIN ≥ 6V
n Programmable Frequency: 100kHz to 2MHz
n Synchronizable Up to 2MHz with an External Clock
n Up to 95% Efficiency
n 30µA No-Load Quiescent Current in Burst Mode
®
Operation
n Ultralow Noise Buck-Boost PWM
n Internal Soft-Start
n 3µA Supply Current in Shutdown
n Programmable Input Undervoltage Lockout
n Small 4mm × 5mm × 0.75mm DFN Package
n Thermally Enhanced 20-Lead TSSOP Package
n AEC-Q100 Qualified for Automotive Applications
n 24V/28V Industrial Applications
n Automotive Power Systems
n Telecom, Servers and Networking Equipment
n FireWire Regulator
n Multiple Power Source Supplies
BST1 BST2
PVIN
VIN
VC
PVOUT
PWM/SYNC
FBRUN
PVCC
VCC
RT
SW1 SW2
GND PGND
LTC3115-1
10µH
0.1µF
BURST PWM
2.7V TO
40V
0.1µF
33pF
(OPTIONAL)
5V
1A VIN > 3.6V
2A VIN ≥ 6V
4.7µF 47µF
1M
249k
4.7µF
3115 TA01a
47.5k
15k
60.4k3300pF
OFF ON
INPUT VOLTAGE (V)
EFFICIENCY (%)
95
90
85
31151 TA01b
70
80
75
40
2 10
ILOAD = 0.5A
ILOAD = 1A
VOUT = 5V
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents including 6404251, 6166527 and others pending.
LTC3115-1
2
Rev. C
For more information www.analog.com
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
VIN, PVIN, PVOUT ........................................ –0.3V to 45V
VSW1
DC ........................................... –0.3V to (PVIN + 0.3V)
Pulsed (<100ns) ...................... –1.5V to (PVIN + 1.5V)
VSW2
DC .........................................–0.3V to (PVOUT + 0.3V)
Pulsed (<100ns) ....................–1.5V to (PVOUT + 1.5V)
VRUN ............................................. –0.3V to (VIN + 0.3V)
VBST1 .....................................VSW1 – 0.3V to VSW1 + 6V
VBST2 .....................................VSW2 – 0.3V to VSW2 + 6V
(Note 1)
VPWM/SYNC ................................................... –0.3V to 6V
Voltage, All Other Pins ................................. –0.3V to 6V
Operating Junction Temperature Range (Notes 2, 4)
LTC3115E-1/LTC3115I-1 ..................... –40°C to 125°C
LTC3115H-1 .......................................–40°C to 150°C
LTC3115MP-1 ..................................... –55°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
FE......................................................................300°C
16
15
14
13
12
11
10
9
PGND
17
1
2
3
4
5
6
7
8
PWM/SYNC
SW1
PVIN
BST1
BST2
PVCC
VIN
VCC
RUN
SW2
PVOUT
GND
GND
VC
FB
RT
TOP VIEW
DHD PACKAGE
16-LEAD (5mm × 4mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W, θJC = 4.3°C/W
EXPOSED PAD (PIN 17) IS PGND, MUST BE SOLDERED TO PCB
FE PACKAGE
20-LEAD PLASTIC TSSOP
TJMAX = 150°C, θJA = 38°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 21) IS PGND, MUST BE SOLDERED
TO PCB FOR RATED THERMAL PERFORMANCE
1
2
3
4
5
6
7
8
9
10
TOP VIEW
20
19
18
17
16
15
14
13
12
11
PGND
RUN
SW2
PVOUT
GND
GND
VC
FB
RT
PGND
PGND
PWM/SYNC
SW1
PVIN
BST1
BST2
PVCC
VIN
VCC
PGND
21
PGND
LTC3115-1
3
Rev. C
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ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL
PART
MARKING* PACKAGE DESCRIPTION
TEMPERATURE
RANGE
LTC3115EDHD-1#PBF LTC3115EDHD-1#TRPBF 31151 16-Lead (5mm × 4mm) Plastic DFN –40°C to 125°C
LTC3115IDHD-1#PBF LTC3115IDHD-1#TRPBF 31151 16-Lead (5mm × 4mm) Plastic DFN –40°C to 125°C
LTC3115EFE-1#PBF LTC3115EFE-1#TRPBF LTC3115FE-1 20-Lead Plastic TSSOP –40°C to 125°C
LTC3115IFE-1#PBF LTC3115IFE-1#TRPBF LTC3115FE-1 20-Lead Plastic TSSOP –40°C to 125°C
LTC3115HFE-1#PBF LTC3115HFE-1#TRPBF LTC3115FE-1 20-Lead Plastic TSSOP –40°C to 150°C
LTC3115MPFE-1#PBF LTC3115MPFE-1#TRPBF LTC3115FE-1 20-Lead Plastic TSSOP –55°C to 150°C
AUTOMOTIVE PRODUCTS**
LEAD FREE FINISH TAPE AND REEL TAPE AND REEL MINI
PART
MARKING* PACKAGE DESCRIPTION
TEMPERATURE
RANGE
LTC3115EDHD-1#WPBF
LTC3115EDHD-1#WTRPBF LTC3115EDHD-1#WTRMPBF 31151 16-Lead (5mm × 4mm) Plastic DFN –40°C to 125°C
LTC3115IDHD-1#WPBF LTC3115IDHD-1#WTRPBF LTC3115IDHD-1#WTRMPBF 31151 16-Lead (5mm × 4mm) Plastic DFN –40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
thesemodels.
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are for TA = 25°C (Note 2). PVIN = VIN = 24V, PVOUT = 5V, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Operating Voltage l2.7 40 V
Output Operating Voltage l2.7 40 V
Input Undervoltage Lockout Threshold VIN Falling
VIN Rising
VIN Rising (0°C to 125°C)
l
l
2.4
2.6 2.7
2.8
2.725
V
V
V
Input Undervoltage Lockout Hysteresis 100 mV
VCC Undervoltage Lockout Threshold VCC Falling l2.4 2.6 V
VCC Undervoltage Lockout Hysteresis 200 mV
Input Current in Shutdown VRUN = 0V 3 10 µA
Input Quiescent Current in Burst Mode Operation VFB = 1.1V (Not Switching), VPWM/SYNC = Low 50 µA
Oscillator Frequency RT = 35.7k, VPWM/SYNC = High l900 1000 1100 kHz
Oscillator Operating Frequency VPWM/SYNC = High l100 2000 kHz
PWM/SYNC Clock Input Frequency l100 2000 kHz
PWM/SYNC Input Logic Threshold l0.5 1.0 1.5 V
Soft-Start Duration 9 ms
Feedback Voltage l977 1000 1017 mV
Feedback Voltage Line Regulation VIN = 2.7V to 40V 0.1 %
Feedback Pin Input Current 1 50 nA
RUN Pin Input Logic Threshold l0.3 0.8 1.1 V
RUN Pin Comparator Threshold VRUN Rising l1.16 1.21 1.26 V
RUN Pin Hysteresis Current 500 nA
RUN Pin Hysteresis Voltage 100 mV
Inductor Current Limit (Note 3) l2.4 3.0 3.7 A
Reverse Inductor Current Limit Current into PVOUT (Note 3) 1.5 A
Burst Mode Inductor Current Limit (Note 3) 0.65 1.0 1.35 A
Maximum Duty Cycle Percentage of Period SW2 is Low in Boost Mode,
RT = 35.7k (Note 5)
l90 95 %
Minimum Duty Cycle Percentage of Period SW1 is High in Buck Mode,
RT = 35.7k (Note 5)
l0 %
SW1, SW2 Minimum Low Time RT = 35.7k (Note 5) 100 ns
N-Channel Switch Resistance Switch A (From PVIN to SW1)
Switch B (From SW1 to PGND)
Switch C (From SW2 to PGND)
Switch D (From PVOUT to SW2)
150
150
150
150
mΩ
mΩ
mΩ
mΩ
N-Channel Switch Leakage PVIN = PVOUT = 40V 0.1 10 µA
PVCC/VCC External Forcing Voltage 4.58 5.5 V
VCC Regulation Voltage IVCC = 1mA 4.33 4.45 4.58 V
VCC Load Regulation IVCC = 1mA to 20mA 1.2 %
VCC Line Regulation IVCC = 1mA, VIN = 5V to 40V 0.5 %
VCC Current Limit VCC = 2.5V 50 110 mA
VCC Dropout Voltage IVCC = 5mA, VIN = 2.7V 50 mV
VCC Reverse Current VCC = 5V, VIN = 3.6V 10 µA
LTC3115-1
4
Rev. C
For more information www.analog.com
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3115-1 is tested under pulsed load conditions such
that TJ ≈ TA. The LTC3115E-1 is guaranteed to meet specifications
from 0°C to 85°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are ensured by design,
characterization and correlation with statistical process controls. The
LTC3115I-1 specifications are guaranteed over the –40°C to 125°C
operating junction temperature range. The LTC3115H-1 specifications are
guaranteed over the –40°C to 150°C operating junction temperature range.
The LTC3115MP-1 specifications are guaranteed over the –55°C to 150°C
operating junction temperature range. High junction temperatures degrade
operating lifetime; operating lifetime is derated for junction temperatures
greater than 125°C. The maximum ambient temperature consistent with
these specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal resistance and
other environmental factors.
The junction temperature (TJ in °C) is calculated from the ambient
temperature (TA in °C) and power dissipation (PD in Watts) according to
the following formula:
TJ = TA + (PD • θJA)
where θJA is the thermal impedance of the package.
Note 3: Current measurements are performed when the LTC3115-1 is
not switching. The current limit values measured in operation will be
somewhat higher due to the propagation delay of the comparators.
Note 4: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 5: Switch timing measurements are made in an open-loop test
configuration. Timing in the application may vary somewhat from these
values due to differences in the switch pin voltage during the non-overlap
durations when switch pin voltage is influenced by the magnitude and
direction of the inductor current.
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are for TA = 25°C (Note 2). PVIN = VIN = 24V, PVOUT = 5V, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
LTC3115-1
5
Rev. C
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
PWM Mode Efficiency, VOUT = 5V,
fSW = 1MHz, Non-Bootstrapped
PWM Mode Efficiency,
VOUT = 12V, fSW = 1MHz
PWM Mode Efficiency,
VOUT = 24V, fSW = 1MHz
PWM Mode Efficiency, VOUT = 5V,
fSW = 500kHz, Non-Bootstrapped
PWM Mode Efficiency,
VOUT = 12V, fSW = 500kHz
PWM Mode Efficiency,
VOUT = 24V, fSW = 500kHz
(TA = 25°C unless otherwise specified)
LOAD CURRENT (A)
0.01
60
EFFICIENCY (%)
80
100
0.10 1
31151 G01
40
50
70
90
30
20
VIN = 3.6V
VIN = 5V
VIN = 12V
VIN = 24V
VIN = 36V
LOAD CURRENT (A)
0.01
70
EFFICIENCY (%)
80
90
100
0.1 1
31151 G02
60
50
40
30
VIN = 5V
VIN = 12V
VIN = 24V
VIN = 36V
LOAD CURRENT (A)
0.01
70
EFFICIENCY (%)
80
90
0.1 1
31151 G03
60
30
50
40
100
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 36V
LOAD CURRENT (A)
0.01
60
EFFICIENCY (%)
80
100
0.1 1
31151 G04
40
50
70
90
30
20
VIN = 3.6V
VIN = 5V
VIN = 12V
VIN = 24V
VIN = 36V
LOAD CURRENT (A)
0.01
70
EFFICIENCY (%)
80
90
100
0.1 1
31151 G05
60
50
40
30
VIN = 5V
VIN = 12V
VIN = 24V
VIN = 36V
LOAD CURRENT (A)
0.01
70
EFFICIENCY (%)
80
90
0.1 1
31151 G06
60
30
40
50
100
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 36V
LTC3115-1
6
Rev. C
For more information www.analog.com
Burst Mode Efficiency, VOUT = 5V,
L = 15µH, Non-Bootstrapped
Burst Mode Efficiency,
VOUT = 12V, L = 15µH
Burst Mode Efficiency,
VOUT = 24V, L = 15µH
TYPICAL PERFORMANCE CHARACTERISTICS
(TA = 25°C unless otherwise specified)
Maximum Load Current
vs VIN, Burst Mode Operation
Burst Mode No-Load Input
Current vs VIN
PWM Mode No-Load Input
Current vs VIN
Maximum Load Current
vs VIN, PWM Mode
Maximum Load Current
vs VIN, PWM Mode
Maximum Load Current
vs VIN, PWM Mode
LOAD CURRENT (mA)
0.1
70
EFFICIENCY (%)
80
90
1 10 100
31151 G07
60
65
75
85
55
50
VIN = 3.6V
VIN = 12V
VIN = 24V
VIN = 36V
LOAD CURRENT (mA)
0.1
70
EFFICIENCY (%)
80
95
90
1 10 100
31151 G08
60
65
75
85
55
50
VIN = 5V
VIN = 12V
VIN = 24V
VIN = 36V
LOAD CURRENT (mA)
0.1
70
EFFICIENCY (%)
80
90
1 10 100
31151 G09
60
65
75
85
55
50
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 36V
INPUT VOLTAGE (V)
2
0
INPUT CURRENT (µA)
100
200
400
10 40
31151 G10
300
50
150
350
250
VOUT = 24V
VOUT = 15V
VOUT = 5V
VOUT = 5V, BOOTSTRAPPED
INPUT VOLTAGE (V)
2
0
INPUT CURRENT (mA)
10
20
30
40
10 40
31151 G11
50
5
15
25
35
45 VOUT = 24V
VOUT = 12V
VOUT = 5V
fSW = 1MHz
INPUT VOLTAGE (V)
LOAD CURRENT (A)
2.5
2.0
1.5
31151 G12
0
1.0
0.5
40
2 10
L = 22µH
fSW = 500kHz
VOUT = 24V
VOUT = 12V
VOUT = 5V
INPUT VOLTAGE (V)
2 10
10
LOAD CURRENT (mA)
100
1000
40
31151 G13
L = 22µH
VOUT = 32V
VOUT = 12V
VOUT = 5V
INPUT VOLTAGE (V)
LOAD CURRENT (A)
2.5
2.0
1.5
31151 G47
0
1.0
0.5
40
2 10
L = 15µH
fSW = 1MHz
VOUT = 24V
VOUT = 12V
VOUT = 5V
INPUT VOLTAGE (V)
LOAD CURRENT (A)
2.5
2.0
1.5
31151 G48
0
1.0
0.5
40
2 10
L = 5.2µH
fSW = 2MHz
VOUT = 12V
VOUT = 5V
LTC3115-1
7
Rev. C
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Combined VCC/PVCC Supply
Current vs VCC
Combined VCC/PVCC Supply
Current vs Temperature Output Voltage Load Regulation
VCC Regulator Load Regulation
(TA = 25°C unless otherwise specified)
VCC Regulator Line Regulation
Output Voltage Line Regulation
VCC Voltage vs Temperature
VCC (V)
2.5
VCC/PVCC CURRENT (mA)
6
8
10
45
31151 G16
4
2
03 3.5 4.5
12
14
16
5.5
fSW = 1MHz
fSW = 500kHz
TEMPERATURE (°C)
–50
11.0
VCC/PVCC CURRENT (mA)
11.1
11.3
11.4
11.5
12.0
11.7
050
31151 G17
11.2
11.8
11.9
11.6
100 150
VIN = 6V
VOUT = 5V
fSW = 1MHz
INPUT VOLTAGE (V)
0
–0.5
CHANGE IN OUTPUT VOLTAGE FROM VIN = 20V (%)
–0.4
–0.2
–0.1
0
0.5
0.2
10 20
31151 G19
–0.3
0.3
0.4
0.1
30 40
TEMPERATURE (°C)
–50
–1.0
CHANGE FROM 25°C (%)
–0.8
–0.4
–0.2
0
1.0
0.4
050
31151 G20
–0.6
0.6
0.8
0.2
100 150
INPUT VOLTAGE (V)
0
–1.0
CHANGE FROM V
IN
= 24V (%)
–0.8
–0.4
–0.2
0
1.0
0.4
10 20
31151 G22
–0.6
0.6
0.8
0.2
30 40
LOAD CURRENT (A)
0
–0.5
CHANGE IN VOLTAGE FROM ZERO LOAD (%)
–0.4
–0.2
–0.1
0
0.5
0.2
0.5 1
31151 G18
–0.3
0.3
0.4
0.1
1.5 2
ICC (mA)
0
CHANGE IN VOLTAGE FROM I
CC
= 0mA (%)
–1.0
–0.5
0
40
31151 G21
–1.5
–2.0
–2.5 10 20 30 50
Efficiency vs Switching Frequency
Combined VCC/PVCC Supply
Current vs Switching Frequency
SWITCHING FREQUENCY (kHz)
0
EFFICIENCY (%)
80
85
2000
31151 G14
75
70 500 1000 1500
95
90
BOOTSTRAPPED
PWM MODE
L = 47µH
VIN = 24V
VOUT = 5V
ILOAD = 0.5A
NON-BOOTSTRAPPED
SWITCHING FREQUENCY (kHz)
0
20
25
35
1500
31151 G15
15
10
500 1000 2000
5
0
30
VCC/PVCC CURRENT (mA)
VIN = 36V
VOUT = 24V
VIN = 12V
VOUT = 5V
LTC3115-1
8
Rev. C
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
VCC Regulator Dropout Voltage
vs Temperature
RUN Pin Threshold
vs Temperature
RUN Pin Hysteresis Current
vs Temperature
Oscillator Frequency vs RT
Oscillator Frequency
vs Temperature
(TA = 25°C unless otherwise specified)
Power Switch Resistance
vs Temperature
Oscillator Frequency vs VIN
RUN Pin Current
vs RUN Pin Voltage
Shutdown Current on VIN/PVIN
vs Input Voltage
TEMPERATURE (°C)
–50
DROPOUT VOLTAGE (V)
0.10
0.15
150
31151 G23
0.05
0050 100
0.25
0.20
VIN = 4V
IVCC = 20mA
TEMPERATURE (°C)
–50
–1.0
CHANGE FROM 25°C (%)
–0.8
–0.4
–0.2
0
1.0
0.4
050
31151 G24
–0.6
0.6
0.8
0.2
100 150
TEMPERATURE (°C)
–50
CHANGE FROM 25°C (%)
0
0.5
1.0
150
31151 G25
–0.5
–1.0
–2.0 050 100
–1.5
2.0
1.5
RT (kΩ)
10
100
SWITCHING FREQUENCY (kHz)
1000
10000
100 1000
31151 G26
TEMPERATURE (°C)
–50
CHANGE FROM 25°C (%)
0
0.5
1.0
150
31151 G27
–0.5
–1.0
–2.0 050 100
–1.5
2.0
1.5
fSW = 1MHz
VIN (V)
2
–2.0
CHANGE FROM VIN = 24V (%)
–1.0
0
2.0
10 40
31151 G28
1.0
–1.5
–0.5
1.5
0.5
fSW = 1MHz
RUN PIN VOLTAGE (V)
0
CURRENT INTO RUN PIN (µA)
3
4
5
40
31151 G29
2
1
–1 10 20 30
0
7VIN = 40V
6
INPUT VOLTAGE (V)
0
0
COMBINED V
IN
/PV
IN
CURRENT (µA)
0.5
1.0
1.5
2.0
2.5
3.0
VRUN = 0V
10 20 30 40
31151 G30
TEMPERATURE (°C)
–50
0
POWER SWITCH (A-D) RESISTANCE (mΩ)
50
100
150
200
250
300
0 50 100 150
31151 G31
LTC3115-1
9
Rev. C
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Inductor Current Limit Thresholds
vs Temperature
(TA = 25°C unless otherwise specified)
SW1, SW2 Minimum Low Time
vs VCC
SW1, SW2 Minimum Low Time
vs Switching Frequency
SW2 Maximum Duty Cycle
vs Switching Frequency
Die Temperature Rise vs Load
Current, VOUT = 5V, fSW = 750kHz
Die Temperature Rise vs Load
Current, VOUT = 5V, fSW = 1.5MHz
SW1, SW2 Minimum Low Time
vs Temperature
TEMPERATURE (°C)
–50
–5
CHANGE FROM 25°C (%)
–4
–2
–1
0
5
2
050
31151 G34
–3
3
4
1
100 150
SWA
CURRENT
LIMIT
SWB
CURRENT
LIMIT
TEMPERATURE (°C)
–50
90
MINIMUM LOW TIME (ns)
92
96
98
100
110
104
050
31151 G35
94
106
108
102
100 150
fSW = 1MHz
NO LOAD
VCC (V)
2.5
60
MINIMUM LOW TIME (ns)
80
100
120
140
180
33.5 4 4.5
31151 G36
5 5.5
160
fSW = 300kHz
fSW = 1MHz
fSW = 2MHz
SWITCHING FREQUENCY (kHz)
0
140
160
200
1500
31151 G37
120
100
500 1000 2000
80
60
180
MINIMUM LOW TIME (ns)
VCC = 2.7V
VCC = 4.4V
SWITCHING FREQUENCY (kHz)
0
MAXIMUM DUTY CYCLE (%)
92
93
2000
31151 G38
91
90 500 1000 1500
95
94
Power Switch Resistance
vs VCC FB Voltage vs Temperature
VCC (V)
2.5
140
POWER SWITCH (A-D) RESISTANCE (mΩ)
145
150
155
160
170
33.5 4 4.5
31151 G32
5 5.5
165
TEMPERATURE (°C)
–50
–1.0
CHANGE FROM 25°C (%)
–0.8
–0.4
–0.2
0
1.0
0.4
050
31151 G33
–0.6
0.6
0.8
0.2
100 150
LOAD CURRENT (A)
0
0
DIE TEMPERATURE CHANGE FROM AMBIENT (°C)
10
20
30
40
50
60
0.5 1 1.5 2
31151 G49
VIN = 36V
VIN = 24V
VIN = 12V
VIN = 6V
VIN = 3.6V
STANDARD DEMO PCB
L = 15µH MSS1048
LOAD CURRENT (A)
0
0
DIE TEMPERATURE CHANGE FROM AMBIENT (°C)
10
20
30
50
70
100
90
40
60
80
0.5 1 1.5
2
31151 G50
VIN = 36V
VIN = 24V
VIN = 12V
VIN = 6V
VIN = 3.6V
STANDARD DEMO PCB
L = 15µH MSS1048
LTC3115-1
10
Rev. C
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Die Temperature Rise vs Load
Current, VOUT = 12V, fSW = 750kHz
Load Transient (0A to 1A),
VIN = 24V, VOUT = 5V
Load Transient (0A to 1A),
VIN = 3.6V, VOUT = 5V
Output Voltage Ripple in
Burst Mode Operation,
VIN = 24V, VOUT = 5V
(TA = 25°C unless otherwise specified)
Phase-Locked Loop Acquisition,
VIN = 24V 1.2MHz Clock
Phase-Locked Loop Release,
VIN = 24V, 1.2MHz Clock
Soft-Start Waveforms
Burst Mode Operation to PWM
Mode Output Voltage Transient
Output Voltage Ripple in PWM
Mode, VIN = 24V, VOUT = 5V
VOUT
(200mV/DIV)
LOAD
CURRENT
(1A/DIV)
FRONT PAGE
APPLICATION 200µs/DIV 31151 G39
INDUCTOR
CURRENT
(1A/DIV)
VOUT
(200mV/DIV)
LOAD
CURRENT
(1A/DIV)
FRONT PAGE
APPLICATION 200µs/DIV 31151 G40
INDUCTOR
CURRENT
(2A/DIV)
VOUT
(50mV/DIV)
L = 15µH
COUT = 22µF
ILOAD = 25mA
20µs/DIV 31151 G41
INDUCTOR
CURRENT
(0.5A/DIV)
VOUT
(5mV/DIV)
L = 22µH
COUT = 22µF
ILOAD = 2A
fSW = 750kHz
1µs/DIV 31151 G43
INDUCTOR
CURRENT
(100mA/DIV)
VPWM/SYNC
(5V/DIV)
VOUT
(200mV/DIV)
FRONT PAGE
APPLICATION 50µs/DIV 31151 G45
INDUCTOR
CURRENT
(1A/DIV)
VPWM/SYNC
(5V/DIV)
VOUT
(200mV/DIV)
FRONT PAGE
APPLICATION 50µs/DIV 31151 G46
INDUCTOR
CURRENT
(1A/DIV)
VOUT
(2V/DIV)
VRUN
(5V/DIV)
VCC
(2V/DIV)
FRONT PAGE
APPLICATION
2ms/DIV
31151 G42
INDUCTOR
CURRENT
(1A/DIV)
VOUT
(200mV/DIV)
VPWM/SYNC
(5V/DIV)
FRONT PAGE
APPLICATION
500µs/DIV
31151 G44
INDUCTOR
CURRENT
(1A/DIV)
LOAD CURRENT (A)
0
0
DIE TEMPERATURE CHANGE FROM AMBIENT (°C)
10
20
30
50
70
80
40
60
0.5 1 1.5
2
31151 G51
VIN = 36V
VIN = 24V
VIN = 12V
VIN = 6V
STANDARD DEMO PCB
L = 15µH MSS1048
LTC3115-1
11
Rev. C
For more information www.analog.com
PIN FUNCTIONS
(DHD/FE)
RUN (Pin 1/Pin 2): Input to Enable and Disable the IC and
Set Custom Input UVLO Thresholds. The RUN pin can be
driven by an external logic signal to enable and disable
the IC. In addition, the voltage on this pin can be set by
a resistor divider connected to the input voltage in order
to provide an accurate undervoltage lockout threshold.
The IC is enabled if RUN exceeds 1.21V nominally. Once
enabled, a 0.5µA current is sourced by the RUN pin to pro-
vide hysteresis. To continuously enable the IC, this pin can
be tied directly to the input voltage. The RUN pin cannot
be forced more than 0.3V above VIN under any condition.
SW2 (Pin 2/Pin 3): Buck-Boost Converter Power Switch
Pin. This pin should be connected to one side of the buck-
boost inductor.
PVOUT (Pin 3/Pin 4): Buck-Boost Converter Power Output.
This pin should be connected to a low ESR capacitor with
a value of at least 10µF. The capacitor should be placed as
close to the IC as possible and should have a short return
path to ground. In applications with VOUT > 20V that are
subject to output overload or short-circuit conditions, it
is recommended that a Schottky diode be installed from
SW2 (anode) to PVOUT (cathode). In applications subject
to output short circuits through an inductive load, it is rec
-
ommended that a Schottky diode be installed from ground
(anode) to PVOUT (cathode) to limit the extent that PVOUT
is driven below ground during the short-circuit transient.
GND (Pins 4, 5/Pins 5, 6): Signal Ground. These pins are
the ground connections for the control circuitry of the IC
and must be tied to ground in the application.
VC (Pin 6/Pin 7): Error Amplifier Output. A frequency
compensation network must be connected between this
pin and FB to stabilize the voltage control loop.
FB (Pin 7/Pin 8): Feedback Voltage Input. A resistor
divider connected to this pin sets the output voltage
for the buck-boost converter. The nominal FB voltage is
1000mV. Care should be taken in the routing of connec-
tions to this pin in order to minimize stray coupling to the
switch pin traces.
RT (Pin 8/Pin 9): Oscillator Frequency Programming Pin.
A resistor placed between this pin and ground sets the
switching frequency of the buck-boost converter.
VCC (Pin 9/Pin 12): Low Voltage Supply Input for IC
Control Circuitry. This pin powers internal IC control cir-
cuitry and must be connected to the PV
CC
pin in the appli-
cation. A 4.7µF or larger bypass capacitor should be con-
nected between this pin and ground. The VCC and PVCC
pins must be connected together in the application.
VIN (Pin 10/Pin 13): Power Supply Connection for Internal
Circuitry and the VCC Regulator. This pin provides power
to the internal VCC regulator and is the input voltage sense
connection for the VIN divider. A 0.1µF bypass capacitor
should be connected between this pin and ground. The
bypass capacitor should be located as close to the IC as
possible and should have a short return path to ground.
PV
CC
(Pin 11/Pin 14): Internal V
CC
Regulator Output. This
pin is the output pin of the internal linear regulator that
generates the VCC rail from VIN. The PVCC pin is also the
supply connection for the power switch gate drivers. If
the trace connecting PVCC to VCC cannot be made short
in length, an additional bypass capacitor should be con-
nected between this pin and ground. The VCC and PVCC
pins must be connected together in the application.
BST2 (Pin 12/Pin 15): Flying Capacitor Pin for SW2. This
pin must be connected to SW2 through a 0.1µF capacitor.
This pin is used to generate the gate drive rail for power
switch D.
BST1 (Pin 13/Pin 16): Flying Capacitor Pin for SW1. This
pin must be connected to SW1 through a 0.1µF capacitor.
This pin is used to generate the gate drive rail for power
switch A.
PVIN (Pin 14/Pin 17): Power Input for the Buck-Boost
Converter. A 4.7µF or larger bypass capacitor should
be connected between this pin and ground. The bypass
capacitor should be located as close to the IC as possible
and should via directly down to the ground plane. When
powered through long leads or from a high ESR power
source, a larger bulk input capacitor (typically 47µF to
100µF) may be required.
SW1 (Pin 15/Pin 18): Buck-Boost Converter Power
Switch Pin. This pin should be connected to one side of
the buck-boost inductor.
LTC3115-1
12
Rev. C
For more information www.analog.com
PIN FUNCTIONS
(DHD/FE)
PWM/SYNC (Pin 16/Pin 19): Burst Mode/PWM Mode
Control Pin and Synchronization Input. Forcing this pin
high causes the IC to operate in fixed frequency PWM
mode at all loads using the internal oscillator at the fre-
quency set by the RT Pin. Forcing this pin low places the
IC into Burst Mode operation for improved efficiency at
light load and reduced standby current. If an external clock
signal is connected to this pin, the buck-boost converter
will synchronize its switching with the external clock
using fixed frequency PWM mode operation. The pulse
width (negative or positive) of the applied clock should
be at least 100ns. The maximum operating voltage for the
PWM/SYNC pin is 5.5V. The PWM/SYNC pin can be con-
nected to VCC to force it high continuously.
PGND (Exposed Pad Pin 17/Pins 1, 10, 11, 20, Exposed
Pad Pin 21): Power Ground Connections. These pins
should be connected to the power ground in the applica-
tion. The exposed pad is the power ground connection. It
must be soldered to the PCB and electrically connected
to ground through the shortest and lowest impedance
connection possible and to the PCB ground plane for
rated thermal performance.
BLOCK DIAGRAM
Pin numbers are shown for the DHD package only.
CURRENT
LIMIT
+
–
3A
DA
PGND
CB
PVOUT
REVERSE
CURRENT
LIMIT
+
–
–1.5A
ZERO
CURRENT
+
–
0A
3
VIN
PVCC*
10
11
BST2 12
BST1 13
VCC*
VCC
VIN
VIN
2.4V
0.5µA
9
SW2
2
GATE
DRIVES
PGND
SOFT-START
RAMP
1000mV
SW1
15
PVIN
14
FB
7
VC
REVERSE
BLOCKING
LDO
BANDGAP
REFERENCE
OVERTEMPERATURE
OSCILLATOR
MODE
SELECTION
1000mV
1.21V
PWM
CHIP
ENABLE
EXPOSED
PAD
BURST/PWM
(PWM MODE IF PWM/SYNC
IS HIGH OR SWITCHING)
VIN
÷
+
+
–
6
RT
8
PWM/SYNC
*PVCC AND VCC MUST BE CONNECTED TOGETHER IN THE APPLICATION
THE EXPOSED PAD IS AN ELECTRICAL CONNECTION AND MUST BE SOLDERED
TO THE BOARD AND ELECTRICALLY CONNECTED TO GROUND
16
INPUT UVLO
+
–
1.21V
PGND
GND
+
–
2.4V
VCC
UVLO
+
–
RUN
3115 BD
1
174
GND
5
LTC3115-1
13
Rev. C
For more information www.analog.com
OPERATION
INTRODUCTION
The LTC3115-1 is a monolithic buck-boost converter
that can operate with input and output voltages from as
low as 2.7V to as high as 40V. Four internal low resis-
tance N-channel DMOS switches minimize the size of the
application circuit and reduce power losses to maximize
efficiency. Internal high side gate drivers, which require
only the addition of two small external capacitors, further
simplify the design process. A proprietary switch control
algorithm allows the buck-boost converter to maintain out-
put voltage regulation with input voltages that are above,
below or equal to the output voltage. Transitions between
these operating modes are seamless and free of transients
and subharmonic switching. The LTC3115-1 can be con-
figured to operate over a wide range of switching frequen-
cies, from 100kHz to 2MHz, allowing applications to be
optimized for board area and efficiency. With its configu-
rability and wide operating voltage range, the LTC3115-1 is
ideally suited to a wide range of power systems especially
those requiring compatibility with a variety of input power
sources such as lead-acid batteries, USB ports, and indus-
trial supply rails as well as from power sources which have
wide or poorly controlled voltage ranges such as FireWire
and unregulated wall adapters.
The LTC3115-1 has an internal fixed-frequency oscillator
with a switching frequency that is easily set by a single
external resistor. In noise sensitive applications, the con-
verter can also be synchronized to an external clock via
the PWM/SYNC pin. The LTC3115-1 has been optimized
to reduce input current in shutdown and standby for appli-
cations which are sensitive to quiescent current draw,
such as battery-powered devices. In Burst Mode opera-
tion, the no-load standby current is only 50µA (typical)
and in shutdown the total supply current is reduced to
3µA (typical).
PWM MODE OPERATION
With the PWM/SYNC pin forced high or driven by an exter-
nal clock, the LTC3115-1 operates in a fixed-frequency
pulse width modulation (PWM) mode using a voltage
mode control loop. This mode of operation maximizes
the output current that can be delivered by the converter,
reduces output voltage ripple, and yields a low noise
fixed-frequency switching spectrum. A proprietary switch-
ing algorithm provides seamless transitions between
operating modes and eliminates discontinuities in the
average inductor current, inductor current ripple, and
loop transfer function throughout all regions of operation.
These advantages result in increased efficiency, improved
loop stability, and lower output voltage ripple in compari-
son to the traditional 4-switch buck-boost converter.
Figure1 shows the topology of the LTC3115-1 power stage
which is comprised of four N-channel DMOS switches and
their associated gate drivers. In PWM mode operation
both switch pins transition on every cycle independent
of the input and output voltage. In response to the error
amplifier output, an internal pulse width modulator gener-
ates the appropriate switch duty cycles to maintain regula-
tion of the output voltage.
When stepping down from a high input voltage to a lower
output voltage, the converter operates in buck mode and
switch D remains on for the entire switching cycle except
for the minimum switch low duration (typically 100ns).
During the switch low duration switch C is turned on which
forces SW2 low and charges the flying capacitor, C
BST2
, to
ensure that the voltage of the switch D gate driver supply
rail is maintained. The duty cycle of switches A and B are
adjusted to provide the appropriate buck mode duty cycle.
If the input voltage is lower than the output voltage, the
converter operates in boost mode. Switch A remains on
for the entire switching cycle except for the minimum
switch low duration (typically 100ns) while switches C
and D are modulated to maintain the required boost mode
Figure1. Power Stage Schematic
A
PVCC
BST1
CBST1 CBST2
L
BST2PVIN PVOUT
SW1 SW2
PVCC
PVCC PVCC
LTC3115-1
PGND PGND
31151 F01
B
D
C
LTC3115-1
14
Rev. C
For more information www.analog.com
OPERATION
duty cycle. The minimum switch low duration ensures
that flying capacitor CBST1 is charged sufficiently to main
-
tain the voltage on the BST1 rail.
Oscillator and Phase-Locked Loop
The LTC3115-1 operates from an internal oscillator with a
switching frequency that is configured by a single external
resistor between the RT pin and ground. For noise sensi-
tive applications, an internal phase-locked loop allows
the LTC3115-1 to be synchronized to an external clock
signal applied to the PWM/SYNC pin. The phase-locked
loop is only able to increase the frequency of the internal
oscillator to obtain synchronization. Therefore, the RT
resistor must be chosen to program the internal oscilla-
tor to a lower frequency than the frequency of the clock
applied to the PWM/SYNC pin. Sufficient margin must
be included to account for the frequency variation of the
external synchronization clock as well as the worst-case
variation in frequency of the internal oscillator. Whether
operating from its internal oscillator or synchronized to
an external clock signal, the LTC3115-1 is able to operate
with a switching frequency from 100kHz to 2MHz, provid-
ing the ability to minimize the size of the external com-
ponents and optimize the power conversion efficiency.
Error Amplifier and VIN Divider
The LTC3115-1 has an internal high gain operational
amplifier which provides frequency compensation of the
control loop that maintains output voltage regulation. To
ensure stability of this control loop, an external compen-
sation network must be installed in the application circuit.
A Type III compensation network as shown in Figure2 is
recommended for most applications since it provides the
flexibility to optimize the converter’s transient response
while simultaneously minimizing any DC error in the out-
put voltage.
As shown in Figure2, the error amplifier is followed by
an internal analog divider which adjusts the loop gain by
the reciprocal of the input voltage in order to minimize
loop-gain variation over changes in the input voltage.
This simplifies design of the compensation network and
optimizes the transient response over the entire range of
input voltages. Details on designing the compensation
network in LTC3115-1 applications can be found in the
Applications Information section of this data sheet.
Inductor Current Limits
The LTC3115-1 has two current limit circuits that are
designed to limit the peak inductor current to ensure that
the switch currents remain within the capabilities of the IC
during output short-circuit or overload conditions. The pri-
mary inductor current limit operates by injecting a current
into the feedback pin which is proportional to the extent
that the inductor current exceeds the current limit thresh-
old (typically 3A). Due to the high gain of the feedback
loop, this injected current forces the error amplifier output
to decrease until the average current through the induc-
tor is approximately reduced to the current limit thresh-
old. This current limit circuit maintains the error ampli-
fier in an active state to ensure a smooth recovery and
minimal overshoot once the current limit fault condition
is removed. However, the reaction speed of this current
limit circuit is limited by the dynamics of the error ampli-
fier. On a hard output short, it is possible for the inductor
current to increase substantially beyond the current limit
threshold before the average current limit has time to react
and reduce the inductor current. For this reason, there is a
second current limit circuit which turns off power switch
A if the current through switch A exceeds approximately
160% of the primary inductor current limit threshold. This
provides additional protection in the case of an instanta-
neous hard output short and provides time for the primary
current limit to react. In addition, if VOUT falls below 1.85V,
the inductor current limit is folded back to half its nominal
value in order to minimize power dissipation.
Figure2. Error Amplifier and Compensation Network
+
–
1000mV
31151 F02
LTC3115-1 VIN
VC
CFB
CPOLE
RFB
FB
RFF
VOUT
RTOP
RBOT
CFF ÷PWM
LTC3115-1
15
Rev. C
For more information www.analog.com
OPERATION
Reverse Current Limit
In PWM mode operation, the LTC3115-1 synchronously
switches all four power devices. As a result, in addition to
being able to supply current to the output, the converter
has the ability to actively conduct current away from the
output if that is necessary to maintain regulation. If the
output is held above regulation, this could result in large
reverse currents. This situation can occur if the output
of the LTC3115-1 is held up momentarily by another
supply as may occur during a power-up or power-down
sequence. To prevent damage to the part under such con-
ditions, the LTC3115-1 has a reverse current comparator
that monitors the current entering power switch D from
the load. If this current exceeds 1.5A (typical) switch D
is turned off for the remainder of the switching cycle in
order to prevent the reverse inductor current from reach-
ing unsafe levels.
Output Current Capability
The maximum output current that can be delivered by the
LTC3115-1 is dependent upon many factors, the most
significant being the input and output voltages. For VOUT
= 5V and V
IN
≥ 3.6V, the LTC3115-1 is able to support
up to a 1A load continuously. For VOUT = 12V and VIN ≥
12V, the LTC3115-1 is able to support up to a 2A load
continuously. Typically, the output current capability is
greatest when the input voltage is approximately equal
to the output voltage. At larger step-up voltage ratios, the
output current capability is reduced because the lower
duty cycle of switch D results in a larger inductor current
being needed to support a given load. Additionally, the
output current capability generally decreases at large step-
down voltage ratios due to higher inductor current ripple
which reduces the maximum attainable inductor current.
The output current capability can also be affected by
inductor characteristics. An inductor with large DC resis-
tance will degrade output current capability, particularly
in boost mode operation. Larger value inductors generally
maximize output current capability by reducing induc-
tor current ripple. In addition, higher switching frequen-
cies (especially above 750kHz) will reduce the maximum
output current that can be supplied (see the Typical
Performance Characteristics for details).
Burst Mode OPERATION
When the PWM/SYNC pin is held low, the buck-boost
converter employs Burst Mode operation using a vari-
able frequency switching algorithm that minimizes the
no-load input quiescent current and improves efficiency
at light load by reducing the amount of switching to the
minimum level required to support the load. The output
current capability in Burst Mode operation is substantially
lower than in PWM mode and is intended to support light
standby loads (typically under 50mA). Curves showing
the maximum Burst Mode load current as a function of
the input and output voltage can be found in the Electrical
Characteristics section of this data sheet. If the converter
load in Burst Mode operation exceeds the maximum Burst
Mode current capability, the output will lose regulation.
Each Burst Mode cycle is initiated when switches A and
C turn on producing a linearly increasing current through
the inductor. When the inductor current reaches the Burst
Mode current limit (1A typically) switches B and D are
turned on, discharging the energy stored in the inductor
into the output capacitor and load. Once the inductor cur-
rent reaches zero, all switches are turned off and the cycle
is complete. Current pulses generated in this manner are
repeated as often as necessary to maintain regulation of
the output voltage. In Burst Mode operation, the error
amplifier is not used but is instead placed in a low current
standby mode to reduce supply current and improve light
load efficiency.
SOFT-START
To minimize input current transients on power-up, the
LTC3115-1 incorporates an internal soft-start circuit with
a nominal duration of 9ms. The soft-start is implemented
by a linearly increasing ramp of the error amplifier refer-
ence voltage during the soft-start duration. As a result,
the duration of the soft-start period is largely unaffected
by the size of the output capacitor or the output regula-
tion voltage. Given the closed-loop nature of the soft-start
implementation, the converter is able to respond to load
transients that occur during the soft-start interval. The
soft-start period is reset by thermal shutdown and UVLO
events on both VIN and VCC.
LTC3115-1
16
Rev. C
For more information www.analog.com
OPERATION
VCC REGULATOR
An internal low dropout regulator generates the 4.45V
(nominal) VCC rail from VIN. The VCC rail powers the inter-
nal control circuitry and power device gate drivers of the
LTC3115-1. The V
CC
regulator is disabled in shutdown
to reduce quiescent current and is enabled by forcing
the RUN pin above its logic threshold. The VCC regula-
tor includes current limit protection to safeguard against
short circuiting of the VCC rail. For applications where the
output voltage is set to 5V, the VCC rail can be driven from
the output rail through a Schottky diode. Bootstrapping in
this manner can provide a significant efficiency improve-
ment, particularly at large voltage step down ratios, and
may also allow operation down to a lower input voltage.
The maximum operating voltage for the VCC pin is 5.5V.
When forcing V
CC
externally, care must be taken to ensure
that this limit is not exceeded.
UNDERVOLTAGE LOCKOUT
To eliminate erratic behavior when the input voltage is
too low to ensure proper operation, the LTC3115-1 incor-
porates internal undervoltage lockout (UVLO) circuitry.
There are two UVLO comparators, one that monitors VIN
and another that monitors VCC. The buck-boost converter
is disabled if either VIN or VCC falls below its respective
UVLO threshold. The input voltage UVLO comparator has
a falling threshold of 2.4V (typical). If the input voltage
falls below this level all switching is disabled until the
input voltage rises above 2.6V (nominal). The VCC UVLO
has a falling threshold of 2.4V. If VCC falls below this
threshold the buck-boost converter is prevented from
switching until VCC rises above 2.6V.
Depending on the particular application circuit it is pos-
sible that either of these UVLO thresholds could be the
factor limiting the minimum input operating voltage of
the LTC3115-1. The dominant factor depends on the volt-
age drop between VIN and VCC which is determined by
the dropout voltage of the VCC regulator and is propor-
tional to the total load current drawn from VCC. The load
current on the VCC regulator is principally generated by
the gate driver supply currents which are proportional to
operating frequency and generally increase with larger
input and output voltages. As a result, at higher switching
frequencies and higher input and output voltages the VCC
regulator dropout voltage will increase, making it more
likely that the VCC UVLO threshold could become the lim-
iting factor. Curves provided in the Typical Performance
Characteristics section of this data sheet show the typical
VCC current and can be used to estimate the VCC regulator
dropout voltage in a particular application. In applications
where VCC is bootstrapped (powered by VOUT or by an
auxiliary supply rail through a Schottky diode) the mini-
mum input operating voltage will be limited only by the
input voltage UVLO threshold.
RUN PIN COMPARATOR
In addition to serving as a logic-level input to enable the
IC, the RUN pin features an accurate internal compara-
tor allowing it to be used to set custom rising and falling
input undervoltage lockout thresholds with the addition
of an external resistor divider. When the RUN pin is driven
above its logic threshold (typically 0.8V) the VCC regulator
is enabled which provides power to the internal control
circuitry of the IC and the accurate RUN pin comparator
is enabled. If the RUN pin voltage is increased further
so that it exceeds the RUN comparator threshold (1.21V
nominal), the buck-boost converter will be enabled.
If the RUN pin is brought below the RUN comparator
threshold, the buck-boost converter will inhibit switching,
but the V
CC
regulator and control circuitry will remain
powered unless the RUN pin is brought below its logic
threshold. Therefore, in order to place the part in shut-
down and reduce the input current to its minimum level
(3µA typical) it is necessary to ensure that the RUN pin
is brought below the worst-case logic threshold (0.3V).
The RUN pin is a high voltage input and can be connected
directly to VIN to continuously enable the part when the
input supply is present. If the RUN pin is forced above
approximately 5V it will sink a small current as given by
the following equation:
IRUN ≅VRUN – 5V
5MΩ
With the addition of an external resistor divider as shown
in Figure3, the RUN pin can be used to establish a custom
LTC3115-1
17
Rev. C
For more information www.analog.com
OPERATION
input undervoltage lockout threshold. The buck-boost con-
verter is enabled when the RUN pin reaches 1.21V which
allows the rising UVLO threshold to be set via the resis-
tor divider ratio. Once the RUN pin reaches the threshold
voltage, the comparator switches and the buck-boost
converter is enabled. In addition, an internal 0.5µA (typi-
cal) current source is enabled which sources current out
of the RUN pin raising the RUN pin voltage away from
the threshold. In order to disable the part, VIN must be
reduced sufficiently to overcome the hysteresis generated
by this current as well as the 100mV hysteresis of the
RUN comparator. As a result, the amount of hysteresis can
be independently programmed without affecting the rising
UVLO threshold by scaling the values of both resistors.
THERMAL CONSIDERATIONS
The power switches in the LTC3115-1 are designed to
operate continuously with currents up to the internal cur-
rent limit thresholds. However, when operating at high
current levels there may be significant heat generated
within the IC. In addition, in many applications the VCC
regulator is operated with large input-to-output voltage
differentials resulting in significant levels of power dis-
sipation in its pass element which can add significantly to
the total power dissipated within the IC. As a result, care-
ful consideration must be given to the thermal environ-
ment of the IC in order to optimize efficiency and ensure
that the LTC3115-1 is able to provide its full-rated output
current. Specifically, the exposed die attach pad of both
the DHD and FE packages should be soldered to the PC
board and the PC board should be designed to maximize
the conduction of heat out of the IC package. This can be
accomplished by utilizing multiple vias from the die attach
pad connection to other PCB layers containing a large area
of exposed copper.
If the die temperature exceeds approximately 165°C, the
IC will enter overtemperature shutdown and all switching
will be inhibited. The part will remain disabled until the
die cools by approximately 10°C. The soft-start circuit is
re-initialized in overtemperature shutdown to provide a
smooth recovery when the fault condition is removed.
Figure3. Accurate RUN Pin Comparator
1.21V
0.8V
VIN
VIN
0.5µA
LTC3115-1
ENA
31151 F03
RUN
R1
R2
ENABLE
SWITCHING
INPUT LOGIC
THRESHOLD
ENABLE
VCC REGULATOR AND
CONTROL CIRCUITS
+
–
+
–
LTC3115-1
18
Rev. C
For more information www.analog.com
APPLICATIONS INFORMATION
The standard LTC3115-1 application circuit is shown
as the typical application on the front page of this data
sheet. The appropriate selection of external components is
dependent upon the required performance of the IC in each
particular application given considerations and trade-offs
such as PCB area, cost, output and input voltage, allowable
ripple voltage, efficiency and thermal considerations. This
section of the data sheet provides some basic guidelines
and considerations to aid in the selection of external com-
ponents and the design of the application circuit.
VCC Capacitor Selection
The VCC output on the LTC3115-1 is generated from the
input voltage by an internal low dropout regulator. The VCC
regulator has been designed for stable operation with a
wide range of output capacitors. For most applications,
a low ESR ceramic capacitor of at least 4.7µF should be
utilized. The capacitor should be placed as close to the
pin as possible and should connect to the PVCC pin and
ground through the shortest traces possible. The PV
CC
pin is the regulator output and is also the internal supply
pin for the gate drivers and boost rail charging diodes.
The VCC pin is the supply connection for the remainder
of the control circuitry. The PVCC and VCC pins must be
connected together on the application PCB. If the trace
connecting VCC to PVCC cannot be made via a short con-
nection, an additional 0.1µF bypass capacitor should be
placed between the VCC pin and ground using the shortest
connections possible.
Inductor Selection
The choice of inductor used in LTC3115-1 application
circuits influences the maximum deliverable output cur-
rent, the magnitude of the inductor current ripple, and
the power conversion efficiency. The inductor must have
low DC series resistance or output current capability and
efficiency will be compromised. Larger inductance values
reduce inductor current ripple and will therefore gener-
ally yield greater output current capability. For a fixed DC
resistance, a larger value of inductance will yield higher
efficiency by reducing the peak current to be closer to the
average output current and therefore minimize resistive
losses due to high RMS currents. However, a larger induc-
tor value within any given inductor family will generally
have a greater series resistance, thereby counteracting
this efficiency advantage. In general, inductors with larger
inductance values and lower DC resistance will increase
the deliverable output current and improve the efficiency
of LTC3115-1 applications.
An inductor used in LTC3115-1 applications should have
a saturation current rating that is greater than the worst-
case average inductor current plus half the ripple current.
The peak-to-peak inductor current ripple for each opera-
tional mode can be calculated from the following formula,
where f is the switching frequency, L is the inductance,
and tLOW is the switch pin minimum low time. The switch
pin minimum low time can be determined from curves
given in the Typical Performance Characteristics section
of this data sheet.
∆IL(P-P)(BUCK)=VOUT
L
VIN – VOUT
VIN
1
f– tLOW
∆IL(P-P)(BOOST) =VIN
L
VOUT – VIN
V
OUT
1
f– tLOW
In addition to its influence on power conversion efficiency,
the inductor DC resistance can also impact the maximum
output current capability of the buck-boost converter par-
ticularly at low input voltages. In buck mode, the output
current of the buck-boost converter is generally limited
only by the inductor current reaching the current limit
threshold. However, in boost mode, especially at large
step-up ratios, the output current capability can also be
limited by the total resistive losses in the power stage.
These include switch resistances, inductor resistance, and
PCB trace resistance. Use of an inductor with high DC
resistance can degrade the output current capability from
that shown in the Typical Performance Characteristics sec-
tion of this data sheet. As a guideline, in most applications
the inductor DC resistance should be significantly smaller
than the typical power switch resistance of 150mΩ.
Different inductor core materials and styles have an impact
on the size and price of an inductor at any given current
rating. Shielded construction is generally preferred as it
minimizes the chances of interference with other circuitry.
The choice of inductor style depends upon the price, siz-
ing, and EMI requirements of a particular application.
LTC3115-1
19
Rev. C
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APPLICATIONS INFORMATION
Table1 provides a small sampling of inductors that are
well suited to many LTC3115-1 applications.
In applications with VOUT ≥ 20V, it is recommended that
a minimum inductance value, LMIN, be utilized where f is
the switching frequency:
LMIN =12H
f /Hz
(
)
Table1. Representative Surface Mount Inductors
PART NUMBER
VALUE
(µH)
DCR
(mΩ)
MAX DC
CURRENT (A)
SIZE (mm)
W × L × H
Coilcraft
LPS6225
LPS6235
MSS1038
D03316P
4.7
6.8
22
15
65
75
70
50
3.2
2.8
3.3
3.0
6.2 × 6.2 × 2.5
6.2 × 6.2 × 3.5
10.2 × 10.5 × 3.8
12.9 × 9.4 × 5.2
Cooper-Bussmann
CD1-150-R
DR1030-100-R
FP3-8R2-R
DR1040-220-R
15
10
8.2
22
50
40
74
54
3.6
3.18
3.4
2.9
10.5 × 10.4 × 4.0
10.3 × 10.5 × 3.0
7.3 × 6.7 × 3.0
10.3 × 10.5 × 4.0
Panasonic
ELLCTV180M
ELLATV100M
18
10
30
23
3.0
3.3
12 × 12 × 4.2
10 × 10 × 4.2
Sumida
CDRH8D28/HP
CDR10D48MNNP
CDRH8D28NP
10
39
4.7
78
105
24.7
3.0
3.0
3.4
8.3 × 8.3 × 3
10.3 × 10.3 × 5
8.3 × 8.3 × 3
Taiyo-Yuden
NR10050T150M
15
46
3.6
9.8 × 9.8 × 5
TOKO
B1047AS-6R8N
B1179BS-150M
892NAS-180M
6.8
15
18
36
56
42
2.9
3.3
3.0
7.6 × 7.6 × 5
10.3 × 10.3 × 4
12.3 × 12.3 × 4.5
Würth
7447789004
744771133
744066150
4.7
33
15
33
49
40
2.9
2.7
3.2
7.3 × 7.3 × 3.2
12 × 12 × 6
10 × 10 × 3.8
is the capacitance, tLOW is the switch pin minimum low
time, and ILOAD is the output current. Curves for the value
of t
LOW
as a function of switching frequency and tempera-
ture can be found in Typical Performance Characteristics
section of this data sheet.
∆VP-P(BUCK) =ILOADtLOW
COUT
∆VP-P(BOOST) =ILOAD
fCOUT
VOUT – VIN +tLOWfVIN
VOUT
The output voltage ripple increases with load current and
is generally higher in boost mode than in buck mode.
These expressions only take into account the output volt-
age ripple that results from the output current being dis-
continuous. They provide a good approximation to the
ripple at any significant load current but underestimate
the output voltage ripple at very light loads where output
voltage ripple is dominated by the inductor current ripple.
In addition to output voltage ripple generated across the
output capacitance, there is also output voltage ripple
produced across the internal resistance of the output
capacitor. The ESR-generated output voltage ripple is pro-
portional to the series resistance of the output capacitor
and is given by the following expressions where RESR is
the series resistance of the output capacitor and all other
terms are as previously defined.
∆VP-P(BUCK) =ILOADRESR
1– tLOWf≅ILOADRESR
∆VP-P(BOOST) =ILOADRESRVOUT
VIN 1– tLOWf
(
)
≅ILOADRESR VOUT
VIN
Input Capacitor Selection
The PVIN pin carries the full inductor current and provides
power to internal control circuits in the IC. To minimize
input voltage ripple and ensure proper operation of the IC,
a low ESR bypass capacitor with a value of at least 4.7µF
should be located as close to this pin as possible. The
traces connecting this capacitor to PVIN and the ground
plane should be made as short as possible. The VIN pin
provides power to the VCC regulator and other internal
circuitry. If the PCB trace connecting VIN to PVIN is long, it
Output Capacitor Selection
A low ESR output capacitor should be utilized at the buck-
boost converter output in order to minimize output volt-
age ripple. Multilayer ceramic capacitors are an excellent
option as they have low ESR and are available in small
footprints. The capacitor value should be chosen large
enough to reduce the output voltage ripple to acceptable
levels. Neglecting the capacitor ESR and ESL, the peak-
to-peak output voltage ripple can be calculated by the fol-
lowing formulas, where f is the switching frequency, COUT
LTC3115-1
20
Rev. C
For more information www.analog.com
APPLICATIONS INFORMATION
may be necessary to add an additional small value bypass
capacitor near the VIN pin.
When powered through long leads or from a high ESR
power source, a larger value bulk input capacitor may
be required. In such applications, a 47µF to 100µF elec-
trolytic capacitor in parallel with a 1µF ceramic capacitor
generally yields a high performance, low cost solution.
Recommended Input and Output Capacitors
The capacitors used to filter the input and output of the
LTC3115-1 must have low ESR and must be rated to
handle the large AC currents generated by switching con-
verters. This is important to maintain proper functioning
of the IC and to reduce output voltage ripple. There are
many capacitor types that are well suited to such appli-
cations including multilayer ceramic, low ESR tantalum,
OS-CON and POSCAP technologies. In addition, there
are certain types of electrolytic capacitors such as solid
aluminum organic polymer capacitors that are designed
for low ESR and high AC currents and these are also well
suited to LTC3115-1 applications (Table2). The choice of
capacitor technology is primarily dictated by a trade-off
between cost, size and leakage current. Notice that some
capacitors such as the OS-CON and POSCAP technolo-
gies can exhibit significant DC leakage currents which
may limit their applicability in devices which require low
no-load quiescent current in Burst Mode operation.
Ceramic capacitors are often utilized in switching con-
verter applications due to their small size, low ESR, and
low leakage currents. However, many ceramic capacitors
designed for power applications experience significant
loss in capacitance from their rated value with increased
DC bias voltages. For example, it is not uncommon for
a small surface mount ceramic capacitor to lose more
than 50% of its rated capacitance when operated near
its rated voltage. As a result, it is sometimes necessary
to use a larger value capacitance or a capacitor with a
higher voltage rating than required in order to actually
realize the intended capacitance at the full operating volt-
age. To ensure that the intended capacitance is realized
in the application circuit, be sure to consult the capacitor
vendor’s curve of capacitance versus DC bias voltage.
Table2. Representative Bypass and Output Capacitors
MANUFACTURER,
PART NUMBER
VALUE
(µF)
VOLTAGE
(V)
SIZE L × W × H (mm),
TYPE, ESR
AVX
12103D226MAT2A 22 25 3.2 × 2.5 × 2.79
X5R Ceramic
TPME226K050R0075 22 50 7.3 × 4.3 × 4.1
Tantalum, 75mΩ
Kemet
C2220X226K3RACTU 22 25 5.7 × 5.0 × 2.4
X7R Ceramic
A700D226M016ATE030 22 16 7.3 × 4.3 × 2.8
Alum. Polymer, 30mΩ
Murata
GRM32ER71E226KE15L
22 25 3.2 × 2.5 × 2.5
X7R Ceramic
Nichicon
PLV1E121MDL1 82 25 8 × 8 × 12
Alum. Polymer, 25mΩ
Panasonic
ECJ-4YB1E226M 22 25 3.2 × 2.5 × 2.5
X5R Ceramic
Sanyo
25TQC22MV 22 25 7.3 × 4.3 × 3.1
POSCAP, 50mΩ
16TQC100M 100 16 7.3 × 4.3 × 1.9
POSCAP, 45mΩ
25SVPF47M 47 25 6.6 × 6.6 × 5.9
OS-CON, 30mΩ
Taiyo Yuden
UMK325BJ106MM-T 10 50 3.2 × 2.5 × 2.5
X5R Ceramic
TMK325BJ226MM-T 22 25 3.2 × 2.5 × 2.5
X5R Ceramic
TDK
KTJ500B226M55BFT00 22 50 6.0 × 5.3 × 5.5
X7R Ceramic
C5750X7R1H106M 10 50 5.7 × 5.0 × 2.0
X7R Ceramic
CKG57NX5R1E476M 47 25 6.5 × 5.5 × 5.5
X5R Ceramic
Vishay
94SVPD476X0035F12 47 35 10.3 × 10.3 × 12.6
OS-CON, 30mΩ
LTC3115-1
21
Rev. C
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APPLICATIONS INFORMATION
Programming Custom Input UVLO Thresholds
With the addition of an external resistor divider connected
to the input voltage as shown in Figure4, the RUN pin
can be used to program the input voltage at which the
LTC3115-1 is enabled and disabled.
For a rising input voltage, the LTC3115-1 is enabled when V
IN
reaches the threshold given by the following equation, where
R1 and R2 are the values of the resistor divider resistors:
VTH(RISING) =1.21V R1+R2
R2
To ensure robust operation in the presence of noise, the
RUN pin has two forms of hysteresis. A fixed 100mV
of hysteresis within the RUN pin comparator provides a
minimum RUN pin hysteresis equal to 8.3% of the input
turn-on voltage independent of the resistor divider values.
In addition, an internal hysteresis current that is sourced
from the RUN pin during operation generates an additive
level of hysteresis which can be programmed by the value
of R1 to increase the overall hysteresis to suit the require-
ments of specific applications.
Once the IC is enabled, it will remain enabled until the
input voltage drops below the comparator threshold by
the hysteresis voltage, VHYST
, as given by the follow-
ing equation where R1 and R2 are values of the divider
resistors:
VHYST = R1•0.5µA+ R1+R2
R2
0.1V
Therefore, the rising UVLO threshold and amount of hys-
teresis can be independently programmed via appropriate
selection of resistors R1 and R2. For high levels of hyster-
esis, the value of R1 can become larger than is desirable
in a practical implementation (greater than 1MΩ to 2MΩ).
In such cases, the amount of hysteresis can be increased
further through the addition of an additional resistor, RH,
as shown in Figure5.
When using the additional RH resistor, the rising RUN pin
threshold remains as given by the original equation and
the hysteresis is given by the following expression:
VHYST =R1+R2
R2
0.1V+ RHR2+RHR1+R1R2
R2 0.5µA
(
)
Figure4. Setting the Input UVLO Threshold and Hysteresis
Figure5. Increasing Input UVLO hysteresis
LTC3115-1
GND
VIN
RUN
R1
R2
31151 F04
LTC3115-1
GND
VIN
RUN
R1 RH
R2
3115 F05
To improve the noise robustness and accuracy of the
UVLO thresholds, the RUN pin input can be filtered by
adding a 1000pF capacitor from RUN to GND. Larger val-
ued capacitors should not be utilized because they could
interfere with operation of the hysteresis.
Bootstrapping the VCC Regulator
The high and low side gate drivers are powered through the
PVCC rail which is generated from the input voltage through
an internal linear regulator. In some applications, especially
at higher operating frequencies and high input and output
voltages, the power dissipation in the linear V
CC
regulator
can become a key factor in the conversion efficiency of the
converter and can even become a significant source of ther-
mal heating. For example, at a 1.2MHz switching frequency,
an input voltage of 36V, and an output voltage of 24V, the
total PVCC/VCC current is approximately 18mA as shown in
the Typical Performance Characteristics section of this data
sheet. As a result, this will generate 568mW of power dissipa-
tion in the VCC regulator which will result in an increase in die
temperature of approximately 24° above ambient in the DFN
package. This significant power loss will have a substantial
impact on the conversion efficiency and the additional heating
may limit the maximum ambient operating temperature for
the application.
LTC3115-1
22
Rev. C
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APPLICATIONS INFORMATION
A significant performance advantage can be attained in
applications which have the converter output voltage pro-
grammed to 5V if the output voltage is utilized to power
the PVCC and VCC rails. This can be done by connect-
ing a Schottky diode from V
OUT
to PV
CC
/V
CC
as shown
in Figure6. With this bootstrap diode installed, the gate
driver currents are generated directly by the buck-boost
converter at high efficiency rather than through the inter-
nal linear regulator. To minimize current drawn from the
output, the internal VCC regulator contains reverse block-
ing circuitry which minimizes the current into the PVCC/
VCC pins when they are driven above the input voltage.
The gain term, G
BUCK
, is comprised of three different com-
ponents: the gain of the analog divider, the gain of the pulse
width modulator, and the gain of the power stage as given
by the following expressions where V
IN
is the input voltage
to the converter, f is the switching frequency, R is the load
resistance, and tLOW is the switch pin minimum low time.
Curves showing the switch pin minimum low time can be
found in the Typical Performance Characteristics section of
this data sheet. The parameter RS represents the average
series resistance of the power stage and can be approxi-
mated as twice the average power switch resistance plus
the DC resistance of the inductor.
GBUCK = GDIVIDER GPWMGPOWER
GDIVIDER =19.8V
VIN
GPWM =3
2V 1– tLOWf
( )
GPOWER =VINR
1– tLOWf
( )
R+RS
( )
Notice that the gain of the analog divider cancels the input
voltage dependence of the power stage. As a result, the
buck mode gain is well approximated by a constant as
given by the following equation:
GBUCK = 29.7
R
R+R
S
≅29.7= 29.5dB
The buck mode transfer function has a single zero which
is generated by the ESR of the output capacitor. The zero
frequency, fZ, is given by the following expression where
RC and CO are the ESR and value of the output filter capac-
itor respectively.
fZ=
1
2π R
C
C
O
In most applications, an output capacitor with a very low
ESR is utilized in order to reduce the output voltage ripple
to acceptable levels. Such low values of capacitor ESR
result in a very high frequency zero and as a result the
zero is commonly too high in frequency to significantly
impact compensation of the feedback loop.
Figure6. Bootstrapping PVCC and VCC
VOUT
4.7µF 31151 F06
PVOUT
LTC3115-1
VCC
PVCC
Buck Mode Small-Signal Model
The LTC3115-1 uses a voltage mode control loop to
maintain regulation of the output voltage. An externally
compensated error amplifier drives the VC pin to generate
the appropriate duty cycle of the power switches. Use of
an external compensation network provides the flexibility
for optimization of closed loop performance over the wide
variety of output voltages, switching frequencies, and
external component values supported by the LTC3115-1.
The small-signal transfer function of the buck-boost con-
verter is different in the buck and boost modes of opera-
tion and care must be taken to ensure stability in both
operating regions. When stepping down from a higher
input voltage to a lower output voltage, the converter
will operate in buck mode and the small-signal transfer
function from the error amplifier output, VC, to the con-
verter output voltage is given by the following equation:
VO
VCBUCKMODE
=GBUCK
1+ s
2πfZ
1+ s
2πfOQ+s
2πfO
2
LTC3115-1
23
Rev. C
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APPLICATIONS INFORMATION
The denominator of the buck mode transfer function
exhibits a pair of resonant poles generated by the LC
filtering of the power stage. The resonant frequency of
the power stage, fO, is given by the following expression
where L is the value of the inductor:
fO=1
2π
R+RS
LCOR+RC
(
)
≅1
2π
1
LCO
The quality factor, Q, has a significant impact on compen-
sation of the voltage loop since a higher Q factor produces
a sharper loss of phase near the resonant frequency. The
quality factor is inversely related to the amount of damp-
ing in the power stage and is substantially influenced
by the average series resistance of the power stage, RS.
Lower values of R
S
will increase the Q and result in a
sharper loss of phase near the resonant frequency and will
require more phase boost or lower bandwidth to maintain
an adequate phase margin.
Q = LCOR+RC
(
)
R+RS
(
)
RRCCO+L +CORSR +RC
(
)
≅LCO
L
R
+CORS
Boost Mode Small-Signal Model
When stepping up from a lower input voltage to a higher
output voltage, the buck-boost converter will operate in
boost mode where the small-signal transfer function from
control voltage, VC, to the output voltage is given by the
following expression.
VO
VCBOOSTMODE
=GBOOST
1+ s
2πfZ
1– s
2πfRHPZ
1+ s
2πfOQ+s
2πfO
2
In boost mode operation, the transfer function is charac-
terized by a pair of resonant poles and a zero generated by
the ESR of the output capacitor as in buck mode. However,
in addition there is a right half plane zero which generates
increasing gain and decreasing phase at higher frequen-
cies. As a result, the crossover frequency in boost mode
operation generally must be set lower than in buck mode
in order to maintain sufficient phase margin.
The boost mode gain, GBOOST
, is comprised of three com-
ponents: the analog divider, the pulse width modulator
and the power stage. The gain of the analog divider and
PWM remain the same as in buck mode operation, but
the gain of the power stage in boost mode is given by the
following equation:
GPOWER ≅VOUT2
1– t
LOW
f
(
)
VIN
By combining the individual terms, the total gain in boost
mode can be reduced to the following expression. Notice
that unlike in buck mode, the gain in boost mode is a
function of both the input and output voltage.
GBOOST ≅29.7VOUT2
V
IN
2
In boost mode operation, the frequency of the right half
plane zero, fRHPZ, is given by the following expression.
The frequency of the right half plane zero decreases at
higher loads and with larger inductors.
fRHPZ =R 1– tLOW f
(
)
2VIN2
2π L V
OUT
2
In boost mode, the resonant frequency of the power
stage has a dependence on the input and output voltage
as shown by the following equation.
fO=1
2π
RS+RVIN2
VOUT2
LCOR +RC
(
)
≅1
2π •VIN
VOUT
1
LC
Finally, the magnitude of the quality factor of the power
stage in boost mode operation is given by the following
expression.
Q=
LCOR RS+RVIN2
VOUT2
L+CORSR
LTC3115-1
24
Rev. C
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APPLICATIONS INFORMATION
Compensation of the Voltage Loop
The small-signal models of the LTC3115-1 reveal that the
transfer function from the error amplifier output, VC, to
the output voltage is characterized by a set of resonant
poles and a possible zero generated by the ESR of the
output capacitor as shown in the Bode plot of Figure7.
In boost mode operation, there is an additional right half
plane zero that produces phase lag and increasing gain at
higher frequencies. Typically, the compensation network
is designed to ensure that the loop crossover frequency is
low enough that the phase loss from the right half plane
zero is minimized. The low frequency gain in buck mode
is a constant, but varies with both VIN and VOUT in boost
mode.
In most applications, the low bandwidth of the Type I
compensated loop will not provide sufficient transient
response performance. To obtain a wider bandwidth feed-
back loop, optimize the transient response, and minimize
the size of the output capacitor, a Type III compensation
network as shown in Figure9 is required.
GAIN
PHASE
BOOST MODE
BUCK MODE
–20dB/DEC
–40dB/DEC
fO
f
31151 F07
fRHPZ
0°
–90°
–180°
–270°
Figure7. Buck-Boost Converter Bode Plot
Figure8. Error Amplifier with Type I Compensation
Figure9. Error Amplifier with Type III Compensation
For charging or other applications that do not require an
optimized output voltage transient response, a simple
Type I compensation network as shown in Figure8 can
be used to stabilize the voltage loop. To ensure sufficient
phase margin, the gain of the error amplifier must be
low enough that the resultant crossover frequency of the
control loop is well below the resonant frequency.
+
–
C1
GND
LTC3115-1
VC
31151 F08
FB
VOUT
RBOT
RTOP 1000mV
CFB RFB
GND
LTC3115-1
VC
31151 F09
FB
VOUT
RBOT
RTOP
RFF
CFF 1000mV
CPOLE
+
–
A Bode plot of the typical Type III compensation network
is shown in Figure10. The Type III compensation network
provides a pole near the origin which produces a very high
loop gain at DC to minimize any steady-state error in the
regulation voltage. Two zeros located at fZERO1 and fZERO2
provide sufficient phase boost to allow the loop crossover
frequency to be set above the resonant frequency, fO, of
the power stage. The Type III compensation network also
introduces a second and third pole. The second pole, at
frequency fPOLE2, reduces the error amplifier gain to a
zero slope to prevent the loop crossover from extending
too high in frequency. The third pole at frequency fPOLE3
provides attenuation of high frequency switching noise.
LTC3115-1
25
Rev. C
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APPLICATIONS INFORMATION
The transfer function of the compensated Type III error
amplifier from the input of the resistor divider to the out-
put of the error amplifier, VC, is:
VC(s)
VOUT(s) = GEA
1+ s
2πfZERO1
1+ s
2πfZERO2
s 1+ s
2πfPOLE2
1+ s
2πfPOLE3
The error amplifier gain is given by the following equation.
The simpler approximate value is sufficiently accurate in
most cases since C
FB
is typically much larger in value
than CPOLE.
GEA =
1
RTOP CFB +CPOLE
(
)
≅
1
RTOPCFB
The pole and zero frequencies of the Type III compensa-
tion network can be calculated from the following equa-
tions where all frequencies are in Hz, resistances are in
ohms, and capacitances are in farads.
fZERO1=
1
2π RFBCFB
fZERO2 =1
2π RTOP +RFF
(
)
CFF
≅1
2π RTOPCFF
fPOLE2 =CFB +CPOLE
2πCFBCPOLERFB
≅1
2π CPOLERFB
fPOLE3 =1
2πCFFRFF
In most applications the compensation network is
designed so that the loop crossover frequency is above
the resonant frequency of the power stage, but sufficiently
below the boost mode right half plane zero to minimize
the additional phase loss. Once the crossover frequency is
decided upon, the phase boost provided by the compen-
sation network is centered at that point in order to maxi-
mize the phase margin. A larger separation in frequency
between the zeros and higher order poles will provide a
higher peak phase boost but may also increase the gain of
the error amplifier which can push out the loop crossover
to a higher frequency.
The Q of the power stage can have a significant influence on
the design of the compensation network because it deter-
mines how rapidly the 180° of phase loss in the power
stage occurs. For very low values of series resistance, RS,
the Q will be higher and the phase loss will occur sharply.
In such cases, the phase of the power stage will fall rapidly
to –180° above the resonant frequency and the total phase
margin must be provided by the compensation network.
However, with higher losses in the power stage (larger RS)
the Q factor will be lower and the phase loss will occur more
gradually. As a result, the power stage phase will not be as
close to –180° at the crossover frequency and less phase
boost is required of the compensation network.
The LTC3115-1 error amplifier is designed to have a
fixed maximum bandwidth in order to provide rejection
of switching noise to prevent it from interfering with the
control loop. From a frequency domain perspective, this
can be viewed as an additional single pole as illustrated in
Figure11. The nominal frequency of this pole is 300kHz.
For typical loop crossover frequencies below about 50kHz
the phase contributed by this additional pole is negligible.
However, for loops with higher crossover frequencies this
additional phase loss should be taken into account when
designing the compensation network.
Figure10. Type III Compensation Bode Plot
fZERO1
PHASE
90°
–90°
0°
GAIN
–20dB/DEC
–20dB/DEC
fZERO2
31151 F10
f
fPOLE2 fPOLE3
Figure11. Internal Loop Filter
+
–
1000mV
FB
LTC3115-1
VC
RFILT
CFILT
31151 F11
INTERNAL
VC
LTC3115-1
26
Rev. C
For more information www.analog.com
APPLICATIONS INFORMATION
Loop Compensation Example
This section provides an example illustrating the design of
a compensation network for a typical LTC3115-1 applica-
tion circuit. In this example a 5V regulated output volt-
age is generated with the ability to supply a 500mA load
from an input power source ranging from 3.5V to 30V.
To reduce switching losses a 750kHz switching frequency
has been chosen for this example. In this application the
maximum inductor current ripple will occur at the high-
est input voltage. An inductor value of 8.2µH has been
chosen to limit the worst-case inductor current ripple to
approximately 600mA. A low ESR output capacitor with
a value of 20µF is specified to yield a worst-case output
voltage ripple (occurring at the worst-case step-up ratio
and maximum load current) of approximately 12mV. In
summary, the key power stage specifications for this
LTC3115-1 example application are given below.
f = 0.75MHz, tLOW = 0.1µs
VIN = 3.5V to 30V
VOUT = 5V at 500mA
COUT = 20µF, RC = 10mΩ
L = 8.2µH, RL = 45mΩ
With the power stage parameters specified, the compen-
sation network can be designed. In most applications, the
most challenging compensation corner is boost mode
operation at the greatest step-up ratio and highest load
current since this generates the lowest frequency right
half plane zero and results in the greatest phase loss.
Therefore, a reasonable approach is to design the com-
pensation network at this worst-case corner and then
verify that sufficient phase margin exists across all other
operating conditions. In this example application, at VIN =
3.5V and the full 500mA load current, the right half plane
zero will be located at 81kHz and this will be a dominant
factor in determining the bandwidth of the control loop.
The first step in designing the compensation network
is to determine the target crossover frequency for the
compensated loop. A reasonable starting point is to
assume that the compensation network will generate a
peak phase boost of approximately 60°. Therefore, in
order to obtain a phase margin of 60°, the loop cross-
over frequency, fC, should be selected as the frequency
at which the phase of the buck-boost converter reaches
–180°. As a result, at the loop crossover frequency the
total phase will be simply the 60° of phase provided by
the error amplifier as shown:
Phase Margin = φBUCK-BOOST + φERRORAMPLIFIER + 180°
= –180° + 60° + 180° = 60°
Similarly, if a phase margin of 45° is required, the target
crossover frequency should be picked as the frequency
at which the buck-boost converter phase reaches –195°
so that the combined phase at the crossover frequency
yields the desired 45° of phase margin.
This example will be designed for a 60° phase margin
to ensure adequate performance over parametric varia-
tions and varying operating conditions. As a result, the
target crossover frequency, fC, will be the point at which
the phase of the buck-boost converter reaches –180°.
It is generally difficult to determine this frequency ana-
lytically given that it is significantly impacted by the Q
factor of the resonance in the power stage. As a result,
it is best determined from a Bode plot of the buck-boost
converter as shown in Figure12. This Bode plot is for the
LTC3115-1 buck-boost converter using the previously
specified power stage parameters and was generated
from the small-signal model equations using LTspice
®
software. In this case, the phase reaches –180° at 24kHz
making fC = 24kHz the target crossover frequency for the
compensated loop.
From the Bode plot of Figure12 the gain of the power
stage at the target crossover frequency is 19dB. Therefore,
in order to make this frequency the crossover frequency
in the compensated loop, the total loop gain at fC must
be adjusted to 0dB. To achieve this, the gain of the com-
pensation network must be designed to be –19dB at the
crossover frequency.
LTC3115-1
27
Rev. C
For more information www.analog.com
APPLICATIONS INFORMATION
by the compensated error amplifier is determined simply
by the amount of separation between the poles and zeros
as shown by the following equation:
φMAX = 4 tan–1 fP
fZ
– 270°
A reasonable choice is to pick the frequency of the poles,
fP
, to be about 50 times higher than the frequency of the
zeros, fZ, which provides a peak phase boost of approxi-
mately φMAX = 60° as was assumed previously. Next, the
phase boost must be centered so that the peak phase
occurs at the target crossover frequency. The frequency
of the maximum phase boost, fCENTER, is the geometric
mean of the pole and zero frequencies as:
fCENTER = fP• fZ= 50 • fZ≅7 • fZ
Therefore, in order to center the phase boost given a fac-
tor of 50 separation between the pole and zero frequen-
cies, the zeros should be located at one seventh of the
crossover frequency and the poles should be located at
seven times the crossover frequency as given by the fol-
lowing equations:
fZ=1
7• fC=1
724kHz
(
)
= 3.43kHz
f
P
= 7 • f
C
= 7 24kHz
(
)
= 168kHz
This placement of the poles and zeros will yield a peak
phase boost of 60° that is centered at the crossover fre-
quency, fC. Next, in order to produce the desired target
crossover frequency, the gain of the compensation net-
work at the point of maximum phase boost, GCENTER,
must be set to –19dB. The gain of the compensated error
amplifier at the point of maximum phase gain is given by:
GCENTER = 10log 2πfP
2πfZ
( )
3RTOPCFB
( )
2
dB
At this point in the design process, there are three con-
straints that have been established for the compensation
network. It must have –19dB gain at fC = 24kHz, a peak
phase boost of 60° and the phase boost must be centered
at f
C
= 24kHz. One way to design a compensation network
to meet these targets is to simulate the compensated error
amplifier Bode plot in LTspice for the typical compensation
network shown on the front page of this data sheet. Then,
the gain, pole frequencies and zero frequencies can be
iteratively adjusted until the required constraints are met.
Alternatively, an analytical approach can be used to design
a compensation network with the desired phase boost,
center frequency and gain. In general, this procedure can
be cumbersome due to the large number of degrees of
freedom in a Type III compensation network. However the
design process can be simplified by assuming that both
compensation zeros occur at the same frequency, fZ, and
both higher order poles (fPOLE2 and fPOLE3) occur at the
common frequency, f
P
. In most cases this is a reasonable
assumption since the zeros are typically located between
1kHz and 10kHz and the poles are typically located
near each other at much higher frequencies. Given this
assumption, the maximum phase boost, fMAX, provided
Figure12. Converter Bode Plot, VIN = 3.5V, ILOAD = 500mA
FREQUENCY (Hz)
10
GAIN (dB)
PHASE (DEG)
0
10
20
10k 1M
31151 F12
–10
–20
–30 100 1k 100k
30
40
50
–200
–160
–120
–240
–280
–320
–80
–40
0
GAIN
PHASE
fC
LTC3115-1
28
Rev. C
For more information www.analog.com
APPLICATIONS INFORMATION
Assuming a multiple of 50 separation between the pole
frequencies and zero frequencies this can be simplified
to the following expression:
GCENTER = 20log 50
2πfCRTOPCFB
dB
This equation completes the set of constraints needed
to determine the compensation component values.
Specifically, the two zeros, fZERO1 and fZERO2, should be
located near 3.43kHz. The two poles, fPOLE2 and fPOLE3,
should be located near 168kHz and the gain should be set
to provide a gain at the crossover frequency of GCENTER
= –19dB.
The first step in defining the compensation component
values is to pick a value for RTOP that provides an accept-
ably low quiescent current through the resistor divider.
A value of RTOP = 1MΩ is a reasonable choice. Next, the
value of CFB can be found in order to set the error ampli-
fier gain at the crossover frequency to –19dB as follows:
GCENTER = –19.1dB
=20log 50
2π 24kHz
(
)
1MΩ
(
)
CFB
CFB =50
2π 24kHz
(
)
1MΩ
(
)
alog –19.1
20
≅3.0nF
The compensation poles can be set at 168kHz and the
zeros at 3.43kHz by using the expressions for the pole
and zero frequencies given in the previous section. Setting
the frequency of the first zero, fZERO1, to 3.43kHz results
in the following value for RFB:
RFB =1
2π 3nF
(
)
3.43kHz
(
)
≅15.4kΩ
This leaves the free parameter, CPOLE, to set the frequency
fPOLE1 to the common pole frequency of 168kHz as given:
CPOLE =1
2π 15.4kΩ
(
)
168kHz
(
)
≅62pF
Next, CFF can be chosen to set the second zero, fZERO2, to
the common zero frequency of 3.43kHz.
CFF =1
2π 1M Ω
(
)
3.43kHz
(
)
≅47 pF
Finally, the resistor value RFF can be chosen to place the
second pole at 168kHz.
RFF =1
2π 47pF
(
)
168Hz
(
)
≅20.0kΩ
Now that the pole frequencies, zero frequencies and gain
of the compensation network have been established, the
next step is to generate a Bode plot for the compensated
error amplifier to confirm its gain and phase properties.
A Bode plot of the error amplifier with the designed com-
pensation component values is shown in Figure13. The
Bode plot confirms that the peak phase occurs at 24kHz
and the phase boost at that point is 57.7°. In addition,
the gain at the peak phase frequency is –19.3dB which is
close to the design target.
FREQUENCY (Hz)
10
–40
GAIN (dB)
PHASE (DEG)
–30
–20
–10
0
100 1k 10k 100k
3115 F13
1M
10
–35
–25
–15
–5
5
15
–90
fC
–60
–30
0
30
60
GAIN
PHASE
90
Figure13. Compensated Error Amplifier Bode Plot
LTC3115-1
29
Rev. C
For more information www.analog.com
APPLICATIONS INFORMATION
The final step in the design process is to compute the
Bode plot for the entire loop using the designed com-
pensation network and confirm its phase margin and
crossover frequency. The complete loop Bode plot for
this example is shown in Figure14. The loop crossover
frequency is 22kHz which is close to the design target and
the phase margin is approximately 60°.
The Bode plot for the complete loop should be checked
over all operating conditions and for variations in compo-
nent values to ensure that sufficient phase margin exists
in all cases. The stability of the loop should also be con-
firmed via time domain simulation and by evaluating the
transient response of the converter in the actual circuit.
Output Voltage Programming
The output voltage is set via the external resistor divider
comprised of resistors R
TOP
and R
BOT
as show in Figure8
and Figure9. The resistor divider values determine the
output regulation voltage according to:
VOUT = 1.000V 1+ RTOP
RBOT
Figure14. Complete Loop Bode Plot
FREQUENCY (Hz)
10
–60
GAIN (dB)
PHASE (DEG)
–40
–20
0
20
40
60
–180
fC
–120
–60
0
60
GAIN
120
180
100 1k 10k 100k
31151 F14
1M
PHASE
In addition to setting the output voltage, the value of
RTOP is instrumental in controlling the dynamics of the
compensation network. When changing the value of this
resistor, care must be taken to understand the impact this
will have on the compensation network.
In addition, the Thevenin equivalent resistance of the
resistor divider controls the gain of the current limit. To
maintain sufficient gain in this loop, it is recommended
that the value of RTOP be chosen to be 1MΩ or larger.
Switching Frequency Selection
The switching frequency is set by the value of a resistor
connected between the RT pin and ground. The switching
frequency, f, is related to the resistor value by the follow-
ing equation where RT is the resistance:
f = 35.7MHz
R
T
/ kΩ
(
)
Higher switching frequencies facilitate the use of smaller
inductors as well as smaller input and output filter capaci-
tors which results in a smaller solution size and reduced
component height. However, higher switching frequencies
also generally reduce conversion efficiency due to the
increased switching losses.
In addition, higher switching frequencies (above 750kHz)
will reduce the maximum output current that can be sup-
plied (see Typical Performance Characteristics for details).
For applications with VOUT ≥ 20V, a maximum switching
frequency of 1MHz is recommended.
LTC3115-1
30
Rev. C
For more information www.analog.com
APPLICATIONS INFORMATION
PCB Layout Considerations
The LTC3115-1 buck-boost converter switches large cur-
rents at high frequencies. Special attention should be paid
to the PC board layout to ensure a stable, noise-free and
efficient application circuit. Figure16 and Figure17 show
a representative PCB layout for each package option to
outline some of the primary considerations. A few key
guidelines are provided below:
1. The parasitic inductance and resistance of all circulating
high current paths should be minimized. This can be
accomplished by keeping the routes to all bold compo-
nents in Figure16 and Figure17 as short and as wide
as possible. Capacitor ground connections should via
down to the ground plane by way of the shortest route
possible. The bypass capacitors on PVIN, PVOUT and
PVCC/VCC should be placed as close to the IC as possible
and should have the shortest possible paths to ground.
2. The exposed pad is the electrical power ground
connection for the LTC3115-1 in the DHD package.
Multiple vias should connect the backpad directly to
the ground plane. In addition, maximization of the met-
allization connected to the backpad will improve the
thermal environment and improve the power handling
capabilities of the IC in both the FE and DHD packages.
3. The components shown in bold and their connections
should all be placed over a complete ground plane to
minimize loop cross-sectional areas. This minimizes
EMI and reduces inductive drops.
4. Connections to all of the components shown in bold
should be made as wide as possible to reduce the
series resistance. This will improve efficiency and
maximize the output current capability of the buck-
boost converter.
5. To prevent large circulating currents in the ground plane
from disrupting operation of the LTC3115-1, all small-
signal grounds should return directly to GND by way
of a dedicated Kelvin route. This includes the ground
connection for the RT pin resistor, and the ground con-
nection for the feedback network as shown in Figure16
and Figure17.
6. Keep the routes connecting to the high impedance,
noise sensitive inputs FB and RT as short as possible
to reduce noise pick-up.
7. The BST1 and BST2 pins transition at the switching
frequency to the full input and output voltage respec-
tively. To minimize radiated noise and coupling, keep
the BST1 and BST2 routes as short as possible and
away from all sensitive circuitry and pins (VC, FB, RT).
In many applications the length of traces connecting to
the boost capacitors can be minimized by placing the
boost capacitors on the back side of the PC board and
routing to them via traces on an internal copper layer.
8 Connections from the BST1 and BST2 capacitors must
Kelvin directly back to the respective SW pin as shown
in Figure15.
THIS ROUTE MUST KELVIN CONNECT
DIRECTLY BACK TO THE SW2 PIN
0.1µF
31151 F15
SW2
LTC3115-1
BST2
Figure15. Kelvin BST Connections
9. If the optional Schottky diode from SW2 to PVOUT is
utilized, the Schottky should be placed as close to the
SW2 and PVOUT pins as possible and connected with
the shortest possible traces.
LTC3115-1
31
Rev. C
For more information www.analog.com
APPLICATIONS INFORMATION
Figure16. PCB Layout Recommended for the DHD Package
[16]
PWM/
SYNC
[15]
SW1
VIA TO GROUND PLANE
(AND TO INNER LAYER
WHERE SHOWN)
INNER PCB
LAYER ROUTES
VIN
UNINTERRUPTED GROUND PLANE SHOULD EXIST UNDER ALL COMPONENTS SHOWN IN
BOLD AND UNDER TRACES CONNECTING TO THOSE COMPONENTS
[14]
PVIN
[13]
BST1
CBST1
CBST2
[12]
BST2
[17]
PGND
[11]
PVCC
[10]
VIN
[9]
VCC
31151 F16
[2]
SW2
[1]
RUN
[3]
PVOUT
[4]
GND
[5]
GND
RBOT
RTOP
VOUT
[6]
VC
KELVIN
BACK TO
GND PIN
OPTIONAL SCHOTTKY DIODE
KELVIN
TO VOUT
[7]
FB
[8]
RT
RT
LTC3115-1
32
Rev. C
For more information www.analog.com
APPLICATIONS INFORMATION
Figure17. PCB Layout Recommended for the FE Package
[19]
PWM/
SYNC
[18]
SW1
[21]
PGND
VIA TO GROUND PLANE
(AND TO INNER LAYER
WHERE SHOWN)
INNER PCB
LAYER ROUTES
VIN
UNINTERRUPTED GROUND PLANE SHOULD EXIST UNDER ALL COMPONENTS SHOWN IN
BOLD AND UNDER TRACES CONNECTING TO THOSE COMPONENTS
[17]
PVIN
[16]
BST1
CBST1
CBST2
[15]
BST2
[14]
PVCC
[13]
VIN
[12]
VCC
31151 F17
[3]
SW2
[2]
RUN
[20]
PGND
[1]
PGND
[4]
PVOUT
[5]
GND
[6]
GND
RBOT
RTOP
VOUT
[7]
VC
KELVIN
BACK TO
GND PIN
KELVIN
TO VOUT
[8]
FB
[9]
RT
[11]
PGND
[10]
PGND
RT
OPTIONAL SCHOTTKY DIODE
LTC3115-1
33
Rev. C
For more information www.analog.com
TYPICAL APPLICATIONS
Wide Input Voltage Range (2.7V to 40V), High Efficiency 300kHz, Low Noise 5V Regulator
BST1 BST2
PVIN
VIN
RUN
PVOUT
VC
FB 27pF
PVCC
PWM/SYNC
VCC
RT
SW1 SW2
GND PGND
LTC3115-1
L1
33µH
D1
CBST1
0.1µF CBST2
0.1µF
2.7V TO
40V
CFF
82pF
C1
4.7µF
5V
1A VIN > 3.6V
2A VIN ≥ 6V
CIN
10µF CO
330µF RTOP
1M
RBOT
249k
CIN: MURATA GRM55DR61H106K
CO: POSCAP 6TPB330M (7.3mm × 4.3mm × 2.8mm)
D1: PANASONIC MA785
L1: COILCRAFT MSS1260
31151 TA02a
RT
121k
RFF
249k
RFB
93.1k
CFB
3300pF
+
PWM Mode Efficiency
vs Load Current
VOUT Transient for a 0A to 2A Load Step, VIN = 24VVOUT Transient for a 0A to 1A Load Step
LOAD CURRENT (A)
0.01
70
EFFICIENCY (%)
75
80
85
90
0.1 1
31151 TA02b
65
60
55
50
95
100
VIN = 5V
VIN = 3.6V
VIN = 2.7V
PWM Mode Efficiency
vs Load Current
LOAD CURRENT (A)
0.01
70
EFFICIENCY (%)
75
80
85
90
0.1 1
31151 TA02c
65
60
55
50
95
100
VIN = 12V
VIN = 24V
VIN = 36V
VOUT
(200mV/DIV)
VOUT
(200mV/DIV)
VOUT
(200mV/DIV)
VOUT
(200mV/DIV)
2ms/DIV
31151 TA02d
VIN = 36V
VIN = 12V
VIN = 5V
VIN = 3.6V
VOUT
(200mV/DIV)
INDUCTOR CURRENT
(2A/DIV)
LOAD CURRENT
(2A/DIV)
2ms/DIV 31151 TA02e
LTC3115-1
34
Rev. C
For more information www.analog.com
TYPICAL APPLICATIONS
Wide Input Voltage Range (10V to 40V) 1MHz 24V Supply at 500mA
Maximum Load Current vs VIN Efficiency vs VIN
Power-Up/Down Waveforms,
ILOAD = 0.5A
BST1 BST2
PVIN
VIN
RUN
PVOUT
VC
FB
PVCC
PWM/SYNC
VCC
RT
SW1 SW2
GND PGND
LTC3115-1
L1
15µH
CBST1
0.1µF CBST2
0.1µF
10V TO 40V
UVLO
PROGRAMMED
TO 10V (1.3V
HYSTERESIS)
CFF
22pF
C1
4.7µF
24V
500mA
CIN
10µF CO
10µF RTOP
1M
RBOT
43.2k
L1: WÜRTH 744 066 150
31151 TA03a
RT
35.7k
R1
953k
R2
130k
RFF
10k
RFB
10k
CFB
3300pF
INPUT VOLTAGE (V)
10
LOAD CURRENT (A)
1.0
1.5
31151 TA03b
0.5
020 30 40
2.5
2.0
INPUT VOLTAGE (V)
10
80
EFFICIENCY (%)
82
84
86
88
ILOAD = 0.5A
ILOAD = 1A
92
20 30
31151 TA03c
40
90
VIN
(5V/DIV)
VOUT
(10V/DIV)
INDUCTOR
CURRENT
(2A/DIV)
50ms/DIV 31151 TA03d
LTC3115-1
35
Rev. C
For more information www.analog.com
TYPICAL APPLICATIONS
Industrial 12V 1MHz Regulator with Custom Input Undervoltage Lockout Thresholds
PWM Mode Efficiency
vs Load Current 0A to 1.5A Load Step, VIN = 24V
BST1 BST2
PVIN
VIN
RUN
PVOUT
VC
FB
PVCC
PWM/SYNC
VCC
RT
SW1 SW2
GND PGND
LTC3115-1
L1
10µH
CBST1
0.1µF CBST2
0.1µF
10V TO
40V
CFF
33pF
C1
4.7µF
12V
1.4A
CIN
10µF CO
22µF RTOP
1M
RBOT
90.9k
CIN: MURATA GRM55DR61H106K
CO: TDK CKG57NX5R1H226M
L1: WÜRTH 744065100
31151 TA04a
RT
35.7k
RFF
10k
RFB
40.2k
CFB
820pF
R1
2M
R2
255k
ENABLED WHEN VIN
REACHES 10.6V
DISABLED WHEN VIN
FALLS BELOW 8.7V
LOAD CURRENT (A)
0.01
40
EFFICIENCY (%)
80
90
100
0.1 1
31151 TA04b
70
60
50
VIN = 10.6V
VIN = 12V
VIN = 24V
VIN = 36V
VOUT
(500mV/DIV)
INDUCTOR
CURRENT
(1A/DIV)
500µs/DIV 31151 TA04c
VOUT
(500mV/DIV)
INDUCTOR
CURRENT
(1A/DIV)
500µs/DIV 31151 TA04d
0A to 1.5A Load Step, VIN = 10.6V 0A to 1.5A Load Step, VIN = 40V
VOUT
(500mV/DIV)
INDUCTOR
CURRENT
(1A/DIV)
500µs/DIV 31151 TA04e
LTC3115-1
36
Rev. C
For more information www.analog.com
TYPICAL APPLICATIONS
24V 750kHz Industrial Rail Restorer
Regulated Output Voltage from a
Time Varying Input Rail 0A to 1.5A Load Step, VIN = 20V
Efficiency vs Load Current
BST1 BST2
PVIN
VIN
RUN
PVOUT
VC
FB
RT
PVCC
VCC
PWM/SYNC
SW1 SW2
GND PGND
LTC3115-1
L1
22µH
CBST1
0.1µF CBST2
0.1µF
20V TO 40V
OPEN
DRAIN
OUTPUT
CFF
47pF
C1
4.7µF
24V
1.5A
CIN
10µF CO
82µF
1µF
*
RTOP
1M
RBOT
43.2k
RT
47.5k
CO: OS-CON 35SVPF82M
L1: TOKO 892NBS-220M
*OPTIONAL: INSTALL IN
APPLICATIONS SUBJECT TO
OUTPUT OVERLOAD OR
SHORT-CIRCUIT CONDITIONS
31151 TA05a
RFF
51k
RFB
25k
CFB
3300pF
100pF
R1
500k
+
ON OFF
VIN
(5V/DIV)
VOUT
(5V/DIV)
10ms/DIV 31151 TA05b
40V
20V
LOAD
CURRENT
(1A/DIV)
INDUCTOR
CURRENT
(2A/DIV)
VOUT
(1V/DIV)
500µs/DIV
31151 TA05c
LOAD CURRENT (A)
0.01
60
EFFICIENCY (%)
80
100
0.10 1
31151 TA05d
40
50
70
90
30
20
VIN = 20V
VIN = 24V
VIN = 36V
LTC3115-1
37
Rev. C
For more information www.analog.com
TYPICAL APPLICATIONS
USB, FireWire, Automotive and Unregulated Wall Adapter to Regulated 5V (750kHz)
Efficiency vs Load Current,
from Automotive Input
Soft-Start Waveform, VIN = 24V, ILOAD = 0.5A
Output Voltage Transient Response,
750mA Load Step, Powered from Automotive Input
BST1 BST2
PVIN
VIN
10µF
RUN
PWM/SYNC
PVOUT
VC
FB
PVCC
VCC
RT
SW1 SW2
GND PGND
LTC3115-1
L1
10µH
D4
D3
D2
D1
CBST1
0.1µF CBST2
0.1µF
USB
4.1V TO 5.5V
FireWire
8V TO 36V
AUTOMOTIVE
3.6V TO 40V
WALL ADAPTER
4V TO 40V
CFF
47pF
C1
4.7µF
5V
750mA
CO
47µF
×2RTOP
1M
RBOT
249k
CIN: MURATA GRM55DR61H106K
CO: GRM43ER60J476
D1-D4: B360A-13-F
L1: COILCRAFT LPS6225
31151 TA06a
RT
47.5k
RFF
51k
RFB
100k
CFB
4700pF
BURST PWM
OFF ON
LOAD CURRENT (A)
0.01
60
EFFICIENCY (%)
80
100
0.1 1
31151 TA06b
40
50
70
90
30
20
VIN = 3.6V
VIN = 5V
VIN = 12V
VIN = 24V
VIN = 36V
VOUT
(200mV/DIV)
VOUT
(200mV/DIV)
VOUT
(200mV/DIV)
1ms/DIV 31151 TA06d
VIN = 36V
VIN = 12V
VIN = 3.6V
VRUN
(5V/DIV)
VOUT
(2V/DIV)
VCC
(5V/DIV)
INDUCTOR
CURRENT
(500mA/DIV)
2ms/DIV 31151 TA06c
LTC3115-1
38
Rev. C
For more information www.analog.com
TYPICAL APPLICATIONS
Miniature Size 1.5MHz 12V Supply
Load Step Transient Response, 0mA to 500mA,
VIN = 6V
Load Step Transient Response, 0mA to 500mA,
VIN = 24V
Efficiency vs Load Current, PWM Mode Efficiency vs Load Current, Burst Mode Operation
BST1 BST2
PVIN
VIN
RUN
PVOUT
VCBURST PWM
FB
PVCC
PWM/SYNC
VCC
RT
SW1 SW2
GND PGND
LTC3115-1
L1
4.7µH
CBST1
0.1µF CBST2
0.1µF
6V TO 40V
CFF
33pF
12V AT 500mA
1A VIN > 10V
C1
4.7µF
CI
4.7µF CO
10µF RTOP
1M
RBOT
90.9k
CO: MURATA GRM55DR61H106K
L1: WÜRTH 7447789004
31151 TA07a
RT
23.7k
RFF
15k
RFB
15k
CFB
1000pF
VOUT
(500mV/DIV)
INDUCTOR
CURRENT
(1A/DIV)
LOAD CURRENT
(500mA/DIV)
200µs/DIV 31151 TA07b
VOUT
(500mV/DIV)
INDUCTOR
CURRENT
(1A/DIV)
LOAD CURRENT
(500mA/DIV)
200µs/DIV 31151 TA07c
LOAD CURRENT (A)
0.01
60
EFFICIENCY (%)
80
100
0.1 1
31151 TA07d
40
50
70
90
30
20
VIN = 6V
VIN = 10V
VIN = 24V
VIN = 36V
LOAD CURRENT (mA)
0.1
60
EFFICIENCY (%)
70
80
90
1 10
100
31151 TA07e
50
40
30
20
VIN = 6V
VIN = 10V
VIN = 24V
VIN = 36V
LTC3115-1
39
Rev. C
For more information www.analog.com
4.00 ±0.10
(2 SIDES)
5.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJGD-2) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
2.44 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
4.34 ±0.10
(2 SIDES)
18
169
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DHD16) DFN REV A 1113
0.25 ±0.05
PIN 1
NOTCH
0.50 BSC
4.34 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
2.44 ±0.05
(2 SIDES)
3.10 ±0.05
0.50 BSC
0.70 ±0.05
4.50 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
DHD Package
16-Lead Plastic DFN (5mm × 4mm)
(Reference LTC DWG # 05-08-1707 Rev A)
PACKAGE DESCRIPTION
LTC3115-1
40
Rev. C
For more information www.analog.com
PACKAGE DESCRIPTION
FE20 (CA) TSSOP REV L 0117
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
RECOMMENDED SOLDER PAD LAYOUT
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
1 3 4 5678 9 10
DETAIL A
DETAIL A
111214 13
6.40 – 6.60*
(.252 – .260)
4.95
(.195)
2.74
(.108)
20 1918 17 16 15
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC 0.195 – 0.30
(.0077 – .0118)
TYP
2
2.74
(.108)
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
6.07
(.239)
6.07
(.239)
4.95
(.195)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
1.98
(.078)
REF
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev L)
Exposed Pad Variation CA
0.56
(.022)
REF
DETAIL A IS THE PART OF
THE LEAD FRAME FEATURE
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
LTC3115-1
41
Rev. C
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 4/13 Clarified Efficiency graph
Clarified Absolute Maximum Rating table, Package Drawing and Order Information
Clarified Electrical Characteristics table
Clarified Pin Functions
Clarified Compensation formula
1
2
3
11
25
B 5/15 Clarified Figure3
Clarified GBUCK formula
Clarified Loop Compensation Example
Clarified PCB Layout Considerations
Added LTC3114-1 to Related Parts list
17
22
26
30, 31, 32
42
C 6/19 Added AEC-Q100 automotive models 1,3
LTC3115-1
42
Rev. C
For more information www.analog.com
ANALOG DEVICES, INC. 2012-2019
06/19
www.analog.com
RELATED PARTS
TYPICAL APPLICATION
750kHz Automotive 5V Regulator with Cold Crank Capability
Cold Crank Line Transient with 1A Load Load Dump Line Transient with 1A Load
Efficiency vs Load Current
VIN = 12V
BST1 BST2
PVIN
VIN
RUN
PWM/SYNC
PVOUT
VC
FB
PVCC
VCC
RT
SW1 SW2
GND PGND
LTC3115-1
L1
6.8µH
CBST1
0.1µF CBST2
0.1µF
AUTOMOTIVE
3.6V TO 40V
CFF
33pF
C1
4.7µF
5V
1A
CIN
10µF CO
47µF RTOP
1M
RBOT
249k D1*
CIN: MURATA GRM55DR61H106K
CO: MURATA GRM43ER60J476K
D1: PANASONIC MA785
L1: SUMIDA CDRH8D43HPNP
*OPTIONAL-INSTALL D1 FOR IMPROVED EFFICIENCY AND LOWER INPUT OPERATING VOLTAGE
31151 TA08a
RT
47.5k
RFF
42.2k
RFB
54.9k
CFB
1000pF
BURST PWM
OFF ON
PART NUMBER DESCRIPTION COMMENTS
LTC3114-1 1A (IOUT), 40V Synchronous Buck-Boost DC/DC Converter VIN = 2.2V to 40V, VOUT
= 2.7V to 40V, IQ = 30µA, ISD < 3µA, DFN
and TSSOP Packages
LTC3112 2.5A (IOUT), 15V Synchronous Buck-Boost DC/DC Converter VIN: 2.7V to 15V, VOUT
: 2.5V to 14V, IQ = 40µA, ISD < 1µA, DFN and
TSSOP Packages
LTC3113 3A (IOUT), 2MHz Synchronous Buck-Boost DC/DC Converter VIN: 1.8V to 5.5V, VOUT
: 1.8V to 5.25V, IQ = 30µA, ISD < 1µA, DFN
and TSSOP Packages
LTC3127 1A (IOUT), 1.2MHz Buck-Boost DC/DC Converter with
Programmable Input Current Limit 96% Efficiency VIN: 1.8V to 5.5V, VOUT
: 1.8V to 5.25V, IQ = 35µA,
ISD < 4µA, MSOP and DFN Packages
LTC3789 High Efficiency, Synchronous, 4-Switch Buck-Boost Controller VIN: 4V to 38V, VOUT
: 0.8V to 38V, IQ = 3mA, ISD < 60µA,
SSOP-28, QFN-28 Packages
LTC3785 ≤10A (IOUT), High Efficiency, 1MHz Synchronous, No RSENSE™
Buck-Boost Controller VIN: 2.7V to 10V, VOUT
: 2.7V to 10V, IQ = 86µA, ISD < 15µA,
QFN Package
LTC3534 7V, 500mA (IOUT), 1MHz Synchronous Buck-Boost DC/DC
Converter 94% Efficiency, VIN: 2.4V to 7V, VOUT
: 1.8V to 7V, IQ = 25µA,
ISD < 1µA, DFN and GN Packages
VIN
(2V/DIV)
VOUT
(200mV/DIV)
INDUCTOR
CURRENT
(1A/DIV)
200ms/DIV 31151 TA08b
12V
6V
15ms FALL TIME
4.5V
VIN
(10V/DIV)
VOUT
(200mV/DIV)
INDUCTOR
CURRENT
(1A/DIV)
2ms/DIV 31151 TA08c
40V
13.8V
LOAD CURRENT (A)
0.01
60
EFFICIENCY (%)
80
100
0.1 1
31151 TA08d
40
50
70
90
30
20
WITH BOOTSTRAP DIODE
WITHOUT BOOTSTRAP DIODE
