AT28C040-20BISL703 - Atmel Corporation

LCC

Top View

A12

A13

A11

A10

I/O0

I/O1

I/O2

VSS

I/O3

I/O4

I/O5

I/O6

I/O7

A15

A16

A18

VCC

A17

A14

Features

•Read Access Time - 200 ns

•Automatic Page Write Operation

– Internal Address and Data Latches for 256 Bytes

– Internal Control Timer

•Fast Write Cycle Time

– Page Write Cycle Time - 10 ms Maximum

– 1 to 256 Byte Page Write Operation

•Low Power Dissipation

– 80 mA Active Current

•Hardware and Software Data Protection

•DATA Polling for End of Write Detection

•High Reliability CMOS Technology

– Enduran ce: 10,000 Cyc le s

– Data Retention: 10 Years

•Single 5V ± 10% Supply

•CMOS and TTL Compatible Inputs and Outputs

•JEDEC Approved Byte-Wide Pinout

Description

The AT28C040 is a hi gh-performance e lectrically erasable a nd programmab le read

only memory (EEPROM). Its 4 megabits of memory is organized as 524,288 words by

8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device

offers access times to 200 ns with power dissipation of just 440 mW.

Rev. 0542B–10/98

Pin Configurations

Pin Name Function

A0 - A18 Addresses

CE Chip Enable

OE Output Enable

WE Write Enable

I/O0 - I/O7 Data Inputs/Outputs

NC No Connect SIDE BRAZE,

FLATPACK

Top View

A18

A16

A15

A12

I/O0

I/O1

I/O2

GND

VCC

A17

A14

A13

A11

A10

I/O7

I/O6

I/O5

I/O4

I/O3

(continued)

4-Megabit

(512K x 8)

Paged Parallel

EEPROMs

AT28C040

The AT28C040 is accessed like a static RAM for the read

or write cycle without the need for external components.

The devi ce c ontai ns a 256-by te pa ge regi ster to a llow writ-

ing of u p to 256 b yt es simul tan eou sl y. Dur in g a wr it e cyc le ,

the address and 1 to 256 bytes of data are internally

latched, freeing the address and data bus for other opera-

tions. Following the initiation of a write cycle, the device will

automatically write the latched data using an internal con-

trol timer. The end of a write cycle can be detected by

DATA POLLING of I/O7. Once th e end of a write cy cle has

been detected, a new access for a read or write can begin.

Atmel's AT28C040 has add itional features to ensure high

quality and manufacturability. The device utilizes internal

error correction for extended endurance and improved data

retention characteristics. An optional software data protec-

tion mechanism is available to guard against inadvertent

writes. The device also includes an extra 256 bytes of

EEPROM for device identification or tracking.

Bloc k Diagram

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause per manent dam-

age to the device . This is a stress ra ting onl y and

funct ion al ope ration of the device at these or an y

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditi ons f or e xtended p eriods ma y af fect dev ice

reliability.

Storage Temperature..................................... -65°C to +150°C

All Input Voltages

(including NC pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to VCC + 0.6V

Voltage on OE and A9

with Respect to Ground...................................-0.6V to +13.5V

AT28C040

Device Operation

READ: The AT28C040 is accessed like a static RAM.

When CE and OE are low and WE is high, the data stored

at the memory l ocation determined by the address pins is

asserted on the outputs. The outputs are put in the high

impedance state when either CE or OE is high. This dual-

line control gives designers flexibility in preventing bus con-

tention in thei r systems.

BYTE WRITE: A lo w pulse on the W E or CE input with CE

or WE lo w (r espe c tive ly ) and OE high initiates a write cycle.

The address is latched on the fallin g edge of CE or WE ,

whichever occurs last. The data is latched by the first rising

edge of CE or WE. Onc e a byte w rite has been started, i t

will automatically time itself to completion. Once a pro-

grammin g operatio n has be en initi ated and for the du ration

of tWC, a read operation will effectively be a polling opera-

tion.

PAGE WR ITE: The page write oper ation of the AT28C040

allows 1 to 256 by tes of data to be written into the d evice

during a single internal programming per iod. A page write

operation is initiated in the same manner as a byte write;

the firs t byte wri tten can then be followe d by 1 to 255 addi-

tional bytes. Each successive byte must be written within

150 µs (tBLC) of the previous byte. If the tBLC limit is

exceed ed, the AT28C 040 will c ease accept ing data an d

commence the internal programming operation. All bytes

during a page write operation must reside on the same

page as d efined by the s tate of the A8 - A18 inputs. F or

each WE high to low transition during the page write opera-

tion, A8 - A18 must be the same.

The A0 to A7 inputs specify which bytes within the page are

to be written. The bytes may be loaded in any order and

may be altered within the same load period. Only bytes

which are specified for writing will be written; unnecessary

cycling of other bytes within the page does not occur.

DATA POLLING: The AT28C040 featu res DATA Polling to

indicate the end of a write cycle. During a byte or page

write cycle an attempted read of the last byte written will

result in the complement of the written data to be presented

on I/O7. Once the write cycle has been completed, true

data is valid on all outputs, and the next write cycle may

begin. D ATA Polling ma y beg in at anyt im e durin g the writ e

cycle.

TOGGLE BIT: In ad diti on to DATA Polling, the AT28C040

provid es a noth er m etho d for d ete rm ining the end of a wr it e

cycle. During the write operation, successive attempts to

read data from the device will result in I/O6 toggling

between one and zero. Once the write has completed, I/O6

will s top togglin g and valid dat a will be read. Re ading th e

toggle bit may begin at any time during the write cycle.

DATA PROTECTION: If precautions are not taken, inad-

verte nt writes may occur duri ng transi tions of th e host sys-

tem power s upply. Atmel has inco rporated both h ardware

and software features that will protect the memory against

inadvertent writes.

HARDWARE PR OTECTION: Hardware features protect

against inadvertent writes to the AT28C040 in the following

ways: (a) VCC sense - if VCC is below 3.8V (typical) the write

function is inhibited; (b) VCC power-on delay - once VCC has

reached 3.8V the device will automatically time out 5 ms

(typical) before allowing a write: (c) write inhibit - holding

any one of OE low, CE high or WE high inhibits write

cycles; (d) noise filter - pulses of less than 15 ns (typical)

on the WE or CE inputs will not initiate a write cycle.

SOFTWARE DATA PROTECTION: A software controlled

data protection feature has been implemented on the

AT28C040. When enabled, the software data protection

(SDP), will prevent inadvertent writes. The SDP feature

may be enabled or disabled by the user; the AT28C040 is

shipped from Atmel with SDP disabled.

SDP is enabled when the host system issues a series of

three write commands; three specific bytes of data are writ-

ten to three specific addresses (refer to Software Data Pro-

tection Algorithm). After writing the 3-byte command

sequenc e and after t WC, the entire AT 28C040 will be pro-

tected against inadvertent write o perations. It should be

noted th at on ce protec ted, the h ost c an sti ll perfor m a b yte

or page write to the AT28C040 . To do so, the same 3-by te

command sequence used to enable SDP must precede the

data to be written.

Once se t, SDP will remain ac tive unless the disabl e com-

mand seq uen ce is i ssue d. P owe r trans iti ons d o not disabl e

SDP, and SDP will p rote ct th e AT2 8C040 during powe r-up

and power-d own c ond iti ons . A ll com man d s eque nc es mus t

conform to the page write timing specifications. The data in

the enable and disable command sequences is not writ ten

to the device, and the memory addresses used in the

sequenc e may be written with d ata in eit her a byte or page

write operation.

After setting SDP, any attempt to write to the device without

the 3-byte comm and sequence will star t the internal write

timer s. No data will be wr itten to the de vice; h oweve r, for

the duration of tWC, read operations will effectively be poll-

ing operations.

DEVICE IDENTIFICATION: An extra 256 bytes of

EEPROM memory are available to the user for device iden-

tification. By raising A9 to 12V ± 0.5V and using address

locations 7FF80H to 7FFFFH, the bytes may be written to

or read from in the same manner as the regular memory

array.

OPTIONAL CHIP ERASE MODE: The entire device can

be er ased using a 6 -byte sof tware er ase c ode. Plea se see

Software Chip Erase application note for details.

AT28C040

Notes: 1. X can be VIL or VIH.

2. Refer to AC Programming Waveforms.

DC and AC Oper ating Range

AT28C040-20 AT28C040-25

Operation Operation

Read Program Read Program

Operating

Temperature

(Case)

Commercial 0°C - 70°C 0°C - 70°C 0°C - 70°C 0°C - 70°C

Industrial -40°C - 85°C -40°C - 85°C -40°C - 85°C -40°C - 85°C

Extended -55°C - 125°C -40°C - 85°C -55°C - 125°C -40°C - 85°C

VCC Power Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10%

Operating Modes

Mode CE OE WE I/O

Read VIL VIL VIH DOUT

Write(2) VIL VIH VIL DIN

Standby/Write Inhibit VIH X(1) X High Z

Write Inhibit X X VIH

Write Inhibit X VIL X

Output Disable X VIH X High Z

DC Characteristics

Symbol Parameter Condition Min Max Units

ILI Input Load Current VIN = 0V to VCC + 1V 10 µA

ILO Output Leakage Current VI/O = 0V to VCC 10 µA

ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC + 1V 3 mA

ISB2 VCC Standby Current TTL CE = 2.0V to VCC + 1V 3 mA

ICC VCC Active Current f = 5 MHz; IOUT = 0 mA 80 mA

VIL Input Low Voltage 0.8 V

VIH Input High Voltage 2.0 V

VOL Output Low Voltage IOL = 2.1 mA 0.45 V

VOH1 Output High Voltage IOH = -400 µA2.4V

OH2 Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V

AT28C040

AC Read Waveforms(1)(2)(3)(4)

Note: 1. CE May be delayed up to tACC - tCE after the address transition wihtout impact on tACC.

2. OE may be delayed up to tCE - tOE afte r the f alli ng edge of CE without impact on t CE or by tACC - tOE after an ad dre ss c han ge

withou t impa ct on tACC.

3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).

4. This parameter is characterized and is not 100% tested.

Input Test Waveforms and

Measurement Level

tR, tF < 5 ns

Output Test Load

Note: 1. This parameter is characterized and is not 100% tested.

AC Read Characteristics

Symbol Parameter

AT28C040-20 AT28C040-25

UnitsMin Max Min Max

tACC Address to Output Delay 200 250 ns

tCE(1) CE to Output Delay 200 250 ns

tOE(2) OE to Output Delay 0 55 0 55 ns

tDF(3)(4) CE or OE to Output Float 0 55 0 55 ns

tOH Output Hold from OE, CE or Address, whichever occurred first 0 0 ns

Pin Capacitance

f = 1 MHz, T = 2 5°C(1)

Symbol Typ Max Units Conditions

CIN 410pFV

IN = 0V

COUT 812pFV

OUT = 0V

AT28C040

AC Write Waveforms

WE Controlled

CE Controlled

AC Write Characteristics

Symbol Parameter Min Max Units

tAS, tOES Address, OE Set-up Time 0 ns

tAH Address Hold Time 50 ns

tCS Chip Select Set-up Time 0 ns

tCH Chip Select Hold Time 0 ns

tWP Write Pulse Width (WE or CE) 100 ns

tDS Data Set-up Time 50 ns

tDH, tOEH Data, OE Hold Time 0 ns

AT28C040

Page Mode Write Waveforms(1)(2)

Notes: 1. A8 through A18 must specify the page address during each high to low transition of WE (or CE).

2. OE must be high only when WE and CE are both low.

Page Mode Characteristics

Symbol Parameter Min Max Units

tWC Write Cycle Time 10 ms

tAS Address Set-up Time 0 ns

tAH Address Hold Time 50 ns

tDS Data Set-up Time 50 ns

tDH Data Hold Time 0 ns

tWP Write Pulse Width 100 ns

tBLC Byte Load Cycle Time 150 µs

tWPH Write Pulse Width High 50 ns

AT28C040

Software Data

Protection Enable Algorithm(1)

Notes: 1. Data Format: I/O7 - I/O0 (Hex);

Address Format: A14 - A0 (Hex).

2. Write Protect state will be activated at end of write

even if no other data is loaded.

3. Write Protec t state will be d eactivat ed at end of write

period even if no other data is loaded.

4. 1 to 256 by tes of data are loaded.

Software Data

Protection Disable Algorithm(1)

Software Protected Program Cycle Waveform(1)(2)(3)

Notes: 1. A0 - A14 must conform to the addressing sequence for the first 3 bytes as shown above.

2. After the com mand sequen ce has been iss ued and a page write op eration f ol low s, the page ad dress inpu ts (A8 - A18) must

be the same for each high to low transition of WE (or CE).

3. OE must be high only when WE and CE are both low.

LOAD DATA AA

ADDRESS 5555

LOAD DATA 55

ADDRESS 2AAA

LOAD DATA A0

ADDRESS 5555

LOAD DATA XX

ANY ADDRESS(4)

LOAD LAST BYTE

LAST ADDRESS ENTER DATA

PROTECT STATE

WRITES ENABLED(2)

LOAD DATA AA

ADDRESS 5555

LOAD DATA 55

ADDRESS 2AAA

LOAD DATA 80

ADDRESS 5555

LOAD DATA AA

ADDRESS 5555

LOAD DATA 20

ADDRESS 5555

LOAD DATA XX

ANY ADDRESS(4)

LOAD LAST BYTE

LAST ADDRESS

LOAD DATA 55

ADDRESS 2AAA

EXIT DATA

PROTECT STATE(3)

AT28C040

Notes: 1. These parameters are characterized and not 100% tested.

2. See AC Read Characteristics.

Data Polling Wavefo rms

Notes: 1. These parameters are characterized and not 100% tested.

2. See AC Read Characteristics.

Toggle Bit Waveforms(1)(2)(3)

Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.

2. Beginning and ending state of I/O6 will vary.

3. Any address location may be used but the address should not vary.

Data Polling Characteristics(1)

Symbol Parameter Min Typ Max Units

tDH Data Hold Time 10 ns

tOEH OE Hold Time 10 ns

tOE OE to Output Delay(2) ns

tWR Write Recovery Time 0 ns

Toggle Bit Characteristics(1)

Symbol Parameter Min Typ Max Units

tDH Data Hold Time 10 ns

tOEH OE Hold Time 10 ns

tOE OE to Output Delay(2) ns

tOEHP OE High Pulse 150 ns

tWR Write Recovery Time 0 ns

AT28C040

Note: 1. See Valid Part Numbers.

Order ing In formation(1)

tACC

(ns)

ICC (mA)

Ordering Code Pa ckage Operation RangeActive Standby

200 80 3 AT28C040-20BC

AT28C040-20FC

AT28C040-20LC

32B

32F

44L

Commercial

(0° to 70°C)

80 3 AT28C040-20BI

AT28C040-20FI

AT28C040-20LI

32B

32F

44L

Industrial

(-40° to 85°C)

80 3 AT28C040-20BI SL703

AT28C040-20FI SL703

AT28C040-20LI SL703

32B

32F

44L

Extended

(See DC and AC Operating

Range Table)

250 80 3 AT28C040-25BC

AT28C040-25FC

AT28C040-25LC

32B

32F

44L

Commercial

(0° to 70°C)

80 3 AT28C040-25BI

AT28C040-25FI

AT28C040-25LI

32B

32F

44L

Industrial

(-40° to 85°C)

80 3 AT28C040-25BI SL703

AT28C040-25FI SL703

AT28C040-25LI SL703

32B

32F

44L

Extended

(See DC and AC Operating

Range Table)

Valid Part Numbers

The following table lists standard Atmel products that can be ordered.

Device Numbers Speed Package and Temperature Combinations

AT28C040 20 BC, BI, FC, FI, LC, LI, BI SL703, FI SL703, LI SL703

AT28C040 25 BC, BI, FC, FI, LC, LI, BI SL703, FI SL703, LI SL703

Die Products

Reference Section: Parallel EEPROM Die Products

Packag e Type

32B 32-Lead, 0.600" Wide, Ceramic Side Braze Dual Inline (Side Braze)

32F 32-Lead, Non- Windowed, Ceramic Bottom-Brazed Flat Package (Fl atpack)

44L 44-Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC)

Options

Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms

AT28C040

Packaging Information

PIN #1 ID .370(9.40)

.270(6.86)

.019(.482)

.015(.381)

.050(1.27) BSC

.045(1.14) MAX

.120(3.05)

.098(2.49)

.045(1.14)

.026(.660)

.072(1.82)

.030(0.76)

.408(10.4)

.355(9.02)

.006(.152)

.004(.101)

.488(12.4)

.472(12.0)

.829(21.1)

.811(20.6)

*Ceramic lid standard unless specified.

32B, 32-Lead, 0.600" Wide, Ceramic Side Braze

Dual Inline (Side Braze)

Dimensions in Inches and (Millimeters)

32F, 32-Lead, Non-Windowed, Ceramic Bottom-

Brazed Flat Package (Flatpack)

Dimension in Inches and (Millimeters)

JEDEC OUTLINE MO-115

44L, 44-Pad, Non-Windowed, Ceramic Leadless

Chip Carrier (LCC)

Dimensions in Inches and (Millimeters)*

MIL-STD-1835 C-5

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-

ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s website. The Company assumes no responsibility for

any errors which may appear in this document, reserves the r ight to change devices or specifications detailed herein at any time without

notice, and does not make any com mitment to update the infor mation contained herein. No licenses to patents or other intellectual prop-

er ty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are

not authorized for use as cr itical components in life suppor t devices or systems.

Marks bearing ® and/or ™ are registered trademarks and trademarks of Atmel Cor poration.

Ter ms and product names in this document may be trademarks of others.

Atmel Headquar ters Atmel Operations

Corporate Headquarters

2325 Orchard Parkway

San Jose, CA 95131

TEL (408) 441- 0311

FAX (408) 487-2600

Europe

Atmel U.K., Ltd.

Coliseum Business Centre

Riverside Way

Camberley, Surrey GU15 3YL

England

TEL (44) 1276- 686677

FAX (44) 1276-686697

Asia

Atmel Asia, Ltd.

Room 1219

Chinachem Golden Plaza

77 Mody Road

Tsimshatsui East

Kowloon, Hong Kong

TEL (852) 27219778

FAX (852) 27221369

Japan

Atmel Japan K.K.

Tonetsu Shinkawa Bldg., 9F

1-24 -8 Shinka wa

Chuo-ku, Tokyo 104-0033

Japan

TEL (81) 3-3523-3551

FAX (81) 3-3523-7581

Atmel Colorado Springs

1150 E. Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TEL (719) 576-3300

FAX (719) 540-1759

Atmel Rousset

Zone Indu strie lle

13106 Rousset Cedex, France

TEL (33) 4 42 53 60 00

FAX (33) 4 42 53 60 01

Fax-on-Demand

North America:

1-(800) 292-8635

International:

1-(408) 441-0732

e-mail

literature@atmel.com

Web Site

http://www.atmel.com

BBS

1-(408) 436-4309

Printed on recycled paper.

0542B–10/98/xM