v1.2 IGLOOe Low-Power Flash FPGAs (R) with Flash*Freeze Technology Features and Benefits Low Power * * * * 1.2 V to 1.5 V Core Voltage Support for Low Power Supports Single-Voltage System Operation Low-Power Active FPGA Operation Flash*Freeze Technology Enables Ultra-Low Power Consumption while Maintaining FPGA Content * Flash*Freeze Pin Allows Easy Entry to / Exit from Ultra-LowPower Flash*Freeze Mode High Capacity * 600 k to 3 Million System Gates * 108 to 504 kbits of True Dual-Port SRAM * Up to 620 User I/Os Reprogrammable Flash Technology * * * * 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process Live-at-Power-Up (LAPU) Level 0 Support Single-Chip Solution Retains Programmed Design when Powered Off In-System Programming (ISP) and Security * Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532-compliant) * FlashLock(R) to Secure FPGA Contents High-Performance Routing Hierarchy * Segmented, Hierarchical Routing and Clock Structure * High-Performance, Low-Skew Global Network * Architecture Supports Ultra-High Utilization Pro (Professional) I/O * * * * * * * * * * * * * 700 Mbps DDR, LVDS-Capable I/Os 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation Bank-Selectable I/O Voltages--Up to 8 Banks per Chip Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS 2.5 V / 5.0 V Input Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3 Class I and II I/O Registers on Input, Output, and Enable Paths Programmable Output Slew Rate and Drive Strength Programmable Input Delay Schmitt Trigger Option on Single-Ended Inputs Weak Pull-Up/-Down IEEE 1149.1 (JTAG) Boundary Scan Test Pin-Compatible Packages across the IGLOO(R)e Family Clock Conditioning Circuit (CCC) and PLL * Six CCC Blocks, Each with an Integrated PLL * Configurable Phase Shift, Multiply/Divide, Delay Capabilities, and External Feedback * Wide Input Frequency Range (1.5 MHz up to 250 MHz) Embedded Memory * 1 kbit of FlashROM User Nonvolatile Memory * SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (x1, x2, x4, x9, and x18 organizations available) * True Dual-Port SRAM (except x18) ARM Processor Support in IGLOOe FPGAs * M1 IGLOOe Devices--CortexTM-M1 Soft Processor Available with or without Debug IGLOOe Product Family IGLOOe Devices AGLE600 ARM-Enabled IGLOOe Devices AGLE3000 M1AGLE3000 System Gates 600 k 3M VersaTiles (D-flip-flops) 13,824 75,264 Quiescent Current (typical) in Flash*Freeze Mode (W) 49 137 RAM kbits (1,024 bits) 108 504 4,608-Bit Blocks 24 112 FlashROM Bits 1k 1k Secure (AES) ISP Yes Yes 6 6 18 18 CCCs with Integrated PLLs VersaNet Globals1 I/O Banks Maximum User I/Os Package Pins FBGA 8 8 270 620 FG256, FG484 FG484, FG896 Notes: 1. Refer to the Cortex-M1 Handbook for more information. 2. Six chip (main) and twelve quadrant global networks are available. 3. For devices supporting lower densities, refer to the IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology handbook. October 2008 (c) 2008 Actel Corporation I I/Os Per Package1 IGLOOe Devices AGLE600 AGLE3000 ARM-Enabled IGLOOe Devices M1AGLE3000 I/O Types Single-Ended I/O1 Differential I/O Pairs Single-Ended I/O1 Differential I/O Pairs FG256 165 79 - - FG484 270 135 341 168 FG896 - - 620 310 Package Notes: 1. When considering migrating your design to a lower- or higher-density device, refer to the IGLOOe Low-Power Flash FPGAs with Flash*Freeze Technology handbook to ensure compliance with design and board migration requirements. 2. Each used differential I/O pair reduces the number of single-ended I/Os available by two. 3. For AGLE3000 devices, the usage of certain I/O standards is limited as follows: - SSTL3(I) and (II): up to 40 I/Os per north or south bank - LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank - SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank 4. FG256 and FG484 are footprint-compatible packages. 5. When using voltage-referenced I/O standards, one I/O pin should be assigned as a voltage-referenced pin (VREF) per minibank (group of I/Os). When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of single-ended user I/Os available is reduced by one. 6. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of singleended user I/Os available is reduced by one. 7. "G" indicates RoHS-compliant packages. Refer to "IGLOOe Ordering Information" on page III for the location of the "G" in the part number. IGLOOe FPGAs Package Sizes Dimensions Package Length x Width (mm x mm) Nominal Area (mm Pitch (mm) Height (mm) II 2) FG256 FG484 FG896 17 x 17 23 x 23 31 x 31 289 529 961 1 1 1 1.6 2.23 2.23 v1.2 IGLOOe Low-Power Flash FPGAs IGLOOe Ordering Information AGLE3000 V2 _ FG G 896 I Application (Temperature Range) Blank = Commercial (0C to +70C Ambient Temperature) I = Industrial (-40C to +85C Ambient Temperature) PP = Pre-Production ES = Engineering Sample (Room Temperature Only) Package Lead Count Lead-Free Packaging Blank = Standard Packaging G = RoHS-Compliant Packaging Package Type FG = Fine Pitch Ball Grid Array (1.0 mm pitch) Speed Grade F = 20% Slower than Standard* Blank = Standard Supply Voltage 2 = 1.2 V to 1.5 V 5 = 1.5 V only Part Number IGLOOe Devices AGLE600 = 600,000 System Gates AGLE3000 = 3,000,000 System Gates IGLOOe Devices with Cortex-M1 M1AGLE3000 = 3,000,000 System Gates Notes: 1. Marking Information: IGLOO V2 devices do not have V2 marking, but IGLOO V5 devices are marked accordingly. 2. The DC and switching characteristics for the -F speed grade targets are based only on simulation. The characteristics provided for the -F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be added and will be reflected in future revisions of this document. The -F speed grade is only supported in the commercial temperature range. v1.2 III Temperature Grade Offerings AGLE600 AGLE3000 M1AGLPE3000 Package FG256 C, I - FG484 C, I C, I FG896 - C, I Note: C = Commercial temperature range: 0C to 70C ambient temperature. I = Industrial temperature range: -40C to 85C ambient temperature. Speed Grade and Temperature Grade Matrix -F 1 Std. C2 3 - Temperature Grade I Notes: 1. The characteristics provided for the -F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be added and will be reflected in future revisions of this document. The -F speed grade is only supported in the commercial temperature range. 2. C = Commercial temperature range: 0C to 70C ambient temperature. 3. I = Industrial temperature range: -40C to 85C ambient temperature. References made to IGLOOe devices also apply to ARM-enabled IGLOOe devices. The ARM-enabled part numbers start with M1 (Cortex-M1). Contact your local Actel representative for device availability: http://www.actel.com/contact/default.aspx. IV v1.2 1 - IGLOOe Device Family Overview General Description The IGLOOe family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a single-chip solution, small footprint packages, reprogrammability, and an abundance of advanced features. The Flash*Freeze technology used in IGLOOe devices enables entering and exiting an ultra-lowpower mode while retaining SRAM and register data. Flash*Freeze technology simplifies power management through I/O and clock management with rapid recovery to operation mode. The Low Power Active capability (static idle) allows for ultra-low-power consumption while the IGLOOe device is completely functional in the system. This allows the IGLOOe device to control system power management based on external inputs (e.g., scanning for keyboard stimulus) while consuming minimal power. Nonvolatile flash technology gives IGLOOe devices the advantage of being a secure, low power, single-chip solution that is live at power-up (LAPU). IGLOOe is reprogrammable and offers time-tomarket benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. IGLOOe devices offer 1 kbit of on-chip, programmable, nonvolatile FlashROM storage as well as clock conditioning circuitry based on 6 integrated phase-locked loops (PLLs). IGLOOe devices have up to 3 million system gates, supported with up to 504 kbits of true dual-port SRAM and up to 620 user I/Os. M1 IGLOOe devices support the high-performance, 32-bit Cortex-M1 processor developed by ARM for implementation in FPGAs. Cortex-M1 is a soft processor that is fully implemented in the FPGA fabric. It has a three-stage pipeline that offers a good balance between low-power consumption and speed when implemented in an M1 IGLOOe device. The processor runs the ARMv6-M instruction set, has a configurable nested interrupt controller, and can be implemented with or without the debug block. Cortex-M1 is available for free from Actel for use in M1 IGLOOe FPGAs. The ARM-enabled devices have Actel ordering numbers that begin with M1AGLE and do not support AES decryption. Flash*Freeze Technology The IGLOOe device offers unique Flash*Freeze technology, allowing the device to enter and exit ultra-low-power Flash*Freeze mode. IGLOOe devices do not need additional components to turn off I/Os or clocks while retaining the design information, SRAM content, and registers. Flash*Freeze technology is combined with in-system programmability, which enables users to quickly and easily upgrade and update their designs in the final stages of manufacturing or in the field. The ability of IGLOOe V2 devices to support a wide range of core voltage (1.2 V to 1.5 V) allows further reduction in power consumption, thus achieving the lowest total system power. When the IGLOOe device enters Flash*Freeze mode, the device automatically shuts off the clocks and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and data is retained. The availability of low-power modes, combined with reprogrammability, a single-chip and singlevoltage solution, and availability of small-footprint, high pin-count packages, make IGLOOe devices the best fit for portable electronics. v1.2 1-1 IGLOOe Device Family Overview Flash Advantages Low Power Flash-based IGLOOe devices exhibit power characteristics similar to those of an ASIC, making them an ideal choice for power-sensitive applications. IGLOOe devices have only a very limited power-on current surge and no high-current transition period, both of which occur on many FPGAs. IGLOOe devices also have low dynamic power consumption to further maximize power savings; power is even further reduced by the use of a 1.2 V core voltage. Low dynamic power consumption, combined with low static power consumption and Flash*Freeze technology, gives the IGLOOe device the lowest total system power offered by any FPGA. Security The nonvolatile, flash-based IGLOOe devices do not require a boot PROM, so there is no vulnerable external bitstream that can be easily copied. IGLOOe devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile flash programming can offer. IGLOOe devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed intellectual property and configuration data. In addition, all FlashROM data in IGLOOe devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption standard. AES was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. IGLOOe devices have a built-in AES decryption engine and a flash-based AES key that make them the most comprehensive programmable logic device security solution available today. IGLOOe devices with AES-based security allow for secure, remote field updates over public networks such as the Internet, and ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. The contents of a programmed IGLOOe device cannot be read back, although secure design verification is possible. Security, built into the FPGA fabric, is an inherent component of the IGLOOe family. The flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. The IGLOOe family, with FlashLock and AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected and secure, making remote ISP possible. An IGLOOe device provides the most impenetrable security for programmable logic designs. Single Chip Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based IGLOOe FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system reliability. Live at Power-Up The Actel flash-based IGLOOe devices support Level 0 of the LAPU classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The LAPU feature of flash-based IGLOOe devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs. In addition, glitches and brownouts in system power will not corrupt the IGLOOe device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-based IGLOOe devices simplify total system design and reduce cost and design risk while increasing system reliability and improving system initialization time. 1 -2 v1.2 IGLOOe Low-Power Flash FPGAs Reduced Cost of Ownership Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-based FPGAs, Flash-based IGLOOe devices allow all functionality to be live at power-up; no external boot PROM is required. On-board security mechanisms prevent access to all the programming information and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property cannot be compromised or copied. Secure ISP can be performed using the industry-standard AES algorithm. The IGLOOe family device architecture mitigates the need for ASIC migration at higher user volumes. This makes the IGLOOe family a cost-effective ASIC replacement solution, especially for applications in the consumer, networking/communications, computing, and avionics markets. Firm-Error Immunity Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not exist in the configuration memory of IGLOOe flashbased FPGAs. Once it is programmed, the flash cell configuration element of IGLOOe FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric. Advanced Flash Technology The IGLOOe family offers many benefits, including nonvolatility and reprogrammability, through an advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of fine granularity, enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization without compromising device routability or performance. Logic functions within the device are interconnected through a four-level routing hierarchy. IGLOOe family FPGAs utilize design and process techniques to minimize power consumption in all modes of operation. Advanced Architecture The proprietary IGLOOe architecture provides granularity comparable to standard-cell ASICs. The IGLOOe device consists of five distinct and programmable architectural features (Figure 1-1 on page 4): * Flash*Freeze technology * FPGA VersaTiles * Dedicated FlashROM * Dedicated SRAM/FIFO memory * Extensive CCCs and PLLs * Pro I/O structure The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnections. The versatility of the IGLOOe core tile as either a three-input lookup table (LUT) equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the Actel ProASIC(R) family of third-generation-architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design. v1.2 1-3 IGLOOe Device Family Overview In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming of IGLOOe devices via an IEEE 1532 JTAG interface. CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Pro I/Os VersaTile ISP AES Decryption* User Nonvolatile FlashRom Flash*Freeze Technology Charge Pumps RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Figure 1-1 * IGLOOe Device Architecture Overview Flash*Freeze Technology The IGLOOe device has an ultra-low power static mode, called Flash*Freeze mode, which retains all SRAM and register information and can still quickly return to normal operation. Flash*Freeze technology enables the user to quickly (within 1 s) enter and exit Flash*Freeze mode by activating the Flash*Freeze pin while all power supplies are kept at their original values. In addition, I/Os and global I/Os can still be driven and can be toggling without impact on power consumption, clocks can still be driven or can be toggling without impact on power consumption, and the device retains all core registers, SRAM information, and states. I/O states are tristated during Flash*Freeze mode or can be set to a certain state using weak pull-up or pull-down I/O attribute configuration. No power is consumed by the I/O banks, clocks, JTAG pins, or PLL in this mode. Flash*Freeze technology allows the user to switch to active mode on demand, thus simplifying the power management of the device. The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to decide when it is safe to transition to this mode. It is also possible to use the Flash*Freeze pin as a regular I/O if Flash*Freeze mode usage is not planned, which is advantageous because of the 1 -4 v1.2 IGLOOe Low-Power Flash FPGAs inherent low power static and dynamic capabilities of the IGLOOe device. Refer to Figure 1-2 for an illustration of entering/exiting Flash*Freeze mode. Actel IGLOOe FPGA Flash*Freeze Mode Control Flash*Freeze Pin Figure 1-2 * IGLOOe Flash*Freeze Mode VersaTiles The IGLOOe core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS(R) core tiles. The IGLOOe VersaTile supports the following: * All 3-input logic functions--LUT-3 equivalent * Latch with clear or set * D-flip-flop with clear or set * Enable D-flip-flop with clear or set Refer to Figure 1-3 for VersaTile configurations. LUT-3 Equivalent X1 X2 X3 LUT-3 D-Flip-Flop with Clear or Set Y Data CLK CLR Y Enable D-Flip-Flop with Clear or Set Data CLK D-FF Y D-FF Enable CLR Figure 1-3 * VersaTile Configurations User Nonvolatile FlashROM Actel IGLOOe devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications: * Internet protocol addressing (wireless or fixed) * System calibration settings * Device serialization and/or inventory control * Subscription-based business models (for example, set-top boxes) * Secure key storage for secure communications algorithms * Asset management/tracking * Date stamping * Version management The FlashROM is written using the standard IGLOOe IEEE 1532 JTAG programming interface. The core can be individually programmed (erased and written), and on-chip AES decryption can be used selectively to securely load data over public networks, as in security keys stored in the FlashROM for a user design. v1.2 1-5 IGLOOe Device Family Overview The FlashROM can be programmed via the JTAG programming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing. Note that the FlashROM can only be programmed from the JTAG interface and cannot be programmed from the internal logic array. The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-bybyte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM address define the byte. The Actel IGLOOe development software solutions, Libero(R) Integrated Design Environment (IDE) and Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequential programming files for applications requiring a unique serial number in each part. Another feature allows the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents. SRAM and FIFO IGLOOe devices have embedded SRAM blocks along their north and south sides. Each variableaspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256x18, 512x9, 1kx4, 2kx2, and 4kx1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro. In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control unit contains the counters necessary for generation of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations. PLL and CCC IGLOOe devices provide designers with very flexible clock conditioning capabilities. Each member of the IGLOOe family contains six CCCs, each with an integrated PLL. The six CCC blocks are located at the four corners and the centers of the east and west sides. One CCC (center west side) has a PLL. The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs located near the CCC that have dedicated connections to the CCC block. The CCC block has these key features: * Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz * Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz * 2 programmable delay types for clock skew minimization * Clock frequency synthesis Additional CCC specifications: * 1 -6 Internal phase shift = 0, 90, 180, and 270. Output phase shift depends on the output divider configuration. * Output duty cycle = 50% 1.5% or better * Low output jitter: worst case < 2.5% x clock period peak-to-peak period jitter when single global network used * Maximum acquisition time is 300 s * Exceptional tolerance to input period jitter--allowable input jitter is up to 1.5 ns * Four precise phases; maximum misalignment between adjacent phases of 40 ps x 250 MHz / fOUT_CCC v1.2 IGLOOe Low-Power Flash FPGAs Global Clocking IGLOOe devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets. Pro I/Os with Advanced I/O Standards The IGLOOe family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V). IGLOOe FPGAs support 19 different I/O standards, including singleended, differential, and voltage-referenced. The I/Os are organized into banks, with eight banks per device (two per side). The configuration of these banks determines the I/O standards supported. Each I/O bank is subdivided into VREF minibanks, which are used by voltage-referenced I/Os. VREF minibanks contain 8 to 18 I/Os. All the I/Os in a given minibank share a common VREF line. Therefore, if any I/O in a given VREF minibank is configured as a VREF pin, the remaining I/Os in that minibank will be able to use that reference voltage. Each I/O module contains several input, output, and enable registers. These registers allow the implementation of the following: * Single-Data-Rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II) Double-Data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II). IGLOOe banks support M-LVDS with 20 multi-drop points. v1.2 1-7 IGLOOe Device Family Overview Part Number and Revision Date Part Number 51700096-001-3 Revised October 2008 List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Current Version (v1.2) Page v1.1 (June 2008) The Quiescent Current values in the "IGLOOe Product Family" table were updated. I v1.0 (April 2008) As a result of the Libero IDE v8.4 release, Actel now offers a wide range of core voltage support. The document was updated to change 1.2 V / 1.5 V to 1.2 V to 1.5 V. N/A 51700096-001-1 (March 2008) This document was divided into two sections and given a version number, starting at v1.0. The first section of the document includes features, benefits, ordering information, and temperature and speed grade offerings. The second section is a device family overview. N/A 51700096-001-0 (January 2008) The "Low Power" section was updated to change "1.2 V and 1.5 V Core Voltage" to "1.2 V and 1.5 V Core and I/O Voltage." The text "(from 25 W)" was removed from "Low-Power Active FPGA Operation." I 1.2_V was added to the list of core and I/O voltages in the "Pro (Professional) I/O" and "Pro I/Os with Advanced I/O Standards" sections. I, 1-7 Advance v0.4 (December 2007) This document was previously in datasheet Advance v0.4. As a result of moving to the handbook format, Actel has restarted the version numbers. The new version number is 51700096-001-0. N/A Advance v0.3 (September 2007) Table 1 * IGLOOe Product Family was updated to change the maximum number of user I/Os for AGLE3000. i Table 2 * IGLOOe FPGAs Package Sizes Dimensions is new. Package dimensions were removed from the "I/Os Per Package1" table. The number of I/Os was updated for FG896. ii A note regarding marking information was added to "IGLOOe Ordering Information". iii Advance v0.2 (July 2007) Cortex-M1 device information was added to Cortex-M1 device information i, ii, iii, iv was added to Table 1 * IGLOOe Product Family, the "I/Os Per Package1" table, "IGLOOe Ordering Information", and Temperature Grade Offerings. Advance v0.1 The words "ambient temperature" were added to the temperature range in the "IGLOOe Ordering Information", "Temperature Grade Offerings", and "Speed Grade and Temperature Grade Matrix" sections. 1 -8 v1.2 iii, iv IGLOOe Low-Power Flash FPGAs Datasheet Categories Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advance," "Preliminary," and "Production." The definition of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized. Preliminary The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Unmarked (production) This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Actel Safety Critical, Life Support, and High-Reliability Applications Policy The Actel products described in this advance status document may not have completed Actel's qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel's Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel's products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information. v1.2 1-9 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. www.actel.com Actel Corporation Actel Europe Ltd. Actel Japan Actel Hong Kong 2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone 650.318.4200 Fax 650.318.4600 River Court,Meadows Business Park Station Approach, Blackwater Camberley Surrey GU17 9AB United Kingdom Phone +44 (0) 1276 609 300 Fax +44 (0) 1276 607 540 EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Phone +81.03.3445.7671 Fax +81.03.3445.7668 http://jp.actel.com Suite 2114, Two Pacific Place 88 Queensway, Admiralty Hong Kong Phone +852 2185 6460 Fax +852 2185 6488 www.actel.com.cn 51700096-001-3/10.08