© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 2
1Publication Order Number:
MC74HCT4051A/D
MC74HCT4051A,
MC74HCT4052A,
MC74HCT4053A
Analog Multiplexers /
Demultiplexers with LSTTL
Compatible Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT4051A, MC74HCT4052A and MC74HCT4053A
utilize silicon−gate CMOS technology to achieve fast propagation
delays, low ON resistances, and low OFF leakage currents. These
analog multiplexers/demultiplexers control analog voltages that may
vary across the complete power supply range (from VCC to VEE).
The HCT4051A, HCT4052A and HCT4053A are identical in
pinout to the metal−gate MC14051AB, MC14052AB and
MC14053AB. The Channel−Select inputs determine which one of the
Analog Inputs/Outputs is to be connected, by means of an analog
switch, to the Common Output/Input. When the Enable pin is HIGH,
all analog switches are turned off.
The Channel−Select and Enable inputs are compatible with standard
CMOS and LSTTL outputs.
These devices have been designed so that the ON resistance (Ron) is
more linear over input voltage than Ron of metal−gate CMOS analog
switches.
For a multiplexer/demultiplexer with injection current protection,
see HC4851A and HCT4851A.
Features
•Fast Switching and Propagation Speeds
•Low Crosstalk Between Switches
•Diode Protection on All Inputs/Outputs
•Analog Power Supply Range (VCC − VEE) = 2.0 to 12.0 V
•Digital (Control) Power Supply Range (VCC − GND) = 2.0 to 6.0 V
•Improved Linearity and Lower ON Resistance Than Metal−Gate
Counterparts
•Low Noise
•In Compliance with the Requirements of JEDEC Standard No. 7 A
•Chip Complexity: HCT4051A − 184 FETs or 46 Equivalent Gates
HCT4052A − 168 FETs or 42 Equivalent Gates
HCT4053A − 156 FETs or 39 Equivalent Gates
•These Devices are Pb−Free and are RoHS Compliant
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MARKING
DIAGRAMS
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
1
16
1
16
1
16
HCT405xAG
AWLYWW
HCT40
5xA
ALYWG
G
1
16
SOIC−16 WIDE
DW SUFFIX
CASE 751G
1
16
HCT405xA
AWLYWWG
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
ORDERING INFORMATION
1
16
x = 1, 2, 3
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G= Pb−Free Package
(Note: Microdot may be in either location)
MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
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2
Figure 1. Logic Diagram − MC74HCT4051A
Single−Pole, 8−Position Plus Common Off
X0 13
X1 14
X2 15
X3 12
X4 1
X5 5
X6 2
X7 4
A11
B10
C9
ENABLE 6
MULTIPLEXER/
DEMULTIPLEXER
X
3
ANALOG
INPUTS/
CHANNEL
INPUTS
PIN 16 = VCC
PIN 7 = VEE
PIN 8 = GND
COMMON
OUTPUT/
INPUT
1516 14 13 12 11 10
21 34567
VCC
9
8
X2 X1 X0 X3 A B C
X4 X6 X X7 X5 Enable VEE GND
Figure 2. Pinout: MC74HCT4051A
(Top View)
OUTPUTS
SELECT
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
X
FUNCTION TABLE − MC74HCT4051A
Control Inputs
ON Channels
Enable
Select
CBA
X0
X1
X2
X3
X4
X5
X6
X7
NONE
L
L
L
L
L
L
L
L
H
X = Don’t Care
Figure 3. Logic Diagram − MC74HCT4052A
Double−Pole, 4−Position Plus Common Off
X0 12
X1 14
X2 15
X3 11
Y0 1
Y1 5
Y2 2
Y3 4
A10
B9
ENABLE 6
X SWITCH
Y SWITCH
X
13
ANALOG
INPUTS/OUTPUTS
CHANNEL‐SELECT
INPUTS PIN 16 = VCC
PIN 7 = VEE
PIN 8 = GND
COMMON
OUTPUTS/INPUTS
L
L
H
H
X
L
H
L
H
X
FUNCTION TABLE − MC74HCT4052A
Control Inputs
ON ChannelsEnable
Select
BA
X0
X1
X2
X3
L
L
L
L
H
X = Don’t Care
Figure 4. Pinout: MC74HCT4052A (Top View)
1516 14 13 12 11 10
21 34567
VCC
9
8
X2 X1 X X0 X3 A B
Y0 Y2 Y Y3 Y1 Enable VEE GND
Y
3
Y0
Y1
Y2
Y3
NONE
MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
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Figure 5. Logic Diagram − MC74HCT4053A
Triple Single−Pole, Double−Position Plus Common Off
X0 12
X1 13
A11
B10
C9
ENABLE 6
X SWITCH
Y SWITCH
X
14
ANALOG
INPUTS/OUTPUTS
CHANNEL‐SELECT
INPUTS
PIN 16 = VCC
PIN 7 = VEE
PIN 8 = GND
COMMON
OUTPUTS/INPUTS
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
X
FUNCTION TABLE − MC74HCT4053A
Control Inputs
ON Channels
Enable
Select
CBA
L
L
L
L
L
L
L
L
H
X = Don’t Care
Figure 6. Pinout: MC74HCT4053A (Top View)
1516 14 13 12 11 10
21 34567
VCC
9
8
Y X X1 X0 A B C
Y1 Y0 Z1 Z Z0 Enable VEE GND
Z0
Z0
Z0
Z0
Z1
Z1
Z1
Z1
Y0
Y0
Y1
Y1
Y0
Y0
Y1
Y1
X0
X1
X0
X1
X0
X1
X0
X1
NONE
Y0 2
Y1 1Y
15
Z0 5
Z1 3Z
4
Z SWITCH
NOTE: This device allows independent control of each switch.
Channel−Select Input A controls the X−Switch, Input B controls
the Y−Switch and Input C controls the Z−Switch
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS
ÎÎÎÎ
ÎÎÎÎ
Symbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Parameter
ÎÎÎÎÎ
ÎÎÎÎÎ
Value
ÎÎÎ
ÎÎÎ
Unit
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
VCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Positive DC Supply Voltage (Referenced to GND)
(Referenced to VEE)
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
−0.5 to +7.0
−0.5 to +14.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
VEE
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Negative DC Supply Voltage (Referenced to GND)
ÎÎÎÎÎ
ÎÎÎÎÎ
−7.0 to +5.0
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
VIS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Analog Input Voltage
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
VEE − 0.5 to
VCC + 0.5
ÎÎÎ
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
Vin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Digital Input Voltage (Referenced to GND)
ÎÎÎÎÎ
ÎÎÎÎÎ
−0.5 to VCC + 0.5
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
I
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC Current, Into or Out of Any Pin
ÎÎÎÎÎ
ÎÎÎÎÎ
±25
ÎÎÎ
ÎÎÎ
mA
ÎÎÎÎ
ÎÎÎÎ
PD
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Power Dissipation in Still Air, SOIC Package†
TSSOP Package†
ÎÎÎÎÎ
ÎÎÎÎÎ
500
450
ÎÎÎ
ÎÎÎ
mW
ÎÎÎÎ
ÎÎÎÎ
Tstg
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Storage Temperature Range
ÎÎÎÎÎ
ÎÎÎÎÎ
−65 to +150
ÎÎÎ
ÎÎÎ
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
†Derating −SOIC Package: − 7 mW/°C from 65°C to 125°C
TSSOP Package: − 6.1 mW/°C from 65°C to 125°C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
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4
RECOMMENDED OPERATING CONDITIONS
ÎÎÎÎ
ÎÎÎÎ
Symbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Parameter
ÎÎÎ
ÎÎÎ
Min
ÎÎÎ
ÎÎÎ
Max
ÎÎÎ
ÎÎÎ
Unit
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
VCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Positive DC Supply Voltage (Referenced to GND)
(Referenced to VEE)
ÎÎÎ
ÎÎÎ
ÎÎÎ
2.0
2.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
6.0
12.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
VEE
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Negative DC Supply Voltage, Output (Referenced to
GND)
ÎÎÎ
ÎÎÎ
−6.0
ÎÎÎ
ÎÎÎ
GND
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
VIS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Analog Input Voltage
ÎÎÎ
ÎÎÎ
VEE
ÎÎÎ
ÎÎÎ
VCC
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
Vin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Digital Input Voltage (Referenced to GND)
ÎÎÎ
ÎÎÎ
GND
ÎÎÎ
ÎÎÎ
VCC
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
VIO*
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Static or Dynamic Voltage Across Switch
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
1.2
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
TA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Operating Temperature Range, All Package Types
ÎÎÎ
ÎÎÎ
−55
ÎÎÎ
ÎÎÎ
+125
ÎÎÎ
ÎÎÎ
°C
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
tr, tf
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Input Rise/Fall Time VCC = 2.0 V
(Channel Select or Enable Inputs) VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
0
0
0
0
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
1000
600
500
400
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ns
*For voltage drops across switch greater than 1.2 V (switch on), excessive VCC current may be
drawn; i.e., the current out of the switch may contain both VCC and switch input components. The
reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC CHARACTERISTICS − Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted
Symbol Parameter Condition
VCC
V
Guaranteed Limit
Unit
−55 to 25°C≤85°C≤125°C
VIH Minimum High−Level Input Voltage,
Channel−Select or Enable Inputs
Ron = Per Spec 4.5 to
5.5
2.0 2.0 2.0 V
VIL Maximum Low−Level Input Voltage,
Channel−Select or Enable Inputs
Ron = Per Spec 4.5 to
5.5
0.8 0.8 0.8 V
Iin Maximum Input Leakage Current,
Channel−Select or Enable Inputs
Vin = VCC or GND,
VEE = − 6.0 V
6.0 ±0.1 ±1.0 ±1.0 mA
ICC Maximum Quiescent Supply
Current (per Package)
Channel Select, Enable and
VIS = VCC or GND; VEE = GND
VIO = 0 V VEE = − 6.0
6.0
6.0
1
4
10
40
20
80
mA
DC CHARACTERISTICS − Analog Section
Symbol Parameter Condition VCC VEE
Guaranteed Limit
Unit
−55 to 25°C≤85°C≤125°C
Ron Maximum “ON” Resistance Vin = VIL or VIH; VIS = VCC to
VEE; IS ≤ 2.0 mA
(Figures 7, 8)
4.5
4.5
6.0
0.0
−4.5
−6.0
190
120
100
240
150
125
280
170
140
W
Vin = VIL or VIH; VIS = VCC or
VEE (Endpoints); IS ≤ 2.0 mA
(Figures 7, 8)
4.5
4.5
6.0
0.0
−4.5
−6.0
150
100
80
190
125
100
230
140
115
DRon Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
Vin = VIL or VIH;
VIS = 1/2 (VCC − VEE);
IS ≤ 2.0 mA
4.5
4.5
6.0
0.0
−4.5
−6.0
30
12
10
35
15
12
40
18
14
W
Ioff Maximum Off−Channel Leakage
Current, Any One Channel
Vin = VIL or VIH;
VIO = VCC − VEE;
Switch Off (Figure 9)
5.0 −5.0 0.1 0.5 1.0
mA
Maximum Off−Channel HCT4051A
Leakage Current, HCT4052A
Common Channel HCT4053A
Vin = VIL or VIH;
VIO = VCC − VEE;
Switch Off (Figure 10)
5.0
5.0
5.0
−5.0
−5.0
−5.0
0.2
0.1
0.1
2.0
1.0
1.0
4.0
2.0
2.0
Ion Maximum On−Channel HCT4051A
Leakage Current, HCT4052A
Channel−to−Channel HCT4053A
Vin = VIL or VIH;
Switch−to−Switch =
VCC − VEE; (Figure 11)
5.0
5.0
5.0
−5.0
−5.0
−5.0
0.2
0.1
0.1
2.0
1.0
1.0
4.0
2.0
2.0
mA
MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
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AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol Parameter
VCC
V
Guaranteed Limit
Unit
−55 to 25°C≤85°C≤125°C
tPLH,
tPHL
Maximum Propagation Delay, Channel−Select to Analog Output
(Figure 15)
2.0
3.0
4.5
6.0
270
90
59
45
320
110
79
65
350
125
85
75
ns
tPLH,
tPHL
Maximum Propagation Delay, Analog Input to Analog Output
(Figure 16)
2.0
3.0
4.5
6.0
40
25
12
10
60
30
15
13
70
32
18
15
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Enable to Analog Output
(Figure 17)
2.0
3.0
4.5
6.0
160
70
48
39
200
95
63
55
220
110
76
63
ns
tPZL,
tPZH
Maximum Propagation Delay, Enable to Analog Output
(Figure 17)
2.0
3.0
4.5
6.0
245
115
49
39
315
145
69
58
345
155
83
67
ns
Cin Maximum Input Capacitance, Channel−Select or Enable Inputs 10 10 10 pF
CI/O Maximum Capacitance Analog I/O 35 35 35 pF
(All Switches Off) Common O/I: HCT4051A
HCT4052A
HCT4053A
130
80
50
130
80
50
130
80
50
Feed−through 1.0 1.0 1.0
CPD Power Dissipation Capacitance (Figure 19)* HCT4051A
HCT4052A
HCT4053A
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
pF
45
80
45
*Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.
MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
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ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
Symbol Parameter Condition
VCC
V
VEE
V
Limit*
Unit
25°C
BW Maximum On−Channel Bandwidth
or Minimum Frequency Response
(Figure 12)
fin = 1 MHz Sine Wave; Adjust fin Voltage
to Obtain 0 dBm at VOS; Increase fin
Frequency Until dB Meter Reads −3 dB;
RL = 50 W, CL = 10 pF
2.25
4.50
6.00
−2.25
−4.50
−6.00
‘51 ‘52 ‘53 MHz
80
80
80
95
95
95
120
120
120
−Off−Channel Feed−through
Isolation (Figure 13)
fin = Sine Wave; Adjust fin Voltage to
Obtain 0 dBm at VIS
fin = 10 kHz, RL = 600 W, CL = 50 pF
2.25
4.50
6.00
−2.25
−4.50
−6.00
−50
−50
−50
dB
fin = 1.0 MHz, RL = 50 W, CL = 10 pF
2.25
4.50
6.00
−2.25
−4.50
−6.00
−40
−40
−40
−Feedthrough Noise.
Channel−Select Input to Common
I/O (Figure 14)
Vin ≤ 1 MHz Square Wave (tr = tf = 6 ns);
Adjust RL at Setup so that IS = 0 A;
Enable = GND RL = 600 W, CL = 50 pF
2.25
4.50
6.00
−2.25
−4.50
−6.00
25
105
135
mVPP
RL = 10 kW, CL = 10 pF
2.25
4.50
6.00
−2.25
−4.50
−6.00
35
145
190
−Crosstalk Between Any Two
Switches (Figure 18)
(Test does not apply to HCT4051A)
fin = Sine Wave; Adjust fin Voltage to
Obtain 0 dBm at VIS
fin = 10 kHz, RL = 600 W, CL = 50 pF
2.25
4.50
6.00
−2.25
−4.50
−6.00
−50
−50
−50
dB
fin = 1.0 MHz, RL = 50 W, CL = 10 pF
2.25
4.50
6.00
−2.25
−4.50
−6.00
−60
−60
−60
THD Total Harmonic Distortion
(Figure 20)
fin = 1 kHz, RL = 10 kW, CL = 50 pF
THD = THDmeasured − THDsource
VIS = 4.0 VPP sine wave
VIS = 8.0 VPP sine wave
VIS = 11.0 VPP sine wave
2.25
4.50
6.00
−2.25
−4.50
−6.00
0.10
0.08
0.05
%
*Limits not tested. Determined by design and verified by qualification.
Figure 7a. Typical On Resistance, VCC − VEE = 2.0 V Figure 7b. Typical On Resistance, VCC − VEE = 3.0 V
250
200
150
100
50
0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
Ron , ON RESISTANCE (OHMS)
100
80
60
40
20
0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.25
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
Ron , ON RESISTANCE (OHMS)
25°C
-55°C
125°C
25°C
-55°C
125°C
2.0
0
300 180
160
140
120
02.5 2.75 3.0
Figure 7.
MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
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Figure 7c. Typical On Resistance, VCC − VEE = 4.5 V Figure 7d. Typical On Resistance, VCC − VEE = 6.0 V
120
100
80
60
40
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
Ron , ON RESISTANCE (OHMS)
75
60
45
30
15
0 1.0 2.0 3.0 4.0 5.0 6.03.5 4.5 5.5
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
Ron , ON RESISTANCE (OHMS)
20
0
25°C
-55°C
125°C
25°C
-55°C
125°C
90
105
00.5 1.5 2.5
Figure 7e. Typical On Resistance, VCC − VEE = 9.0 V
01
70
60
50
40
30
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
Ron , ON RESISTANCE (OHMS)
20
10
234 56789
25°C
-55°C
125°C
80
0
Figure 7f. Typical On Resistance, VCC − VEE = 12.0 V
01
60
50
40
30
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
Ron , ON RESISTANCE (OHMS)
20
10
234 89101112
25°C
-55°C
125°C
0576
Figure 8. On Resistance Test Set−Up
PLOTTER
MINI COMPUTER
PROGRAMMABLE
POWER
SUPPLY
DC ANALYZER
VCC
DEVICE
UNDER TEST
+-
VEE
ANALOG IN COMMON OUT
GND
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Figure 9. Maximum Off Channel Leakage Current,
Any One Channel, Test Set−Up
Figure 10. Maximum Off Channel Leakage Current,
Common Channel, Test Set−Up
Figure 11. Maximum On Channel Leakage Current,
Channel to Channel, Test Set−Up
Figure 12. Maximum On Channel Bandwidth,
Test Set−Up
Figure 13. Off Channel Feedthrough Isolation,
Test Set−Up
Figure 14. Feedthrough Noise, Channel Select to
Common Out, Test Set−Up
OFF
OFF
6
7
8
16
COMMON O/I
VCC
VEE
VIH
NC
A
VCC
VEE
VCC
OFF
OFF
6
7
8
16
COMMON O/I
VCC
VEE
VIH
ANALOG I/O
VCC
VEE
VCC
ON
OFF
6
7
8
16
COMMON O/I
VCC
VEE
VIL
VCC
VEE
VCC
N/C
A
ANALOG I/O
ON
6
7
8
16
VCC
VEE
0.1mF
CL*
fin
RL
dB
METER
*Includes all probe and jig capacitance
OFF
6
7
8
16
VCC
VEE
0.1mF
CL*
fin
RL
dB
METER
*Includes all probe and jig capacitance
VOS
VOS
RL
VIS
VIL or VIH
CHANNEL SELECT
ON/OFF
6
7
8
16
VCC
VEE
CL*
RL
*Includes all probe and jig capacitance
CHANNEL SELECT
TEST
POINT
COMMON O/I
11
VCC
OFF/ON
ANALOG I/O
RL
RL
3.0 V
GND
Vin ≤1 MHz
tr = tf = 6 ns
MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
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9
Figure 15a. Propagation Delays, Channel Select
to Analog Out
Figure 15b. Propagation Delay, Test Set−Up Channel
Select to Analog Out
Figure 16a. Propagation Delays, Analog In
to Analog Out
Figure 16b. Propagation Delay, Test Set−Up
Analog In to Analog Out
Figure 17a. Propagation Delays, Enable to
Analog Out
Figure 17b. Propagation Delay, Test Set−Up
Enable to Analog Out
VCC
GND
CHANNEL
SELECT
ANALOG
OUT 50%
tPLH tPHL
Vm
ON/OFF
6
7
8
16
VCC
CL*
*Includes all probe and jig capacitance
CHANNEL SELECT
TEST
POINT
COMMON O/I
OFF/ON
ANALOG I/O
VCC
VCC
GND
ANALOG
IN
ANALOG
OUT 50%
tPLH tPHL
50%
ON
6
7
8
16
VCC
CL*
*Includes all probe and jig capacitance
TEST
POINT
COMMON O/I
ANALOG I/O
ON/OFF
6
7
8
ENABLE
VCC
ENABLE VM
tftr
VCC
GND
ANALOG
OUT
tPZL
ANALOG
OUT
tPZH
HIGH
IMPEDANCE
VOL
VOH
HIGH
IMPEDANCE
10%
90%
tPLZ
tPHZ
50%
50%
ANALOG I/O
CL*
TEST
POINT
16
VCC
1kW
1
2
1
2
POSITION 1 WHEN TESTING tPHZ AND tPZH
POSITION 2 WHEN TESTING tPLZ AND tPZL
(VI)
VI = GND to 3.0 V
Vm = 1.3 V
(VI)
VI = GND to 3.0 V
Vm = 1.3 V
Figure 15.
Figure 16.
Figure 17.
90%
10%
VM
MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
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10
RL
Figure 18. Crosstalk Between Any Two
Switches, Test Set−Up
Figure 19. Power Dissipation Capacitance,
Test Set−Up
Figure 20a. Total Harmonic Distortion, Test Set−Up Figure 20b. Plot, Harmonic Distortion
0
-10
-20
-30
-40
-50
- 100 1.0 2.0 3.125
FREQUENCY (kHz)
dB
-60
-70
-80
-90
FUNDAMENTAL FREQUENCY
DEVICE
SOURCE
ON
6
7
8
16
VEE CL*
*Includes all probe and jig capacitance
OFF
RL
RL
VIS
RLCL*
VOS
fin
0.1mF
ON/OFF
6
7
8
16
VCC
CHANNEL SELECT
NC
COMMON O/I
OFF/ON
ANALOG I/O
VCC
A
11
VCC
VEE
ON
6
7
8
16
VCC
VEE
0.1mF
CL*
fin
RL
TO
DISTORTION
METER
*Includes all probe and jig capacitance
VOS
VIS
Figure 20.
APPLICATIONS INFORMATION
The maximum analog voltage swings are determined by
the supply voltages VCC and VEE. The positive peak analog
voltage should not exceed VCC. Similarly, the negative peak
analog voltage should not go below VEE. In this example,
the difference between VCC and VEE is ten volts. Therefore,
using the configuration of Figure 21, a maximum analog
signal of ten volts peak−to−peak can be controlled. Unused
analog inputs/outputs may be left floating (i.e., not
connected). However, tying unused analog inputs and
outputs to VCC or GND through a low value resistor helps
minimize crosstalk and feed−through noise that may be
picked up by an unused switch.
Although used here, balanced supplies are not a
requirement. The only constraints on the power supplies are
that:
VCC − GND = 2 to 6 V
VEE − GND = 0 to −6 V
VCC − VEE = 2 to 12 V
and VEE ≤ GND
When voltage transients above VCC and/or below VEE are
anticipated on the analog channels, external Germanium or
Schottky diodes (Dx) are recommended as shown in
Figure 22. These diodes should be able to absorb the
maximum anticipated current surges during clipping.
MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
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11
ANALOG
SIGNAL
Figure 21. Application Example Figure 22. External Germanium or
Schottky Clipping Diodes
a. Using Pull−Up Resistors with a HC Device b. Using HCT Interface
Figure 23. Interfacing LSTTL/NMOS to CMOS Inputs
ON
6
7
8
16
+5V
-5V
ANALOG
SIGNAL
+5V
-5V
+5V
-5V
11
10
9
TO EXTERNAL CMOS
CIRCUITRY 0 to 5V
DIGITAL SIGNALS
ON/OFF
7
8
16
VCC
VEE
VEE
Dx
VCC
Dx
VEE
Dx
VCC
Dx
ANALOG
SIGNAL
ON/OFF
6
7
8
16
+5V
VEE
ANALOG
SIGNAL
+5V
VEE
+5V
VEE
11
10
9
R
*
R R
LSTTL/NMOS
CIRCUITRY
+5V
* 2K ≤ R ≤ 10K
ANALOG
SIGNAL
ON/OFF
6
7
8
16
+5V
VEE
ANALOG
SIGNAL
+5V
VEE
+5V
VEE
11
10
9
LSTTL/NMOS
CIRCUITRY
+5V
Figure 24. Function Diagram, HCT4051A
13 X0
14 X1
15 X2
12 X3
1X4
5X5
2X6
4X7
3X
LEVEL
SHIFTER
LEVEL
SHIFTER
LEVEL
SHIFTER
LEVEL
SHIFTER
11
A
10
B
9
C
6
ENABLE
HC405x HCT405x
MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
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12
Figure 25. Function Diagram, HCT4053A
Figure 26. Function Diagram, HCT4052A
13 X1
12 X0
1Y1
2Y0
3Z1
5Z0
14 X
LEVEL
SHIFTER
LEVEL
SHIFTER
LEVEL
SHIFTER
LEVEL
SHIFTER
11
A
10
B
9
C
6
ENABLE
12 X0
14 X1
15 X2
11 X3
1Y0
5Y1
2Y2
4Y3
3Y
LEVEL
SHIFTER
LEVEL
SHIFTER
LEVEL
SHIFTER
10
A
9
B
6
ENABLE
13 X
15 Y
4Z
MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
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13
ORDERING INFORMATION
Device Package Shipping†
MC74HCT4051ADG SOIC−16
(Pb−Free)
48 Units / Rail
MC74HCT4051ADR2G SOIC−16
(Pb−Free)
2500 / Tape & Reel
MC74HCT4051ADTG TSSOP−16* 96 Units / Rail
M74HCT4051ADTR2G TSSOP−16* 2500 / Tape & Reel
MC74HCT4052ADG SOIC−16
(Pb−Free)
48 Units / Rail
MC74HCT4052ADR2G SOIC−16
(Pb−Free)
2500 / Tape & Reel
MC74HCT4052ADTG TSSOP−16* 96 Units / Rail
M74HCT4052ADTR2G TSSOP−16* 2500 / Tape & Reel
MC74HCT4052ADWG SOIC−16 WIDE
(Pb−Free)
48 Units / Rail
M74HCT4052ADWR2G SOIC−16 WIDE
(Pb−Free)
1000 / Tape & Reel
MC74HCT4053ADG SOIC−16
(Pb−Free)
48 Units / Rail
MC74HCT4053ADR2G SOIC−16
(Pb−Free)
2500 / Tape & Reel
MC74HCT4053ADTG TSSOP−16* 96 Units / Rail
M74HCT4053ADTR2G TSSOP−16* 2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
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14
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE B
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
ÇÇÇ
ÇÇÇ
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.18 0.28 0.007 0.011
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
____
SECTION N−N
SEATING
PLANE
IDENT.
PIN 1
18
16 9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
ÉÉ
ÉÉ
DETAIL E
F
M
L
2X L/2
−U−
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
−T−
−V−
−W−
0.25 (0.010)
16X REFK
N
N
7.06
16X
0.36 16X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
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15
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45_
G
8 PLP
−B−
−A−
M
0.25 (0.010) B S
−T−
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
6.40
16X
0.58
16X 1.12
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
16
89
8X
MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
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16
PACKAGE DIMENSIONS
SOIC−16 WIDE
DW SUFFIX
CASE 751G−03
ISSUE C
D
14X
B16X
SEATING
PLANE
S
A
M
0.25 B S
T
16 9
81
hX 45_
M
B
M
0.25
H8X
E
B
A
e
T
A1
A
L
C
q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
DIM MIN MAX
MILLIMETERS
A2.35 2.65
A1 0.10 0.25
B0.35 0.49
C0.23 0.32
D10.15 10.45
E7.40 7.60
e1.27 BSC
H10.05 10.55
h0.25 0.75
L0.50 0.90
q0 7
__
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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Phone: 81−3−5773−3850
MC74HCT4051A/D
LITERATURE FULFILLMENT:
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