Enpirion® Power Datasheet
EN2390Q I 9A Pow er SoC
Volt age M ode Synchr onous Buck
With Integrated In ductor
Not Recom m ended for New Desi gns
Description
The EN2390QI is a Power System on a Chip
(PowerS oC) DC-DC converter. I t integrates M OSFET
switches, small-signal control circuits, compensation
and an integrated inductor in an advanced
11x10x3mm QFN module. It offers high efficiency,
excellent line and load regulation over temperature.
The EN2390QI operates over a wide input voltage
range and is specifically designed to m eet the precise
voltage and fast transient requirements of high-
performance products. The EN2390QI features
frequency synchro nization to an external clock, powe r
OK output voltage monitor, programmable soft-start
along with thermal and short circuit protection. The
device’s advanced circui t design, ultra high switching
frequency and proprietary integrated inductor
technology delivers high-quality, ultra compact, non-
isolated DC-DC conversion.
The Altera Enpirion solution significantly helps in
system design and productivity by offering greatly
simplified board design, layout and manufacturing
requirements. In addition, overall system level
reliability is improved given the small number of
components required with the Altera Enpirion
solution.
All Altera Enpirion products are RoHS compliant,
halogen free and are compatible with lead-free
manufacturing environments.
Features
• I ntegrated I nductor, M OSFETS, Contro ller
• Total S olution Size Estim ate: 235mm2
• Wide I nput V oltage Range: 4.5V – 14V
• 1% Initial Output Voltage Accuracy
• Master/Slave Configurat ion for Parallel Operation
o Up to 4 Devices with 29A capability
• Frequency Synchro niz ation (Externa l Clock)
• Output Enable Pin and Power OK Signal
• Program m able S oft-Start Tim e
• Under V oltage Lockout P rotection (UVLO)
• Short Circuit Protection
• Therm al Shutdow n Protection
• RoHS Com pliant, M S L Level 3, 260oC Reflow
Applications
• Space Constrained Applications
• Distributed Power Architectures
• Output Voltage Ripple Sensitive Applications
• Beat Frequency Sensitive Applications
• Servers, Em bedded C omputing S ystem s,
LAN/SAN Adapter Cards, RAI D Storage Systems,
Industrial Automation, Test and M easurement,
and Telecommunications
V
OUT
V
IN
2x
22µF
1206
VOUT
ENABLE
AGND
PVIN
AVIN
PGND PGND
47nF
VFB
R
A
R
B
R
CA
C
A
RCLX
2x
47µF
0805
AVINO
PG
BTMP
EN2390QI
SS
VDDB
BGND
FQADJ
4.75k
1µF
0.22µF
47nF
R
FS
100k
1µF
CGND M/S
OFF
ON
EAIN
R
EA
Figure 1. Sim plif ied App licati ons Circuit (Footprint Optimized)
Figure 2. Highest Ef ficie ncy in Sm allest Solution Size
0
10
20
30
40
50
60
70
80
90
100
0123456789
EFFICIENCY (%)
OUTPUT CURRENT (A)
Efficiency vs. Output Current
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 1.0V
CONDITIONS
V
IN
= 12.0V
AVIN = 3.3V
Dual Supply
07515 June 2, 2015 Rev D
EN2390QI
Ordering Information
Part Num be r
Package Markings
TAMBIENT Ratin g (° C)
Package Description
EN2390QI
EN2390QI
-40 to +85
76-pin (11mm x 10mm x 3mm) QFN T&R
EVB-EN2390QI
EN2390QI
QF N E valuati on B oard
Packi ng and Marki ng I nform a tion: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
Pin Assignments (Top View)
NC
1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
2
3
4
5
6
7
8
9
KEEP OUT
KEEP OUT
KEEP OUT
NC
15
NC
NC
NC
16
17
18
77
PGND
10
11
12
13
14
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
NC
NC(SW)
NC(SW)
PGND
PGND
PGND
PGND
PGND
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
NC
NC
PGND
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
AVINO
PG
BGND
VDDB
S_IN
BTMP
S_OUT
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
PVIN
PVIN
PVIN
PVIN
NC(SW)
NC(SW)
FQADJ
NC
RCLX
SS
EAIN
VFB
M/S
AGND
AVIN
ENABLE
POK
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
CGND
NC(SW)
57
NC
NC
NC
NC
NC
Figure 3: P i n O ut Di agram (Top View)
NOTE A: NC pins are not to be electrically connec ted to each other or to any external signal, ground, or voltage. A ll pins
including NC pins must be soldered to the PCB. Failure to follow this guideline may res ult in part malf unction or dam age.
NOTE B: Shaded area highlights exposed metal below the package that is not to be mechanically or electrically
connected to t he PCB. Refer t o F i gure 16 for detail s.
NOT E C : White ‘ dot ’ on top left i s pin 1 i ndi cat or on top of the devi ce package.
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07515 June 2, 2015 Rev D
EN2390QI
Pin Description
I/O Legend: P=Power G=Ground NC=No C onnect I=Input O=Output I/O=Input/Output
PIN
NAME
I/O
FUNCTION
1-19, 29,
30, 67,
72-76
NC NC
NO CONNECT – T hese pins may be internally connect ed. Do not conne ct them to each
other or to any other electrical signal . Failure to follow this guideline may res ult in device
damage.
20-28 VOUT O
Regulated converter output. Connect these pins to the load and place output capacitor
between these pins and PGND pins 33-35.
31, 32,
69-71 NC(SW) NC
NO CONNECT – T hese pins are internally connect ed to the com mon switchi ng node of
the internal MOSFET s. T hey are not to be electrically connect ed to any external signal,
ground, or voltage. Failure to f ollow this guideline may resul t in damage to th e device.
33-38 PGND G
I nput/Output power ground. Connect these pins to the ground elect rode of the input and
output f ilter capacitors. See VOUT and PVI N pin descript ions f or more details.
39-49 PVIN P
I nput power supply. Connect to input power supply. Decouple wit h input capacitor to
PGND pins 36-38.
50 AVINO O
I nternal 3.4V linear regulator output. Connect this pin to AV IN f or applications where
operation f rom a single input voltage (PVI N) is required. I f AVIN O is being used, place a
1µF, X5R, capacitor between AVIN O and AGND as clos e as possi ble to AV I NO.
51
PG
I/O
PMOS gate. Place a 47nF, X5R, capacitor between this pin and BT MP.
52
BTMP
I/O
Bottom plate ground. See pin 51 descr ipti on.
53 VDDB O
I nternal regulated voltage used for the internal control circuit ry. Place a 0.22µF, X5R,
capacitor between this pin and BGND.
54
BGND
G
Ground f or VDD B. Do not connect BGND to any other ground. See pin 53 description.
55 S_IN I
Digital synchronizat ion input. T his pin accept s either an input clock to phase lock the
internal switching frequency or a S_OUT signal fr om another EN2390QI. Leave this pin
f loating if not used.
56 S_OUT O
Digital synchronizat ion output . PWM signal is output on this pin. Leave this pin floating if
not used.
57 POK O
Power OK is an open drain transistor (pulled up to AVI N or simi lar voltage) used f or
power system state indicat ion. POK is logic high when VOUT is within -10% to +20% of
VOUT nominal. Leave this pin floating if not used.
58 ENABLE I
Output enable. Applying a logic high to this pin enables the output and initi ates a sof t-
start. Apply ing a logic low disables the outp ut. ENABLE logic cannot be higher than
AVIN ( refer to Absolute Maxi mum Ratings). Do not leave floating. See Power Up/Dow n
Sequencing sect ion for details.
59 AVIN P
3.3V Input power supply f or the controller. Place a 1µF, X5R, capacit or between AVI N
and AGND
60 AGND G
Analog ground. T his is the ground return f or the controller. All AGND pins need to be
connected to a quiet ground.
61 M/S
A logic level low configures the device as Master and a logic level high configures the
device as a Slave. Connect to ground in standalone mode.
62 VFB I/O
External f eedback input. T he f eedback loop is cl osed thr ough this pin. A voltage divider at
VOUT is used to set the output voltage. T he mid-point of the divider is connected to VFB .
A phase lead network f rom this pin to VOUT is also required to st abili ze the loop.
63 EAIN I
Optional error amplif ier input. Allows for custom izati on of the control loop f or
perf ormance optimizati on. Leave this pin f loating if not used.
64 SS I/O
Soft-start node. T he sof t-start capac itor is connected between this pin and AGND. T he
value of this capacitor determ ines the startup ti me. See Sof t-S tart Operation in the
Functional Descript ion sect ion for details.
65
RCLX
I/O
Short circuit protec ti on. Connect a 100k resistor f rom RCLX to ground.
66 FQADJ I/O
Adding a resistor (R
FS
) to this pin will adjust the switchi ng f requency of the EN2390QI.
See T able 1 for suggested r esis tor values on RFS for various PVI N/VOUT combinati on s to
maximize ef ficiency. Do not leave this pin floating.
68
CGND
T est pin. For Enpirion I nternal Use Only. Connect to GND plane at all times.
77 PGND
Not a perimeter pin. Device thermal pad to be connected to the sy stem GND plane for
heat-sinking purposes.
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07515 June 2, 2015 Rev D
EN2390QI
Absolute Maximum Ratings
CAUTION: Absolute M axi mum ratings are stress rati ngs only. F unc ti onal operat i on beyond t he recom mended operating
conditions is not implied. S t ress bey ond t he absolute m axim um ratings m ay im pai r devi c e l i fe. Exposure t o absolute
m axi m um rated c ondi tions for ext ended peri ods may affect devi ce reli abi l i t y.
PARAMETER
SYMBOL
MIN
MAX
UNITS
Pin Voltages – PVI N, VOU T, PG
-0.5
15
V
Pin Voltages – ENABLE, S_IN, M/S, POK
-0.5
AV
IN
+ 0.3
V
Pin Voltages – AVINO, AVIN, ENABLE, S_IN, S_OUT , M/S
-0.5
6.0
V
Pin Voltages – VFB, SS, EAIN, RCLX, FQADJ, VDDB, BT MP
-0.5
2.75
V
Dual Supply PVIN R ising and Falling Sl ew R ate (Note 1)
0.3
25
V/ms
Single Supply PVI N Risi ng and Falling Sle w Rate (Note 1)
0.3
6
V/ms
Maximum Continuous Output Curr ent
I
OUT_CONT_MAX
14
A
Storage T emperature Range
T
STG
-65
150
°C
Maximum Operating Junc tion T emperatu re
T
J-ABS Max
150
°C
Ref low T emp, 10 Sec, MSL3 JEDEC J -STD-020A
260
°C
ESD Rating (based on Human Body Model)
2000
V
Recommended Operating Conditions
PARAMETER
SYMBOL
MIN
MAX
UNITS
I nput Voltage Range
PVIN
4.5
14
V
AVIN: Controller Supply Volt age
AVIN
2.5
5.5
V
Output Voltage Range (Note 2)
V
OUT
0.75
3.3
V
Output Curr ent
I
OUT
0
9
A
Operating Ambient T emperature
T
A
-40
+85
°C
Operating Junction T emperature
T
J
-40
+125
°C
Thermal Characteristics
PARAMETER
SYMBOL
TYP
UNITS
T hermal Resistance: Junction to A mbient (0 LFM) (Note 3)
θ
JA
15
°C/W
T hermal Resistance: Junction to Cas e (0 LFM)
θJC
1.5
°C/W
T hermal Shutdown
T
SD
160
°C
T hermal Shutdown H ysteresi s
T
SDH
35
°C
Note 1: PVI N rising and f alling slew rates cannot be outs i de of s peci fi cati on. F or accurat e power up sequenc i ng, us e a
fast E NA BLE l ogi c (>3V /100µs) after bot h A VIN and P VIN are high.
No te 2: Dropout : Maxi m um V OUT ≤ VIN - 2.5V
Note 3: Based on 2oz. external copper layers and proper thermal design in l i ne wi t h EIJ/ JE DE C JESD51-7 st andard for
high therm al conducti vi ty boards.
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07515 June 2, 2015 Rev D
EN2390QI
Electrical Characteristics
NOTE: VIN=12V, Minim um and Maxim um values are over operating am bi ent t em perature range unl ess otherwise not ed.
Typical values are at TA = 25°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Operating Input
Voltage PVIN 4.5 14.0 V
Controller Input
Voltage AVIN 2.5 5.5 V
AVIN U nder Voltage
Lock-out rising AVINUVLOR
Voltage above which UVLO is not
asserted 2.3 V
AVIN U nder Voltage
Lock-out f alling AVINOVLOF
Voltage below which UVLO is
asserted 2.1 V
AVIN pin I nput Curr ent
I
AVIN
11
mA
I nternal Linear
Regulator Output
Voltage AVINO 3.4 V
Shut-Dow n Supply
Current
IPVIN
S
PVIN =1 2V, AVI N =3 .4V, ENABLE=0V
300
µA
IAVIN
S
PVIN =1 2V, AVI N =3 .4V, ENABLE=0V
50
µA
Feedback Pin Volt age VFB
Feedback node voltage at:
VIN = 12V, ILOAD = 0, T A = 25°C Only 0.594 0.60 0.606 V
Feedback Pin Volt age VFB
Feedback node voltage at:
4.5V ≤ VIN ≤ 14V
0A ≤ ILOAD ≤ 9A, TA = -40 to 85°C
0.588 0.60 0.612 V
Feedback pin I nput
Leakage Current IFB
VFB pin input leakage current
(Note 4) -5 5 nA
V
OUT
R ise Time
t
RISE
C
SS
= 47nF (Note 4, Note 5, Note 6)
1.96
2.8
3.64
ms
Soft Start Capacitor
Range CSS_RANGE 10 47 68 nF
Continuous Output
Current IOUT_MAX_CONT Subject to thermal derati ng 0 9 A
ENABLE Logic High
V
ENABLE_HIGH
4.5V ≤ V
IN
≤ 14V;
1.25
AV
IN
V
ENABLE Logic Low
V
ENABLE_LOW
4.5V ≤ V
IN
≤ 14V;
0
0.95
V
ENABLE Lockout
Time TENLOCKOUT 8 ms
ENABLE pin Input
Current IENABLE
AVIN = 5.5V
EN ABL E = 1 .8 V ;
EN ABL E = 3 .3 V ;
EN ABL E = 5 .5 V;
5
11
23
8
18
32
µA
Switching Frequency
F
SW
R
FS
=3.01kΩ
1.0
MHz
External SYNC Clock
Frequency Lock
Range FPLL_LOCK Range of SYNC clock f requency (See
Tabl e 1) 0.8 1.8 MHz
S_IN T hreshold – Low
V
S_IN_LO
S_IN Clock Logic Low Level (Note 3)
0.8
V
S_IN T hreshold – High
V
S_IN_HI
S_IN Clock Logic High Level (Note 3)
1.8
2.5
V
S_OUT T hreshold –
Low VS_OUT_LO
S_OUT Clock Logic Low Level
(Note 3) 0.8 V
S_OUT T hreshold –
V
S_OUT_HI
S_OUT Clock Logic High Level
1.8
2.5
V
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07515 June 2, 2015 Rev D
EN2390QI
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
High
(Note 3)
POK Lower T hreshold POKLT
Percentage of Nominal Output
Voltage for POK to be Low 90 %
POK Output low
Voltage VPOKL With 4mA Current Sink into PO K 0.4 V
POK Output Hi
Voltage VPOKH PVIN Range: 4.5V ≤ VIN ≤ 14V AVIN V
POK pin V
OH
leakage
current IPOKL POK High (Note 3) 1 µA
M/S Pin Logic Low
V
T-LOW
Tie Pin to GND
0.8
V
M/S Pin Logic High VT-HIGH
Pull up to AVIN Through an External
Resistor REXT 1.8 V
M/S Pin Input Curr ent IM/S
REXT = 15kΩ;
AVIN = 3 .4 V;
AVIN = 5 .5 V;
65
175 µA
Note 4: Parameter not produc ti on t est ed but is guarant eed by design.
Note 5: Ri se t i m e calculation begi ns when AVIN > V UVLO and E NABLE = HIGH.
Note 6: VOUT Ri se Ti m e A ccuracy does not incl ude soft-s t art c apaci t or tolerance.
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07515 June 2, 2015 Rev D
EN2390QI
Typical Performance Curves
0
10
20
30
40
50
60
70
80
90
100
0123456 7 8 9
EFFICIENCY (%)
OUTPUT CURRENT (A)
Efficiency vs. Output Current
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 1.0V
CONDITIONS
V
IN = 12.0V
Single Supply
0
10
20
30
40
50
60
70
80
90
100
0 1 2 3 45678 9
EFFICIENCY (%)
OUTPUT CURRENT (A)
Efficiency vs. Output Current
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 1.0V
CONDITIONS
V
IN
= 12.0V
AVIN = 3.3V
Dual Supply
2
3
4
5
6
7
8
9
10
25 30 35 40 45 50 55 60 65 70 75 80 85
MAXIMUM OUTP UT CURRENT (A)
AMBIENT TEMPER ATURE (°C)
Output Current De-rating
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
CONDITIONS
V
IN
= 12V
T
JMAX
= 125°C
θ
JA
= 15°C/W
11x10x3mm QFN
No Air Flow
2
3
4
5
6
7
8
9
10
25 30 35 40 45 50 55 60 65 70 75 80 85
MAXIMUM OUTP UT CURRENT (A)
AMBIENT TEMPER ATURE (°C)
Output Current De-rating
with A ir Flow (200fpm)
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
CONDITIONS
V
IN
= 12V
T
JMAX
= 125°C
θ
JA
= 12.5°C/W
11x10x3mm QFN
Air Flow (200fpm)
2
3
4
5
6
7
8
9
10
25 30 35 40 45 50 55 60 65 70 75 80 85
MAXIMUM OUTP UT CURRENT (A)
AMBIENT TEMPER ATURE (°C)
Output Current De-rating
with A ir Flow (400fpm)
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
CONDITIONS
V
IN
= 12V
T
JMAX
= 125°C
θ
JA
= 11°C/W
11x10x3mm QFN
Air Flow (400fpm)
2
3
4
5
6
7
8
9
10
25 30 35 40 45 50 55 60 65 70 75 80 85
MAXIMUM OUTP UT CURRENT (A)
AMBIENT TEMPER ATURE (°C)
Output Current De-rating
with Heat Sink
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
CONDITIONS
V
IN
= 12V
T
JMAX
= 125°C
θ
JA
= 14°C/W
11x10x3mm QFN
Heat Sink -Wakefield
Thermal Solutions
P/N 651-B
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07515 June 2, 2015 Rev D
EN2390QI
Typical Performance Curves
2
3
4
5
6
7
8
9
10
25 30 35 40 45 50 55 60 65 70 75 80 85
MAXIMUM OUTP UT CURRENT (A)
AMBIENT TEMPER ATURE (°C)
Output Current De-rating
w/ Heat Sink and Air Flow (200fpm)
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
CONDITIONS
V
IN
= 12V
T
JMAX
= 125°C
θ
JA
= 11.5°C/W
11x10x3mm QFN
Air Flow (200fpm)
Heat Sink -Wakefield
Thermal Solutions
P/N 651-B
2
3
4
5
6
7
8
9
10
25 30 35 40 45 50 55 60 65 70 75 80 85
MAXIMUM OUTP UT CURRENT (A)
AMBIENT TEMPER ATURE (°C)
Output Current De-rating
w/ Heat Sink and Air Flow (400fpm)
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
CONDITIONS
V
IN
= 12V
T
JMAX
= 125°C
θ
JA
= 10°C/W
11x10x3mm QFN
Air Flow (400fpm)
Heat Sink -Wakefield
Thermal Solutions
P/N 651-B
0.995
0.996
0.997
0.998
0.999
1.000
1.001
1.002
1.003
1.004
1.005
0123456789
O UTPUT VO LTAGE ( V)
O UTPUT CURRENT (A)
Output Voltage vs. Output Current
VIN = 8V
VIN = 10V
VIN = 12V
CONDITIONS
V
OUT_NOM
= 1. 0V
1.195
1.196
1.197
1.198
1.199
1.200
1.201
1.202
1.203
1.204
1.205
0 1 2 3 4 5 6 7 8 9
O UTPUT VO LTAGE ( V)
O UTPUT CURRENT (A)
Output Voltage vs. Output Current
VIN = 8V
VIN = 10V
VIN = 12V
CONDITIONS
V
OUT_NOM
= 1. 2V
1.795
1.796
1.797
1.798
1.799
1.800
1.801
1.802
1.803
1.804
1.805
0123456789
O UTPUT VO LTAGE ( V)
O UTPUT CURRENT (A)
Output Voltage vs. Output Current
VIN = 8V
VIN = 10V
VIN = 12V
CONDITIONS
V
OUT_NOM
= 1. 8V
2.495
2.496
2.497
2.498
2.499
2.500
2.501
2.502
2.503
2.504
2.505
0 1 2 3 4 5 6 7 8 9
O UTPUT VO LTAGE ( V)
O UTPUT CURRENT (A)
Output Voltage vs. Output Current
VIN = 8V
VIN = 10V
VIN = 12V
CONDITIONS
V
OUT_NOM
= 2. 5V
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07515 June 2, 2015 Rev D
EN2390QI
Typical Performance Curves
1.196
1.197
1.198
1.199
1.200
1.201
1.202
1.203
1.204
-40 -15 10 35 60 85
O UTPUT VO LTAGE ( V)
AM BIENT TEMPERAT URE ( C)
Output Voltage vs. Tempe rature
LOAD = 0A
LOAD = 2A
LOAD = 4A
LOAD = 6A
LOAD = 9A
CONDITIONS
V
IN
= 14V
V
OUT_NOM
= 1. 2V
1.196
1.197
1.198
1.199
1.200
1.201
1.202
1.203
1.204
-40 -15 10 35 60 85
O UTPUT VO LTAGE ( V)
AM BIENT TEMPERAT URE ( C)
Output Voltage vs. Tempe rature
LOAD = 0A
LOAD = 2A
LOAD = 4A
LOAD = 6A
LOAD = 9A
CONDITIONS
V
IN
= 12V
V
OUT_NOM
= 1. 2V
1.196
1.197
1.198
1.199
1.200
1.201
1.202
1.203
1.204
-40 -15 10 35 60 85
O UTPUT VO LTAGE ( V)
AM BIENT TEMPERAT URE ( C)
Output Voltage vs. Tempe rature
LOAD = 0A
LOAD = 1A
LOAD = 2A
LOAD = 3A
LOAD = 4A
CONDITIONS
V
IN
= 10V
V
OUT_NOM
= 1. 2V
1.196
1.197
1.198
1.199
1.200
1.201
1.202
1.203
1.204
-40 -15 10 35 60 85
O UTPUT VO LTAGE ( V)
AM BIENT TEMPERAT URE ( C)
Output Voltage vs. Tempe rature
LOAD = 0A
LOAD = 1A
LOAD = 2A
LOAD = 3A
LOAD = 4A
CONDITIONS
V
IN
= 8V
V
OUT_NOM
= 1. 2V
0
1
2
3
4
5
6
7
8
9
10
2 4 6 8 10 12 14 16
INDIVIDUAL OUT PUT CURRENT (A)
TOTAL OUTPUT CURRENT (A)
Par allel C ur ren t Sh are Br eakdown
MASTER
SLAVE
IDEAL
CONDITIONS
EN2390QI
V
IN
= 12V
V
OUT
= 1. 2V
www.altera.com/enpirion Page 9
07515 June 2, 2015 Rev D
EN2390QI
Typical Performance Characteristics
ENABLE
Enable Startup/Shutdown Waveform (0A)
CONDITIONS
VIN = 12V, VOUT = 1 .8 V, Load = 0A, Css = 47nF
CIN = 2x22µF(1206) , CO U T = 2x47µF(1206)+ 100µF( 1206)
VOUT
POK
LOAD
ENABLE
Enable Startup/Shutdown Waveform (3A)
CONDITIONS
VIN = 12V, VOUT = 1 .8 V, Load = 3A, Css = 47nF
CIN = 2x22µF(1206) , CO U T = 2x47µF(1206)+ 100µF( 1206)
VOUT
POK
LOAD
ENABLE
Enable Startup/Shutdown Waveform (6A)
CONDITIONS
VIN = 12V, VOUT = 1 .8 V, Load = 6A, Css = 47nF
CIN = 2x22µF(1206) , CO U T = 2x47µF(1206)+ 100µF( 1206)
VOUT
POK
LOAD
ENABLE
Enable Startup/Shutdown Waveform (9A)
CONDITIONS
VIN = 12V, VOUT = 1 .8 V, Load = 9A, Css = 47nF
CIN = 2x22µF(1206) , CO U T = 2x47µF(1206)+ 100µF( 1206)
VOUT
POK
LOAD
PVIN
Power Up Waveform (0A)
VOUT
POK
LOAD
CONDITIONS
VIN = 12V, VOUT = 1 .8 V, Load = 9A, Css = 47nF
CIN = 2x22µF(1206) , CO U T = 2x47µF(1206)+ 100µF( 1206)
PVIN
Power Up Waveform (4.5A)
VOUT
POK
LOAD
CONDITIONS
VIN = 12V, VOUT = 1 .8 V, Load = 4.5A, Css = 47nF
CIN = 2x22µF(1206) , CO U T = 2x47µF(1206)+ 100µF( 1206)
www.altera.com/enpirion Page 10
07515 June 2, 2015 Rev D
EN2390QI
Typical Performance Characteristics
PVIN
Power Up Waveform (6A)
VOUT
POK
LOAD
CONDITIONS
VIN = 12V, VOUT = 1 .8 V, Load = 6A, Css = 47nF
CIN = 2x22µF(1206) , CO U T = 2x47µF(1206)+ 100µF( 1206)
PVIN
Power Up Waveform (9A)
VOUT
POK
LOAD
CONDITIONS
VIN = 12V, VOUT = 1 .8 V, Load = 9A, Css = 47nF
CIN = 2x22µF(1206) , CO U T = 2x47µF(1206)+ 100µF( 1206)
VOUT = 1V
(AC Coupled)
Output Ripple at 20MHz Bandwidth
CONDITIONS
VIN = 12V, CIN = 2x22µF ( 1206) , COUT = 2x47µF + 100µF (1206)
VOUT = 1.8V
(AC Coupled)
VOUT = 3.3V
(AC Coupled)
LOAD = 0A
20mV / DIV
VOUT = 1V
(AC Coupled)
Output Ripple at 20MHz Bandwidth
CONDITIONS
VIN = 12V, CIN = 2x22µF ( 1206) , COUT = 2x47µF + 100µF (1206)
VOUT = 1.8V
(AC Coupled)
VOUT = 3.3V
(AC Coupled)
LOAD = 9A
20mV / DIV
VOUT = 1V
(AC Coupled)
Output Ripple at 500M Hz Bandwidth
CONDITIONS
VIN = 12V, CIN = 2x22µF ( 1206) , COUT = 2x47µF + 100µF (1206)
VOUT = 1.8V
(AC Coupled)
VOUT = 3.3V
(AC Coupled)
LOAD = 0A
20mV / DIV
VOUT = 1V
(AC Coupled)
Output Ripple at 500M Hz Bandwidth
CONDITIONS
VIN = 12V, CIN = 2x22µF ( 1206) , COUT = 2x47µF + 100µF (1206)
VOUT = 1.8V
(AC Coupled)
VOUT = 3.3V
(AC Coupled)
LOAD = 9A
20mV / DIV
www.altera.com/enpirion Page 11
07515 June 2, 2015 Rev D
EN2390QI
Typical Performance Characteristics
VOUT
(A C C ouple d)
Load Transient from 0 to 3 A (V
OUT
=1V)
CONDITIONS
VIN = 12V, VOUT = 1.0V
CIN = 2x22µF (1206)
CO UT = 2 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
LOAD
VOUT
(A C C ouple d)
Load Transi ent fr om 0 to 4.5A (V
OUT
=1V)
CONDITIONS
VIN = 12V, VOUT = 1.0V
CIN = 2x22µF (1206)
CO UT = 2 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
LOAD
VOUT
(A C C ouple d)
Load Transient from 0 to 6 A (V
OUT
=1V)
CONDITIONS
VIN = 12V, VOUT = 1.0V
CIN = 2x22µF (1206)
CO UT = 2 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
LOAD
VOUT
(A C C ouple d)
Load Transient from 0 to 9 A (V
OUT
=1V)
CONDITIONS
VIN = 12V, VOUT = 1.0V
CIN = 2x22µF (1206)
CO UT = 2 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
LOAD
VOUT
(A C C ouple d)
Load Transient from 0 to 3 A (V
OUT
=3.3V)
CONDITIONS
VIN = 12V, VOUT = 3.3V
CIN = 2x22µF (1206)
CO UT = 2 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
LOAD
VOUT
(A C C ouple d)
Load Tr ansient from 0 to 4.5A (V
OUT
=3.3V)
CONDITIONS
VIN = 12V, VOUT = 3.3V
CIN = 2x22µF (1206)
CO UT = 2 x 47µF (1206) + 100µF ( 1206)
Using Best Performance Configur ation
LOAD
www.altera.com/enpirion Page 12
07515 June 2, 2015 Rev D
EN2390QI
Typical Performance Characteristics
VOUT
(A C C ouple d)
Load Transient from 0 to 6 A (V
OUT
=3.3V)
CONDITIONS
VIN = 12V, VOUT = 3.3V
CIN = 2x22µF (1206)
CO UT = 2 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
LOAD
VOUT
(A C C ouple d)
Load Transient from 0 to 9 A (V
OUT
=3.3V)
CONDITIONS
VIN = 12V, VOUT = 3.3V
CIN = 2x22µF (1206)
CO UT = 2 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
LOAD
www.altera.com/enpirion Page 13
07515 June 2, 2015 Rev D
EN2390QI
Functional Block Diagram
Soft Start
Power
Good
Logic
Band Gap
Reference
Voltage Reference Generator
Compensation
Network
Thermal Limit
UVLO
Short Circuit
Protection Gate Drive
PLL/Sawtooth
Generator
FADJ
ENABLE
SS
AGND
POK
AVIN
VFB
PGND
VOUT
NC(SW)
PVIN
S_IN
Error
Amp
PWM
Comp
(+)
(-)
(-)
(+)
Digital I/O
S_OUT
To PLL
EN2390QI
Linear
Regulator AVINO
300k
R
M/S
Compensation
Network
EAIN
PG
BTMP
BGND
VDDB
7.5k
Figure 4: F uncti onal Block Diagram
Functional Description
Synchr onous Buck Conver t e r
The EN2390QI is a highly integrated synchronous,
buck converter with integrated controller, power
MOSFET switches and integrated inductor. The
nominal input voltage (PVIN) range is 4.5V to 14V
and can support up to 9A of continuous output
current. The output voltage is programmed using
an external resistor divider network. The control
loop utili z es a Type I V Voltage-Mode compensation
network and maximizes on a low-noise PWM
topology. Much of the compensation circuitry is
internal to the device. However, a phase lead
capacitor is required along with the output voltage
feedback resistor divider to complete the Type IV
compensation network.. The high switching
frequency of the EN2390QI enables the use of
sm all size input and output filter capacitors, as well
as a wide loop bandwidth within a small foot print.
Protection Features:
The power supply has the following protection
features:
• Short Circuit Protection
• Therm al Shutdow n with Hysteresis.
• AVIN Under-Voltage Lockout P rote ction
Additional Features:
• Sw itching Frequency S ynchr onization .
• Program m able S oft-Start
• Pow er OK Output M onitoring
www.altera.com/enpirion Page 14
07515 June 2, 2015 Rev D
EN2390QI
Power Up Sequence
The EN2390QI is designed to be powered by either
a single input supply (PVIN) or two separate
supplies: one for PVIN and the other for AVIN. The
EN2390QI is not “hot pluggable.” Refer to the PVIN
Slew Rate specification on page 4.
Single Input Supply Application (PVIN):
VOUT
VIN
2x
22µF
1206
VOUT
ENABLE
AGND
PVIN
AVIN
PGND PGND
47nF
VFB
R
A
R
B
R
CA
C
A
RCLX
2x
47µF
0805
AVINO
PG
BTMP
EN2390QI
SS
VDDB
BGND
FADJ
4.75k
0.22µF
47nF
R
FS
100k
CGND M/S
EAIN
R
EA
10k
2.26k
1µF 1µF
Figure 5: Single Input Supply S chem ati c
The EN2390QI has an i nternal linear regulator that
converts PVIN to 3.4V. The output of the linear
regulator is provided on the AVINO pin once the
device is enabled. AVINO should be connected to
AVIN on the EN2390QI. In this application, the
following external components are required: Place
a 1µF, X5R/X7R capacitor between AVINO and
AGND as close as possible to AVINO. Place a
1µF, X5R/X7R capacitor between AVIN and AGND
as close as possible to AVIN. In addition, place a
resistor (RVB) between VDDB and AVIN, as shown
in Figure 5. Altera recom m ends RVB=4.75kΩ. In this
application, ENABLE cannot be asserted before
PVIN. See diagram below for a recommended
startup and shutdown sequencing.
Fi gure 6: S i ngl e S uppl y S tart up/Shut down S equence
If no external enable signal is used, a resister
divider (see Figure 5) fr om PVIN to ENABLE an d
then to ground can be used to enable and disable
the device at a programmed PVIN voltage level.
The lower resistor (2.26k) can be adjusted to set
startup and shutdown at a specific PVIN voltage
level. In this operating mode the minimum PVIN is
6.8V due to the ENABLE threshold. See ENABLE
and DISABLE thresholds in the Electrical
Characteristics table.
Dual Input Supply Application (PVIN and AVIN) :
V
OUT
V
IN
2x
22µF
1206
VOUT
ENABLE
AGND
PVIN
AVIN
PGND PGND
47nF VFB
R
A
R
B
R
CA
C
A
RCLX
2x
47µF
0805
AVINO
PG BTMP
EN2390QI
SS
VDDB BGND
FADJ
0.22µF
47nF
R
FS
100k
1µF
CGND M/S
OFF
ON EAIN
R
EA
V
AVIN
Figure 7: Dual Input Suppl y S chem at i c
I n this application, place a 1µF, X5R/X7R, capacit o r
between AVIN and AGND as close as possible to
AVIN. Refer to Figure 7 for a recommended
schematic for a dual input supply application.
For dual input supply applications, the sequencing
of the two input supplies, PVIN and AVIN, is very
im portant. There are two com m on acceptable turn-
on sequences for the device. AVIN can always
come up before PVIN. If PVIN comes up before
AVIN, then ENABLE must be toggled last, after
AVIN is asserted. Do not turn off AVIN before PVIN
and ENABLE during shutdown. Doing so will
disable the internal controller while there may s till
be energy in the system. The device will not soft-
shutdown properly and damage may occur. See
diagram below for a recommended startup and
shutdown sequencing.
Figure 8: Dual Supply St artup/Shutdown Sequ enci ng
PVIN
ENABLE
0V
12V
3.3V
0V
VOUT
Soft Start Time ≈ 2ms
w/Css=47nF
Delay from ENABLE rising
edge to soft start begin
~ 1ms
Delay from ENABLE falling
edge to soft shutdown
begin ~ 1.5ms
Soft Shutdown
Time ≈ 1.3ms
w/Css=47nF
PVIN –Recommended
to be ramped down
after the Vout soft-
shutdown occurs
PVIN slew rate limitations
as per datasheet
AVIN
PVIN
ENABLE
0V
12V
3.3V
0V
3.3V
0V
VOUT
Soft Start Time ≈ 2ms
w/Css=47nF
Delay from ENABLE rising
edge to soft start begin
~ 1ms
Delay from ENABLE falling
edge to soft shutdown
begin ~ 1.5ms
Soft Shutdown
Time ≈ 1.3ms
w/Css=47nF
AVIN powered up before PVIN
PVIN powered
down before AVIN
PVIN/AVIN –
Recommended
to be ramped down
after the Vout soft-
shutdown occurs
PVIN slew rate limitations
as per datasheet
www.altera.com/enpirion Page 15
07515 June 2, 2015 Rev D
EN2390QI
En able Operation
The ENABLE pin provides a means to enable
normal operation or to shut down the device. A
logic high will enable the converter into normal
operation. When the E N A BLE pin is asserted (high )
the device will under go a nor mal soft-start. A lo gic
lo w will disable the converter. A logic low will power
down the device in a controlled manner and the
device is subsequently shut down. The ENABLE
signal has to be low for at least the ENABLE
Lockout Tim e (8ms) in order for the device to be re-
enabled. To ensure accurate startup sequencing
the E N A BLE/DIS AB LE signal should be faster than
1V/100µs. A slower ENABLE/DISABLE signal may
result in a delayed startup and shutdow n response.
Do not leave ENABLE floating.
Pre-B ias Operation
The EN2390QI is not designed to be turned on into
a pre-biased output voltage. Be sure the output
capacitors are not charged or the output of the
EN2390QI is not pre-biased when the EN2390QI is
first enabled.
Frequency Synchronization
The switching frequency of the EN2390QI can be
phase-locked to an external clock source to move
unwanted beat frequencies out of band. The
internal switching clock of the EN2390QI can be
phase locked to a clock signal applied to the S_IN
pin. An activity detector recognizes the prese n ce o f
an external clock signal and automatically phase-
locks the internal oscillator to this external clock.
Phase-lock will occur as long as the input clock
frequency is in the range of 0.8M Hz to 1.8M H z. The
external clock frequency must be within ±10% of
the nominal switching frequency set by the RFS
resistor. It is recommended to use a synchronized
clock frequency close to the typical frequency
recommendations in Table 1. A 3.01kΩ resistor
from FQADJ to ground is recommended for clock
frequencies within ±10% of 1MHz. When no clock
is present, the device reverts to the free running
frequency of the internal oscillator set by the RFS
resistor.
The efficiency performance of the EN2390QI for
various P VI N/V OU T com binations can be opti m ize d
by adjusting the switching frequency. Table 1
shows recommended RFS values for various
PVIN/VOUT combinations in order to optimize
performance of the EN2390QI.
Figure 9. RFS versus Switching Frequency
The efficiency performance of the EN2390QI for
various VOUTs can be optimized by adjusting the
switching frequency. T able 1 shows recommended
RFS values for various VOUTs in order to optimize
performance of the EN2390QI.
PVIN
VOUT
RFS
Typical fsw
12V
3.3V
22k
1.42 MHz
2.5V
10k
1.3 MHz
1.8V
4.87k
1.15 MHz
1.5V
3.01k
1.0 MHz
1.2V
1.65k
0.95 MHz
<1.0V
1.3k
0.8 MHz
5V
2.5V
22.1k
1.4 MHz
1.8V
10k
1.3 MHz
1.5V
6.65k
1.25 MHz
1.2V
4.87k
1.15 MHz
<1.0V
3.01k
1.0 MHz
Table 1: Rec om m ended RFS Values
Soft-Start Operation
Soft start is a means to ramp the output voltage
gradually upon start-up. The output voltage rise
time is controlled by the choice of soft-start
capacitor, which is placed between the SS pin and
the AGND pin. During start-up of the convert er, the
reference voltage to the error amplifier is linearly
increased to its final level by an internal current
source of approx im ately 10µA. The soft-start time is
m easured from when VIN > VUVLOR and ENABLE pin
voltage crosses its logic high threshold to when
VOUT reaches its program m ed value. The total soft-
start time can be calculated by:
Soft Star t Time (ms): T SS ≈ Css [nF] x 0 .0 6
0.600
0.800
1.000
1.200
1.400
1.600
1.800
0246810 12 14 16 18 20 22
SWITCHING FREQUENCY (MHz)
R
FS
RESIST OR V ALUE (kΩ)
Rfs v s. SW Frequency
CONDITIONS
V
IN
= 6V to 12V
V
OUT
= 0.8V to 3.3V
www.altera.com/enpirion Page 16
07515 June 2, 2015 Rev D
EN2390QI
Typical soft-start time is approximately 2.8ms with
SS capacitor value of 47nF.
P OK Op e r a tio n
The POK signal is an open drain signal (requires a
pull up resistor to AVIN or similar voltage) from the
converter indicating the output voltage is within the
specified range. Typically, a 100kΩ or lower
resistance is used as the pull-up resistor. The PO K
signal will be logic high (AVIN) when the output
voltage is above 90% of the programmed voltage
level. If the output voltage is below this point, the
POK signal will be a logic low. The POK signal can
be used to sequence down-stream converters by
tying to their enable pins.
Short Circuit Protection
The short circuit protection feature will protect the
device if the output is shorted to ground. Short
circuit protection is achieved by sensing the curre nt
flowing through a sense PFET. When the sensed
current exceeds the threshold for more than 32
cycles, both power FET s are turned off for the rest
of the switching cycle. If the short circuit condition
is removed, the device will reacti vate soft-star t and
resume PWM operation. In the event the short
circuit trips consistently in normal operation, the
device enters a hiccup mode. While in hiccup
mode, the device is disabled for a short while and
restarted with a normal soft-start. The hiccup time
is approximately 32ms. This cycle can continue
indefinitely as long as the short circuit condition
persists. Use a resistor value of 100k from the
RCLX pin to ground to enable this feature.
Thermal Overload Protection
Thermal shutdown circuit will disable device
operation when the junction temper atur e exceeds
approximately 160°C. After a thermal shutdown
event, when the junction temperature drops by
approx 35°C, the converter will re-start with a
normal soft-start.
AVIN Under-Voltage Lock-Out (UVLO)
Internal circuits ensure that the converter will not
start sw itching until the AVIN input voltage is above
the specified minimum voltage. Hysteresis, input
de-glitch and output leadin g edge blanking ensures
high noise immunity and prevents false UVLO
triggers.
Master / Slave (P arallel) Operation:
Up to four EN2390QI devices may be connected in
a Master/Slave configuration to handle larger load
currents. The maximum output current for each
parallel device will need to be de-rated by 20
percent so that no devices will over current due to
current mis-match. The Master device’s switching
clock may be phase-locked to an external clock
source via the S_IN pin or left open and use its
default switchi ng frequency. The device is placed in
Master mode by pulling the M/S pin low or in Slave
m ode by pulli ng M /S pin high. Note that the M /S pin
is also pulled low for standalone mode. In Master
mode, the internal PWM signal is output on the
S_OUT pin. This PWM signal from the Master is
fed to the Slave device at its S_IN input. The Slave
device acts like an extension of the power FETs in
the Master. The inductor in the Slave prevents
crow-bar currents from Master to Slave due to
timing delays. Parallel operation in dual supply
mode is shown in Figure 11. Single supply mode
operation may also be implemented similarly. Note
that only critical components are shown. The red
text and red lines indicate the important parallel
operation connec tions and care should be taken in
layout to ensure low impedance between those
paths. The parallel curre nt m atchi ng is illustrated in
Figure 10.
Figure 10. Par allel Cur r ent Matching
0
1
2
3
4
5
6
7
8
9
10
2 4 6 8 10 12 14 16
INDIVIDUAL OUT PUT CURRENT (A)
TOTAL OUTPUT CURRENT (A)
Par allel C ur rent Sh are Br eakdown
MASTER
SLAVE
IDEAL
CONDITIONS
EN2390QI
VIN = 12V
VOUT = 1.2V
www.altera.com/enpirion Page 17
07515 June 2, 2015 Rev D
EN2390QI
V
OUT
V
IN
2x
22µF
1206
VOUT
ENA
AGND
SS
PVIN
AVIN
PGND PGND
EN2390QI
(MASTER)
47nF
VFB
R
A
R
B
R
1
C
A
FQADJ
2x
47µF
1206
M/S
S_OUT
2x
22µF
1206
VOUT
ENA
AGND
PVIN
AVIN
PGND PGND
EN2390QI
(SLAVE)
FQADJ
2x
47µF
1206
M/S
S_IN
VFB
open
SS
47nF
AVIN
AVIN
Note 2:
The Master and Slave VOUTs should be
connected with very low impedance as
shown by the double red line connections
in parallel.
Note 3:
The Master and Slave PGNDs should be
connected with very low impedance as shown by
the double red line connections in parallel.
Note 1:
The Master and Slave VINs should be connected
with very low impedance as shown by the double
red line connections in parallel.
Note 4:
Up to 3 Slaves may
be used in parallel
with the Master
Slave #1
15k
Figure 11. Parallel Operation Illustration
www.altera.com/enpirion Page 18
07515 June 2, 2015 Rev D
EN2390QI
Application Information
Output Voltage Programming and Loop
Compensation
The EN2390QI uses a Type IV Voltage Mode
compensation network. Type IV Voltage Mode
control is a proprietary Altera Enpirion control
scheme that maximizes control loop bandwidth to
deliver excellent load transient responses and
maintain output regulation with pin point accuracy.
For ease of use, most of this network has been
customized and is integrated within the device
package. The EN2390QI output voltage is
program m ed using a sim ple resi stor divider netwo r k
(RA and RB). The feedback voltage at VFB is
nominally 0.6V. RA is predetermined based on
Table 4 and RB can be calculated based on Figure
12. The values recom m ended for COUT, CA, RCA and
REA make up the external compensation of the
EN2390QI. It will vary with each PVIN and VOUT
combination to optimize on performance. The
EN2390QI solution can be optimized for either
smallest size or highest performance. Please see
Table 4 for a list of recommended RA, CA, RCA, REA
and COUT values for each solution. Since VFB i s a
sensitive node, do not touch the VFB node while
the device is in operation as doing so may
introduce parasitic capa citan ce into the contr ol loo p
that causes the device to behave abnormally and
damage may occur.
VOUT
VOUT
PGND
VFB
R
A
R
B
R
CA
C
A
C
OUT
EAIN
R
EA
R
A
V
FB
V
FB
V
OUT
x-
=
V
FB
= 0.6V
EN2390QI
Figure 12: VOUT Resistor Divider & Compensati on
Components. See T able 4 for details.
In put C apacitor S election
The EN2390QI requires two 22µF/1206 input
capacitors. Low-cost, low-ESR ceramic capacitors
should be used as input capacitors for this
converter. The dielectric must be X5R or X7R
rated. Y5V or eq ui val ent dielec tric formulations
must not be used as these lose too much
capacitance with freq uen cy, temperat ur e and
bias voltage. In some applications, lower value
capacitors are needed in parallel with the larger,
capacitors in order to provide high frequency
decoupling. Table 2 contains a list of
recommended input capacitors.
Recommended Input Capacitors
Description
MFG
P/N
22µF, 16V, X5R,
10%, 1206 Murata GRM31CR61C226ME15
22µF, 16V, X5R,
20%, 1206
Taiyo
Yuden EMK316ABJ226ML-T
Ta bl e 2: Rec om mended Input Capaci tors
Ou tp ut Cap acitor Selectio n
As seen from Table 4, the EN2390QI has been
optimized for use with one 100µF/1206 plus two
47µF/1206 outpu t capacit ors for best perform ance.
For smallest solution size, various combinations of
output capacitance may be used. See Table 4 for
details. Low ESR ceramic capacitors are required
with X5R or X7R rated dielectric formulation. Y5V
or equivalent dielectric formulations must not
be used as t hese lo se too much capacitan ce
with frequency, temperature and bias voltage.
Table 4 contains a list of recommended output
capacitors
Output ripple voltage is determined by the
aggregate output capacitor impedance. Capacitor
impedance, denoted as Z, is comprised of
capacitive reactance, effective series resistance,
ESR, and effective series inductance, ESL
reactance.
Placing output capacitors in parallel reduces the
impedance and will hence result in lower ripple
voltage.
nTotal
ZZZZ 1
...
111
21
+++=
Recommended Output Capacitors
Description
MFG
P/N
47µF, 6.3V , X5R,
20%, 1206
Murata GRM31CR60J476ME19L
47µF, 10V, X 5R,
20%, 1206
Taiyo Yuden LMK316BJ476ML-T
22µF, 10V, X 5R,
20%, 0805
Panasonic ECJ-2FB1A226M
22µF, 10V, X 5R,
20%, 0805
Taiyo Yuden LMK212BJ226MG-T
100µF, 6.3V , X5R,
20%, 1206 Murata GRM31CR60J107ME39L
Taiyo Yuden
JMK316BJ107ML-T
Table 3: Rec om m ended O ut put Capac i t ors
www.altera.com/enpirion Page 19
07515 June 2, 2015 Rev D
EN2390QI
Best Performance
Smallest Solution Siz e
CIN = 2x22µF/1206
CIN = 2x22µF/1206
COUT = 2x47µF/1206 + 100µF/1206
V
OUT
≤ 1.8V, C
OUT
= 2x47µF /0805
1.8V < VOUT ≤ 3.3V, COUT = 2x47µF /1206
R
A
= 200 kΩ
R
A
= 75k
PVIN
(V)
VOUT
(V)
C
A
(pF)
R
CA
(kΩ)
R
EA
(kΩ)
Ripple
(mV)
Deviation
(mV)
PVIN
(V)
VOUT
(V)
C
A
(pF)
R
CA
(kΩ)
R
EA
(kΩ)
Ripple
(mV)
Deviation
(mV)
14V
0.9V
15
18
0
5.83
44
14V
0.9V
18
8.2
Open
15
93
1.2V 15 22 0 7.22 48
1.2V 18 8.2 Open 21 104
1.5V
18
22
0
8.63
38
1.5V
18
8.2
Open
27
110
1.8V
15
22
0
10.8
50
1.8V
18
8.2
Open
35
120
2.5V 27 5.1 33 14.6 72
2.5V 15 8.2 Open 54 150
3.3V
22
8.2
33
26.1
76
3.3V
10
8.2
Open
81
215
12V
0.9V 27 18 0 5.21 40
12V
0.9V 27 5.1 Open 15 96
1.2V
22
22
0
6.7
36
1.2V
27
5.1
Open
21
104
1.5V
18
22
0
8.98
44
1.5V
27
5.1
Open
27
112
1.8V
18
22
0
10
50
1.8V
27
5.1
Open
34
130
2.5V
27
5.1
33
12.6
76
2.5V
22
5.1
Open
52
162
3.3V
22
8.2
33
23.6
72
3.3V
15
5.1
Open
77
221
10V
0.9V
27
18
0
5.01
44
10V
0.9V
56
2
Open
15
99
1.2V 22 22 0 6.28 40
1.2V 56 2 Open 20 107
1.5V
18
22
0
8.57
54
1.5V
39
2
Open
26
122
1.8V 18 22 0 9.44 60
1.8V 39 2 Open 33 126
2.5V
33
5.1
33
11
64
2.5V
33
2
Open
50
169
3.3V
27
8.2
33
21.6
68
3.3V
22
2
Open
71
241
8V
0.9V
27
18
0
4.9
44
8V
0.9V
100
0
Open
15
108
1.2V
22
22
0
5.82
48
1.2V
100
0
Open
20
113
1.5V 22 22 0 7.48 56
1.5V 82 0 Open 25 122
1.8V
22
22
0
8.01
54
1.8V
68
0
Open
31
136
2.5V 33 5.1 33 10.7 76
2.5V 47 0 Open 46 183
3.3V
27
8.2
33
20.5
84
3.3V
33
0
Open
62
253
6.6V
0.9V
33
18
0
4.58
46
6.6V
0.9V
100
0
Open
14
121
1.2V
27
22
0
5.28
54
1.2V
100
0
Open
19
128
1.5V
27
22
0
6.44
54
1.5V
100
0
Open
24
138
1.8V
22
22
0
7.2
58
1.8V
100
0
Open
29
149
2.5V
33
5.1
33
11.4
84
2.5V
68
0
Open
41
188
3.3V
33
8.2
33
18.4
96
3.3V
47
0
Open
53
239
5V
0.9V
39
18
0
4.1
54
5V
0.9V
100
0
Open
13
152
1.2V
33
22
0
5.1
62
1.2V
100
0
Open
18
161
1.5V
27
22
0
6.2
66
1.5V
100
0
Open
22
177
1.8V 27 22 0 7.02 68
1.8V 100 0 Open 25 183
2.5V
39
5.1
33
9.84
104
2.5V
100
0
Open
33
216
Table 4 : RA, CA, RCA and R EA Values f or Various PVIN /VOUT Combinations: B est Perf ormanc e vs. Small es t Sol ution
Size. Use the equations in Figure 12 to calculat e RB. Output ripple is measured at no load and nominal deviation
is for a 9A load transient step. For a voltage in between the specif ied output voltages, choose com pensati on
values of the lower output voltage setting.
www.altera.com/enpirion Page 20
07515 June 2, 2015 Rev D
EN2390QI
Thermal Considerations
Therm al consideratio ns are im porta nt power supply
design facts that cannot be avoided in the real
world. Whenever there are power losses in a
system, the heat that is generated by the power
dissipation needs to be accounted for. The Altera
Enpirion PowerSoC helps alleviate some of those
concerns.
The Altera Enpirion EN2390QI DC-DC converter is
packaged in a 10x11x3mm 76-pin QFN package.
The QF N package is constructed with copper lead
frames that have exposed thermal pads. The
exposed thermal pad on the package should be
soldered directly on to a copper ground pad on the
printed circuit board (PCB) to act as a heat sink.
The r ecommended maximum junction temperature
for continuous operation is 125°C. Continuous
operation above 125°C may reduce long-term
reliability. The device has a thermal overload
protection circuit designed to turn off the device at
an approximate junction temperature value of
160°C.
The following example and calculations illustrate
the thermal performance of the EN2390QI.
Example:
VIN = 12V
VOUT = 1.2V
IOUT = 9A
First calculate the output power .
POUT = 1.2V x 9A = 10.8W
Next, determine the input power based on the
efficiency (η) shown in F igure 13.
Figure 13: Effici ency vs. Output Current
For VIN = 12V, VOUT = 1.2V at 9A, η ≈ 82%
η = POUT / PIN = 82% = 0. 82
PIN = POUT / η
PIN ≈ 10.8W / 0.8 ≈ 13.17W
The pow er dissipation (PD) is the power loss in the
system and can be calculated by subtracting the
output power from the input power .
PD = PIN – POUT
≈ 13.17W – 10.8W ≈ 2.37W
With the power dissipation known, the temperature
rise in the device may be estimated based on the
theta JA value (θJA). The θJA parameter estimates
how m uch the tem perature will rise in the device for
every watt of pow er dissipation. The EN2390QI has
a θJA value of 15 ºC/W without airflow.
Determine the change in temperature (ΔT) based
on PD and θJA.
ΔT = PD x θJA
ΔT ≈ 2.37W x 15°C/W = 35.56°C ≈ 36°C
The junction temperature (TJ) of the device is
approximately the ambient temperature (TA) plus
the change in temperature. We assume the initial
ambient temperature to be 25°C.
TJ = TA + ΔT
TJ ≈ 25°C + 36°C ≈ 61°C
The maximum operating junction temperature
(TJMAX) of the device is 125°C, so the device can
operate at a higher ambient temperature. The
m ax i m um am bient tem perature (TAMAX) allowed can
be calculated.
TAMAX = TJMAX – PD x θJA
≈ 125°C – 36°C ≈ 89°C
The m ax im um am bient tem perature the devi ce can
reach is 89°C gi ven the input and output cond itio n s.
Note that the efficiency will be slightly lower at
higher temperatures and this calculation is an
estimate. Check De-rating Curves for guaranteed
maximum output current over temperature.
0
10
20
30
40
50
60
70
80
90
100
0123456789
EFFICIENCY (%)
OUTPUT CURRENT (A)
Efficiency vs. Output Current
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 1.0V
CONDITIONS
V
IN
= 12.0V
AVIN = 3.3V
Dual Supply
www.altera.com/enpirion Page 21
07515 June 2, 2015 Rev D
EN2390QI
Engineering Schematic
Figure 14: E ngi neeri ng S chem at i c for Smallest S ol ution Size
Css 47n
0402
0402
M/S must be tied to ground
for stand-alone operation.
Enable can also be
driven with an external
logic signal depending
on the application.
Output capacitors & compensation
network optimized for 12Vin to
3.3Vout. See datasheet for other
Vin/Vout cases.
Choose RPOK so
that max sink
current is not
exceeded.
0402
0402
0201
Cavin
1u
Rclx 100k
Rfs 15k
RPOK 100k
0402
A single through-hole test
point connects the AGND
pin to the GND plane.
Rfs values
chosen for 12Vin/3.3Vout.
0402
Optional EAIN test point used for loop
optimization purposes. Do not connect
a voltage probe to this test point.
U1
EN2390
NC1
1
NC2
2
NC3
3
NC4
4
NC5
5
NC6
6
NC7
7
NC8
8
NC9
9
NC10
10
NC11
11
NC12
12
NC13
13
NC14
14
NC15
15
NC16
16
NC17
17
NC18
18
NC19
19
VOUT
20
VOUT
21
VOUT
22
VOUT
23
VOUT
24
VOUT
25
VOUT
26
VOUT
27
VOUT
28
NC29
29
NC30
30
NC(SW)31
31
NC(SW)32
32
PGND
33
PGND
34
PGND
35
PGND
36
PGND
37
PGND
38
S_OUT 56
S_IN 55
BGND 54
VDDB 53
BTMP 52
PG 51
AVINO 50
PVIN 49
PVIN 48
PVIN 47
PVIN 46
PVIN 45
PVIN 44
PVIN 43
PVIN 42
PVIN 41
PVIN 40
PVIN 39
NC76 76
NC75 75
NC74 74
NC73 73
NC72 72
NC(SW)71 71
NC(SW)70 70
NC(SW)69 69
CGND 68
NC67 67
FADJ 66
RCLX 65
SS 64
EAIN 63
VFB 62
M/S 61
AGND 60
AVIN 59
ENABLE 58
POK 57
VOUT
Cavino
1u
Rvb
4.75k
Cb
0.22u
0402
Cpg 47n
POK
AGND
EAIN
Cin2 22u
Cin1 22u
Cout1 47u
Cout2 47u
Connect input and output
cap grounds to the GND
plane through multiple vias
(See the Gerber files).
PVIN
Ca
15p
Ra
75k
Rb
16.5k
Rca
5.1k
0402
0402
0402
0402
0402
PVIN = 12 VDC
1206
1206
1206
1206
www.altera.com/enpirion Page 22
07515 June 2, 2015 Rev D
EN2390QI
Layout Recommendation
Figure 15: Cri t i cal Com ponent Lay out for Mi ni m um
Footprint (Top Layer). See F igure 14 for s chemati c .
Thi s l ayout onl y s hows t he cri t i cal com ponents and top
layer traces for minimum footprint in single-supply,
master mode with ENABLE tied to AV IN. Alt ernate circui t
configurations & other low-
power pins need to be
connected and routed according to custom er applicatio n.
P l ease see t he Gerber fil es at www.altera.com/enpirion
f or detail s on al l l ayers .
Recommendation 1: Input and output filter
capacitors should be placed on the same side of
the PCB, and as close to the EN2390QI package
as possible. They should be connected to the
device with very short and wide traces. Do not use
thermal reliefs or spokes when connecting the
capacitor pads to the respectiv e nodes. The +V a n d
GND traces between the capacitors and the
EN2390QI should be as close to each other as
possible so that the gap between the two nodes is
minimized, even under the capacitors.
Re comme ndation 2: The PGND connections for
the input and output capacitors on layer 1 need to
have a slit between them in order to provide some
separation betw een input and output current loops.
Recommendation 3: The system ground plane
should be the first layer immediately below the
surface layer. This ground plane should be
conti nuous and un-interrupted below the converter
and the input/output capacitors.
Recommendation 4: The therm al pad underneath
the component must be connected to the system
ground plane through as many vias as possible.
The drill diameter of the vias should be 0.33mm,
and the vi as m ust have at least 1 oz. copper plating
on the inside wall, making the finished hole size
around 0.20-0.26mm. Do not use thermal reliefs or
spokes to connect the vias to the ground plane.
This connection provides the path for heat
dissipation from the converter.
Recommendation 5: M ultiple small vias (the same
size as the thermal vias discussed in
recommendation 4) should be used to connect
ground terminal of the input capacitor and output
capacitors to the system ground plane. It is
preferred to put these vias along the edge of the
G ND c o pper closest to the +V copper. T hese vias
connect the input/output filter capacitors to the
GND plane, and help reduce parasitic inductances
in the input and output curre nt loops. If vias cannot
be placed under the capacitor s, then place them on
both si des of the slit in the top layer PGND copper.
Recommendation 6: AVIN is the power supply for
the small-signal control circuits. AVINO powers
AVIN in single supply mode. AVIN and AVINO
should have a decoupling capacitor close to each
of their pins. Refer to F igure 15.
Recommendation 7: The layer 1 metal under the
device must not be more than shown in Figure13.
Refer to the section regarding Exposed Metal on
Bottom of Package. As with any switch-mode
DC/DC converter, try not to run sensitive signal or
control lines underneath the converter package on
other layers.
Recommendation 8: The VOUT sense point should
be just after the last output filter capacitor . Keep t he
sense trace short in order to avoid noise coupling
into the node. Contact Altera MySupport for any
remote sensing applications.
Recommendation 9: Keep RA, CA, RB, and RCA
close to the V FB pin (Refer to Figure 15). The VFB
pin is a high-impedance, sensitive node. Keep the
trace to this pin as short as possible. Whenever
possible, connect RB directly to the AGND instead
of going through the GND plane.
Recommendation 10: Follow all the layout
recommendations as close as possible to optimize
performance. Altera pr ovides schematic and layout
reviews for all customer designs. Contact Altera
MySupport
for detailed support
(www.altera.com/mysupport).
www.altera.com/enpirion Page 23
07515 June 2, 2015 Rev D
EN2390QI
Design Considerations for Lead-Frame Based Modules
Expose d Me tal on Bottom of Package
Lead-frames offer many advantages in thermal performance, in reduced electrical lead resistance, and in
overall foot print. However, they do require some special consider ations.
I n the assem bly process lead fram e constructio n requ ires that, for m echanica l suppor t, some of the lead-frame
canti levers be ex posed at the point w here wire-bond or internal passives are attached. T his results in several
small pads being exposed on the bottom of the package as shown in Figure 16.
Only the therm al pad and the perim eter pads are to be m echanica lly or electrically connected to the P C board.
The PC B top layer under the EN2390QI should be clear of any m etal (copper pou rs, tra ces, or vias) ex cept for
the therm al pad. The “shaded-ou t” are a in Figure 16 r epr esents the area that should be clear of any metal on
the top layer of the PCB. Any layer 1 metal under the shaded-out area r uns the risk of undesirable shorted
connections even if it is covered by soldermask.
The solder stencil aperture should be smaller than the PCB ground pad. This will pr event excess solder from
causing bridging between adjacent pins or other exposed metal under the package. Please consult the
E N2390QI QFN P ackage Solderi ng Gui del i nes for more details and recommendations.
Fi gure 16: Lead-F rame exposed m et al (B ott om Vi ew)
Shaded area hi ghl ights exposed m et al that i s not to be m echani call y or electri cal ly connec ted t o the P CB .
www.altera.com/enpirion Page 24
07515 June 2, 2015 Rev D
EN2390QI
Package and Mechanical
Fi gure 18: EN2390QI P ac kage Dimensi ons (B ot tom View)
Packi ng and Marki ng I nform a tion: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
Contact Information
Altera Corporation
101 Innovation Drive
San Jos e, CA 95134
Phone: 408-544-7000
www.altera.com
© 2013 Altera Corporation—Confidential. All rights reser ved. ALT ERA, ARRI A, CYC LON E, ENPIRI ON , HA RDC OPY, M AX, M EGACORE, NIOS, QUART US and STRA T IX
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trademarks or service marks are the propert y of their respec tive holders as describe d at w w w .altera. c om/c ommon/ legal. ht ml. Alte ra w arrants performance of its semicondu c t or
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www.altera.com/enpirion Page 26
07515 June 2, 2015 Rev D
