AM27F010-120FIB - Advanced Micro Devices

FINAL

Publicatio n# 11559 Rev: HAmendment/+2

Issue Date: J a nua ry 1998

Am28F010

1 Me gab i t ( 1 28 K x 8-B it)

CMOS 12.0 Volt, Bulk Eras e Flash Memory

DISTINCTIVE CHARACTERISTICS

■High performance

— 70 ns maximum access time

■CMOS Low power consumption

— 30 mA maximum active current

— 100 µA maximum standby current

— No data retention power consumption

■Compatible with JEDEC-standard byte-wide

32-Pin EPROM pinouts

— 32-pin PDIP

— 32-pin PLCC

— 32-pin TSOP

■10,000 write/erase cycles minimum

■Write and erase voltage 12.0 V ±5%

■Latch-up protected to 100 mA

from –1 V to VCC +1 V

■Flasherase™ Electrical Bulk Chip-Erase

— One second typical chip-erase

■Flashrite™ Programming

— 10 µs typical byte-program

— Two seconds typical chip program

■Command register architecture for

microprocessor/microcontro ller compatible

write interface

■On-chip address and data latches

■Advanced CMOS flash memory technology

— Low cost single transistor memory cell

■Automatic write/erase pulse stop tim er

GENERAL DESCRIPTION

The Am28F010 is a 1 Megabit Flash memory orga-

nized as 128 Kbytes of 8 bits each. AMD’ s Flash mem-

ories offer the most cost-effective and reliable read/

write non-volatile random access memory. The

Am28F010 is packaged in 32-pin PDIP, PLCC, and

TSOP versions. It is designed to be reprogrammed

and erased in-system or in standard EPROM pro-

grammers. The Am28F010 is erased when shipped

from the factory.

The standard Am28F010 off ers acce ss times as f ast as

70 ns, allowing operation of high-speed microproces-

sors without wait states. To eliminate bus contention,

the Am28F010 has separate chip enable (CE#) and

output enable (OE#) controls.

AMD’s Flash memories augment E PROM functionality

with in-circuit electrical erasure and programming. The

Am28F010 uses a command register to manage this

functionality, while maintaining a JEDEC Flash Stan-

dard 32-pin pinout. The command register allows for

100% TTL level control inputs and fixed power supply

levels during erase and programming, while maintain-

ing maximum EPROM compatibility.

AMD’s Flash technology reliably stores memory con-

tents e v en after 10,000 er ase and prog r am cycl es . The

AMD cell is designed to optimize the erase and pro-

gr ammi ng mechanis ms. In additi on, the com bination of

advanced tunnel oxide processing and low internal

electric fields for erase and programming operations

produces reliable cycling. The Am28F010 uses a

12.0V±5% VPP high voltage input to perform the

Flasherase and Flashrite algorithms.

The highest degree of latch-up protection is achieved

with AMD’s propr ietary non- epi process. Latch-up pro-

tection is provided for stresses up to 100 milliamps on

address and data pins from –1 V to VCC +1 V.

The Am28F010 is byte prog rammab le using 10 ms pro-

gramming pulses in accordance with AMD’s Flashrite

programming algorithm. The typical room temperature

programming time of the Am28F010 is two seconds.

The entir e chip i s bulk erased usi ng 10 ms erase pulses

according to AMD’s Flasherase alrogithm. Typical era-

sure at room temperature is accomplished in less than

one second. The windowed package and the 15–20

2 Am28F010

minutes required for EPROM erasure using ultra-violet

light are eliminated.

Commands are written to the command register using

standar d mi cropr oces sor w ri te ti ming s. Re gister co n-

tents serve as inputs to an internal state-machine

which controls the erase and programming circuitry.

During write cycles, the command register internally

latches address and data needed f or the programming

and erase operations. For system design simplifica-

tion, the Am28F010 is designed to support either WE#

or CE# controlled writes. During a system write cycl e,

addresses are latched on the falling edge of WE# or

CE# whichever occurs last. Data is latched on the ris-

ing edge of WE# or CE# whichever occurs first. To

simplify the following discussion , the WE# pin is used

as the write cycle control pin throughout the rest of

this text . All se tup an d hold times are w ith res pect to

the WE# signal.

AMD’s Flash technology combines years of EPROM

and EEPR OM ex perience to produce the hi ghest le vels

of quality, reliability, and cost effectiveness. The

Am28F010 electrically erases all bits simultaneously

using Fowler-Nordheim tunneling. The bytes are pro-

grammed one byte at a time using the EPROM pro-

gramming mechanism of hot electron injection.

BLOCK DIAGRAM

PRODUCT SELECTOR GUIDE

Fa mily Part N u mber Am28F010

Speed Options (VCC = 5.0 V ± 10%) -70 -90 -120 -150 -200

M ax A cc ess Time (ns) 70 90 120 150 200

CE# (E#) Access (ns) 70 90 120 150 200

OE# (G#) Access (ns) 35 35 50 55 55

Erase Voltage

Switch Input/Output

Buffers

Data

Latch

Y-Gating

1,048,576 Bit

Cell Matrix

X-Decoder

Y-Decoder

Addr ess Latch

Chip Enable

Output Enable

Logic

Program

Voltage Switch

State

Control

Command

WE#

CE#

OE#

A0–A16

DQ0–DQ7

VCC

VSS

11559H-1

Low VCC

Detector

Program/Erase

Pulse Timer

VPP

To Array

Am28F010 3

CONNECTION DIAGRAMS

Note: Pin 1 is marked for orientation.

11559H-2

PDIP

A16

DQ0

A15

A12

DQ1

DQ2

VSS

A11

OE# (G#)

A10

CE# (E#)

DQ7

VCC

WE# (W#)

DQ6

A14

A13

DQ5

DQ4

DQ3

VPP

DQ6

DQ5

DQ4

DQ3

131 30

13 17 18 19 2016

DQ0

A14

A13

A11

OE# (G#)

A10

CE# (E#)

DQ7

A12

A15

A16

VCC

WE# (W#)

DQ1

DQ2

VSS

PLCC

11559H-3

4 Am28F010

CONNECTION DIAGRAMS (continued)

LOGIC SYMBOL

TSOP

32-Pin TSOP—St a ndard Pinout

A11

A13

A14

WE#

VCC

A16

A15

A12

OE#

A10

CE#

VSS

32-Pin TSOP—Reverse Pinout

A11

A13

A14

WE#

VCC

A16

A15

A12

OE#

A10

CE#

VSS

11559H-4

DQ0–DQ7

A0–A16

CE# (E#)

OE# (G#)

WE# (W#)

11559H-5

Am28F010 5

ORDERING INFORMATION

Standard Products

AMD s tandard pro ducts are av ailab le i n several pac kages a nd opera ting r ange s. The or der numb er (V a lid Co mbination) i s f ormed

by a combination of:

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in vo lume for this device. Consult the local AMD sales

office to confirm a vailability of specific v alid combi nations and

to check on newly released combinations.

DEVICE NUMBER/DESCRIPTION

Am28F010

1 Megabit (128 K x 8-Bit) CMOS Flash Memory

AM28F010 -70 J C

OPTIONAL PROCESSING

Blank = Standard Processing

B=Burn-In

Contact an AMD representative for more information.

TEMPERATUR E RANGE

C = Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

E = Extended (–55°C to +125°C)

PACKAGE TYPE

P = 32-Pin Plastic DIP (PD 032)

J = 32-Pin Rectangular Plastic Leaded Chip

Carrier (PL 032)

E = 32-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 032)

F = 32-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR032)

SPEED OPTION

See Product Selector Guide and Valid Combinations

Valid Combinations

AM28F010-70

PC, PI, PE,

JC, JI, JE,

EC, EI, EE,

FC, FI, FE

AM28F010-90

AM28F010-120

AM28F010-150

AM28F010-200

6 Am28F010

PIN DESCRIPTION

A0–A16

Address Inputs for memory locations. Inter nal latches

hold addresses during write cycles.

CE# (E#)

Chip Enable active low input activates the chip’s con-

trol logic and input buffers. Chip Enable high will dese-

lect the device and operates the chip in stand-by mode.

DQ0–DQ7

Data Inputs during memory write cycles. Internal

latches hold data during write cycles. Data Outputs

during memory read cycles.

No Connect-corresponding pin is not connected

internally to the die.

OE# (G #)

Output Enable active low input gates the outputs of the

device through the data buffers during m emory read

cycles. Output Enable is high during command

sequencing and program/erase operations.

VCC

P o wer supply f or de vice operation. (5.0 V ± 5% or 10%)

VPP

Program voltage input. V PP must be at high voltage in

order to write to the command register. The command

regis ter controls all functions required to alter the mem-

ory array contents . Memory contents cannot be alter ed

when VPP ≤ VCC +2 V.

VSS

Ground

WE# (W #)

Write Enable ac tive l ow input controls the write function

of the command register to the memor y array. The tar-

get address is latched on the falling edge of the Write

Enab le pulse and the appropriate data is la tched on the

rising edge of the pulse. Write Enable high inhibits

writing to the device.

Am28F010 7

BASIC PRINCIPLES

The device uses 100% TTL-level control inputs to

manage the command register. Erase and repro-

gramming operations use a fixed 12.0 V ± 5% high

voltage input.

Read Only Memory

Without high VPP voltage, the device functions as a

read only memory and operates like a standard

EPROM. The control inputs still manage traditional

read, standby, output disable, and Auto select modes.

Command Register

The command register is enabled only when high volt-

age is applied to the VPP pin. The erase and repro-

gramming operations are only accessed via the

for erase and reprogramming operations. The tradi-

tional read, standby, output disable, and Auto select

modes are available via the register.

The device’s command register is written using stan-

dard microprocess or write timings. The register con-

trol s an internal state machine that manages all device

operations. For system design simplification, the de-

vice is designed to support either WE# or CE# con-

trolled writes. During a system write cycle, addresses

are latched on the falling edge of WE# or CE# w hich-

ever occurs last. D ata is latched on the rising edge of

WE# or CE# whichever occur first. To simplify the fol-

lowing discussion, the WE# pin is used as the write

cycle control pin throughout the rest of this text. All

setup and hold times are with respect to the WE# sig-

nal.

Over v iew of Eras e/P rogr am Ope ra ti on s

Flasherase™ Sequ ence

A multiple step command sequence is required to

erase the Flash device (a two-cycle Erase command

and repeated one cycle verify commands).

Note: The Flash memory array must be completely

programmed to 0’s prior to erasure. Refer to the

Flashrite™ Programming Algorithm.

1. Erase Setup: Write the Setup Erase command to

the command register.

2. Erase: Wr ite the Erase command (same as Setup

Erase command) to the command register again.

The second command ini t iates the er ase operation.

The system software routines must now time-out

the erase pulse width (10 ms) prior to issuing the

Erase-verify command. An integrated stop timer

prevents any possibility of overerasure.

3. Erase-Verify: Write the Erase-verify command to

the command register. This command terminates

the erase operation. After the erase operation,

each byte of the arra y m ust be verified. Address in-

formation must be supplied with the Erase-verify

command. This command verifies the margin and

outputs the addressed byte in order to compare the

array data with FFh data (Byte erased).

After successful data verification the Erase-verify

command is written again with new address infor-

mation. E ach byte of the a rray is sequentially veri-

fied in this manner.

If data of the addressed location is not verified, the

Erase sequence is repeated until the entire array is

successfully verified or the sequence is repeated

1000 times.

Flashrite Programming Sequence

A three step c ommand sequence (a two-cy cle Progr am

command and one cycle Verify command) is required

to prog ram a b yte of the Flash arra y. Ref er to the Flash-

rite Algorithm.

1. Program Setup: Write the Setup Program com-

mand to the command register.

2. Program: Writ e the Progr am c ommand to the com-

mand register with the appropriate Address and

Data. The sys tem softwar e routines m ust no w time-

out the program pulse width (10 µs) prior to issuing

the Program-verify command. An integrated stop

timer prevents any possibility of overprogramming.

3. Program-Verify: Write the Program-verify com-

mand to the command register. This command ter-

minates the programming operation. In addition,

this command verifies the margin and outputs the

by te just pr ogr ammed in or der to compare the arr a y

data with the original data programmed. After suc-

cessful data verification, the programming se-

quence is i nitiated again f or the ne xt b yte address to

be programmed.

If data is not verified successfully, the Program se-

quence is repeated until a successful comparison is

verified or the sequence is repeated 25 times.

Data Protection

The device is designed to off er protection against acci-

dental erasure or programming caused by spurious

system le v el signals that ma y e xist during power transi-

tions . The device power s up i n its read only s tate. A lso,

with its control register architecture, alteration of the

memory contents only occurs after successful comple-

tion of specific command sequences.

The device also incorporates several features to pre-

v ent inadv ertent write cycles result ing fromVCC po w er-

up and power-down transitions or system noise.

Lo w VCC Write Inhibit

To avoid initiation of a write cycle during VCC power -up

and power-down, the device locks out w rite cycles for

8 Am28F010
VCC < VLKO (see DC Characteristics section for
voltages). When VCC < VLKO, the command register is
disabled, all internal program/erase circuits are
disabled, and the device resets to the read mode. T he
device ignores all writes until VCC > VLKO. The user
must ensure that the control pins are in the correct logic
state w hen VCC > VLKO to prevent uninitentional  writes.
Write Pulse “Glitch” Protection
Noise pulses of less than 10 ns (typical) on OE# , CE#
or WE#  will not initiate a write cycle.
Logical Inhibit
Writing i s inhibited by holding any one of OE# = VIL, CE#
= VIH or WE# = VIH. To initiate a write cycle CE# and
WE# must be a logical zero whil e OE# is  a logical one.
Power-Up Write Inhibit
Power-up of the device with WE# = CE# = VIL and
OE# = VIH will not accept commands on the rising
edge of  W E# . T he in ter n al st ate ma chin e is a utoma t-
ically reset to the read mode on power-up.
FUNCTIONAL DESCRIPTION
Description of User Modes
Table 1. Am28F010 Device Bus Operations
Legend:
X = Don’t care, where Don’t Care is either VIL or VIH levels. VPPL = VPP 
≤
 VCC + 2 V. See DC  C haracteristics for voltage levels 
of VPPH. 0 V < An < VCC + 2 V, (normal TTL or CMOS input levels, where n = 0 or 9).
Notes:
1. VPPL may be gro unded, connecte d wit h  a res i stor to ground,  or < VCC + 2.0 V. VPPH is the progr ammi ng voltag e spec if ied  for 
the device. Refer to the DC characteristics. When VPP = VPPL, memory contents can be read but not written or erased.
2. Manu facturer and device codes may also be accessed via a command register write sequence. Refer to Table 2.
3. 11.5  < VID < 13.0 V. Minimum VID rise time and fall time (between 0 and VID voltages) is 500 ns.
4. Read operation with VPP = VPPH may access array data or the Auto select codes.
5. With VPP at high voltage, the standby current is ICC + IPP (standby).
6. Refer to Table  3 for valid DIN during a write operation.
7. All inputs are Don’t Care unless otherwise stated, where Don’t Care is either VIL or VIH levels. In  th e Auto select mode all 
addresses except A9 and A0 must be held at VIL.
8. If VCC 
≤ 
1.0 Volt, the voltage difference between VPP and VCC should not exceed 10.0 volts. Also, the Am 28F010 has a VPP 
rise time and fall time specification of 500 ns minimum .
Operation CE# (E#)OE
#
 (G#)WE
#
 (W#)VPP 
( Note 1) A0 A9 I /O
Read-Only
Read VIL VIL XV
PPL A0 A9 DOUT
Standby VIH XXV
PPL XXHIGH Z
Ou tp ut D is able V IL VIH VIH VPPL XXHIGH Z
Auto-Select M anufacturer 
Code  (N ote 2) VIL VIL VIH VPPL VIL VID 
( Note 3) COD E 
(01h)
Auto-Select Device Code
( Note 2) VIL VIL VIH VPPL VIH VID 
( Note 3) COD E 
(A7h)
Read/Write
Read VIL VIL VIH VPPH A0 A9 DOUT 
(Note 4)
Standby (N ote 5) VIH XXV
PPH XXHIGH Z
Ou tp ut D is able V IL VIH VIH VPPH XXHIGH Z
Write VIL VIH VIL VPPH A0 A9 DIN (Note 6)

Am28F010 9

READ ONLY MODE

When VPP is less than VCC + 2 V, the command r egister

is inactive. The device can either read array or autose-

lect data, or be standby mode.

Read

The device functi ons as a read only memory when VPP

< VCC + 2 V. The de vice has two control func tions. Both

must be satisfied in order to output data. CE # controls

power to the device. This pin should be used for spe-

cific device selection. OE# controls the device outputs

and should be used to gate data to the output pins if a

device is selected.

Address access time tACC is equal to the delay from

stable addresses to valid output data. The chip enable

access time tCE is the delay fr om stable addres ses and

stable C E# to valid data at the output pins. The output

enable access time is the del a y from the falling edge of

OE# to valid data at the output pins (assuming the ad-

dresses have been stable at least tACC–tOE).

Standby Mode

The device has two standby modes. The CMOS

standby m ode (CE # input held a t VCC ± 0.5 V ), con-

sumes less than 100 µA of current. TTL standb y mode

(CE# is held at VIH) reduces the current requirements

to less than 1m A. Whe n in the sta ndby mode the out-

puts are in a high impedance state, independent of the

OE # input.

If the device is deselected dur ing erasure, program-

ming, or program/erase verification, the device will

draw active current until the operation is terminated.

Output Disable

Output from the device is disabled when OE# is at a

logic high level. When disabled, output pins are in a

high impedance state.

Auto Select

Flash memories can be programmed in-system or in a

standard PROM programmer. The device may be sol-

dered to the circuit board upon r ecei pt of shipment and

programmed in-system. Alternatively, the device may

initially be programmed in a PROM programmer prior

to soldering the device to the board.

The Auto select mode allows the reading out of a binary

code from the device that will identify its manufacturer

and type. This mode is intended for the purpose

of automatically matching the device to be pro-

grammed with its corresponding programming algo-

rithm. This mode is functional over the entire

temperature range of the device.

Programming In A PROM Programmer

To activate this mode, the programming equipment

must force VID (11.5 V to 13.0 V) on address A9. Two

identifier bytes may then be sequenced from the de vice

outputs b y toggling addr ess A0 from VIL to VIH. All other

address lines must be held at VIL, and VPP must be

less than or equal to VCC + 2.0 V while using this Auto

select mode. Byte 0 (A0 = VIL) represents the man ufac-

turer code and byte 1 (A0 = V IH) the device identifier

code. For the devi ce these tw o by tes are giv en in Tab le

2 below. All identifiers for manufacturer and device

codes will exhibit odd parity with the MSB (DQ7) de-

fined as the parity bit.

Table 2. Am28F010 Auto Select Code

Type A0 Code ( HEX )

M anufact ur er Code V IL 01

Device Code VIH A7

10 Am28F010
ERASE, PROGRAM, AND READ MODE
When VPP is equal to  12.0 V ± 5%, the command reg-
ister is active. All functions are available. That is, the
device can program, erase, read array or autoselect
data, or be standby mode.
Write Operations
High voltage must be applied to the VPP pin in order to
activa te the command register. Data written to the reg-
ister serves as input to the internal state machine. The
output of the state mac hine determines the  operational
function of the device.
T he  co mma nd  r eg is ter does  no t occupy an  add r es s ab l e
memory location. The register is a latch that stores the
com m an d, al on g w ith  th e ad dr es s  a nd  data  in for m atio n
needed to ex ecute the command. The register is written
by br inging  WE# and CE# to VIL,  while OE# is at VIH.
Ad dres ses ar e latc hed on th e f a lli ng edge of  WE#, wh il e
data is latched on the rising edge of the WE# pulse.
Standard microprocessor write timings are used.
The device requires the OE# pin to be VIH f or  write op-
erations. This condition eliminates the possibility for
bus contention during programming operations. In
order to write, OE# must be VIH, and CE# and WE#
must be VIL. If any pin is not in the correct state a write
command will not be executed.
Refer to AC Write Characteristics and the Erase/Pro-
gramming Waveforms for specific timing parameters.
Command Definitions 
The contents of the command register default to 00h
(Read Mode) in the absence of high voltage applied to
the VPP pin. The device operates as a read only mem-
ory. High vol t age on the VPP pin enables the command
regis ter. Devic e operati ons ar e s elected b y  writing spe-
cific data codes into the command register. Table 3 de-
fines these register commands.
Read Command
Memory contents can  be accessed via the read com-
mand when V PP is high. To read from the device, write
00h in to the command register. Standard micropr oces-
sor read cycles access data from the memory. The de-
vice will remain in the read mode until the command
register contents are altered.
The command register defaults to 00h (read mode)
upon VPP power -up . The 00h (Read Mode) register de-
fault helps ensure that inadvertent alteration of the
memory  contents does  not oc cur during the VPP po wer
transition. Refer to the AC Read Characteristics and
Waveforms for the specific timing parameters. 
Table 3. Am28F010 Command Definitions
Notes:
1. Bus operations are defined in Table 1.
2. RA = Address of the memory location to be read.
EA = Address of the memory location to be read during erase-verify.
PA = Address of the memory location to be programmed.
X = Don ’t care.
Addresses are latched on the falling edge of the WE
#
 pulse.
3. RD = D ata read from location RA during read operation.
EVD = Data Read from location EA during erase-verify.
PD = Data to be programmed at location PA. Data latched on the rising edge of  W E
#
.
PVD = Data read from location PA during program-verify. PA is latched on the Program command.
4. Refer to the appropriate section for algorithms and timing diagrams.
Command (Note 4)
First Bus Cycle Second B us Cycle
Operation 
(No te 1) Address 
(Note 2) Data 
(Note 3) Operation 
(Note 1) Address 
(Note 2) Data
( Note 3)
Read Memo ry Write X 00h/F Fh Read R A RD
Read Auto select Write X 80h or 90h Read 00h/01h 01h/A7h
Erase Setup/Erase W rite Write X 20h Write X 20h
Erase-Verify Write EA A0h Read X EVD
Program  Setup/Program Write X 40h Write PA PD
Program-Verify Write X C0h Read X PVD
Reset Write X FFh Write X FFh

Am28F010 11

FLASHERASE E RASE SEQ UENCE

Erase Setup

Eras e Setup is the fi rst of a two-cycle erase command.

It is a command-only operation that stages the device

for bulk chip erase. The array contents are not altered

with this command. 20h i s written to the command reg-

ister in order to perform the E rase Setup operation.

Erase

The second two-cycle erase command initiates the

bulk erase operation. You must write the Erase com-

mand (20h) again to the register. The erase operation

begins with the rising edge of the WE# pulse. The

erase operation must be terminated by writing a new

command (Erase-verify) to the register.

This two step sequence of the Setup and Erase com-

mands helps to ensure that memory contents are not

accidentally erased. A lso, chip erasure can only occur

when hi gh v ol tage is applied to the VPP pi n and al l c on-

trol pins are in their proper state . In absence of this high

voltage, memory contents cannot be altered. Refer to

AC Erase Characteristics and Waveforms for specific

timing parameters.

Note: The Flash memory device must be fully

programmed to 00h data prior to erasure. This

equalizes the charge on all memory cells ensuring

reliable erasure.

Erase-Verify Command

The erase operation erases all bytes of the array

in parallel. After the erase operation, all bytes must be

sequentially v erified. The E rase- verify oper ation is initi -

ated by w riting A0h to the regis ter. The byte address to

be verified mus t be supplied with the command. Ad-

dresses are latched on the falling edge of the WE#

pulse or CE# pulse, whichever occurs later. The rising

edge of the WE# pulse terminates the erase oper ation.

Margin Ve rify

During the Erase-verify operation, the device applies

an internally generated margin voltage to the

address ed b yte . Reading FFh from the addressed b yte

indicates that all bits in the byte are proper ly erased.

Verify Next Address

You must write the Erase-ver ify command with the ap-

propriate address to the register pr ior to verification of

each address . Each ne w address is latched on the fall-

ing edge of WE# or CE# pulse, whi che ver occurs later .

The process continues for each byte in the memory

array until a byte does not return FFh data or all the

bytes in the array are accessed and verified.

If an address is not v erified to FFh data, the entire chip

is erased again (refer to Erase Setup/Erase). Erase

verification then resumes at the address that failed to

verify. Erase is complete when all bytes in the array

have been verified. The device is now ready to be pro-

gr ammed. At this point, the verification operation is ter-

minated by writing a valid command (e.g. Program

Setup) to the command register. Figure 1 and Table 4,

the Flasherase electrical eras e algorithm, illust rate how

commands and bus operations are combined to per-

form electrical eras ure. Ref er to A C Er ase Characteris-

tics and Waveforms for specific timing parameters.

12 Am28F010

FLASHERASE ELECTRICAL ERASE ALGORITHM

This Flash memory device erases the entire array in

parallel. The erase time depends on VPP

, temperature,

and number of erase/program cycles on the device. In

general, reprogramming time increases as the number

of erase/program cycles increases.

The Flasherase electrical erase algorithm employs an

interactive closed loop flow to simultaneously erase all

bits in the arra y . Erasure begins with a read of the mem-

ory contents. The device is erased when shipped from

the factory. Reading FFh data from the device would

immediately be f ollo wed by ex ecuting the Flashrite pro-

gramming algorithm with the appropriate data pattern.

Should the dev ice be currentl y programmed, data other

than FFh will be returned from address locations.

Follow the Flasherase algorithm. Uniform and reliable

erasure is ensured by first programming all bits in the

device to their charged state (Data = 00h). This is

accomplished using the Flashrite Programming

algorithm. Erasure then continues with an initial erase

operation. Erase verification (Data = FFh) begins at

address 0000h and continues through the array to the

last address, or until data other than FFh is

encountered. If a byte fails to verify, the device is

erased again. With each erase operation, an

increasing number of bytes verify to the erased state.

Typically, devices are erased in less than 100 pulses

(one second). Erase efficiency may be improved by

storing the address of the last byte that fails to verify in

a register. Following the next erase operation,

ver ification may star t at the stored address location. A

total of 1000 erase pulses are allowed per reprogram

cycle, which corresponds to approximately 10 seconds

of cum ulative erase ti me. The enti re sequenc e of er ase

and byte verification is performed with high voltage

applied to the VPP pin. Figure 1 i llustrates the electrical

erase algorithm.

Table 4. Flasherase Electrical Erase Algorithm

Notes:

1. See AC and DC Characteristics for values of VPP parameters. The VPP power supply can be hard-wired to the device or

switchable. When VPP is sw itc hed, VPPL m ay be ground, no connect with a resistor tied to ground, or less than VCC + 2.0 V.

2. Era se V erify is performed only after chip erasure. A final read compare may be performed (optional) after the register is written

with the read command.

3. The erase algorithm Must Be Followed to ensure proper and reliable operation of the device.

Bus Operations Command Comments

Entire memory must = 00h before erasure (Note 3)

Note: Use Flashrite program ming algorithm (Figure 3) for

programming.

Standby

Wait for VPP Ra mp to VPPH (Note 1)

Initialize:

Addresses

PLSCNT (Pulse count)

Write Erase Setup Data = 20h

Erase Data = 20h

Standby Duration of Erase Operation (tWHWH2)

Write Erase-Verify (Note 2) Address = Byte to Verify

Data = A0h

Stops Erase Operation

Standby Write Recovery Time before Read = 6 µs

Read Read byte to ver ify erasure

Standby Compare output to FF h

Increment pulse count

Write Reset Data = FFh, reset the register for read operations

Standby Wait for VPP R a mp to VPPL (Note 1)

Am28F010 13

Figure 1. Flash erase Electrical Erase Algorithm

Start

Program All Bytes to 00h

Appl y VPPH

Address = 00h

PLSCNT = 0

Write Erase Setup Command

Write Erase Com mand

Time out 10 ms

Write Erase Verify

Time out 6 µs

Read Data from Device

Data = FFh

Last Addre ss

Write Reset Command

Apply VPPL

Erasure Completed

PLSCNT =

1000

Increment Address

Apply VPPL

Erase Error

Yes

11559G-6

Yes

Yes Yes

Increment

PLSCNT

Data = 00h

14 Am28F010

Figure 2. AC Waveforms For Erase Operations

Analysis of Erase Timing Waveform

Note: This analysis does not include the requirement

to progr am the entire arra y to 00h data prior to er asure.

Refer to the Flashrite

Programming algorithm.

Erase Setup/Erase

This analysis illustrates the use of two-cycle erase

commands (section A and B). The first erase com-

mand (20h) is a Setup command and does not affect

the array data (section A). The second erase com-

mand (20h) initiates the erase operation (section B)

on th e r isi ng ed ge o f thi s W E # pu lse. A ll bytes of t he

memory array are erased in parallel. No address infor-

mation is required.

The erase pulse occurs in section C.

Time-Out

A software timing routine (10 ms duration) must be ini-

tiated on the rising edge of the WE# pulse of section B.

Note: An integrated stop timer prev ents any possibil-

ity of overerasure by limiting each time-out period of

10 ms.

Erase-Verify

Upon completion of the erase software timing routine,

the microprocessor must write the Erase-verify com-

mand (A0h). This c ommand terminates the eras e oper-

ation on the rising edge of the WE # pulse (section D).

The Erase-verify command also stages the device for

data verification (section F).

After each erase operation each byte must be verified.

The byte address to be verified must be supplied with

Addresses

CE#

OE#

WE#

Data

VPP

VCC

11559G-7

20h

Section

A0h Data

Out

Bus Cycle W rite Write Time-out Write Time-out Read Standby

Command 20h 20h N/A A0h N/A Compare

Data N/A

Function Erase

Setup Erase Erase

(10 ms) Erase-

Verify Transition

(6 µs) Erase

Verification

Proceed per

Erase

Algorithm

AB DEFCG

Am28F010 15

the Erase-ver ify command (section D). Addresses are

latched on the falling edge of the WE # pulse.

Another softw are timing routine (6 µs duration) mus t be

executed to allow f or generati on of internal v oltages for

margin checking and read operation (section E).

During Eras e-v erification (section F) eac h address that

returns FFh data is successfully er ased. Each address

of the arra y is sequentially v erified in this manner by re-

peating sections D thru F until the entir e array is veri-

fied or an address fails to verify. Should an address

location fail to verify to FFh data, erase the device

again. Repeat sections A thru F. Resume verification

(section D) with the failed address.

Each data change sequence allows the device to use

up to 1,000 eras e pulses to completel y erase . Typic ally

100 erase pulses are required.

Note: All address locations must be programmed to

00h prior to erase. This equalizes the charge on all

memory cells and ensures reliable erasure.

FLASHRITE PROGRAMMING SEQUENCE

Program Setup

The device is programmed byte by byte. Bytes may be

programmed sequentially or at random. Program Setup

is the first of a two-cycle program command. It stages

the device for byte programming. The Program Setup

operation is performed by writing 40h to the command

Program

Only after the program Setup operation is completed

will the next WE # pulse initiate the active programming

operation. The appropriate address and data for pro-

g ramming must be av ailab le on the s econd WE# pulse.

Addresses and data are internall y latched on the f alling

and rising edge of the WE# pulse respectiv ely. The ris-

ing edge of WE # also begins the programming opera-

tion. You must write the Program-verify command to

terminate the programming operation. This two step

sequence of the Setup and Program commands helps

to ensure that memory contents are not accidentally

written. Also, programming can only occur when high

v oltage is applied to the VPP pin and all control pins are

in their proper state. In absence of this high voltage,

memory contents cannot be programmed.

Ref er to AC Characteristi cs and W av ef orms for specific

timing parameters.

Program Verify Command

Following each programming operation, the byte just

programmed must be verified.

Write C0h into the command r egister i n or der to initiate

the Program-verify operation. The rising edge of this

WE pulse terminates the programming operation. The

Program-verify oper ation stages the de vi ce for v erifica-

tion of the last byte programmed. Addresses were pre-

viously latched. No new information is required.

Margin Ve rify

During the Program-verify operation, the device applies

an internally generated margin voltage to the ad-

dress ed b yte . A normal mi croprocessor read c ycle out-

puts the data. A successful comparison between the

programmed byte and the tr ue data indicates that the

byte was successfully programmed. The original pro-

grammed data should be stored for comparison. Pro-

gramming then proceeds to the next desired byte

location. Should the byte fail to verify, reprogram (refer

to Program Setup/Program). Figure 3 and Table 5 indi-

cate how instructions are combined with the bus oper-

ations to perform byte programming. Refer to AC

Programming Characteristics and Waveforms for spe-

cific timing parameters.

Flashrite Programming Algorithm

The device Flashrite P rogram ming algorithm employs

an interactive closed loop flow to program data byte by

b y te. Bytes ma y be pr ogrammed sequentiall y or at ran-

dom. The Flashrite Programming algorithm uses 10 µs

programming pulses. Each operation is followed by a

by te v eri fication to determi ne when the addr essed b yte

has been successfully programmed. The program al-

gorithm al lows f or up to 25 progr amming oper ations per

byte per r eprogramming cycle. Most bytes verify after

the first or second pulse. The entire sequence of pr o-

gramming and byte ver ification is performed w ith high

voltage applied to the VPP pin. Figure 3 and Table 5 il-

lustrate the programming algorithm.

16 Am28F010

Figure 3. Flashrite Programming Algorithm

Start

Apply VPPH

PLSCNT = 0

Write Program Setup Command

Write Pr og ram C ommand (A/D)

Time out 10 µs

Write Prog ra m Verif y Command

Time out 6 µs

Read Data from Device

Last Address

Write Reset Command

Apply VPPL

Programming Completed

PLSCNT =

25?

Increment Address

Apply VPPL

De vi ce Failed

11559G-8

Yes

No No

Verify Byte Incre ment PLSC NT

Yes

Am28F010 17

Table 5. Flashrite Programming Algorithm

Notes:

1. See AC and DC Characteristics for values of VPP parameters. The VPP power supply can be hard-wired to the device or

switchable. When VPP is sw itc hed, VPPL m ay be ground, no connect with a resistor tied to ground, or less than VCC + 2.0 V.

2. Pro gr am Verif y is pe rf ormed only after b y te prog rammin g. A fi nal r ead/c ompare may be pe rformed (opti onal) af ter th e r egister

is written with the read command.

Bus Operations Command Comments

Standby Wait for VPP Ramp to VPPH (Note 1)

Initialize Pulse counter

Write Program Setup Data = 40h

Program Valid Address/Data

Standby Duration of Programming Operation (tWHWH1)

Write Program-Verify (Note 2) Data = C0h Stops Program Operation

Standby Write Recovery Time before Read = 6 µs

Read Read Byte to Verify Programming

Standby Co mpare Data Output to Data Expected

Write Reset Data = FFh, resets the register for read operations.

Standby Wait for VPP R a mp to VPPL (Note 1)

18 Am28F010

Figure 4. AC Waveforms for Programming Operations

ANALYSIS OF PROGRAM TIMING WAVEFORMS

Program Setup/Program

Two-cycle write commands are required for program

operations (section A and B). The first program com-

mand (40h) is a Setup command and does not affect

the array data (section A). The second program com-

mand latches address and data required for program-

ming on the falling and rising edge of WE# respectiv ely

(s ection B). The rising edge of this WE# pulse (section

B) also initiates the programming pulse. The device is

prog rammed on a by te by b yte basis either sequenti ally

or randomly.

The program pulse occurs in section C.

Time-Out

A softwar e timing routine (10 µs dur ati on) must be initi-

ated on the rising edge of the WE# pulse of section B.

Note: An integrated stop timer prev ents any possibi lity

of overprogramming by limiting each time-out period of

10 µs.

Program-Verify

Upon completion of the progr am timing routine , the mi-

croprocessor must write the program-verify command

(C0h) . This command terminates the progr ammi ng op-

er ation on the rising edge of the WE# pulse (secti on D).

The program-verify command also stages the device

f or data verification (section F). Another software timing

Addresses

CE#

OE#

WE#

Data

VPP

VCC

11559G-9

Data

20h

Section

A0h Data

Out

Bus Cycle W rite Write Time-out Write Time-out R ead Standby

Command 40h Program

Address,

Program Data N/A C0h

(Stops

Program) N/A Compare

Data N/A

Function Program

Setup

Program

Command

Latch

Address and

Data

Program

(10 µs) Program

Verify Transition

(6 µs) Program

Verification

Proceed per

Programming

Algorithm

AB DEFCG

DE FCG

Am28F010 19

routine (6 µs duration) must be executed to allow for

gener ation of internal v ol t ages for margin chec k ing and

read operations (section E).

During program-verification (section F) each byte just

programmed is read to compare arra y data with original

prog ram data. When succes sfully veri fied, the next de-

sir ed address is programmed. Should a b yte f ail to v er-

ify, reprogram the by te (repeat section A thru F). Each

data change sequence allows the device to use up to

25 program pulses per byte . Typical ly, bytes ar e v erified

within one or two pulses.

Algorithm Timing Delays

There are four different timing delays associated with

the Flasherase and Flashrite algorithms:

1. The first delay is associated with the VPP r ise-time

when VPP first turns on. The capacitors on the VPP

bus cause an R C ramp. After switching on the VPP

the delay required is propor tional to the number of

devices being erased and the 0.1 mF/device. VPP

must reach its final value 100 ns before commands

are executed.

2. The second dela y time is the erase time pulse width

(10 ms). A software timing routine should be run by

the local microprocessor to time out the delay. The

erase operation must be terminated at the conclu-

sion of the timing routine or prior to executing any

system interrupts that may occur during the erase

operation. To ensure proper device operation, write

the Erase-verify operation after each pulse.

3. A third delay time is required for each programming

pulse width (10 ms). The programming algorithm is

interactive and verifies each byte after a program

pulse . The program oper ation must be terminated at

the conclusion of the timing routine or prior to exe-

cuting any system interrupts that may occur during

the programming operation.

4. A fourth timing delay associated with both the

Flasherase and Flashrite algorithms is the wr ite re-

cov ery time (6 ms). During this time internal circuitry

is changing voltage levels from the erase/ program

level to those used for margin ver ify and read oper-

ations . A n attempt to read the device during this pe-

riod will result in possible false data (it may appear

the device is not properly erased or programmed).

Note: Software timing routines should be written in

machine language for each of the dela ys. Code written

in machine language requires kno wledge of the appro-

priate microprocessor clock speed in order to accu-

rately time each delay.

Parallel Device Erasure

Many applications will use more than one Flash

memory device. Total erase time may be minimized by

implementing a parallel erase algorithm. Flash

memories may erase at different rates. Therefore each

device must be verified separately. When a device is

completely erased and verified use a masking code to

pre v ent further er asure. The other de vices will continue

to eras e until verified. The masking code applied could

be the read command ( 00h).

Power-Up/Power-Down Sequence

The device powers-up in the Read only mode. Power

supply sequencing is not required. Note that if VCC ≤

1.0 Volt, the voltage difference betw een VPP and V CC

should not exceed 10.0 Volts. A lso , the de vice has VPP

rise time and fall time specification of 500 ns mini mum.

Reset Command

The Reset command initializes the Flash memory de-

vice to the Read mode. In addition, it also provides the

user with a safe method to abort any device operation

(including program or erase).

The Reset command must be w ritten two consecutive

times after the setup Program command (40h). This will

reset the device to the Read mode.

Following any other Flash command write the Reset

command once to the de vice. This will saf ely abort any

previous operation and initialize the device to the

Read mode.

The Setup Program command (40h) is the only com-

mand that requires a two sequence reset cycle. The

first Reset command is inter preted as program data.

However, FFh data is considered null data dur ing pr o-

gramming operations (memory cells are only pro-

grammed from a logical “1” to “0”). The second Reset

command safely abor ts the programming operation

and resets the device to the Read mode.

Memory contents are not altered in any case.

This detailed information is for your reference. It may

prove easier to always issue the Reset command two

consecutive times. This eliminates the need to deter-

mine if you are in the setup Program state or not.

Programming In-System

Flash memories can be programmed in-system or in a

standard PROM programmer. The device may be sol-

dered to the circuit board upon r ecei pt of shipment and

programmed in-system. Alternatively, the device may

initially be programmed in a PROM programmer prior

to soldering the device to the board.

20 Am28F010

Auto Select Command

AMD’ s Flash memories are designed for use in applica-

tions w here the local CPU alters memory contents. Ac-

cordingly, manufacturer and device codes must be

accessible while the device resides in the target sys-

tem. PROM programmers typically access the signa-

ture codes by raising A9 to a high voltage. However,

multiplexing high voltage onto address lines is not a

generally desired system design practice.

The device contains an Auto Select operation to sup-

plement traditional PROM programming methodology.

The operation is initiated by writing 80h or 90h into the

command register. Following this command, a read

cycle address 0000h retrieves the manufacturer code

of 01h. A read cycle from address 0001h returns the

de vice code. To terminate the operati on, it is necessary

to write another valid command, such as Reset (FFh),

into the register.

Am28F010 21

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . .–55°C to + 125°C

Voltage with Respect To Ground

All pins except A9 and VPP (Note 1) .–2.0 V to +7.0 V

VCC (Note 1). . . . . . . . . . . . . . . . . . . .–2.0 V to +7.0 V

A9 (Note 2). . . . . . . . . . . . . . . . . . . .–2.0 V to +14.0 V

VPP (Note 2). . . . . . . . . . . . . . . . . . .–2.0 V to +14.0 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Mini mum DC voltage on input or I/O pins is – 0. 5 V. During

v oltage transitions, inputs may overs hoot VSS to –2.0 V for

peri ods of up to 20 ns. Maxim um DC v oltage on i nput and

I/O pins is V CC + 0.5 V. During voltage transitions, input

and I/O pins may overshoot to VCC + 2.0V for periods up

to 20n s.

2. Minimum DC input voltage on A9 and VPP pins is -0.5 V.

During voltage transitions, A9 and V PP may overshoot

VSS t o –2.0 V for periods of up to 20 ns. Maximum DC

input voltage on A9 and V PP is +13.0 V which may

overshoot to 14.0 V for periods up to 20 ns.

3. No more than one output shorted to ground at a time.

Duration of the short circuit should not be greater than

one second.

Stresses above those listed under “Absolute Maximum Rat-

ings” may cause permanent damage to the device. This is a

stress rating only; functional operation of the device at these

or any other conditions above those indicated in the opera-

t ional se ctions of th is specif icatio n i s n ot implie d. Exposure of

the device to absolute maximum rating conditions for

extended periods may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (TA). . . . . . . . . . . .0°C to +70°C

Industrial (I) Devices

Ambient Temperature (TA). . . . . . . . . .–40°C to +85°C

Extended (E) Device s

Ambient Temperature (TA). . . . . . . . .–55°C to +125°C

VCC Supply Voltages

VCC . . . . . . . . . . . . . . . . . . . . . . . . +4.50 V to +5.50 V

VPP Voltages

Read . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +12.6 V

Program, Erase, and Verify. . . . . . +11.4 V to +12.6 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

22 Am28F010

MAXIMUM O VERSHO OT

20 ns

+0.8 V

–0.5 V

20 ns

–2.0 V

11559H-10

Maximum Negative Input Overshoot

20 ns

VCC + 0.5 V

2.0 V

20 ns 20 ns

VCC + 2.0 V

11559H-11

Maximum Positive Input Overshoot

11559H-12

Maximum VPP Overshoot

20 ns

13.5 V

VCC + 0.5 V

20 ns 20 ns

14.0 V

Am28F010 23

DC CHARACTERISTICS over operating range unless otherw ise specified

TTL/NMOS Compatible

Notes:

1. Caution: The Am28 F010 m ust not be re mo v ed f rom (or inserted into) a soc k et when VCC or VPP is applie d. If VCC

≤

1.0 Volt,

the voltage difference between VPP and VCC should not exceed 10.0 Volts. Also, the Am28F010 has a VPP rise time and fa ll

time specification of 500 ns minimum.

2. ICC1 is tested with OE

= VIH to simulate open outputs.

3. Maximum active power usage is the sum of ICC and I PP

4. Not 100% tested.

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

ILI Input Leakage Current VCC = VCC Max, VIN = VCC or VSS ±1.0 µA

ILO Output Leakage C urrent VCC = VCC Max, VOUT = VCC or VSS ±1.0 µA

ICCS VCC Standby Current VCC = VCC Ma x, CE# = VIH 0.2 1.0 mA

ICC1 VCC Active Read Current VCC = VCC Max, CE# = VIL, OE# = VIH

IOUT = 0 mA, at 6 MHz 20 30 mA

ICC2 VCC Programming Current CE = VIL Programming in Progress

( Note 4) 20 30 mA

ICC3 VCC Erase C urrent CE# = VILErasure in Progress (Note 4) 20 30 mA

IPPS VPP Standby Current VPP = VPPL ±1.0 µA

IPP1 VPP Read Current VPP = VPPH 70 200 µA

VPP = VPPL ±1.0

IPP2 VPP Programming Current VPP = VPPH

Programming in Progress (Note 4) 10 30 mA

IPP3 VPP Erase Current VPP = VPPH

Erasure in Progress (Note 4) 10 30 mA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 2.0 VCC + 0.5 V

VOL Output Low Voltage IOL = 5 .8 mA , VCC = VCC Min 0.4 5 V

VOH1 Output High Voltage IOH = –2.5 mA, VCC = VCC Min 2.4 V

VID A9 Auto Select Voltage A9 = VID 11.5 13.0 V

IID A9 Auto Select Current A9 = V ID Max , VCC = VCC Max 5 50 µA

VPPL VPP duri ng Re ad-Only

Operations

Note: Erase/Program are inhibited

when VPP = VPPL

0.0 VCC +2 .0 V

VPPH VPP during Read/W rite

Operations 11.4 12.6 V

VLKO Low VCC Lock-out Voltage 3.2 3.7 V

24 Am28F010

DC CHARACTERISTICS

CMOS Compatible

Notes:

1. Caution: The A m28F 010 mu st not be remo v e d f rom (or i nse rted into) a soc k et w hen VCC or VPP is applied. If VCC

≤

1.0 v olt ,

the voltage difference between VPP and VCC should no t ex ceed 10. 0 volt s . Also, the Am28F010 has a VPP rise time and fall

time specification of 500 ns minimum.

2. ICC1 is tested with OE

= VIH to simulate open outputs.

3. Maximum active power usage is the sum of ICC and IPP

4. Not 100% tested.

Parameter

Symbol Parameter Descr ipt io n Test Condi t i ons Min Typ Max U ni t

ILI Input Leakage Current VCC = VCC Max, VIN = VCC or VSS ±1.0 µA

ILO Output Leakage C urrent VCC = VCC Ma x, VOUT = VCC or VSS ±1.0 µA

ICCS VCC Standby Current VCC = VCC Max, CE# = VCC + 0.5 V 15 100 µA

ICC1 VCC Active Read Current VCC = VCC Ma x, CE# = VIL, OE# = VIH

IOUT = 0 mA, at 6 MHz 20 30 mA

ICC2 VCC Programming Current CE# = VILProgram m ing in Progress

(Note 4) 20 30 mA

ICC3 VCC Erase C urrent CE# = VILErasure in Progress

(Note 4) 20 30 mA

IPPS VPP Standby Current VPP = VPPL ±1.0 µA

IPP1 VPP Read Current VPP = VPPH 70 200 µA

IPP2 VPP Programming Current VPP = VPPH

Programming in Progress (Note 4) 10 30 mA

IPP3 VPP Erase Current VPP = VPPH

Erasure in Progress (Note 4) 10 30 mA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 0.7 VCC VCC + 0.5 V

VOL Output Low Voltage IOL = 5.8 mA, VCC = VCC Min 0.45 V

VOH1 Output High Voltage IOH = – 2.5 mA, VCC = VCC M in 0.85 VCC V

VOH2 IOH = –100 µA, VCC = VCC Min VCC – 0.4

VID A9 Auto Select Voltage A9 = VID 11.5 13.0 V

IID A9 Auto Select Current A9 = VID Max , VCC = VCC Max 5 50 µA

VPPL VPPL during Read-Only

Operations

Note: Erase/Program are inhibited

when VPP = VPPL

0.0 VCC + 2.0 V

VPPH VPP d ur ing Re ad/W rite

Operations 11.4 12.6 V

VLKO Low VCC Lock-out Voltage 3.2 3.7 V

Am28F010 25

Figure 5. Am28F010—Average ICC Active vs. Frequency

VCC = 5.5 V, A ddressing Pattern = Minmax

Data Pattern = Checkerboar

TEST CONDITIONS Table 6. Test Sp ecifications

ICC Active in mA

0123456789101112

Frequency in MHz 11559G-13

55°C

0°C

25°C

70°C

125°C

2.7 kΩ

CL6.2 kΩ

5.0 V

Device

Under

Test

11559H-14

Figure 6. Test Setup

Not e: Diodes are IN3064 or equivalent

Test Condition -70 All others Unit

Output Load 1 TTL gate

Output Load Cap acitance, CL

(including jig capacitance) 30 100 pF

Input Rise and Fall Times ≤10 ns

Input Pulse Levels 0. 0–3.0 0. 45–2 .4 V

Input timing measurem ent

reference levels 1.5 0.8, 2.0 V

Output timing measurement

reference levels 1.5 0.8 , 2 .0 V

26 Am28F010

SWITCHING TEST WAVEFORMS

SWITCHING CHARACTERISTICS over operating range unless otherwise specified

AC Characteristics—Read Only Operation

Notes:

1. Guaranteed by design; not tested.

2. Not 100% tested.

Parameter

Symbols Am28F010 Speed Options

JEDEC Standard Parameter Desc ription -70 -90 -120 -150 -200 Unit

tAVAV tRC Read Cycle Time (Note 2) Min 70 90 120 150 200 ns

tELQV tCE Chip Enable AccessTime Max 70 90 120 150 200 ns

tAVQV tACC Address Access Time Max 70 90 120 150 200 ns

tGLQV tOE Output Enable Access Time Max3535505555ns

ELQX tLZ Chip Enable to Output in Low Z (Note 2)Min00000ns

EHQZ tDF Chip Disable to Output in High Z (Note 1) M a x 20 20 30 35 35 ns

tGLQX tOLZ Output Enable to Output in Low Z (Note 2)Min00000ns

GHQZ tDF Output Disable to Output in High Z (Note 2) Max 20 20 3 0 35 35 n s

tAXQX tOH Output Hold from first of Address, CE#, or

OE# Change (Note 2) Min00000ns

WHGL Write Recovery Time before Read Min66666µs

VCS VCC Setup Time to Valid Read (Note 2) M in 50 50 50 50 50 µs

11559H-15

3 V

0 V Input Output

1.5 V 1.5 V

Test Points

AC Testing for -70 devices: Inputs are driven at 3.0 V for a

lo gic “1 ” and 0 V f or a l ogic “0”. I nput pulse rise and fall t ime

are

≤

10 ns.

2.4 V

0.45 V Input Output

Test Po ints

2.0 V 2.0 V

0.8 V0.8 V

A C Testing (all sp eed options e xcept -70): Inputs are driven at

2. 4 V for a lo gi c “ 1” a nd 0.45 V f or a logic “0”. Input pulse rise

and fall times are

≤

10 ns.

Am28F010 27

AC CHARACTERISTICS—Write/Erase/Program Operations

Notes:

1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC

Characteristics for Read Only operations.

2. Maximum pulse widths not required beca use the on-chip program/erase stop timer will term inate the pulse widths intern ally

on th e devi ce.

3. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In

systems where Chip-Enab le defines the Write Pulse Width (within a longer Writ e-Enable timing waveform) all set-up , hold and

inactive Write-Enable times should be measured relative to the Chip-Enable waveform.

4. Not 100% tested.

Parameter Symbols Am28F 010 Speed Options

JEDEC Standard Description -70 -90 -120 -150 -200 Unit

tAVAV tWC Write Cycle Time (Note 4) Min 70 90 120 150 200 ns

tAVWL tAS Address Setup Time Min 0 0 0 0 0 ns

tWLAX tAH Address Hold Time Min4545506075ns

DVWH tDS Data Setup Time Min 45 45 50 50 50 ns

tWHDX tDH Data Hold Tim e Min 10 10 1 0 10 10 ns

tWHGL tWR Write Recovery Time Before Read Min 6 6 6 6 6 µs

tGHWL Read Recovery TIme Before Write Min 0 0 0 0 0 µs

tELWL tCS CE# Setup TIme Min0 0 0 0 0ns

WHEH tCH CE# Hold TIme Min 0 0 0 0 0 ns

tWLWH tWP Write Pulse Width Min 45 45 50 60 60 ns

tWHWL tWPH Write Pulse Width High Min 20 20 20 20 20 ns

tWHWH1 Duration of Programming Operation

( Note 2) Min1010101010µs

WHWH2 Duration of Erase Operation (Note 2) Min 9.5 9.5 9.5 9.5 9.5 ms

tVPEL VPP Setup Time to Chip Enable Low (Note 4) Min 100 100 100 100 100 ns

tVCS VCC Setup Time to Chip Enable Low (N ote 4) Min 50 50 50 50 50 µs

tVPPR VPP Rise Time (Note 4) 90% VPPH Min 500 500 500 500 500 ns

tVPPF VPP Fall Time (N ote 4) 10% VPPL Min 500 500 500 500 500 ns

tLKO VCC < VLKO to Reset (Note 4) Min 100 100 100 100 100 ns

28 Am28F010

KEY TO SWITCHING WAVEFORMS

SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted Changing, State Unknow n

Does Not Apply Center Line is High Impedance State (High Z)

Addresses

CE# (E#)

OE# (G#)

WE# (W#)

Data (DQ)

5.0 V

VCC

0 V

Power-up, S tandby Device and

Address Selection Outputs

Enabled Data

Valid Standby, P ower-do wn

Addresses Stable

High Z High Z

tWHGL

tAVQV (tACC)

tEHQZ

(tDF)

tGHQZ

(tDF)

tELQX (tLZ)

tGLQX (tOLZ)

tELQV (tCE)

tGLQV (tOE)

tAXQX (tOH)

Output Valid

tAVAV (tRC)

tVCS

11559H-16

Figure 7. AC Waveforms for Read Operations

Am28F010 29

SWITCHING WAVEFORMS

Figure 8. AC Waveforms for Erase Operations

DATA IN

= A0h VALID

DATA

OUT

Erase- Verify

Command Erase

Verification Standb y,

Power-down

tWLAX (tAH)

tEHQZ (tDF)

tWHGL

tGHQZ (tDF)

tGLQX (tOLZ)

tGLQV (tOE)

tELQV (tCE)

11559G-17

tELQX (tLZ)

tAVAV (tRC)

tAXQX (tOH)

DA T A IN

= 20h DA T A IN

= 2 0h

Setup Erase

Command E ras e

Command

P o w er-up,

Standby

tAVWL (tAS)

tAVAV (tWC)

tELWL (tCS)

tGHWL (tOES)

tWHEH (tCH)

tWHWH2

tWHWL (tWPH)

tWHDX (tDH)

tWL WH (tWP)

tDVWH (tDS)

tVCS

tVPEL

Addresses

HIGH Z

CE# (E#)

OE# (G#)

WE# (W#)

Data (DQ)

5.0 V

VCC

0 V

VPPH

VPP

VPPL

Erasure

30 Am28F010

SWITCHING WAVEFORMS

Figure 9. AC Waveforms for Programming Operations

DA T A IN =

C0h VALID

DATA

OUT

Verify

Command Programming

Verification Stan dby,

Power-down

tWLAX (tAH)

tGHQZ (tDF)

tWHGL

tGHQZ (tDF)

tGLQX (tOLZ)

tGLQV (tOE)

tELQV (tCE)

11559G-18

tELQX (tLZ)

tAVAV (tRC)

tAXQX (tOH)

DA T A IN

= 40h DATA IN

Setup Program

Command

Program

Command

Latch Address

and Data

Power-up,

Standby

tAVWL (tAS)

tAVAV (tWC)

tELWL (tCS)

tGHWL (tOES)

tWHEH (tCH)

tWHWH1

tWH WL (tWPH)

tWHDX (tDH)

tWL WH (tWP)

tDVWH (tDS)

tVCS

tVPEL

Addresses

HIGH Z

CE# (E#)

OE# (G#)

WE# (W#)

Data (DQ)

5.0 V

VCC

0 V

VPPH

VPP

VPPL

Programming

Am28F010 31

ERASE AND PROGRAMMING PERFORMANCE

Notes:

1. 25

C, 12 V VPP

2. Maximum time specified is lower than worst case. Worst case is derived from the Flasherase/Flashrite pulse count

(Flashera se = 1000 max and Flashrite = 25 max). Typical worst case for program and erase is significantly less than the actual

device limit.

LATCHUP CHARACTERISTICS

PIN CAPACITANCE

Note: Sampled, not 100% tested. Test conditions TA = 25°C, f = 1.0 MH z.

DATA RETENTIO N

Parameter

Limits

CommentsMin Typ

(Note 1) Max

(Note 2) Unit

Chip Erase Time 1 10 sec Excludes 00h programm ing prior to erasure

Chip Programming Time 2 12.5 sec Excludes system-level overhead

Write/Erase Cycles 10,000 Cycles

Parameter Min Max

Input Voltage with respect to VSS on all pins except I/O pins (Including A9 and VPP) –1.0 V 13.5 V

Input Voltage with respect to VSS on all pins I/O pins –1.0 V VCC + 1.0 V

Current –100 mA +100 mA

Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time.

Parameter

Symbol Parameter Description Test Conditions Typ Max Unit

CIN Input Capa cit anc e VIN = 0 8 10 pF

COUT Ou tp ut C apacitanc e VOUT = 0 8 1 2 pF

CIN2 VPP Input Capacitance VPP = 0 8 12 pF

Parameter Test Conditions Min Unit

Minimum Pattern Da ta Retention Time 150°C10Years

125°C20Years

32 Am28F010

PHYS ICAL DIMEN SION S

PD032—32-Pin Plastic DIP (measured in inches)

PL032—32-Pin Plastic Leaded Chip Carrier (measured in inches)

Pin 1 I.D.

1.640

1.670

.530

.580

.005 MIN

.045

.065

.090

.110

.140

.225

.120

.160 .016

.022

SEATING PLANE

.015

.060

16-038-S_AG

PD 032

EC75

5-28-97 lv

32 17

16 .630

.700

0°

10°

.600

.625

.009

.015

.050 REF.

.026

.032 TOP VIEW

Pin 1 I.D.

.485

.495

.447

.453

.585

.595

.547

.553

16-038FPO-5

PL 032

DA79

6-28-94 ae

SIDE VIEW

SEATING

PLANE

.125

.140

.009

.015

.080

.095

.042

.056

.013

.021

.400

REF. .490

.530

Am28F010 33

PHYS ICAL DIMEN SION S

TS032—32-Pin Standard Thin Small Outline Package (measured in millimeters)

Pin 1 I.D.

18.30

18.50

7.90

8.10

0.50 BSC

0.05

0.15

0.95

1.05

16-038-TSOP-2

TS 032

DA95

3-25-97 lv

19.80

20.20

1.20

MAX

0.50

0.70

0.10

0.21

0°

5°

0.08

0.20

34 Am28F010

PHYS ICAL DIMEN SION S

TSR032—32-Pin Reversed Thin Small Outline Package (measured in millimeters)

18.30

18.50

19.80

20.20

7.90

8.10

0.50 BSC

0.05

0.15

0.95

1.05

16-038-TSOP-2

TSR032

DA95

3-25-97 lv

Pin 1 I.D.

1.20

MAX

0.50

0.70

0.10

0.21

0°

5°

0.08

0.20

Am28F010 35

REVISION SUMMARY FOR AM28F010

Revision G+1

Distinctive Characteristics:

High Per for mance:

The fastest speed option available

is now 70 ns.

General Description:

Paragraph 2: Changed fastest speed option to 70 ns.

Product Selector Guide:

Added -70, deleted -95 and -250 speed options.

Ordering Information, Standard Products:

The -70 speed option is now listed in the example.

Valid Combinations:

Added -70, deleted -95 and -250

combinations.

Operating Ranges:

Supply Voltages:

Added -70, deleted -95 and -250

speed options.

AC Characteristics:

Read Only Operations Characteristics:

Added the - 70

column and test conditions.

Deleted -95 and -250 speed options.

AC Characteristics:

Write/Erase/Program Operations:

Added the -70 col-

umn. Deleted -95 and -250 speed options. Changed

speed option in Note 2 to -70.

Switching Test Waveforms:

In the 3.0 V waveform caption, changed -95 to -70.

Revision H

Matched formatting to other current data sheets.

Revision H+1

Figure 3, Fl ashrite Progr amming Algorithm:

Mo ved end

of arrow originating from Increment Address box so

that it points to the P LSCNT = 0 bo x, not the Write Pro-

gram Verify Command box. This is a correction to the

diagram on page 6-189 of the 1998 Flash Memory

Data Book.

Revision H+2

Programming In A PROM Programmer:

Deleted the paragraph “(Refer to the AUTO SELECT

paragraph in the ERASE, PROGRAM, and READ

MODE section for programming the Flash memory de-

vice in-system).”

Trademarks

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.