© Semiconductor Components Industries, LLC, 2016
February, 2016 Rev. 6
1Publication Order Number:
KAI16000/D
KAI-16000
4872 (H) x 3248 (V)
Interline CCD Image Sensor
Description
The KAI16000 is an interline transfer CCD offering 16 million
pixels at up to 3 frames per second through 2 outputs. This image
sensor is organized into an array of 4,872 (H) x 3,248 (V) with
7.4 micron square pixels and full 35 mm optical format. As an
interline transfer CCD, the KAI16000 includes additional features
such as progressive scan readout, electronic shutter, low noise, high
dynamic range, and blooming suppression. These features make the
KAI16000 the perfect sensor for applications in Industrial, Aerial,
Security, and Scientific markets.
Table 1. GENERAL SPECIFICATIONS
Parameter Typical Value
Architecture Interline CCD; Progressive Scan
Total Number of Pixels 4960 (H) x 3324 (V) = 16.6M
Number of Effective Pixels 4904 (H) x 3280 (V) = 16.1M
Number of Active Pixels 4872 (H) x 3248 (V) = 15.8M
Pixel Size 7.4 mm (H) x 7.4 mm (V)
Active Image Size 36.1 mm (H) x 24.0 mm (V)
43.3 mm (diagonal),
35 mm Optical Format
Aspect Ratio 3:2
Number of Outputs 1 or 2
Saturation Signal 30,000 electrons
Output Sensitivity 30 mV/e
Quantum Efficiency
KAI16000AXA
KAI16000CXA (RGB)
KAI16000FXA (RGB)
47%
29%, 38%, 44%
31%, 39%, 45%
Read Noise (f = 30 MHz) 16 electrons
Dark Current < 0.5 nA/cm2
Dark Current Doubling Temperature 7°C
Dynamic Range 65 dB
Charge Transfer Efficiency 0.99999
Blooming Suppression > 100 X
Smear < 80 dB
Image Lag < 10 electrons
Maximum Data Rate 30 MHz per channel
Package 40 pin Grid Array
Cover Glass AR coated, 2 sides
or Clear Glass
NOTE: All parameters are specified at T = 40°C unless otherwise noted.
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Figure 1. KAI16000 CCD Image Sensor
Features
16 Million Pixel Resolution
Electronic Shutter
35 mm Optical Format
Progressive Scan Readout
High Sensitivity
Fast Frame Rate
> 60 dB Dynamic Range
Applications
Industrial
Aerial Photography
Security
Scientific
See detailed ordering and shipping information on page 2 of
this data sheet.
ORDERING INFORMATION
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ORDERING INFORMATION
Table 2. ORDERING INFORMATION
Part Number Description Marking Code
KAI16000AAAJRB1* Monochrome, No Microlens, PGA Package,
Taped Clear Cover Glass with AR coating (2 sides), Grade 1
KAI16000AAA
Serial Number
KAI16000AAAJRB2* Monochrome, No Microlens, PGA Package,
Taped Clear Cover Glass with AR coating (2 sides), Grade 2
KAI16000AAAJRAE* Monochrome, No Microlens, PGA Package, Taped Clear Cover
Glass with AR coating (2 sides), Engineering Grade
KAI16000AAAJPB1 Monochrome, No Microlens, PGA Package,
Taped Clear Cover Glass, Grade 1
KAI16000AAAJPB2 Monochrome, No Microlens, PGA Package,
Taped Clear Cover Glass, Grade 2
KAI16000AAAJPAE Monochrome, No Microlens, PGA Package,
Taped Clear Cover Glass, Engineering Grade
KAI16000AAAJDB1 Monochrome, No Microlens, PGA Package,
Sealed Clear Cover Glass with AR coating (2 sides), Grade 1
KAI16000AAAJDB2 Monochrome, No Microlens, PGA Package,
Sealed Clear Cover Glass with AR coating (2 sides), Grade 2
KAI16000AAAJDAE Monochrome, No Microlens, PGA Package, Sealed Clear Cover
Glass with AR coating (2 sides), Engineering Grade
KAI16000AXAJDBX Monochrome, Special Microlens, PGA Package,
Clear Cover Glass with AR coating (both sides), Special Grade
KAI16000AXA
Serial Number
KAI16000AXAJDB1 Monochrome, Special Microlens, PGA Package,
Clear Cover Glass with AR coating (both sides), Grade 1
KAI16000AXAJDB2 Monochrome, Special Microlens, PGA Package,
Clear Cover Glass with AR coating (both sides), Grade 2
KAI16000AXAJDAE Monochrome, Special Microlens, PGA Package, Clear Cover
Glass with AR coating (both sides), Engineering Grade
KAI16000AXAJRB1* Monochrome, Special Microlens, PGA Package,
Taped Clear Cover Glass with AR coating (2 sides), Grade 1
KAI16000AXAJRB2* Monochrome, Special Microlens, PGA Package,
Taped Clear Cover Glass with AR coating (2 sides), Grade 2
KAI16000AXAJRAE* Monochrome, Special Microlens, PGA Package, Taped Clear
Cover Glass with AR coating (2 sides), Engineering Grade
KAI16000AXAJPB1 Monochrome, Special Microlens, PGA Package,
Taped Clear Cover Glass, Grade 1
KAI16000AXAJPB2 Monochrome, Special Microlens, PGA Package,
Taped Clear Cover Glass, Grade 2
KAI16000AXAJPAE Monochrome, Special Microlens, PGA Package,
Taped Clear Cover Glass, Engineering Grade
KAI16000FXAJDB1 Gen2 Color (Bayer RGB), Special Microlens, PGA Package,
Clear Cover Glass with AR coating (both sides), Grade 1
KAI16000FXA
Serial Number
KAI16000FXAJDB2 Gen2 Color (Bayer RGB), Special Microlens, PGA Package,
Clear Cover Glass with AR coating (both sides), Grade 2
KAI16000FXAJDAE Gen2 Color (Bayer RGB), Special Microlens, PGA Package,
Clear Cover Glass with AR coating (both sides), Engineering
Grade
*Not recommended for new designs.
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Table 2. ORDERING INFORMATION
Part Number Marking CodeDescription
KAI16000CXAJDB1* Gen1 Color (Bayer RGB), Special Microlens, PGA Package,
Clear Cover Glass with AR coating (both sides), Grade 1
KAI16000CXA
Serial Number
KAI16000CXAJDB2* Gen1 Color (Bayer RGB), Special Microlens, PGA Package,
Clear Cover Glass with AR coating (both sides), Grade 2
KAI16000CXAJDAE* Gen1 Color (Bayer RGB), Special Microlens, PGA Package,
Clear Cover Glass with AR coating (both sides), Engineering
Grade
*Not recommended for new designs.
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
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DEVICE DESCRIPTION
Architecture
Figure 2. Sensor Architecture
4872 (H) x 3248 (V)
Active Pixels
G
G
R
B
G
G
R
B
G
G
R
B
G
G
R
B
Pixel
1,1
16 Buffer Rows
16 Buffer Rows
40 Gray Rows
16 Buffer Columns
16 Buffer Columns
28 Black Columns
28 Black Columns
12 Dummy Pixels
12 Dummy Pixels
Dual
Output
or
Video L Video R
12 28 16 4872 16 28
Single
12 28 16 2436 2436 16 28 12
Fast Line Dump Left 2480
4 Gray Rows
Fast Line Dump Right 2480
There are 40 light shielded gray rows followed 3280
photoactive rows and finally 4 more light shielded gray
rows. The first 16 and the last 16 photoactive rows are buffer
rows giving a total of 3248 lines of image data.
In the single output mode all pixels are clocked out of the
Video L output in the lower left corner of the sensor. The first
12 empty pixels of each line do not receive charge from the
vertical shift register. The next 28 pixels receive charge from
the left light shielded edge followed by 4904 photosensitive
pixels and finally 28 more light shielded pixels from the
right edge of the sensor. The first 16 and last 16
photosensitive pixels are buffer pixels giving a total of 4872
pixels of image data.
In the dual output mode the clocking of the right half of the
horizontal CCD is reversed. The left half of the image is
clocked out Video L and the right half of the image is clocked
out Video R. For the Video L each row consists of 12 empty
pixels followed by 28 light shielded pixels followed by 2452
photosensitive pixels. For the Video R each row consists of
12 empty pixels followed by 28 light shielded pixels
followed by 2452 photosensitive pixels. When
reconstructing the image, data from Video R will have to be
reversed in a line buffer and appended to the Video L data.
The gray rows are not entirely dark and so should not be
used for a dark reference level. Use the dark columns on the
left or right side of the image sensor as a dark reference.
Of the dark columns, the first and last dark columns
should not be used for determining the zero signal level.
Some light does leak into the first and last dark columns.
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PHYSICAL DESCRIPTION
Pin Description and Device Orientation
Figure 3. Package Pin Designations Top View
Pixel 1,1
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
12345678910 11 12 13 14 15 16 17 18 19 20
Table 3. PINOUT
Pin Name Description
1 VOUTL Video Output, Left
2 VDDL VDD, Left
3 GND Ground
4 RESETL Reset Gate, Left
5 HLASTL Horizontal Clock, Last Stage, Left
6 H2BL Horizontal Clock, Phase 2, Barrier, Left
7 H1BL Horizontal Clock, Phase 1, Barrier, Left
8 H1SL Horizontal Clock, Phase 1, Storage, Left
9 H2SL Horizontal Clock, Phase 2, Storage, Left
10 ESD ESD Protection Disable
11 GND Ground
12 H2SR Horizontal Clock, Phase 2, Storage, Right
13 H1SR Horizontal Clock, Phase 1, Storage, Right
14 H1BR Horizontal Clock, Phase 1, Barrier, Right
15 H2BR Horizontal Clock, Phase 2, Barrier, Right
16 HLASTR Horizontal Clock, Last Stage, Right
17 RESETR Reset Gate, Right
18 GND Ground
19 VDDR VDD, Right
20 VOUTR Video Output, Right
Pin Name Description
40 FDGL Fast Line Dump Gate, Left
39 RDL Reset Drain, Left
38 SUB Substrate
37 GND Ground
36 V1 VCCD Gate 1, Phase 2
35 V5 VCCD Gate 5, Phase 2
34 V9 VCCD Gate 9, Phase 2
33 V3 VCCD Gate 3, Phase 2
32 V7 VCCD Gate 7, Phase 2
31 V11 VCCD Gate 11, Phase 2
30 V2 VCCD Gate 2, Phase 1
29 V6 VCCD Gate 6, Phase 1
28 V10 VCCD Gate 10, Phase 1
27 V4 VCCD Gate 4, Phase 1
26 V8 VCCD Gate 8, Phase 1
25 V12 VCCD Gate 12, Phase 1
24 GND Ground
23 SUB Substrate
22 RDR Reset Drain, Right
21 FDGR Fast Line Dump Gate, Right
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IMAGING PERFORMANCE
Table 4. TYPICAL OPERATION CONDITIONS
Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions.
Description Condition Notes
Frame Time 908 msec 1
Horizontal Clock Frequency 20 MHz
Light Source Continuous red, green and blue illumination centered at 450, 530 and 650 nm 2, 3
Operation Nominal operating voltages and timing
1. Electronic shutter is not used. Integration time equals frame time.
2. LEDs used: Blue: Nichia NLPB500, Green: Nichia NSPG500S and Red: HP HLMP8115.
3. For monochrome sensor, only green LED used.
Table 5. SPECIFICATIONS
Description Symbol Min. Nom. Max. Units
Sample
Plan 7
Temperature
Tested At
(5C) Notes
Global NonUniformity n/a 2.5 5.0 %rms Die 27, 40 1
Maximum Photoresponse
Nonlinearity
NL n/a 2 % Design 2, 3
Maximum Gain Difference Between
Outputs
DGn/a 10 % Design 2, 3
Maximum Signal Error due to
Nonlinearity Differences
DNL n/a 1 % Design 2, 3
Horizontal CCD Charge Capacity HNe 100 keDesign
Vertical CCD Charge Capacity VNe 50 keDie 27, 40
Photodiode Charge Capacity PNe 28 30 keDie 27, 40 4
Horizontal CCD Charge Transfer
Efficiency
HCTE 0.99999 n/a Design
Vertical CCD Charge Transfer
Efficiency
VCTE 0.99999 Design
Photodiode Dark Current Ipd n/a
n/a
40
0.01
350
0.1
e/p/s
nA/cm2Die 40
Vertical CCD Dark Current Ivd n/a
n/a
400
0.12
1711
0.5
e/p/s
nA/cm2Die 40
Dark Current Doubling Temperature DTn/a 7 n/a °C Design
Image Lag Lag n/a <10 50 eDesign
Antiblooming Factor Xab 100 300 n/a Design
Vertical Smear Smr n/a 80 75 dB Design
Read Noise neT16 erms Design 5
Dynamic Range DR 65 dB Design 5, 6
Output Amplifier DC Offset Vodc 4 9.5 14 V Die 27, 40
Output Amplifier Bandwidth F3db 140 MHz Design
Output Amplifier Impedance ROUT 100 130 200 WDie 27, 40
Output Amplifier Sensitivity DV/DN30 mV/eDesign
1. Per color
2. Value is over the range of 10% to 90% of photodiode saturation.
3. Value is for the sensor operated without binning.
4. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of Vab is set such
that the photodiode charge capacity is 30,000 electrons.
5. At 30 MHz
6. Uses 20LOG (PNe/ neT)
7. “Die” indicates a parameter that is measured on every sensor during the production testing. “Design” designates a parameter that is quantified
during the design verification activity.
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Table 6. KAI16000AAA
Description Symbol Min. Nom. Max. Units
Sample
Plan 1
Temperature
Tested At
(5C) Notes
Peak Quantum Efficiency QEmax 11 n/a % Design
Peak Quantum Efficiency
Wavelength
lQE n/a 500 n/a nm Design
1. “Die” indicates a parameter that is measured on every sensor during the production testing. “Design” designates a parameter that is quantified
during the design verification activity.
Table 7. KAI16000AXA
Description Symbol Min. Nom. Max. Units
Sample
Plan 1
Temperature
Tested At
(5C) Notes
Peak Quantum Efficiency QEmax 45 n/a % Design
Peak Quantum Efficiency
Wavelength
lQE n/a 500 n/a nm Design
1. “Die” indicates a parameter that is measured on every sensor during the production testing. “Design” designates a parameter that is quantified
during the design verification activity.
Table 8. KAI16000FXA (Gen2)
Description Symbol Min. Nom. Max. Units
Sample
Plan 1
Temperature
Tested At
(5C) Notes
Peak Quantum Efficiency Blue
Green
Red
QEmax 45
39
31
n/a
n/a
n/a
% Design
Peak Quantum Efficiency
Wavelength
Blue
Green
Red
lQE n/a
n/a
n/a
460
525
600
n/a
n/a
n/a
nm Design
1. “Design” designates a parameter that is quantified during the design verification activity.
Table 9. KAI16000CXA (Gen1)
Description Symbol Min. Nom. Max. Units
Sample
Plan 1
Temperature
Tested At
(5C) Notes
Peak Quantum Efficiency Blue
Green
Red
QEmax 44
38
29
n/a
n/a
n/a
% Design 2
Peak Quantum Efficiency
Wavelength
Blue
Green
Red
lQE n/a
n/a
n/a
470
540
620
n/a
n/a
n/a
nm Design 2
1. “Design” designates a parameter that is quantified during the design verification activity.
2. This color filter set configuration (Gen1) is not recommended for new designs.
NOTE: n/a = not applicable
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TYPICAL PERFORMANCE CURVES
Monochrome with Microlens Quantum Efficiency
Figure 4. Monochrome with Microlens Quantum Efficiency
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
300 400 500 600 700 800 900 1000 1100
Absolute Quantum Efficiency
Wavelength (nm)
Measured with AR
coated cover glass
Monochrome without Microlens Quantum Efficiency
Figure 5. Monochrome without Microlens Quantum Efficiency
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
300 400 500 600 700 800 900 1000 1100
Absolute Quantum Efficiency
Wavelength (nm)
Measured without AR
coated cover glass
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Color with Microlens Quantum Efficiency
Figure 6. Color with Microlens Quantum Efficiency
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Angular Quantum Efficiency
For the curves marked “Horizontal”, the incident light
angle is varied in a plane parallel to the HCCD.
For the curves marked “Vertical”, the incident light angle
is varied in a plane parallel to the VCCD.
Monochrome with Microlens
Figure 7. Monochrome with Microlens Angular Quantum Efficiency
0
10
20
30
40
50
60
70
80
90
100
30 20 10 0 10 20 30
Relative Quantum Efficiency (%)
Angle (degress)
Vertical
Horizontal
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DEFECT DEFINITIONS
Operational Conditions
All defect tests performed at tint = tframe = 908 msec
Table 10. SPECIFICATIONS
Description Definition
Class X Monochrome
with Microlens Only Class 1
Class 2
Monochrome
Class 2
Color Notes
Major dark field defective
bright pixel
Defect 245 mV 150 150 300 300 2
Major bright field defective
dark pixel
Defect 15%
Minor dark field defective
bright pixel
Defect 126 mV 1500 1500 3000 3000 3
Cluster defect A group of 2 to “N”
contiguous major
defective pixels, but no
more than “W”
adjacent defects
horizontally.
0 30
N = 20
W = 4
30
N = 20
W = 4
30
N = 20
W = 4
1, 2
Column defect A group of more than
10 contiguous major
defective pixels along
a single column
0 0 4 15 1, 2
1. Column and cluster defects are separated by no less than two (2) pixels in any direction (excluding single pixel defects).
2. Tested at 27°C and 40°C.
3. Tested at 40°C.
NOTE: Class X sensors are offered strictly “as available”. ON Semiconductor cannot guarantee delivery dates. Please call for availability.
Defect Map
The defect map supplied with each sensor is based upon
testing at an ambient (27°C) temperature. Minor point
defects are not included in the defect map. All defective
pixels are reference to pixel 1, 1 in the defect maps.
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TEST DEFINITIONS
Test Regions of Interest
Image Area ROI: Pixel (1, 1) to Pixel (4872, 3248)
Only the active pixels are used for performance and defect tests.
Overclocking
The test system timing is configured such that the sensor
is overclocked in both the vertical and horizontal directions.
See Figure 8 for a pictorial representation of the regions.
Figure 8. Overclock Regions of Interest
Pixel 1,1
Vertical Overclock
Horizontal Overclock
H
V
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Tests
Global NonUniformity
This test is performed with the imager illuminated to a
level such that the output is at 70% of saturation
(approximately 630 mV). Prior to this test being performed
the substrate voltage has been set such that the charge
capacity of the sensor is 900 mV. Global nonuniformity is
defined as
GlobalNonUniformity +100 ǒActiveAreaStandardDeviation
ActiveAreaSignal Ǔ
Units: %rms.
Active Area Signal = Active Area Average Dark Column
Average
Dark Field Defect Test
This test is performed under dark field conditions. The
sensor is partitioned into 384 sub regions of interest, each of
which is 203 by 203 pixels in size. In each region of interest,
the median value of all pixels is found. For each region of
interest, a pixel is marked defective if it is greater than or
equal to the median value of that region of interest plus the
defect threshold specified in the “Defect Definitions”
section.
Bright Field Defect Test
This test is performed with the imager illuminated to a
level such that the output is at approximately 630 mV. Prior
to this test being performed the substrate voltage has been set
such that the charge capacity of the sensor is 900 mV. The
average signal level of all active pixels is found. The bright
and dark thresholds are set as:
Dark defect threshold = Active Area Signal * threshold
Bright defect threshold = Active Area Signal * threshold
The sensor is then partitioned into 384 sub regions of
interest, each of which is 203 by 203 pixels in size. In each
region of interest, the average value of all pixels is found.
For each region of interest, a pixel is marked defective if it
is greater than or equal to the median value of that region of
interest plus the bright threshold specified or if it is less than
or equal to the median value of that region of interest minus
the dark threshold specified.
Example for major bright field defective pixels:
Average value of all active pixels is found to be
630 mV
Dark defect threshold: 630 mV * 15% = 95 mV
Bright defect threshold: 630 mV * 15% = 95 mV
Region of interest #1 selected. This region of interest is
pixels 1, 1 to pixels 203, 203.
Median of this region of interest is found to be
630 mV.
Any pixel in this region of interest that
is (630 + 95 mV) 725 mV in intensity will be
marked defective.
Any pixel in this region of interest that
is (630 95 mV) 535 mV in intensity will be
marked defective.
All remaining 384 sub regions of interest are analyzed
for defective pixels in the same manner.
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OPERATION
Table 11. ABSOLUTE MAXIMUM RATINGS
Description Symbol Minimum Maximum Units Notes
Operating Temperature TOP 50 70 °C 1
Humidity RH 5 90 % 2
Output Bias Current Iout 0.0 40 mA 3
Offchip Load CL10 pF
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Noise performance will degrade at higher temperatures.
2. T = 25°C. Excessive humidity will degrade MTTF.
3. Total for all outputs. Maximum current is 20 mA for each output. Avoid shorting output pins to ground or any low impedance source during
operation. Amplifier bandwidth increases at higher current and lower load capacitance at the expense of reduced gain (sensitivity). Operation
at these values will reduce MTTF.
Table 12. MAXIMUM VOLTAGE RATINGS BETWEEN PINS
Description Minimum Maximum Units Notes
RL, RR, H1SL, H1BL, H2SL, H2BL, H1SR, H1BR, H2SR, H2BR,
HLASTL, HLASTR to ESD
0 17 V
Pin to Pin with ESD Protection 17 17 V 1
VDDL, VDDR to GND 0 25 V
1. Pins with ESD protection are: RL, RR, H1SL, H1BL, H2SL, H2BL, H1SR, H1BR, H2SR, H2SR, HLASTL, and HLASTR
PowerUp Sequence
1. Substrate
2. ESD Protection Disable
3. All other clocks and biaeses
Table 13. DC BIAS OPERATING CONDITIONS
Description Symbol Pins Minimum Nominal Maximum Units
Maximum DC
Current (mA) Notes
Reset Drain RD RDL, RDR +11.5 +12.0 +12.0 V
Output Amplifier Supply VDD VDDL, VDDR +14.5 +15.0 +15.5 V 4
Ground GND GND 0.0 0.0 0.0 V
Substrate SUB SUB +8.0 VAB +16.0 V 1, 5
ESD Protection Disable ESD ESD 9.25 9.0 8.75 V 2
Output Bias Current Iout VOUTL,
VOUTR
5.0 10.0 mA 3
1. The operating of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of Vab is set such that the
photodiode charge capacity is 30,000 electrons.
2. VESD must be at least 1 V more negative than H1_lo and H2_lo during sensor operation AND during camera power turn on.
3. An output load sink must be applied to Vout to activate output amplifier.
4. The maximum DC current is for one output unloaded. This is the maximum current that the first two stages of one output amplifier will draw.
This value is with Vout disconnected.
5. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions
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AC Operating Conditions
Table 14. CLOCK LEVELS
Description Pins Symbol Minimum Nominal Maximum Units Notes
Vertical CCD Clock High V1, V3, V5, V7,
V9, V11
V_2hi +8.5 +9.0 +9.5 V
Vertical CCD Clocks
Midlevel
V1, V2, V3, V4,
V5, V6, V7, V8,
V9, V10, V11,
V12
V_1mid,
V_2mid
0.2 0.0 +0.2 V
Vertical CCD Clocks Low V1, V2, V3, V4,
V5, V6, V7, V8,
V9, V10, V11,
V12
V_1lo, V_2lo 9.5 9.0 8.5 V
Horizontal CCD Clocks
Amplitude, Phase 1 Stor-
age
H1SaH1SL,
H1BL, H2SL,
H2BL, H1SR,
H1BR, H2SR,
H2BRK
H_amp +4.5 +5.0 +5.5 V
Horizontal CCD Clocks
Low
H1SL, H1BL,
H2SL, H2BL,
H1SR, H1BR,
H2SR, H2BR
H_lo 5.0 4.5 4.0 V
Horizontal Last CCD
Amplitude
HLASTL,
HLASTR
HLAST_amp +4.5 +5.0 +5.5 V
Horizontal Last CCD Low HLASTL,
HLASTR
HLAST_lo 5.0 4.5 4.0 V
Reset Clock Amplitude RESETL,
RESETR
R_amp +4.5 +5.0 +5.5 V
Reset Clock Low RESETL,
RESETR
R_lo 3.5 3.0 2.5 V
Electronic Shutter Voltage SUB Vshutter +44 +48 +52 V 1
Fast Dump High FDL, FDR FD_hi +4.5 +5.0 +5.5 V
Fast Dump Low FDL, FDR FD_lo 9.5 9.0 8.5 V
1. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions
The figure below shows the DC bias (SUB) and AC clock
(Vshutter) applied to the SUB pin. Both the DC bias and AC
clock are referenced to ground.
Figure 9.
SUB
Vshutter
GND GND
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Table 15. CLOCK LINE CAPACITANCES
Clocks Capacitance Units Notes
Vertical CCD Phase 1 to GND 108 nF 1, 3
Vertical CCD Phase 2 to GND 118 nF 1, 4
Vertical CCD Phase 1 to Vertical CCD Phase 2 56 nF 3, 4
H1S to GND 27 pF 2
H2S to GND 27 pF 2
H1B to GND 13 pF 2
H2B to GND 4 pF 2
H1S to H2B and H2S 13 pF 2
H1B to H2B and H2S 13 pF 2
H2S to H1B and H1S 13 pF 2
H2B to H1B and H1S 13 pF 2
HLAST to GND 20 pF 2
RESET to GND 10 pF
FD to GND 20 pF
1. Gate capacitance to GND is voltage dependent. Value is for nominal VCCD clock voltages.
2. For nominal HCCD clock voltages, these values are for half of the imager (H1SL, H1BL, H2SL, H2BL and H1BINL or H1SR, H1BR, H2SR,
H2BR and H1BINR).
3. Vertical CCD Phase 1: V2, V4, V6, V8, V10, V12
4. Vertical CCD Phase 2: V1, V3, V5, V7, V9, V11
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TIMING
Table 16. REQUIREMENTS AND CHARACTERISTICS
Description Symbol Minimum Nominal Maximum Units Notes
VCCD to HCCD Delay THD 4 6 ms
VCCD Transfer Time TVCCD 4 6 ms
HCCD to VCCD Delay THL 50 ns
Photodiode Transfer Time TV3rd 10 12 ms
VCCD Pedestal Time T3P 200 600 ms
VCCD Delay T3D 12 20 ms
VCCD Delay Before Pedestal TDEL 50 ns
VCCD Delay Before 1st Line TD1L 10 60 ms
Reset Pulse Time TR3.25 ms
VCCD to HCCD Delay Shutter THDS 6ms
Shutter Pulse TIme TS4ms
Shutter Pulse Delay TSD 1.5 ms
HCCD Clock Period TH33.3 ns
VCCD Rise/Fall Time TVR 0.2 ms
Fast Dump Gate Leading Delay TFDL 0.5 ms
Fast Dump Gate Trailing Delay TFDT 0.5 ms
VCCD Line Clock Leading Edge Delay TVL 0.2 0.3 0.4 ms
VCCD Line Clock Trailing Edge Delay TVT 0.0 0.2 0.4 ms
Main Timing Continuous Mode
Figure 10. Main Timing Continuous Mode
Repeat for 3324
Lines
Line Timing
Vertical Frame
Timing
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18
Frame Timing Continuous Mode
Figure 11. Framing Timing
V1, V3, V5,
V7, V9, V11
V2, V4, V6,
V8, V10, V12
H1SL, H1BL,
H1SR, H2BR
H2SL, H2BL,
H2SR, H1BR
HLASTL,
HLASTR
V_2lo
V_2mid
V_1lo
V_1mid
V_2hi
T3P T3D
TD1L
TDEL
TV3rd
H_lo
H_lo
H_amp
H_amp
HLAST_lo
HLAST_amp
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Line Timing Continuous Mode
Line Timing Single Output
Figure 12. Line Timing Single Output
TVCCD
TL
THD
R
2
1
pixel count
39
11
12
13
14
40
41
42
43
4941
4942
4943
4945
4946
4971
4972
44
4944
4970
V2, V4, V6,
V8, V10, V12
V1, V3, V5,
V7, V9, V11
H1SL, H1BL,
H1SR, H2BR
H2SL, H2BL,
H2SR, H1BR
HLASTL, HLASTR
Line Timing Double Output
Figure 13. Line Timing Dual Output
2483
2484
2485
2487
2488
2491
2492
2486
2490
2489
TVCCD
TL
THD
R
2
1
pixel count
39
11
12
13
14
40
41
42
43
44
V2, V4, V6,
V8, V10, V12
V1, V3, V5,
V7, V9, V11
H1SL, H1BL,
H1SR, H1BR
H2SL, H2BL,
H2SR, H2BR
HLASTL, HLASTR
KAI16000
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Line Timing Detail Single Output
Figure 14. Line Timing Detail Single Output
TVCCD
THD
THL
V2, V4, V6,
V8, V10, V12
V1, V3, V5,
V7, V9, V11
H1SL, H1BL,
H1SR, H2BR
H2SL, H2BL,
H2SR, H1BR
HLASTL, HLASTR
H_lo
H_lo
H_amp
H_amp
HLAST_lo
HLAST_am
p
V_2lo
V_2mid
V_1lo
V_1mid
Line Timing Detail Edge Alignment
Figure 15. Line Timing Detail Edge Alignment
Low 0%
10%
High 100%
90%
50%
V1, V3,
V5, V7,
V9, V11
V2, V4,
V6, V8,
V10, V12
TVL TVT
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Pixel Timing
Figure 16. Pixel Timing
HLAST_lo
HLAST_amp
H_lo
H_amp
H_lo
H_amp
R_lo
R_amp
H1SL, H1BL,
H1SR, H2BR
H2SL, H2BL,
H2SR, H1BR
HLASTL, HLASTR
RR, RL
TR
KAI16000
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Fast Line Dump Timing
Figure 17. Fast Line Dump Timing
H1SL, H1BL,
H1SR, H2BR
V2, V4, V6,
V8, V10, V12
V1, V3, V5,
V7, V9, V11
FDR,
FDL
FD_lo
FD_hi
TVCCD
TFDL TFDT
THD
TVCCD TVCCD
KAI16000
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Electronic Shutter Timing
Figure 18. Electronic Shutter Timing
H1SL, H1BL,
H1SR, H2BR
H2SL, H2BL,
H2SR, H1BR
HLASTL, HLASTR
V2, V4, V6,
V8, V10, V12
V1, V3, V5,
V7, V9, V11
SUB
GND
VSUB
VES
THDS
TSD
TS
Electronic Shutter Integration Time Definition
Figure 19. Integration Time Definition
Integration Time
VShutter
VSUB
V1, V3, V5,
V7, V9, V11
KAI16000
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24
STORAGE AND HANDLING
Table 17. STORAGE CONDITIONS
Description Symbol Minimum Maximum Units Notes
Temperature T 55 80 °C 1
Humidity RH 5 90 % 2
1. Longterm exposure toward the maximum temperature will accelerate color filter degradation.
2. T = 25°C. Excessive humidity will degrade MTTF.
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For information on soldering recommendations, please
download the Soldering and Mounting Techniques
Reference Manual (SOLDERRM/D) from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
KAI16000
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25
MECHANICAL DRAWINGS
Completed Assembly
Figure 20. Completed Assembly (1 of 2)
KAI16000
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Figure 21. Completed Assembly (2 of 2)
KAI16000
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27
Cover Glass
Figure 22. Glass Drawing
Notes:
Double Sided AR Coated Glass
1. MultiLayer AntiReflective Coating on 2 sides:
Double Sided Reflectance:
Range (nm)
420 450 nm < 2%
450 630 nm < 1%
630 680 nm < 2%
2. Dust, Scratch Specification 20 microns max.
3. Substrate Schott D263T eco or equivalent
4. Epoxy: NCO150HB
Thickness: 0.002” 0.005”
Clear Glass
1. Materials: Substrate Schott D263T eco or equivalent
2. No epoxy
3. Dust, Scratch Count 20 microns max.
4. Reflectance:
420 435 nm < 10%
435 630 nm < 10%
630 680 nm < 10%
Coat Both Sides
Chamfer 0.008" [0.20] (Typ.
8 plcs.)
Epoxy: NC0-150 HB
Thk. 0.002" - 0.005"
Chamfer 0.020" [0.50] (Typ. 4 plcs.)
0.020R [0.50] (Typ. 8 plcs.)
Ref. AR coat area
KAI16000
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28
Glass Transmission
Figure 23. MAR and Clear Glass Transmission
ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/PatentMarking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Phone: 81358171050
KAI16000/D
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