7-966
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
CD4066BMS
CMOS Quad Bilateral Switch
Description
CD4066BMS is a quad bilateral switch intended for the
transmission or multiplexing of analog or digital signals. It is
pin for pin compatible with CD4016B, but exhibits a much
lower on state resistance. In addition, the on-state resistance
is relatively constant over the full input signal range.
The CD4066BMS consists of four independent bilateral
switches. A single control signal is required per switch. Both
the p and the n device in a given switch are biased on or off
simultaneously by the control signal. As shown in Figure 1,
the well of the n channel device on each switch is either tied
to the input when the switch is on or to VSS when the switch
is off. This configuration eliminates the variation of the switch
transistor threshold voltage with input signal, and thus keeps
the on-state resistance low over the full operating signal
range.
The advantages over single channel switches include peak
input signal voltage swings equal to the full supply voltage,
and more constant on-state impedance over the input signal
range. For sample and hold applications, however, the
CD4016B is recommended.
The CD4066BMS is supplied in these 14-lead outline pack-
ages:
Pinout
CD4066BMS
TOP VIEW
Braze Seal DIP H4Q
Frit Seal DIP H1B
Ceramic Flatpack H3W
IN/OUT A
OUT/IN A
OUT/IN B
IN/OUT B
CONT B
CONT C
VSS
VDD
CONT A
CONT D
IN/OUT D
OUT/IN D
OUT/IN C
IN/OUT C
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Features
• For Transmission or Multiplexing of Analog or Digital
Signals
• High Voltage Types (20V Rating)
• 15V Digital or ±7.5V Peak-to-Peak Switching
• 125Ω Typical On-State Resistance for 15V Operation
• Switch On-State Resistance Matched to Within 5Ω
Over 15V Signal Input Range
• On-State Resistance Flat Over Full Peak-to-Peak Sig-
nal Range
• High On/Off Output Voltage Ratio
- 80dB Typ. at FIS = 10kHz, RL = 1kΩ
• High Degree of Linearity: <0.5% Distortion Typ. at
FIS = 1kHz, VIS = 5Vp-p, VDD - VSS ≥ 10V, RL = 10kΩ
• Extremely Low Off-State Switch Leakage Resulting in
Very Low Offset Current and High Effective Off-State
Resistance: 10pA Typ. at VDD - VSS = 10V, T A = +25oC
• Extremely High Control Input Impedance (Control Cir-
cuit Isolated from Signal Circuit): 1012Ω Typ.
• Low Crosstalk Between Switches: -50dB Typ. at FIS =
8MHz, RL = 1kΩ
• Matched Control Input to Signal Output
Capacitance: Reduces Output Signal Transients
• Frequency Response, Switch on = 40MHz (Typ.)
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
“B” Series CMOS Devices”
Applications
• Analog Signal Switching/Multiplexing
- Signal Gating - Modulator
- Squelch Control - Demodulator
- Chopper - Commutating Switch
• Digital Signal Switching/Multiplexing
• Transmission Gate Logic Implementation
• Analog to Digital & Digital to Analog Conversion
• Digital Control of Frequency, Impedance, Phase, and
Analog Signal Gain
December 1992
File Number 3319
7-967
Specifications CD4066BMS
Absolute Maximum Ratings Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Thermal Resistance . . . . . . . . . . . . . . . . θja θjc
Ceramic DIP and FRIT Package. . . . . 80oC/W 20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K). . . . . .500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . .Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS (NOTE 1) GROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITSMIN MAX
Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC - 0.5 µA
2 +125oC-50µA
VDD = 18V, VIN = VDD or GND 3 -55oC - 0.5 µA
Input Leakage Current IIL VC = VDD or GND 1 +25oC -100 - nA
2 +125oC -1000 - nA
3 -55oC -100 - nA
Input Leakage Current IIH VC = VDD or GND 1 +25oC - 100 nA
2 +125oC - 1000 nA
3 -55oC - 100 nA
Input/Output Leakage
Current (Switch OFF) IOZL VC = 0V, VIS = 18V,
VOS = 0V, VIS = 0V,
VOS = 18V
VDD = 20 1 +25oC -100 - nA
2 +125oC -1000 - nA
VDD = 18V 3 -55oC -100 - nA
IOZH VDD = 20 1 +25oC - 100 nA
2 +125oC - 1000 nA
VDD = 18V 3 -55oC - 100 nA
On Resistance RON5 VC = VDD, RL = 10kW
returned to VDD -
VSS/2
VIS = VSS to VDD
VDD = 5V 1 +25oC 1050 - Ω
RON10 VDD = 10V 1 +25oC 400 - Ω
RON15 VDD = 15V 1 +25oC 240 - Ω
On Resistance RON5 VDD = 5V 1, 2 +125oC - 1300 Ω
-55oC - 800 Ω
On Resistance RON10 VDD = 10V 1, 2 +125oC - 550 Ω
-55oC - 310 Ω
On Resistance RON15 VDD = 15V 1, 2 +125oC - 320 Ω
-55oC - 220 Ω
Functional
(Note 3) F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH >
VDD/2 VOL <
VDD/2 V
VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC
Switch Threshold
RL = 100k to VDD SWTHRH5 VDD = 5V, VC = 1.5V, VIS = GND 1, 2, 3 +25oC, +125oC, -55oC 4.1 - V
SWTHRH15 VDD = 15V, VC = 2V, VIS = GND 1, 2, 3 +25oC, +125oC, -55oC 14.1 - V
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
7-968
Specifications CD4066BMS
Control Input Low
Voltage (Note 2)
|IIS| < 10µa, VIS = VSS,
VOS = VDD and
VIS = VDD, VOS = VSS
VILC5 VDD = 5V 1, 2, 3 +25oC, +125oC, -55oC- 1 V
VILC15 VDD = 15V 1, 2, 3 +25oC, +125oC, -55oC- 2 V
Control Input High
Voltage
(Note 2, Figure 2)
VIS = VSS and VIS =
VDD
VIHC VDD = 5V, |IIS| = .51mA, 4.6V <
VOS < 0.4V 1 +25oC 3.5 - V
VDD = 5V, |IIS| = .36mA, 4.6V <
VOS < 0.4V 2 +125oC 3.5 - V
VDD = 5V, |IIS| = .64mA, 4.6V <
VOS < 0.4V 3 -55oC 3.5 - V
VIHC VDD = 15V, |IIS| = 3.4mA, 13.5V <
VOS <1.5V 1 +25oC11-V
VDD = 15V, |IIS| = 2.4mA, 13.5V <
VOS < 1.5V 2 +125oC11-V
VDD = 15V, |IIS| = 4.2mA, 13.5V <
VOS <1.5V 3 -55oC11-V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
3. VDD = 2.8V/3.0V, RL = 100K to VDD
VDD = 20V/18V, RL = 10K to VDD
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS GROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITSMIN MAX
Propagation Delay
Signal Input to Signal
Output
TPLH
TPHL VC = VDD = 5V, VSS = GND
(Notes 2, 3) 9 +25oC - 40 ns
10, 11 +125oC, -55oC - 54 ns
Propagation Delay
Turn-On, Turn-Off TPHZ/ZH
TPLZ/ZL VIS = VDD = 5V (Notes 1, 2) 9 +25oC - 70 ns
10, 11 +125oC, -55oC - 95 ns
NOTES:
1. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - 0.25 µA
+125oC - 7.5 µA
VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC - 0.5 µA
+125oC-15µA
VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC - 0.5 µA
+125oC-30µA
Control Input Low
Voltage
|IIS| < 10µa, VIS = VSS,
VOS = VDD and
VIS = VDD, VOS = VSS
VILC10 VDD = 10V 1, 2 +25oC, +125oC,
-55oC-2V
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS (NOTE 1) GROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITSMIN MAX
7-969
Specifications CD4066BMS
Control Input High
Voltage (See Figure 2) VIHC10 VDD = 10V, VIS = VDD or GND 2 +25oC, +125oC,
-55oC7-V
Propagation Delay
Signal Input to
Signal Output
TPLH
TPHL VDD = 10V 1, 2, 3 +25oC - 20 ns
VDD = 15V 1, 2, 3 +25oC - 15 ns
Propagation Delay
Turn-On, Turn-Off TPHZ/ZH
TPLZ/ZL VDD = 10V 1, 2, 3 +25oC - 40 ns
VDD = 15V 1, 2, 3 +25oC - 30 ns
Input Capacitance CIN Any Input 1, 2 +25oC - 7.5 pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC-25µA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
N Threshold Voltage
Delta ∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC-±1V
P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage
Delta ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC-±1V
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH >
VDD/2 VOL <
VDD/2 V
VDD = 3V, VIN = VDD or GND
Propagation Delay Time TPHL
TPLH VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x
+25oC
Limit
ns
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 3. See Table 2 for +25oC limit.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC
PARAMETER SYMBOL DELTA LIMIT
Supply Current - SSI IDD ±0.1µA
ON Resistance RONDEL10 ± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP MIL-STD-883
METHOD GROUP A SUBGROUPS READ AND RECORD
Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A, RONDEL10
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A, RONDEL10
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A, RONDEL10
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A, RONDEL10
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
970
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Specifications CD4066BMS
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6 Sample 5005 1, 7, 9
Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS MIL-STD-883
METHOD
TEST READ AND RECORD
PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD
Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
FUNCTION OPEN GROUND VDD 9V ± -0.5V
OSCILLATOR
50kHz 25kHz
Static Burn-In 1 (Note 1) 2, 3, 9, 10 1, 4-8, 11-13 14
Static Burn-In 2 (Note 1) 2, 3, 9, 10 7 1, 4-6, 8, 11-14
Dynamic Burn-In (Note 1) - 7 14 2, 3, 9, 10 5, 6, 12, 13 1, 4, 8, 11
Irradiation (Note 2) 2, 3, 9, 10 7 1, 4-6, 8, 11-14
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ±5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V
Functional Diagram
TRUTH TABLE EACH SWITCH
INPUT OUTPUT
VC VIS VOS
100
111
0 0 Open
0 1 Open
Positive Logic: Switch ON VC = “1”
Switch OFF VC = “0”
TABLE 6. APPLICABLE SUBGROUPS (Continued)
CONFORMANCE GROUP MIL-STD-883
METHOD GROUP A SUBGROUPS READ AND RECORD
IN/OUT
OUT/IN
OUT/IN
IN/OUT
CONTROL B
CONTROL C
VSS
VDD
CONTROL A
CONTROL D
IN/OUT
OUT/IN
OUT/IN
IN/OUT
1
2
3
4
5
6
7
14
13
12
11
10
9
8
SW
A
SIG A
SW
D
SW
B
SW
C
SIG B
SIG C
SIG D
7-971
CD4066BMS
Schematic
FIGURE 1. SCHEMATIC DIAGRAM OF 1 OF 4 IDENTICAL SWITCHES AND ITS ASSOCIATED CONTROL CIRCUITRY
FIGURE 2. DETERMINATION OF RON AS A TEST CONDITION
FOR CONTROL INPUT HIGH VOLTAGE (VIHC)
SPECIFICATION
FIGURE 3. CHANNEL ON-STATE RESISTANCE MEASURE-
MENT CIRCUIT
FIGURE 4. CAPACITANCE TEST CIRCUIT FIGURE 5. OFF SWITCH INPUT OR OUTPUT LEAKAGE
FIGURE 6. PROPAGATION DELAY TIME SIGNAL INPUT (VIS)
TO SIGNAL OUTPUT (VOS) FIGURE 7. CROSSTALK CONTROL INPUT TO SIGNAL OUTPUT
IN
VSS
N
P
CONTROL
VDD
N
VC
*
P
N
VIS
OUT
VOS
SIGNAL LEVEL RANGE:
VSS ≤ VIS ≤ VDD
CONTROL
SWITCH
VSS
NORMAL OPERATION CONTROL
SWITCH ON, VC “I” = VDD
SWITCH OFF, VC “O” = VSS
NOTE:
All “P” Substrates
Connected to VDD
LINE BIASING:
ALL CONTROL INPUTS ARE
PROTECTED BY THE CMOS
PROTECTION NETWORK
*
CD4066BMS
1 OF 4 SWITCHES
IIS VOS
VIS
|VIS - VOS|
|IIS|
RON =
TG
“ON”
VDD
VSS
10kΩ1kΩ
RANGE X-Y
PLOT TER
Y
X
H P
MOSELEY
7030A
KEITHLY 160 DIGITAL
MULTIMETER
CD4066BMS
1 OF 4 SWITCHES
VDD = +5VVC = -5V
VSS = -5V COSCIS
CIOS MEASURED ON BOONTON
CAPACITANCE BRIDGE
MODEL 75A (1MHz)
TEST FIXTURE CAPACITANCE
NULLED OUT
CD4066BMS
1 OF 4 SWITCHES
VDD
VC = VSS
VSS
ALL UNUSED TERMINALS
ARE CONNECTED TO VSS
VIS = VDD
Ι
CD4066BMS
1 OF 4 SWITCHES
VDD
VC = VDD
VSS
ALL UNUSED INPUTS
ARE CONNECTED TO VSS
ViS
50 200kΩ
pF
VDDtr = tf = 20ns
VOS CD4066BMS
1 OF 4 SWITCHES
VDDVC
VSS
ALL UNUSED TERMINALS
ARE CONNECTED TO VSS
10kΩ
+10V
tr = tf = 20ns
VOS
1kΩ
VIS
7-972
CD4066BMS
FIGURE 8. PROPAGATION DELAY TPLH, TPHL CONTROL
SIGNAL OUTPUT. DELAY IS MEASURED AT VOS
LEVEL OF +10% FROM GROUND (TURN ON) OR
ON-STATE OUTPUT LEVEL (TURN OFF).
FIGURE 9. MAXIMUM ALLOWABLE CONTROL INPUT REPETI-
TION RATE
FIGURE 10. 4 CHANNEL PAM MULTIPLEX SYSTEM DIAGRAM
CD4066BMS
1 OF 4 SWITCHES
VDD
VC = VDD
VSS
ALL UNUSED TERMINALS
ARE CONNECTED TO VSS
VDD
50 1kΩ
pF
VDDtr = tf = 20ns
VOS CD4066BMS
1 OF 4 SWITCHES
VDD = +10V
VC
VSS
ALL UNUSED INPUTS
ARE CONNECTED TO VSS
VIS = +10V
50 1kΩ
pF
+10V
tr = tf = 20ns VOS = 1/2VOS
AT 1kHz
VOS
VC
tr = tf = 20ns
REP
RATE
90% 10% 1
0
20ns 20ns
PE J1 J2 J3 J4 J5
Q1 Q2
CD4018B
14
15
1
51
RESET
CLOCK
13
1/4 CD4066B 2
PE J1 J2 J3 J4 J5
Q1 Q2
CD4018B
14
15
1
45
10 3 7 9 122
CLOCK
2
12
CD4066B
3
4
6CD4001B
5
9
13
8
5 4
3 2
12
2
6
1/3 CD4049B
1
1
4
8
11
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
SIGNALS
INPUTS
PACKAGE COUNT
2 - CD4001B
1 - CD4049B
3 - CD4066BMS
2 - CD4018B
10K
3
9
10
513
EXT
RESET
CLOCK
MAX. ALLOWABLE
SIGNAL LEVEL
VDD
30% (VDD - VSS)
VSS
CHAN. 1 CHAN. 2 CHAN. 3 CHAN. 4
910
7
1/3 CD4049B
11
CD4001B
65
913 812 2 1
6
4
11 12
5
1/6 CD4049B
1/4 CD4066B
4
8
11
1
3
12 6 5
10 4 3
11
2CHANNEL 1
LPF
10K
3CHANNEL 2
LPF
10K
9CHANNEL 3
LPF
10K
10 CHANNEL 4
LPF
10K
CD4066B
21297310
4
11
10
SIGNALS
OUTPUTS
7-973
CD4066BMS
FIGURE 11. BIDIRECTIONAL SIGNAL TRANSMISSION VIA DIGITAL CONTROL LOGIC
Typical Performance Characteristics
FIGURE 12. TYPICAL ON-STATE RESISTANCE vs INPUT
SIGNAL VOLTAGE (ALL TYPES) FIGURE 13. TYPICAL ON-STATE vs INPUT SIGNAL VOLTAGE
(ALL TYPES).
FIGURE 14. TYPICAL ON-STATE RESISTANCE vs INPUT
SIGNAL VOLTAGE (ALL TYPES) FIGURE 15. ON-STATE RESISTANCE vs INPUT SIGNAL
VOLTAGE (ALL TYPES)
CD4054B
SWA
SWB
SWC
SWD
VEE = -5V
VSS = 0V
DIGITAL
CONTROL
INPUTS
IN
VDD = 5V
5V
0
VDD = +5V
ANALOG INPUTS (±5V)
CD4066BMS
ANALOG OUTPUTS (±5V) VSS = -5V
+5
-5
SUPPLY VOLTAGE (VDD - VEE) = 5V
AMBIENT TEMPERATURE
(TA) = +125oC
-55oC
+25oC
600
500
400
300
200
100
0
CHANNEL ON-STATE RESISTANCE (RON) (Ω)
-4-3-2-101234
INPUT SIGNAL VOLTAGE (VIS) (V)
SUPPLY VOLTAGE (VDD - VEE) = 10V
AMBIENT TEMPERATURE
(TA) = +125oC
-55oC
+25oC
300
250
200
150
100
50
0
CHANNEL ON-STATE RESISTANCE (RON) (Ω)
-10.0 -7.5 -5.0 -2.5 0 2.5 5.0 7.5 10.0
INPUT SIGNAL VOLTAGE (VIS) (V)
SUPPLY VOLTAGE (VDD - VSS) = 15V
AMBIENT TEMPERATURE
(TA) = +125oC
300
250
200
150
100
50
0
CHANNEL ON-STATE RESISTANCE (RON) (Ω)
-10.0 -7.5 -5.0 -2.5 0 2.5 5.0 7.5 10.0
INPUT SIGNAL VOLTAGE (VIS) (V)
-55oC
+25oC
SUPPLY VOLTAGE (VDD - VSS) = 5V
AMBIENT TEMPERATURE
(TA) = +25oC
600
500
400
300
200
100
0
CHANNEL ON-STATE RESISTANCE (RON) (Ω)
-10.0 -7.5 -5.0 -2.5 0 2.5 5.0 7.5 10.0
INPUT SIGNAL VOLTAGE (VIS) (V)
15V
10V
7-974
CD4066BMS
FIGURE 16. TYPICAL ON CHARACTERISTICS FOR 1 OF 4
CHANNELS FIGURE 17. POWER DISSIPATION PER PACKAGE vs
SWITCHING FREQUENCY
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch).
Typical Performance Characteristics (Continued)
VC = VDD VDD
VIS VOS
RL
VSS
CD4066BMS
1 OF 4
SWITCHES
ALL UNUSED TERMINALS
ARE CONNECTED TO VSS
AMBIENT TEMPERATURE (TA) = +25oC
VDD = 2.5V, VSS = -2.5V
INPUT = TERM 1, OUTPUT = TERM 2
OUTPUT VOLTAGE (VO) (V)
3
2
1
0
-1
-2
-3-3 -2 -1 0 1 2 3 4
INPUT VOLTAGE (VI) (V)
100Ω
100K
RL = 100K 1K
10K
500Ω
100Ω
500Ω
1K
10K
CD4066/
14
7
VDD
VSS
13
12
6
5
BMS
f
POWER DISSIPATION PER PACKAGE (PD) (µW)
10V
5V
8642
SWITCHING FREQUENCY (f) (kHz)
10 102
8
6
4
2
8
6
4
2
8
6
4
2
104
103
102
10
AMBIENT TEMPERATURE (TA) = +25oC
SUPPLY VOLTAGE (VDD) = 15V
8642 103
Special Considerations
In applications that employ separate power sources to drive
VDD and the signal inputs, the VDD current capability
should exceed VDD/RL (RL = effective external load of the
four CD4066B bilateral switches). This provision avoids any
permanent current flow or clamp action on the VDD supply
when power is applied or removed from the CD4066B.
In certain applications, the external load-resistor current may
include both VDD and signal line components. To avoid
drawing VDD current when switch current flows into termi-
nals 1, 4, 8 or 11 the voltage drop across the bidirectional
switch must not exceed 0.8 volts (calculated from RON val-
ues shown).
No VDD current will flow through RL if the switch current
flows into terminals 2, 3, 9, or 10.
METALLIZATION: Thickness: 11kÅ−14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
