ISP1183BSTM - ST-Ericsson - Product.Network

1. General description

The ISP1183 is a Universal Serial Bus (USB) Peripheral Controller that complies with

Universal Serial Bus Specification Rev. 2.0, supporting data transfer at full-speed

(12 Mbit/s). It provides full-speed USB communication capacity to microcontroller or

microprocessor-based systems. The ISP1183 communicates with the system’s

microcontroller or microprocessor through a fast general-purpose parallel interface.

The ISP1183 supports fully autonomous, multiconfigurable Direct Memory Access (DMA)

operation.

The modular approach to implementing a USB Peripheral Controller allows designer to

select the optimum system microcontroller from the wide variety available. The ability to

reuse existing architecture and firmware investments shortens development time,

eliminates risks an d re du ce s co sts. The result is fast and efficient develop m en t of th e

most cost-effective USB peripheral solution.

The ISP1183 supports I/O voltage range of 1.65 V to 3.6 V enabling it to be directly

interfaced to battery-operated devices, such as mobile phones. The ISP1183 is ideally

suited for battery-operated (low power) application in many portable peripherals such as

mobile phones, Personal Digital Assistants (PDAs) an d MP3 players. This device can be

used in bus-powered or hybrid-powered applications. Also , more number of endpoints in

the ISP1183 enable the device to be used in applications such as multifunctional printers,

other than standard applications such as printers, communication devices, scanners,

external mass storage devices and digital still cameras.

2. Features

Complies with Universal Serial Bus Specification Rev. 2.0 and most device class

specifications

Complies with ACPI, OnNow and USB power management requirements

Supports data transfer at full-speed (12 Mbit/s)

High performance USB Peripheral Controller with integrated Serial Interface Engine

(SIE), FIFO memory, transceiver and 3.3 V voltage regulator

High-speed (11.1 MB/s or 90 ns read/write cycle) parallel interface

Fully autonomous and multiconfiguration DMA operation

Up to 14 programmable USB endpoints with 2 fixed co ntrol IN/OUT endpoints

Integrated physical 2462 bytes of multiconfiguration FIFO memory

Endpoints with double buffering to increase throughput and ease real-time data

transfer

Seamless interface with most microcontrollers and microprocessors

Bus-powered capability with low power consumption and low suspend current

ISP1183

Low-power USB peripheral controller with DMA

Rev. 04 — 29 September 2009 Product data sheet

Product data sheet Rev. 04 — 29 September 2009 2 of 61

ISP1183

Low-power USB peripheral controller with DMA

Software controlled connection to the USB bus (SoftConnect1)

Support s internal power-on and low-voltage reset circuit

Supports software reset

Hybrid-powered capability with low-power consumption required from the system

VBUS indication

6 MHz crystal oscillator input with integrated PLL for low EMI

Supports I/O voltage range of 1.65 V to 3.6 V

Operation over the extended USB bus voltage range (4.0 V to 5.5 V) with 3.3 V

tolerant I/O pads

Operating temperature range of −40 °C to +85 °C

Full-scan design with high fault coverage

Available in HVQFN32 lead-free and halogen-free package

3. Applications

Battery-operated device, for example:

Mobile phone

MP3 player

Personal Digital Assistant (PDA)

Communication device, for example:

Router

Modem

Digital camera

Mass storage device, for example:

Zip drive

Printer

Scanner

4. Ordering information

1. SoftConnect is a trademark of ST-Ericsson.

Table 1. Ordering information

Commercial

product code Package description Packing Minimum sellable

quantity

ISP1183BSTM HVQFN32; 32 terminals; body 5 × 5 × 0.85 mm 13 inch tape and reel non-dry pack 6000 pieces

ISP1183BSF A HVQFN32; 32 terminals; body 5 × 5 × 0.85 mm single tray non-dry pack 490 pieces

xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx

xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx

xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x

Product data sheet Rev. 04 — 29 September 2009 3 of 61

ISP1183

Low-power USB peripheral controller with DMA

5. Block diagram

Fig 1. Block diagram

004aaa288

1.5 kΩ

ISP1183

BUS

INTERFACE

ANALOG

Tx/Rx

3.3 V

VOLTAGE

REGULATOR

POWER-ON

RESET

MEMORY

MANAGEMENT

UNIT

INTEGRATED

RAM

MICRO-

CONTROLLER

HANDLER

ENDPOINT

HANDLER

6 MHz

XTAL2XTAL1

to and from USB

to and from

microcontroller

PLL

OSCILLATOR

BIT CLOCK

RECOVERY

ST-

Ericsson

SIE

SoftConnect

INT_N

internal

reset

3.3 V

WR_N

DATA[7:0]

VBUS

DMDP

VREG(3V3)

AGND

RESET_N

1.65 V to

3.6 V

LEVEL

SHIFTER

PADS

SUSPEND

WAKEUP

DMA

HANDLER

VDD(I/O)

DGND

VBUSDET_N

DREQ

DACK

VOUT3V3

48 MHz

12 MHz

2CS_N

RD_N

5, 22, 25

11 12

18, 30

19, 20,

23, 24,

26 to 29

Product data sheet Rev. 04 — 29 September 2009 4 of 61

ISP1183

Low-power USB peripheral controller with DMA

6. Pinning information

6.1 Pinning

6.2 Pin description

Fig 2. Pin configuration HVQFN32

004aaa433

ISP1183BSTM

ISP1183BSFA

Transparent top view

XTAL2

BUS

DD(I/O)

XTAL1 DATA0

DGND DATA1

RD_N VOUT3V3

WR_N DGND

CS_N DATA2

INT_N DATA3

AGND

REG(3V3)

VBUSDET_N

DREQ

DACK

RESET_N

SUSPEND

WAKEUP

DD(I/O)

DATA7

DATA6

DATA5

DATA4

DGND

8 17

7 18

6 19

5 20

4 21

3 22

2 23

1 24

terminal 1

index area

GND

(exposed die pad)

Table 2. Pin description

Symbol[1] Pin Type[2] Description

INT_N 1 O interrupt output; active LOW

3.3 V tolerant I/O pad

CS_N 2 I chip select input

3.3 V tolerant I/O pad

WR_N 3 I write strobe input

3.3 V tolerant I/O pad

RD_N 4 I rea d strobe input

3.3 V tolerant I/O pad

DGND 5 - digital ground supply

XTAL1 6 I crystal oscillator input (6 MHz); connect a fundamen tal

parallel-resonant cryst al or an external clock source (leave pin

XTAL2 unconnected)

XTAL2 7 O crystal oscillator output (6 MHz); connect a fundamental

parallel-resonant crystal; leave this pin open when using an

external clock source on pin XTAL1

VBUS 8IV

BUS sensing input and power supply input; see Section 7.11

DM 9 AI/O USB D− line connection (analog)

DP 10 AI/O USB D+ line connection (analog)

Product data sheet Rev. 04 — 29 September 2009 5 of 61

ISP1183

Low-power USB peripheral controller with DMA

AGND 11 - analog ground supply

VREG(3V3) 12 - regulated supply voltage (3.3 V ± 10 %) from the internal

regulator; used to connect a 0.1 μF decoupling capacitor and

pull-up resist or on pin DP

Remark: Cannot be used to supply external devices.

VBUSDET_

N13 O VBUS indicator output (active LOW); see Table 3

DREQ 14 O DMA request output (4 mA; programmable polarity, see

Table 21); signals to the DMA controller that the ISP118 3 wants

to start a DMA transfer

3.3 V tolerant I/O pad

DACK 15 I DMA acknowledge input (programmable polarity, see Table 21);

used by the DMA controller to signal the start of a DMA transfer

requested by the ISP1183; when not in use, connect this pin to

ground through a 10 kΩ resistor

When the RESET_N pin is LOW, ensure that the DACK and

WAKEUP pins are LOW. Otherwise, the device will enter test

mode.

3.3 V tolerant I/O pad

RESET_N 16 I reset input (Schmitt trigger); a LOW level produces an

asynchronous reset

When the RESET_N pin is LOW, ensure that the DACK and

WAKEUP pins are LOW. Otherwise, the device will enter test

mode.

3.3 V tolerant I/O pad

A0 17 I address input; selects command (A0 = HIGH) or data (A0 =

LOW)

3.3 V tolerant I/O pad

VDD(I/O) 18 - I/O power supply; add a decoupling capacitor of 0.1 μF (1.65 V to

3.6 V); see Section 7.11

DATA0 19 I/O data bit 0 input and output

bidirectional (4 mA), 3.3 V tolerant I/O pad

DATA1 20 I/O data bit 1 input and output

bidirectional (4 mA), 3.3 V tolerant I/O pad

VOUT3V3 21 - 3.3 V output voltage; internally connected to the regulator output;

connect to a decoupling capacitor of 0.1 μF

DGND 22 digital ground supply

DATA2 23 I/O data bit 2 input and output

bidirectional (4 mA), 3.3 V tolerant I/O pad

DATA3 24 I/O data bit 3 input and output

bidirectional (4 mA), 3.3 V tolerant I/O pad

DGND 25 - digital ground supply

DATA4 26 I/O data bit 4 input and output

bidirectional (4 mA), 3.3 V tolerant I/O pad

DATA5 27 I/O data bit 5 input and output

bidirectional (4 mA), 3.3 V tolerant I/O pad

Table 2. Pin description …continued

Symbol[1] Pin Type[2] Description

Product data sheet Rev. 04 — 29 September 2009 6 of 61

ISP1183

Low-power USB peripheral controller with DMA

[1] Symbol names ending with underscore N (for example, NAME_N) represent active LOW signals.

[2] I = input; O = output; I/O = input/output; AI/O = analog input/output.

DATA6 28 I/O data bit 6 input and output

bidirectional (4 mA), 3.3 V tolerant I/O pad

DATA7 29 I/O data bit 7 input and output

bidirectional (4 mA), 3.3 V tolerant I/O pad

VDD(I/O) 30 - I/O power supply; add a decoupling capacitor of 0.1 μF

WAKEUP 31 I wake-up input (edge triggered, LOW to HIGH); generates a

remote wake-up from the suspend state; when not in use,

connect this pin to ground through a 10 kΩ resistor

When the RESET_N pin is LOW, ensure that the DACK and

WAKEUP pins are LOW. Otherwise, the device will enter test

mode.

3.3 V tolerant I/O pad

SUSPEND 32 O suspend state indicator output (4 mA)

3.3 V tolerant I/O pad

GND exposed

die pad - ground supply; down bonded to the exposed die pad (heat sink);

to be connected to the DGND during the PCB layout

Table 2. Pin description …continued

Symbol[1] Pin Type[2] Description

Product data sheet Rev. 04 — 29 September 2009 7 of 61

ISP1183

Low-power USB peripheral controller with DMA

7. Functional description

The ISP1183 is a full-speed USB Peripheral Controller with up to 14 configurable

endpoints. It has a fast general-purpose parallel interface for communication with many

types of microcontrollers and microprocessors . It support s an 8-bit dat a bus with sep arate

address and data. The block diagram is given in Figure 1.

The ISP1183 has 2462 bytes of internal FIFO memory that is shared among enabled USB

endpoints. The type and FIFO size of each endpoint can individually be configured,

depending on the required packet size. Isochronous and bulk endpoints are

double-buffered for increased data throughput.

The ISP1183 requires two supply voltages. The core voltage is supplied from VBUS

through an internal regulator, which transforms +5.0 V to +3.3 V when VBUS is powered.

The I/O interface voltage is supplied from VDD(I/O), which can be 1.65 V to 3.6 V.

The ISP1183 operates on a 6 MHz oscillator frequency.

7.1 Analog transceiver

The transceiver is compliant with Universal Serial Bus Specification Rev. 2.0. It directly

interfaces to the USB cable through external termination resistors.

7.2 ST-Ericsson SIE

The ST-Ericsson Serial Interface En gine (SIE) imple ments th e full USB protocol layer. It is

completely hardwired for speed and needs no firmware intervention. The functions of this

block include: synchronization pattern recognition, parallel-to-serial con version, bit stuf fing

and de-stuffing, CRC checking and generation, Packet Identifier (PID) verification and

generation, address recognition, and handshake evaluation and generation.

7.3 MMU and integrated RAM

The Memory Management Unit (MMU) and the integrated RAM provide the conversion

between the USB speed (full-speed: 12 Mbit/s bursts) and the p arallel interface to the

microcontroller (maximum 11.1 MB/s). This allows the microcontroller to read and write

USB packets at its own speed.

7.4 SoftConnect

The connection to USB is accomplished by pulling pin DP (for full-speed USB devices) to

HIGH throug h a 1. 5 k Ω pull-up resistor. In the ISP1183, by default, the 1.5 kΩ pull-up

resistor is integrated on-chip. The connection is established by a co mmand sent from the

external or system microcontroller. This allows the system microcontroller to complete its

initialization sequence before deciding to establish connection with USB. Re-initialization

of the USB connection can also be performed without disconnecting the cable.

Remark: The tolerance of the internal resistors is 25 %. This is higher than the 5 %

tolerance specified by Universal Serial Bus Specification Rev. 2.0. The overall voltage

specification for the connection, however, can still be met with a good margin. The

decision to make use of this feature lies with the USB equipment designer.

Product data sheet Rev. 04 — 29 September 2009 8 of 61

ISP1183

Low-power USB peripheral controller with DMA

7.5 Bit clock recovery

The bit clock recovery circuit recovers the clock from the incoming USB data str eam using

a 4 × over-sampling principle. It can track jitter and frequency drift as specified in

Universal Serial Bus Specification Rev. 2.0.

7.6 Voltage regulator

A 5 V-to-3.3 V voltage regulator is integrated on-chip to supply the analog transceiver and

internal logic. This voltage is available at pin VREG(3V3) to supply an external 1.5 kΩ

pull-up resistor on pin DP. Alternatively , the ISP1 183 p rovides the SoftConnect technology

through an integrated 1.5 kΩ pull-up resistor (see Section 7.4).

7.7 PLL clock multiplier

A 6 MHz-to-48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip. This

allows for the use of a low-cost 6 MHz crystal, which also minimizes EMI. No external

components are required for the operation of the PLL.

7.8 PIO and DMA interfaces

A generic Parallel I/O (PIO) interface is defined for speed and ease-of-use. It also allows

direct interfacing to most mi crocontrolle rs. To a microco ntroller, the ISP1183 appears as a

memory device with an 8-bit data bus and a 1-bit address bus. The ISP1183 supports

non-multiplexed address and data buses.

The ISP1183 can also be configured as a Direct Memory Access (DMA) slave device to

allow more ef ficient data transfe r. One of the 14 endpoint FIFOs may directly transfer dat a

to or from the local shared mem ory. The DMA interface can independently be configured

from the PIO interface.

It can be directly interfaced to microprocessors or microcontrollers with an I/O supply

voltage as low as 1.65 V.

7.9 VBUS indicator

The ISP1183 indicates the availability of VBUS using th e VBUS p in. When VBUS is available

(at pin VBUS), pin VBUSDET_N will output LOW . When VBUS is not available (at pin VBUS),

pin VBUSDET_N will output HIGH. Pin VBUSDET_N will change from HIGH-to-LOW

level in approximately 2.5 ms to 3.5 ms. See Section 17.

7.10 Operation modes

The ISP1183 can be operated in several operation modes as given in Table 3.

Table 3. ISP1183 operation modes

Pin name Plug-out state Dead state Reset state Plug-in state Normal state

VBUS 0VX 5V5V5V

VDD(I/O) 1.8V 0V 1.8V 1.8V 1.8V

WAKEUP X X L L L

RESET_N X X L H H

INT_N H L[1] HH-

[2]

Product data sheet Rev. 04 — 29 September 2009 9 of 61

ISP1183

Low-power USB peripheral controller with DMA

[1] Not driven to LOW. There is, however, no current flow through pads because no I/O supply voltage is

available. Therefore, no potential will develop at the output.

[2] During the normal operation, when VBUS is available, pin SUSPEN D is LOW. If there is no activity on the

USB bus for 3 ms or more, a suspend interrupt is generated on pin INT_N. On receiving the suspend

interrupt, the external processor issues a GOSUSP command to the device. Once the GOSUSP command

is issued by the processor, the device starts to prepare itself to go to suspend mode. During suspend, to

reduce the power consumption, internal clocks can be shut d own. Once the device is completely ready to

go into suspend mode, it will assert pin SUSPEND to HIGH and go into suspend mode. The typical time

between the issuing of the GOSUSP command to the device and the device asserting pin SUSPEND to

HIGH is approximately 2 ms.

[3] Independent of the external reset. Depends only on the power-on reset.

[4] On connecting the USB cable (VBUS), pin VBUSDET_N will change from HIGH level to LOW level in

approximately 2.5 ms to 3.5 ms.

7.11 Power supply

The ISP1183 is powered from a single supply voltage, rang ing from 4.0 V to 5.5 V. An

integrated voltage regulator provides a 3.3 V supply voltage for the internal logic and the

USB transceiver. This voltage is available at pin VREG(3V3) to connect an external pull-up

resistor on USB connection pin DP. See Figure 3.

The ISP1183 can also be operated from a 3.0 V to 3.6 V supply, as shown in Figure 4. In

this case, the internal voltage regulator is disabled and pin VREG(3V3) must be connected

to VBUS. For details, see Section 17.

7.12 Crystal oscillator

The ISP1183 has a crystal oscillator designed for a 6 MHz parallel-resonant crystal

(fundamental). A typical circuit is shown in Figure 5. Alternatively, an external clock signal

of 6 MHz can be applied to input XTAL1, while leaving output XTAL2 open.

SUSPEND H L[1] LLL

VBUSDET_N H L[1] L[3] H→ L[4] L

DATA Hi-Z L[1] Hi-Z Hi-Z -

Table 3. ISP1183 operation modes …continued

Pin name Plug-out state Dead state Reset state Plug-in state Normal state

Fig 3. ISP118 3 with a 4.0 V to 5.5 V supply Fig 4. ISP1183 with a 3.0 V to 3.6 V supply

VBUS

VREG(3V3)

VDD(I/O)

ISP1183

004aaa295

4.0 V to 5.5 V

VDD(I/O) 1.65 V to 3.6 V

VOUT3V3

3.0 V to 3.6 V

004aaa296

VBUS

VREG(3V3)

VDD(I/O)

ISP1183 VDD(I/O)

VOUT3V3 8

Product data sheet Rev. 04 — 29 September 2009 10 of 61

ISP1183

Low-power USB peripheral controller with DMA

The 6 MHz oscillator frequency is multiplied to 48 MHz by an internal PLL.

In the suspend state, the crysta l oscillator and the PLL are switched off to save power.

The oscillator operation is controlled by using bit CLKRUN in the Hardware Configuration

7.13 Power-on reset

The ISP1183 has an internal Power-On Reset (POR) circuit. The clock signal normally

requires 3 ms to 4 ms to stabilize.

The triggering voltage of the POR circuit is 0.5 V nominal. A POR is automatically

generated when VDD(I/O) goes below the trigger voltage for a duration longer than 50 μs.

Fig 5. Typical oscillator circuit

6 MHz

18 pF

XTAL2

XTAL1

004aaa294

ISP1183 6

t1: clock is running

t2: registers are accessible

Fig 6. POR timing

004aaa390

t1t2

VDD(I/O)

0.5 V

0 V

≤ 350 ms 2 ms

POR

Product data sheet Rev. 04 — 29 September 2009 11 of 61

ISP1183

Low-power USB peripheral controller with DMA

A hardware reset disables all USB endpoints and clears all Endpoint Configuration

Registers (ECRs), except for the control endpoint that is fixed and always enabled.

Section 9.3 explains how to initialize and re-initialize endpoints.

8. Interrupts

Figure 8 shows the interrupt logic of the ISP1183. Each of the indicated USB events is

logged in a status bit of the Interrupt reg ister. Corresponding bits in the Interrupt Enable

Interrupts can be masked globally using bit INTENA of the Mode register (see Table 18).

The signaling mode of output INT_N is controlled by bit INTLVL of the Hardware

Configuration register (see Table 20). Default settings after reset is level mode. When

pulse mode is selected, a pulse of 166 ns is generated when the OR-ed combination of all

interrupt bits changes from logic 0 to logic 1.

Stable external clock available at A.

Fig 7. Clock with respect to th e external POR

POR

EXTERNAL CLOCK

004aaa365

Product data sheet Rev. 04 — 29 September 2009 12 of 61

ISP1183

Low-power USB peripheral controller with DMA

Bits SUSPND, RESET, RESUME, SP_EOT, EOT and SOF are cleared when the Interrupt

Endpoint Status register is read.

Bit BUSTATUS follows the USB bus status exactly, allowing firmware to get the current

bus status when reading the Interrupt register.

SETUP and OUT token inte rrupt s are g enerate d af ter the ISP1183 has acknowledged the

associated data packet. In bulk transfer mode, the ISP1183 will issue interrupts for every

ACK received for an OUT token or transmitted for an IN token.

In isochronous mode, an interrupt is issued on each packet transaction. Firmware is

responsible for timing synchronization with the host. This can be done using the Pseudo

Start-Of-Frame (PSOF) interrupt, enabled using bit IEPSOF in the Interrupt Enable

allows firmware to ke ep data transfer synchronized wi th the host. After three missed SOF

events, the ISP1183 will enter the suspend state.

An alternative way of handling the isochronous data transfer is to enable both the SOF

and PSOF interrupts, and disable the interrupt for each isochronous endpoint.

Fig 8. Interrupt logic

004aaa255

IERST

Interrupt

Enable register

IESUSP

IERESM

IESOF

IEP14

...

IEP0IN

IEP0OUT

Device Mode

INTENA

INTLVL

Hardware Configuration

PULSE

GENERATOR

INT_N

Interrupt register

RESET

SUSPND

RESUME

SOF

EP14

...

EP0IN

EP0OUT

RESET

reset interrupt source

suspend interrupt source

EPn interrupt source

(clear EPn interrupt; reading EPn

Status register will set this signal)

(clear SUSPEND interrupt; reading

Interrupt register will set this signal)

(clear RESET interrupt; reading

Interrupt register will set this signal)

Product data sheet Rev. 04 — 29 September 2009 13 of 61

ISP1183

Low-power USB peripheral controller with DMA

9. Endpoint description

Each USB device is logically composed of several independent endpoints. An endpoint

acts as a terminus of a communication flow between the host and the device. At design

time, each endpoint is assigned a unique number (endpoint identifier, see Table 4). The

combination of the device address (given by the host during enumeration), the endpoint

number, and the transfer direction allows each endpoint to be unique ly referenced.

The ISP1183 has 16 endpoints: endpoint 0 (control IN and OUT) plus 14 configurable

endpoints, which can individually be defined as interrupt, bulk or isochronous: IN or OUT.

Each enabled endpoint ha s an associa te d F IF O, which can be accessed either usin g th e

PIO or DMA interface.

9.1 Endpoint access

Table 4 lists endpoint access modes and programmability. All endpoint s support I/O mode

access. Endpoints 1 to 14 also support DMA access. FIFO DMA access is selected and

enabled through bits EPDIX[3:0] of the DMA Configuration register and bit DMAEN of the

DMA Function and Scratch register. A detailed description of the DMA opera tion is given

in Section 10.

[1] The total amount of FIFO storage allocated to enabled endpoints must not exceed 2462 bytes.

[2] IN: input for the USB host (ISP1183 transmits); OUT: output from the USB host (ISP1183 receives). The data flow direction is

determined by bit EPDIR in the Endpoint Configuration register.

9.2 Endpoint FIFO size

The FIFO size determines the maximum packet size that the hardware can support for a

given endpoint. Only enabled endpoints are allocated space in the shared FIFO storage,

disabled endpoints have zero bytes. Table 5 lists programmable FIFO sizes.

The following bits in the Endpoint Configuration Reg ister (ECR) affect FIFO allocation:

•Endpoint enable bit (FIFOEN)

•Size bits of an enabled endpoint (FFOSZ[3:0])

•Isochronous bit of an enab le d en dpoint (F F OIS O)

Remark: Register changes that affect the allocation of the shared FIFO storage among

endpoint s must not be ma de while valid d ata is present in any F IFO of enabled endp oint s.

Such changes will render all FIFO contents undefined.

Table 4. Endpoint access and p rogrammability

Endpoint

identifier FIFO size (bytes)[1] Double buffering I/O mode

access DMA mode

access Endpoint type

0 64 (fixed) no yes no control OUT[2]

0 64 (fixed) no yes no control IN[2]

1 to 14 programmable supported supported supported programmable

Product data sheet Rev. 04 — 29 September 2009 14 of 61

ISP1183

Low-power USB peripheral controller with DMA

Each programmable FIFO can independently be configured through its ECR. The total

physical size of all enabled endpoints (IN plus OUT), however, must not exceed

2462 bytes.

Table 6 shows an example of a configuration fitting in the maximum available space of

2462 bytes. The tota l number of logical bytes in the example is 1311. The physical storage

capacity used for double buffering is managed by the device hardware and is transparent

to the user.

9.3 Endpoint initialization

In response to standard USB request Set Interface, firmware must program all 16 ECRs

of the ISP1183 in sequence (see Table 4), whet he r en dpoints are ena ble d or not . Th e

hardware will then automatically allocate FIFO storage space.

If all endp oints have successfully been configured, firmware must return an empty packet

to the control IN endpoint to acknowledge success to the host. If there are errors in the

endpoint configuration, firmware must stall the control IN endpoint.

Table 5. Prog ramma bl e FIF O si ze

FFOSZ[3:0] Non-isochronous Isochronous

0000 8 bytes 16 bytes

0001 16 bytes 32 bytes

0010 32 bytes 48 bytes

0011 64 bytes 64 bytes

0100 reserved 96 bytes

0101 reserved 128 bytes

0110 reserved 160 bytes

0111 reserved 192 bytes

1000 reserved 256 bytes

1001 reserved 320 bytes

1010 reserved 384 bytes

1011 reserved 512 bytes

1100 reserved 640 bytes

1101 reserved 768 bytes

1110 reserved 896 bytes

1111 reserved 1023 bytes

Table 6. Memory configuration example

Physical size (bytes) Logical size (byte s ) Endpoint description

64 64 control IN (64-byte fixed)

64 64 control OUT (64-byte fixed)

2046 1023 double-buffered 1023-byte isochronous endpoint

16 16 16-byte interrupt OUT

16 16 16-byte interrupt IN

128 64 double-buffered 64-byte bulk OUT

128 64 double-buffered 64-byte bulk IN

Product data sheet Rev. 04 — 29 September 2009 15 of 61

ISP1183

Low-power USB peripheral controller with DMA

When reset by hardware or th rough th e USB bus, th e ISP1183 disables all endpoin ts and

clears all ECRs, except for the control endpoint, which is fixed and always enabled.

Endpoint in itialization can b e done at any time. It is, h owever, valid only after enumeration.

9.4 Endpoint I/O mode access

When an endpoint event occurs (a packet is transmitted or received), the associated

endpoint in terrupt bits (EPn) of the Interr upt Register (IR) are set by the SIE. Firmware

then responds to the interrupt and selects the endpoint for processing.

The endpoin t interrupt bit is cleared when the End point S t atus Register (ESR) is read. The

ESR also contains information on the status of the endpoint buffer.

For an OUT (= receive) endp oint, the pa cket length an d the p acket d at a can be read fro m

the ISP1183 by using the Read Buffer command. When the whole packet is read,

firmware sends a Clear Buffer command to enable the reception of new packets.

For an IN (= transm it) endpoint, the p acket length and data to be sent ca n be written to the

ISP1183 by using the Write Buffer command. When the whole packet is written to the

buf fer, firmware sends a Validate Buffer comma nd to enable dat a transmission to the host.

9.5 Special actions on control endpoints

Control endpoin ts require special firmwar e actions. The arrival of a SETUP p acket flushes

the IN buffer, and disables the Validate Buffer and Clear Buffe r commands for the control

IN and OUT endpoints. The microcontroller must re-enable these commands by sending

an Acknowledge Setup command to both control endpoints.

This ensures that the last SETUP packet stays in the buffer and that no packets can be

sent back to the host until the microcontr oller has explicitly ac knowledged that it has seen

the SETUP packet.

Product data sheet Rev. 04 — 29 September 2009 16 of 61

ISP1183

Low-power USB peripheral controller with DMA

10. DMA transfer

Direct Memory Access ( D MA) is a me th od to tra nsfer d ata from one lo ca tio n to ano ther in

a computer system, witho ut intervention of the CPU. Many implementations of DMA exist.

The ISP1183 supports two methods:

•8237 compatible mode: based on the DMA subsystem of the IBM personal

computers (PC, AT and all its successors and clones); this architecture uses the Intel

8237 DMA controller and has separate address spaces for memory and I/O

•DACK-only mode: based on the DMA implementation in some embedded RISC

processors, which has a single add ress space for both memory and I/O

The ISP1183 supports DMA transfer for all 14 configurable endpoints (see Table 4). Only

one endpoint can be selected at a time for DMA transfer. The DMA operation of the

ISP1183 can be interleaved with norma l I/O mo d e ac ces s to ot he r en dpoints.

The following features are supported:

•Single-cycle or burst transfers (up to 16 bytes per cycle)

•Programmable transfer direction (read or write)

•Programmable signal levels on pins DREQ and DACK

10.1 Selecting an endpoint for DMA transfer

The targe t endpoint for DMA access is selected through bits EPDIX[3:0] in the DMA

Configuration register, see Table 7. The transfer direction (read or write) is automatically

set by bit EPDIR in the associated ECR, to match the selected endpoint type (OUT

endpoint: read; IN endpoint: write).

Asserting input DACK automatically selects the endpoint specified in the DMA

Configuration register, regardless of the current endpoint used for the I/O mo de access.

Table 7. Endpoint selection for the DMA transfer

Endpoint identifier EPDIX[3:0] Transfer direction

EPDIR = 0 EPDIR = 1

1 0010 OUT: read IN: write

2 0011 OUT: read IN: write

3 0100 OUT: read IN: write

4 0101 OUT: read IN: write

5 0110 OUT: read IN: write

6 0111 OUT: read IN: write

7 1000 OUT: read IN: write

8 1001 OUT: read IN: write

9 1010 OUT: read IN: write

10 1011 OUT: read IN: write

11 1100 OUT: read IN: write

12 1101 OUT: read IN: write

13 1110 OUT: read IN: write

14 1111 OUT: read IN: write

Product data sheet Rev. 04 — 29 September 2009 17 of 61

ISP1183

Low-power USB peripheral controller with DMA

10.2 8237 compatible mode

8237 compatible DMA mode is selected by clearing bit DAKOLY in the Hardware

Configuration register (see Table 20). The pin functio ns for this mode are shown in

Table 8.

The DMA subsystem of an IBM-comp atible PC is based on the Intel 8237 DM A controller.

It operates as a ‘fly-by’ DMA controller: data is not stored in the DMA controller, but it is

transferred between an I/O port and a memory address. A typical example of the ISP1183

in 8237-compatible DMA mode is given in Figure 9.

The 8237 has two control signals for each DMA channel: DREQ (DMA request) and

DACK_N (DMA acknowledge). General control sign als are HRQ (hold request) and HLDA

(hold acknowledge). The bus operation is controlled using MEMR_N (memory read),

MEMW_N (memory write), IOR_N (I/O read) and IOW_N (I/O write).

The following example shows the steps that occur in a typical DMA transfer:

1. The ISP1183 receives a data packet in one of its endp oint FIFOs. The pa cket must be

transferred to memory address 1234h.

2. The ISP1183 asserts the DREQ signal requesting the 8237 for a DMA transfer.

3. The 8237 asks the CPU to release the bus by asserting the HRQ signal.

4. After completing the current instruction cycle, CPU places bus control signals

(MEMR_N, MEMW_N, IOR_N and IO W_N ) an d ad d ress line s in 3-s tate and as ser ts

HLDA to inform the 8237 that it has control of the bus.

5. The 8237 sets its address lines to 1234h and activates the MEMW_N and IOR_N

control signals.

6. The 8237 asserts DACK_N to inform the ISP1183 that it will start a DMA transfer.

Table 8. 8237 compatible mode: pin functions

Symbol Description I/O Function

DREQ DMA request O ISP1183 requests a DMA transfer

DACK DMA acknowledge I DMA controller confirms the transfer

RD_N read strobe I instructs the ISP1183 to put data on the bus

WR_N write strobe I instructs the ISP1183 to get data from the bus

Fig 9. ISP1183 in 8237-compatible DMA mode

DATA[7:0]

CPU

004aaa291

RAM

ISP1183

DMA

CONTROLLER

8237

DREQ

DACK

DREQ HRQ

HLDA

HRQ

HLDA

DACK_N

IOR_N

IOW_N

MEMR_N

MEMW_N

RD_N

WR_N

Product data sheet Rev. 04 — 29 September 2009 18 of 61

ISP1183

Low-power USB peripheral controller with DMA

7. The ISP1183 places the byte or word to be transferred on data bus lines because its

RD_N signal was asserted by the 8237.

8. The 8237 waits one DMA clock period and then de-asserts MEMW_N and IOR_N.

This latches and stores the byte or word at the desired memory location. It also

informs the ISP1183 that data on bus lines has been transferred.

9. The ISP1183 de-asserts the DREQ signal to indicate to the 8237 that DMA is no

longer needed. In single-cycle mode, this is done after each byte or word; in burst

mode following the last transferred byte or word of the DMA cycle.

10. The 8237 de-asserts the DACK_N output, indicating that the ISP1183 must stop

placing data on the bus.

11. The 8237 places bus control signals (MEMR_N, MEMW_N, IOR_N and IOW_N) and

address lines in 3-st ate and de -asser ts the HRQ signal, informing the CPU that it has

released the bus.

12. The CPU acknowledges control of the bus by de-asserting HLDA. After activating bus

control lines (MEMR_N, MEMW_N , IOR_ N an d IO W_ N) an d add re ss line s, th e CPU

resumes the execution of instructions.

For a typical bu lk transfer , the preced ing process is repeated 64 times, once for each byte.

After each byte, the Address register in the DMA controller is incremented and the byte

counter is decremented.

10.3 DACK-only mode

DACK-only DMA mode is selected by setting bit DAKOLY in the Hardware Configuration

example of the ISP118 3 in DACK- o nly DM A mode is given in Figure 10.

In DACK-only mode, the ISP1183 uses the DACK signal as data strobe. Input signals

RD_N and WR_N are ignored. This mode is used in CPU systems that have a single

address space for memory and I/O access. Such systems have no separate MEMW_N

and MEMR_N signals: the RD_N and WR_N signals are also used as memory data

strobes.

Table 9. DACK-only mode: pin functions

Symbol Description I/O Function

DREQ DMA request O ISP1183 requests a DMA transfer

DACK DMA acknowledge I DMA controller confirms the transfer; also functions

as data strobe

RD_N read strobe I not used

WR_N write strobe I not used

Product data sheet Rev. 04 — 29 September 2009 19 of 61

ISP1183

Low-power USB peripheral controller with DMA

10.4 EOT conditions

10.4.1 Bulk endpoints

A DMA transfer to or from a bulk endpoi nt can be terminated by any of the following

conditions (for bit names, see the DMA Function and Scratch register in Table 30 and the

DMA Configuration register in Table 32):

•The DMA transfer completes as programmed in the DMA Counter register

(CNTREN = 1).

•A short packet is received on an enabled OUT endpoint (SHORTP = 1).

•DMA operation is disabled by clearing bit DMAEN.

10.4.1.1 DMA Counter register

An End-Of-Transfer (EOT) from the DMA Counter register is enabled by setting

bit CNTREN in the DMA Configuration register. The ISP1183 has a 16-bit DMA Counter

(DMAEN = 1), the internal DMA counter is loaded with the value from the DMA Counter

counter, an EOT condition is generated and the DMA operation stops.

10.4.1.2 Short packet

Normally, the transfer byte count must be set though a control endpoint before any DMA

transfer occurs. When a short p acket has be en enab led as EOT indi cator ( SHORTP = 1),

the transfer size is determined by the presence of a short packet in data. This mechanism

permits the use of a fully autonomous data tr ansfer protocol.

When reading from an OUT endpoint, reception of a short packet at an OUT token will

stop the DMA operation after transferring the data bytes of this packet.

Fig 10. ISP1183 in DACK-only DMA mode

RAM

ISP1183 DMA

CONTROLLER CPU

DREQ

DACK HRQ

HLDA

HRQ

HLDA

DREQ_N

DACK_N

RD_N

WR_N

DATA[7:0]

004aaa292

Product data sheet Rev. 04 — 29 September 2009 20 of 61

ISP1183

Low-power USB peripheral controller with DMA

[1] The DMA transfer stops. No interrupt, however, is generated.

10.4.2 Isochronous endpoints

A DMA transfer to or from an isochronous endpoint can be terminated by any of the

following conditions (for bit names, see the DMA Function and Scratch register in Table 30

and the DMA Configuration register in Table 32):

•The DMA transfer completes as programmed in the DMA Counter register

(CNTREN = 1).

•DMA operation is disabled by clearing bit DMAEN.

Table 10. Summary of EOT conditions for a bulk endpoint

EOT condition OUT endpoint IN endpoint

DMA Counter register transfer comple te s as

programmed in the DMA

Counter register

transfer completes as

programmed in the DMA

Counter register

Short packet short packet is received and

transferred counter reaches zero in the

middle of the buffer

DMAEN bit in the DMA

Function and Scratch register DMAEN = 0[1] DMAEN = 0[1]

Table 11. Recommended EOT usage for isochronous endpoints

EOT condition OUT endpoint IN endpoint

DMA Counter register zero do not use preferred

Clear DMAEN bit preferred do not use

Product data sheet Rev. 04 — 29 September 2009 21 of 61

ISP1183

Low-power USB peripheral controller with DMA

11 . Suspend and resume

11.1 Suspend conditions

The ISP1183 detects a USB suspend status when a constant idle state is present on the

USB bus for more than 3 ms.

The bus-powered devices that are suspended must not consume more than 500 μA of

current. This is achieved by shutting down power to system components or supplying

them with a reduced voltage.

The steps leading up to the suspend status are:

1. On detecting a wake-up-to-suspend transition, the ISP1183 sets bit SUSPND in the

Interrupt register. This will generate an interrupt if bit IESUSP in the Interrupt Enable

2. When firmware detects a suspend conditi on, it must prepare all system components

for the suspend state:

a. All signals connected to the ISP1183 must enter appropriate states to meet the

power consumption requirement s of the suspend state.

b. All input pins of the ISP1183 must have a CMOS LOW or HIGH level.

3. In the interrupt service routine, firmware must check the current status of the USB

bus. When bit BUSTATUS in the Interrupt register is logic 0, the USB bus has left

suspend mode and the process must be aborted. Otherwise, the next step can be

executed.

4. To meet suspend current requirement s for a bus-powered device, internal clocks must

be switched off by clearing bit CLKRUN in the Hardware Configuration register.

5. When firmware has set and cleared bit GOSUSP in the Mode register, the ISP1183

enters the suspend state. In powered-off application, the ISP1183 asserts output

SUSPEND and switches off internal clocks after 2 ms.

Figure 11 shows a typical timing diagram.

Product data sheet Rev. 04 — 29 September 2009 22 of 61

ISP1183

Low-power USB peripheral controller with DMA

In Figure 11:

•A: indicates the point at which the USB bus enters the idle state.

•B: indicates resume condition, wh ich can be a 20 ms K-st ate on the USB bus, a HIGH

level on pin WAKEUP, or a LOW level on pin CS_N.

•C: indicates remote wake-up. The ISP1183 will drive a K-state on the USB bus for

10 ms after pin WAKEUP goes HIGH or pin CS_N goes LOW.

•D: after detecting the suspend interrupt, set and clear bit GOSUSP in the Mode

11.1.1 Powered-off application

Figure 12 shows a typical bus-powered modem application using the ISP1183. The

SUSPEND output switches off power to the microcontroller and other external circuits

during the suspend st ate. The ISP1183 is woken up through the USB bus (global resume)

or by the ring detection circuit on the telephone line.

Fig 11. Suspend and resume timing

004aaa359

INT_N

> 5 ms

suspend

interrupt

USB bus

GOSUSP

WAKEUP

SUSPEND

idle state

10 ms

K-state

> 3 ms

1.8 ms to 2.2 ms

0.5 ms to 3.5 ms

resume

interrupt

Fig 12. SUSPEND and WAKEUP signals in a powe red-off modem application

WAKEUP

8031

RST

RING DETECTION

ISP1183

USB

BUS

LINE

004aaa293

SUSPEND

Product data sheet Rev. 04 — 29 September 2009 23 of 61

ISP1183

Low-power USB peripheral controller with DMA

11.2 Resume conditions

A wake-up from the suspend state is initiated either by the USB host or by the application:

•USB host: drives a K-state on the USB bus (global resume).

•Application: remote wake-up through a HIGH level on input WAKEUP or a LOW

level on input CS_N (if enabled using bit WKUPCS in the Hardware Configuration

The steps of a wake-up sequence are:

1. The internal oscillator and the PLL multiplier are re-enabled. When stabilized, clock

signals are routed to all internal circuits of the ISP1183.

2. The SUSPEND output is de-asserted, and bit RESUME in the Interrupt register is set.

This will generate an interrupt if bit IERESUME in the Interrupt Enable register is set.

3. Maximum 15 ms after starting the wake-up sequence, the ISP1183 resumes its

normal functionality.

4. In case of a remote wake-up, the ISP1183 drives a K-state on the USB bu s for 10 ms.

5. Following the de-a sser tion of ou tp ut SUSPE ND, the application restores itself and

other system components to normal operating mode.

6. After wake-up, the internal registers of the ISP1183 are write-protected to prevent

corruption by inadvertent writing during power-up of external components. Firmware

must send an Unlock Device command to the ISP1183 to restore its full functionality.

For details, see Section 12.4.2.

11.3 Control bits in suspend and resume

Table 12. Summary of control bits

Interrupt SUSPND a transition from awake to the suspend state was detected

BUSTATUS monitors USB bus status (logic 1 = suspend); used when interrupt is serviced

RESUME a transition from suspend to the resume state was detected

Interrupt Enable IESUSP enables output INT_N to signal the suspend state

IERESUME enables output INT_N to signal the resume state

Mode SOFTCT enables SoftConnect pull-up resistor to the USB bus

GOSUSP a HIGH-to-LOW transition enables the suspend state

Hardware

Configuration EXTPUL sele cts internal (SoftConnect) or external pull-up resistor

WKUPCS enables wake -up on LOW level of input CS_N

Unlock all sending data AA37h unlocks internal registers for writing after a resume

Product data sheet Rev. 04 — 29 September 2009 24 of 61

ISP1183

Low-power USB peripheral controller with DMA

12. Commands and registers

The functions and r egisters of the ISP1183 are accessed using commands, which consist

of a command code, followed by optional data bytes (read or write action). An overview of

the available commands an d registers is given in Table 13.

A complete access consists of two phases:

1. Command phase: when address pin A0 = HIGH, the ISP1183 interprets the data on

the lower byte of bus pins D[7:0] as a command code. Commands without a data

phase are immediately executed.

2. Data phase (optional): when address pin A0 = LOW, the ISP1183 transfers the data

on the bus to or from a register or endpoint FIFO. Multi-b yte registers are accessed

least significant byte or word first.

Table 13. Command and register overview

Name Destination Code Transaction Reference

Initialization commands

Write Control OUT

Configuration Endpoint Configuration

Write Control IN Configuration Endpoint Configuration

Write Endpoint n Configuration

(n= 1to14) Endpoint Configuration

Read Control OUT

Configuration Endpoint Configuration

Read Control IN Confi guration Endpoint Configuration

Read Endpoint n Configuration

(n= 1to14) Endpoint Configuration

Write or read Device Address Address register B6h/B7h write or read 1 byte Section 12.1.2 on page 27

Write or read Mode register Mode register B8h/B9h write or read 1 byte Section 12.1.3 on page 28

Write or read Hardware

Configuration Hardware Configuration

2bytes Section 12.1.4 on page 28

Write or read Interrupt Enable

4bytes Section 12.1.5 on page 29

Reset Device resets all registers F6h - Section 12.1.6 on page 31

Product data sheet Rev. 04 — 29 September 2009 25 of 61

ISP1183

Low-power USB peripheral controller with DMA

Data flow commands

Write Control OUT Buffer illegal: endpoint is

read-only (00h) - Section 12.2.1 on page 31

Write Control IN Buffer FIFO endpoint 0 IN 01h N ≤ 64 bytes

Write Endpoint n Buffer (n =

1to14) FIFO endpoints 1 to 14 (IN

endpoints only) 02h to 0Fh isochronous: N ≤

1023 bytes

interrupt or bulk:

N≤ 64 bytes

Read Control OUT Buffer FIFO endpoint 0 OUT 10h N ≤ 64 bytes

Read Control IN Buffer illegal: endpoint is

write-only (11h) -

Read Endpoint n Buffer (n =

1to14) FIFO endpoints 1 to 14

(OUT endpoints on l y) 12h to 1Fh isochronous: N ≤

1023 bytes

interrupt or bulk:

N≤ 64 bytes

Stall Control OUT Endpoint endpoint 0 OUT 40h - Section 12.2.3 on page 33

Stall Control IN Endpoint endpoint 0 IN 41h -

Stall Endpoint n (n = 1 to 14) endpoints 1 to 14 42h to 4Fh -

Read Control OUT Status Endpoint Status register

endpoint 0 OUT 50h read 1 byte Section 12.2.2 on page 32

Read Control IN Status Endpoint Status register

endpoint 0 IN 51h read 1 byte

Read Endpoint n Status (n =

1to14) Endpoint Status register n

endpoints 1to14 52hto5Fh read 1byte

Validate Contro l OUT Buffer illegal : IN endpoints only[1] (60h) - Section 12.2.4 on page 33

Validate Control IN Buffer FIFO endpoint 0 IN 61h -

Validate Endpoint n Buffer (n =

1to14) FIFO endpoints 1 to 14 (IN

endpoints only)[1] 62hto6Fh -

Clear Control OUT Buffer FIFO endpoint 0 OUT 70h - Section 12.2.5 on page 34

Clear Control IN Buffer illegal[2] (71h) -

Clear Endpoint n Buffer (n =

1to14) FIFO endpoints 1 to 14

(OUTendpoints only)[2] 72hto7Fh -

Unstall Control OUT Endpoint endpoint 0 OUT 80h - Section 12.2.3 on page 33

Unstall Control IN Endpoint endpoint 0 IN 81h -

Unstall Endpoint n (n = 1 to 14) endpoints 1 to 14 82h to 8Fh -

Check Control OUT Status[3] Endpoint Status Image

Check Control IN Status[3] Endpoint Status Image

Check Endpoint n Status (n =

1to14)

[3] Endpoint Status Image

1to14

D2htoDFh read 1byte

Acknowledge Setup endpoint 0 IN and OUT F4h - Section 12.2.7 on page 35

Table 13. Command and register overview …continued

Name Destination Code Transaction Reference

Product data sheet Rev. 04 — 29 September 2009 26 of 61

ISP1183

Low-power USB peripheral controller with DMA

[1] Validating an OUT endpoint buffer causes unpredictable behavior of the ISP1183.

[2] Clearing an IN endpoint buffer causes unpredictable behavior of the ISP1183.

[3] Reads a copy of the Status register: executing this command does not clear any status bits or interrupt bits.

12.1 Initialization commands

Initialization commands are used dur ing the enumeration process of the USB network.

These commands are used to configure and enable embedde d endpoints. They also set

the USB assigned address of the ISP1183 and perform device reset.

12.1.1 Endpoint Configuration register (R/W: 30h to 3Fh/20h to 2Fh)

This command accesses the Endpoint Configuration Register (ECR) of the target

endpoint. It defines the endpoint type (isochronous or bulk/inter rupt), direction (OUT/IN),

FIFO size and buffering scheme. It also enables the endpoint FIFO. The register bit

allocation is shown in Table 14. A bus reset will disable all endpoints.

The allocation of FIFO memory takes place only after all 16 endpoints have been

configured in sequence (fro m endpoint 0 OUT to endpoint 14). Although control end points

have fixed configurations, they must be included in the initialization sequ en ce and

configured with their default values (see Table 4). Automatic FIFO allocation starts when

endpoint 14 is configured.

Remark: If any change is made to an end point configuration that affects th e allocated

memory (size, enable/disable), the FIFO memory contents of all endpoint s become

invalid. Therefore, all valid data must be removed from enabled endpoints before

changing the configuration.

Code: 20hto2Fh — write (control OUT, control IN, endpoints 1 to 14)

DMA commands

Write or read DMA Function

and Scratch register DMA Function and Scratch

2bytes Section 12.3.1 on page 35

Write or read DMA

Configuration DMA Configuration

2bytes Section 12.3.2 on page 36

Write or read DMA Counter DMA Counter register F2h/F3h write or read

2bytes Section 12.3.3 on page 36

General commands

Read Control OUT Error Code Error Code register

endpoint 0 OUT A0h read 1 byte Section 12.4.1 on page 37

Read Control IN Error Code Error Code register

endpoint 0 IN A1h read 1 byte

Read Endpoint n Error Code

(n= 1to14) Error Code register

endpoints 1to14 A2htoAFh read 1byte

Unlock Device all registers with write

access B0h write 2 bytes Section 12.4.2 on page 38

Read Frame Number Frame Number register B4h read 1 byte or

2bytes Section 12.4.3 on page 39

Read Chip ID Chip ID register B5h read 2 bytes Section 12.4.4 on page 39

Read Interrupt register Interrupt register C0h read 4 bytes Section 12.4.5 on page 40

Table 13. Command and register overview …continued

Name Destination Code Transaction Reference

Product data sheet Rev. 04 — 29 September 2009 27 of 61

ISP1183

Low-power USB peripheral controller with DMA

Code: 30hto3Fh — read (control OUT, control IN, endpoints 1 to 14)

Transaction — write or read 1 byte

[1] The reset value of the control OUT endpoint is fixed as 83h for the Endpoint Configuration register.

[2] The reset value of the control IN endpoint is fixed as C3h for the Endpoint Configuration register.

12.1.2 Address register (R/W: B7h/B6h)

This command sets the USB assigned address in the Address register and enables the

USB device. The Address register bit allocation is shown in Table 16.

A USB bus reset sets the device address to 00h (internally) and enables the device. The

value of the Address register (accessible by the microcontroller) is not altered by the bus

reset. In response to the standard USB request (Set Address), fir mware must issue a

Write Device Address command, followed by sending an empty packet to the host. The

new device address is activated when the host acknowledges the empty packet.

Code: B6h/B7h — write or read Address register

Transaction — write or read 1 byte

Table 14. Endpoint Configuration register: bit allocation

Bit 76543210

Symbol FIFOEN EPDIR DBLBUF FFOISO FFOSZ[3:0]

Reset[1][2] 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 15. Endpoint Configuration re gister: bit descriptio n

Bit Symbol Description

7 FIFOEN Logic 1 indicates an enabled FIFO with allocated memory . Logic 0 indicates

a disabled FIFO (no bytes allocated).

6 EPDIR This bit defines the endpoint direction (0 = OUT, 1 = IN). It also determines

the DMA transfer direction (0 = read, 1 = write).

5 DBLBUF Logic 1 in dicates that this endpoint has double buffering.

4 FFOISO Logic 1 indicates an isochronous endpoint. Logic 0 indicates a bulk or

interrupt endpoint.

3 to 0 FFOSZ[3:0] This field specifies the FIFO size according to Table 5.

Table 16. Address register: bit allocatio n

Bit 76543210

Symbol DEVEN DEVADR[6:0]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 17. Address register: bit description

Bit Symbol Description

7 DEVEN Logic 1 enables the device.

6 to 0 DEVADR[6:0] This field specifies the USB device address.

Product data sheet Rev. 04 — 29 September 2009 28 of 61

ISP1183

Low-power USB peripheral controller with DMA

12.1.3 Mode register (R/W: B9h/B8h)

This command accesses the ISP1183 Mode register, which consists of 1 byte (bit

allocation: see Table 18). In 16-bit bus mode, the upper byte is ignored.

The Mode register controls the DMA bus width, resume and suspen d modes, interrupt

activity and SoftConnect operation. It can be used to enable debug mode, in which all

errors and Not Acknowledge (NAK) conditions will generate an interrupt.

Code: B8h/B9h — write or read Mode register

Transaction — write or read 1 byte

[1] Unchanged by a bus reset.

12.1.4 Hardware Configuration register (R/W: BBh/BAh)

This command accesses the Hardware Configuration register that consists of 2 bytes.

The first (lower) byte contains the device configuratio n and control values, the second

(upper) byte holds clock control bits and the clock division factor. The bit allocation is

given in Table 20. A bus reset will not change any of the programmed bit values.

The Hardware Configuration register controls the connection to the USB bus, clock

activity and power supply during the suspend state, output clock frequency, DMA

operating mode and pin configurations (polarity, signaling mode).

Code: BAh/BBh — write or read Hardware Configuration register

Transaction — write or read 2 bytes

Table 18. Mode register: bit allocation

Bit 76543210

Symbol reserved reserved GOSUSP reserved INTENA DBGMOD reserved SOFTCT

Reset 0[1] 0000

[1] 0[1] 0[1] 0[1]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 19. Mode register: bit description

Bit Symbol Description

7 reserved This bit should be always written as logic 0.

6 - reserved

5 GOSUSP Writing logic 1, followed by logic 0 will activate suspend mode.

4 - reserved

3 INTENA Logic 1 enables all interrupts. Bus reset value: unchanged .

2 DBGMOD Logic 1 enables debug mode, in which all NAKs and errors will

generate an interrupt. Logic 0 selects normal operation, in which

interrupts are generated on every ACK (bulk endpoints) or af ter every

data transfer (isochronous endpoints). Bus reset value: unchanged.

1 - reserved

0 SOFTCT Logic 1 enables SoftConnect (see Section 7.4). This bit is ignore d if

EXTPUL = 1 in the Hardware Configuration register (see Table 20).

Bus reset value: unchanged.

Product data sheet Rev. 04 — 29 September 2009 29 of 61

ISP1183

Low-power USB peripheral controller with DMA

12.1.5 Interrupt Enable register (R/W: C3h/C2h)

This command individually enable s or disables interrupts from all endpoints, as well as

interrupts caused by events on the USB bus (SOF, SOF lost, EOT, suspend, resume,

reset). A bus reset will not change any of the programmed bit values.

The command accesses the Interrupt Enable register that consists of 4 bytes. The bit

allocation is given in Table 22.

Code: C2h/C3h — write or read Interrupt Enable register

Table 20. Hardware Configuration register: bit allocation

Bit 15 14 13 12 11 10 9 8

Symbol reserved EXTPUL reserved CLKRUN reserved

Reset 00100011

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 7 6 5 4 3 2 1 0

Symbol DAKOLY DRQPOL DAKPOL reserved WKUPCS reserved INTLVL reserved

Reset 01000100

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 21. Hardware Configuration register: bit description

Bit Symbol Description

15 - reserved

14 EXTPUL Logic 1 indicates that an external 1.5 kΩ pull-up resistor is used on pin DP

and that SoftConnect is not used. Bus reset value: unchanged.

13 - reserved

12 CLKRUN Logic 1 indicates that internal clocks are always running, even during the

suspend state. Logic 0 switches off the internal oscillator and PLL, when

they are not needed. During th e suspend state, this bit must be made

logic 0 to meet suspend current requirements. The clock is stopped after a

delay of approximately 2 ms, following the setting of bit GOSUSP in the

Mode register. Bus reset value: unchanged.

11 to 8 - reserved

7 DAKOLY Logic 1 selects DACK-only DMA mode. Logic 0 selects 8237 compatible

DMA mode. Bus reset value: unchanged.

6 DRQPOL Selects the DREQ signal polarity (0 = active LOW, 1 = active HIGH). Bus

reset value: unchanged.

5 DAKPOL Selects the DACK signal polarity (0 = active LOW, 1 = active HIGH). Bus

reset value: unchanged.

4 reserved This bit should be always written as logic 0.

3 WKUPCS Logic 1 enables remote wake-up through a LOW level on input CS_N (For

wake-up on CS_N to work, VBUS must be present). Bus reset value:

unchanged.

2 - reserved

1 INTL VL Selects interrupt signaling mode on output INT_N (0 = level, 1 = pulsed). In

pulsed mode, an interrupt produces 166 ns pulse. For details, see

Section 11. Bus reset value: unchanged.

0 reserved This bit should be always written as logic 0.

Product data sheet Rev. 04 — 29 September 2009 30 of 61

ISP1183

Low-power USB peripheral controller with DMA

Transaction — write or read 4 bytes

Table 22. Interrupt Enable register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol reserved

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 23 22 21 20 19 18 17 16

Symbol IEP14 IEP13 IEP12 IEP11 IEP10 IEP9 IEP8 IEP7

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 15 14 13 12 11 10 9 8

Symbol IEP6 IEP5 IEP4 IEP3 IEP2 IEP1 IEP0IN IEP0OUT

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 7 6 5 4 3 2 1 0

Symbol reserved SP_IEEOT IEPSOF IESOF IEEOT IESUSP IERESM IERST

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 23. Interrupt Enable register: bit description

Bit Symbol Description

31 to 24 - reserved; must write logic 0

23 IEP14 Logic 1 enables in terrupts from endpoint 14.

22 IEP13 Logic 1 enables in terrupts from endpoint 13.

21 IEP12 Logic 1 enables in terrupts from endpoint 12.

20 IEP11 Logic 1 enables interrupts from endpoint 11.

19 IEP10 Logic 1 enables in terrupts from endpoint 10.

18 IEP9 Logic 1 enables interrupts from endpoint 9.

17 IEP8 Logic 1 enables interrupts from endpoint 8.

16 IEP7 Logic 1 enables interrupts from endpoint 7.

15 IEP6 Logic 1 enables interrupts from endpoint 6.

14 IEP5 Logic 1 enables interrupts from endpoint 5.

13 IEP4 Logic 1 enables interrupts from endpoint 4.

12 IEP3 Logic 1 enables interrupts from endpoint 3.

11 IEP2 Lo gic 1 enables interrupts from endpoint 2.

10 IEP1 Logic 1 enables interrupts from endpoint 1.

9 IEP0IN Logic 1 enables interrupts from the control IN endpoint.

8 IEP0OUT Logic 1 enables interru pts from the control OUT endpoint.

7- reserved

6 SP_IEEOT Logic 1 enables interrupt on detection of a short packet.

5 IEPSOF Logic 1 enables 1 m s interrupts on detection of pseudo SOF.

4 IESOF Logic 1 enables interrupt on SOF detection.

3 IEEOT Logic 1 enables interrupt on EOT detection.

Product data sheet Rev. 04 — 29 September 2009 31 of 61

ISP1183

Low-power USB peripheral controller with DMA

12.1.6 Reset Device (F6h)

This command resets the ISP1183 in the same way as an external hardware reset

through input RESET_N. All registers are initialized to their reset values.

Code: F6h — reset the device

Transaction — none

12.2 Data flow commands

Data flow command s are used to manage the data transmission between USB endpoints

and the system microcontroller. Much of the data flow is initiated throug h an inte rr up t to

the microcontroller. Data flow commands are used to access endpoints and determine

whether endpoint FI F Os co ntain valid da ta.

Remark: The IN buffer of an endpoint contains input data for the host. The OUT buffer

receives output data from the ho st.

12.2.1 Endpoint Buffer (R/W: 10h, 12h to 1Fh/01h to 0Fh)

This command accesses endpoint FIFO buffers for reading or writing. First, the buffer

pointer is reset to the beginning of the buffer. Following the command, a maximum of

(N + 2) bytes can be written or read, N represe nting the size of the endpoint buffer. After

each read or write action, the buffer pointer is automatically incremented by one (8-bit bus

width).

In DMA access, the first two bytes (the packet length) are skipped: transfers start at the

third byte of the endpoint buffer. When reading, the ISP1183 can detect the last byte

through the EOP condition. When writing to a bulk or interrupt endpoint, the endpoint

buffer must be completely filled before sending data to the host.

Remark: Reading data after a Write Endpoint Buffer command or writing data after a

Read Endpoint Buffer command data will caus e un pr ed ictable be ha vio r of the ISP118 3.

Code: 01hto0Fh — write (control IN, endpoints 1 to 14)

Code: 10h, 12h to 1Fh — read (control OUT, endpoints 1 to 14)

Transaction — write or read maximum (N + 2) bytes (isochronous endpoint: N ≤1023,

bulk or interrupt endpoint: N ≤64)

The dat a in the endpoint FIFO must be organized as shown in Table 24. Examples of

endpoint FIFO access are given in Table 25.

2 IESUSP Logic 1 enables interrupt on detection of a suspend state.

1 IERESM Logic 1 enables interru pt on detection of a resume state.

0 IERST Logic 1 enables interrupt on detection of a bus reset.

Table 23. Interrupt Enable register: bit description …continued

Bit Symbol Description

Product data sheet Rev. 04 — 29 September 2009 32 of 61

ISP1183

Low-power USB peripheral controller with DMA

Remark: There is no protection against writing or reading past a bu ffer’s boundary,

against writing into an OUT bu ffer, or reading from an IN buf fer. Any of these actions could

cause an incorrect operation. Data residing in an OUT buf fer is meaningful only after a

successful transaction. Exception: during DMA access of a double-buffered endpoint, the

buffer pointer automatically points to the secondary buffer after reaching the end of the

primary buffer.

12.2.2 Endpoint Status register (R: 50h to 5Fh)

This command reads the status of an endpo int FIFO. The command accesses the

Endpoint Status register, the bit allocation of which is shown in Table 26. Reading the

Endpoint Status register will clear the interrupt bit set for the corresponding end point in the

Interrupt register (see Table 46).

All bits of the Endpoint Status re gister are read-only. Bit EPSTAL is controlled by the Stall

or Unstall commands and by the reception of a SETUP token (see Section 12.2.3).

Code: 50hto5Fh — read (control OUT, control IN, endpoints 1 to 14)

Transaction — read 1 byte

Table 24. Endpoi nt FIF O orga n iza tio n

Byte # (8-bit bus) Description

0 packet length (lower byte)

1 packet length (upper byte)

2 data byte 1

3 data byte 2

(N + 1) data byte N

Table 25. Example of endpoint FIFO access

A0 Phase Bus lines Byte # Description

HIGH command D[7:0] - command code (00h to 1Fh)

LOW data D[7:0] 0 packet length (lower byte)

LOW data D[7:0] 1 packet length (upper byte)

LOW data D[7:0] 2 data byte 1

LOW data D[7:0] 3 data byte 2

LOW data D[7:0] 4 data byte 3

LOW data D[7:0] 5 data byte 4

:: : : :

Table 26. Endpoint Status register: bit allocation

Bit 76543210

Symbol EPSTAL EPFULL1 EPFULL0 DATA_PID OVER

WRITE SETUPT CPUBUF reserved

Reset 00000000

Access RRRRRRRR

Product data sheet Rev. 04 — 29 September 2009 33 of 61

ISP1183

Low-power USB peripheral controller with DMA

12.2.3 Stall or Unstall Endpoint (40h to 4Fh/80h to 8Fh)

These commands are used to stall or unstall an endpoint. The commands modify the

content of the Endpoin t Status register (see Table 26).

A stalled control endpoint is automatically unstalled when it receives a SETUP token,

regardless of the packet content. If the endpoint should sta y in its stalled state, the

microcontroller can re-stall it with the Stall Endpoint command.

When a stalled endpoint is unstalled (either by the Unstall Endpoint command or by

receiving a SETUP token), it is also re-initialized. This flushes the buffer: if it is an OUT

buffer, it waits for a DATA0 PID; if it is an IN buffer, it writes a DATA0 PID.

Code: 40hto4Fh — stall (control OUT, control IN, endpoints 1 to 14)

Code: 80hto8Fh — unstall (control OUT, control IN, endpoints 1 to 14)

Transaction — none

Remark: When unstalling a stalled endpoint, issue the unstall command two times. The

first unstall command will update the Endp oint Status register in RAM. The second unstall

command will reset buffer pointers.

12.2.4 Validate Endpoint Buffer (61h to 6Fh)

This command signals the presence of valid data for transmission to the USB host, by

setting the Buffer Full flag of the selected IN endpoint. This indicates that the data in the

buffer is valid and can be sent to th e host, when the next IN token is received. For a

double-buffered endpoint, this command switches the current FIFO for CPU access.

Remark: For special aspe cts of the cont ro l IN endpoint, see Section 9.5.

Table 27. Endpoint Status register: bit description

Bit Symbol Description

7 EPSTAL This bit indicates whether the endpoint is st alled or not (1 = stalled, 0 = not

stalled).

Set by a Stall Endpoint command. Cleared by an Unstall Endpoint

command. The endpoint is automatically unstalled on receiving a SETUP

token.

6 EPFULL1 Logic 1 indicates that the secondary endpoint buffer is full.

5 EPFULL0 Logic 1 indicates that the primary endpoint buffer is full.

4 DATA_PID This bit indicates the data PID of the next packet (0 = DATA0 PID, 1 =

DATA1 PID).

3 OVERWRITE This bit is set by hardware. Logic 1 indicates that a new set-up packet has

overwritten the previous set-up information, before it was acknowledged or

before the endpoint was stalled. This bit is cleared by reading, if writing the

set-up data has finished.

Firmware must check this bit before sending an Acknowledge Setup

command or stalling the endpoint. On reading logic 1, firmware must stop

ongoing set-up actions and wait for a new set-up packet.

2 SETUPT Logic 1 indicates that the buffer contains a set-up packet.

1 CPUBUF This bit indicates which buffer is currently selected for CPU access (0 =

primary buffer, 1 = secondary buffer).

0- reserved

Product data sheet Rev. 04 — 29 September 2009 34 of 61

ISP1183

Low-power USB peripheral controller with DMA

Code: 61hto6Fh — validate en dpoint buffer (con tr ol IN, endpoints 1 to 14)

Transaction — none

12.2.5 Clear Endpoint Buffer (70h, 72h to 7Fh)

This command unlocks and clears the buffer of the selected OUT endpoint, allowing the

reception of new packets. Reception of a complete packet causes the Buffer Full flag of an

OUT endpoint to be set. Any subsequent packets are refused by returning a NAK

condition, until the buffer is unlocked using this command. For a double-buffered

endpoint, this command switches the current FIFO for CPU access.

Remark: For special aspe cts of the control OUT endpoint , see Section 9.5.

Code: 70h, 72h to 7Fh — clear endpoint buffer (control OUT, endpoints 1 to 14)

Transaction — none

12.2.6 Check Endpoint Status (D0h to DFh)

This command checks the status of the selected endpoint FIFO without clearing any

status or interr upt bits. The comman d accesses the Endpoint Status Image reg ister , wh ich

contains a copy of the Endpoint Status register. The bit allocation of the Endpoint Status

Image register is shown in Table 28.

Code: D0h to DFh — check status (control OUT, control IN, endpoints 1 to 14)

Transaction — write or read 1 byte

Table 28. Endpoint Status Image register: bit allocation

Bit 76543210

Symbol EPSTAL EPFULL1 EPFULL0 DATA_PID OVER

WRITE SETUPT CPUBUF reserved

Reset 00000000

Access RRRRRRRR

Table 29. Endpoint Status Image regis t er: bit desc ription

Bit Symbol Description

7 EPSTAL This bit indicates whether the endpoint is stalled or not (1 = stalled, 0 =

not stalled).

6 EPFULL1 Logic 1 indicates that the secondary endpoint buffer is full.

5 EPFULL0 Logic 1 indica tes that the primary endpoint buffer is full.

4 DATA_PID This bit indicates the da ta PID of the next packet (0 = DATA0 PID, 1 =

DATA1 PID).

3 OVER

WRITE This bit is set by hardware. Logic 1 indicates that a new set-up packet

has overwritten the previous set-up information, before it was

acknowledged or before the endpoint was stalled. This bit is cleared by

reading, if writing the set-up data has finished.

Firmware must check this bit before sendi ng an Acknowledge Setup

command or stalling the endpoint. On reading logic 1, firmware must stop

ongoing set-up actions and wait for a new set-up packet.

Product data sheet Rev. 04 — 29 September 2009 35 of 61

ISP1183

Low-power USB peripheral controller with DMA

12.2.7 Acknowledge Setup (F4h)

This command acknowledges to the host that a SETUP packet was received. The arrival

of a SETUP packet disables the Validate Buffer and Clear Buffer commands for the

control IN and OUT endpoints. The microcontroller needs to re-en able these commands

by sending an Acknowledge Setup comm and, see Section 9.5.

Code: F4h — acknowledge setup

Transaction — none

12.3 DMA commands

12.3.1 DMA Function and Scratch register (R/W: B3h/B2h)

This command accesses the 16 -bit DMA Function and Scratch register, which can be

used by firmware to sav e an d rest or e inf or m ation. For example, the device status before

powering down in the suspend state. The register bit allocation is given in Table 30.

Code: B2h/B3h — write or read DMA Function and Scratch register

Transaction — write or read 2 bytes

2 SETUPT Logic 1 indi cates that the buffer contains a set-up packet.

1 CPUBUF This bit indicates which buffer is currently selected for CPU access (0 =

primary buffer, 1 = secondary buffer).

0 - reserved

Table 29. Endpoint Status Image regis t er: bit desc ription …continued

Bit Symbol Description

Table 30. DMA Function and Scratch register: bit allocation

Bit 15 14 13 12 11 10 9 8

Symbol DMAEN reserved SFIRH[4:0]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 7 6 5 4 3 2 1 0

Symbol SFIRL[7:0]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 31. DMA Function and Scratc h register: bit description

Bit Symbol Description

15 DMAEN Writing logic 1 enables DMA function.

14 to 13 - reserved; must be logic 0

12 to 8 SFIRH[4:0] Scratch Information register (high byte)

7 to 0 SFIRL[7:0] Scratch Information re gister (low byte)

Product data sheet Rev. 04 — 29 September 2009 36 of 61

ISP1183

Low-power USB peripheral controller with DMA

12.3.2 DMA Configuration register (R/W: F1h/F0h)

This command defines the DMA configuration of the ISP1183 and enables or disables

DMA transfers. The command accesses the DMA Configuration register, which consists

of 2 bytes. The bit allocation is given in Table 32. A bus reset will clear bit DMAEN (DMA

disabled), all other bits remain unchanged.

Code: F0h/F1h — write or read DMA Configuration

Transaction — write or read 2 bytes

[1] Unchanged by a bus reset.

12.3.3 DMA Counter register (R/W: F3h/F2h)

This command accesses the DMA Counter register, which consists of 2 bytes. The bit

allocation is given in Table 34. Writing to the register sets the number of bytes for a DMA

transfer. Reading the register returns the number of remaining bytes in the current

transfer. A bus reset will not change programmed bit values.

Table 32. DMA Configuration register: bit allocation

Bit 15 14 13 12 11 10 9 8

Symbol CNTREN SHORTP reserved

Reset 0[1] 0[1] 0[1] 0[1] 0[1] 0[1] 0[1] 0[1]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 7 6 5 4 3 2 1 0

Symbol EPDIX[3:0] DMA

START reserved BURSTL[1:0]

Reset 0[1] 0[1] 0[1] 0[1] 000

[1] 0[1]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 33. DMA Configuration register: bit description

Bit Symbol Description

15 CNTREN Logic 1 enables the generation of an EOT condition, when the DMA

Counter register reaches zero. Bus reset value: unchanged.

14 SHORTP Logic 1 enables short or empty packet mode. When receiving (OUT

endpoint) a short or empty packet, an EOT condition is generated. When

transmitting (IN endpoint), this bit should be cleared. Bus reset value:

unchanged.

13 to 8 - reserved

7 to 4 EPDIX[3:0] Indicates the destinati o n en dpoint for DMA, see Table 7.

3 DMASTART Writing logic 1 starts a DMA transfer. Logic 0 forces the end of an

ongoing DMA transfer . Reading this bit indicates whether DMA is started

(0 = DMA stopped, 1 = DMA started). This bit is cleared by a bus reset.

2- reserved

1 to 0 BURSTL[1:0] Selects the DMA burst length:

00 — single-cycle mode (1 byte)

01 — burst mode (4 bytes)

10 — burst mode (8 bytes)

11 — burst mode (16 bytes)

Bus reset value: unchanged.

Product data sheet Rev. 04 — 29 September 2009 37 of 61

ISP1183

Low-power USB peripheral controller with DMA

The internal DMA counter is automatically reloaded from the DMA Counter register when

DMA is re-enabled (DMAEN = 1). For details, see Section 12.3.2.

Code: F2h/F3h — write or read DMA Counter register

Transaction — write or read 2 bytes

12.4 General commands

12.4.1 Endpoint Error Code (R: A0h to AFh)

This command return s the status of the last tran saction of the selected endpoint, as stor ed

in the Error Code register. Each new transaction overwrites the previous status

information. The bit allocation of the Error Code register is shown in Table 36.

Code: A0h to AFh — read error code (control OUT, control IN, endpoints 1 to 14)

Transaction — read 1 byte

Table 34. DMA Counter register: bit allocation

Bit 15 14 13 12 11 10 9 8

Symbol DMACRH[7:0]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 7 6 5 4 3 2 1 0

Symbol DMACRL[7:0]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 35. DMA Counter register: bit description

Bit Symbol Description

15 to 8 DMACRH[7:0] DMA Counter register (high byte)

7 to 0 DMACRL[7:0] DMA Counter register (low byte)

Table 36. Error Code register: bit allocation

Bit 76543210

Symbol UNREAD DATA01 reserved ERROR[3:0] RTOK

Reset 00000000

Access RRRRRRRR

Table 37. Error Code register: bit description

Bit Symbol Description

7 UNREAD Logic 1 indicates that a new even t occurred before the previous status

was read.

6 DATA01 This bit indicates the PID type of the last successfully received or

transmitted packet (0 = DATA0 PID, 1 = DATA1 PID).

5 - reserved

4 to 1 ERROR[3:0] Error code. For error description, see Table 38.

0 RTOK Logic 1 indicates that data was successfu lly received or transmitted.

Product data sheet Rev. 04 — 29 September 2009 38 of 61

ISP1183

Low-power USB peripheral controller with DMA

12.4.2 Unlock Device (B0h)

This command unlocks the ISP1183 from write-protection mode after a resume. In the

suspend state, all registers and FIFOs are write-protect ed to pr ev en t da ta corrup tio n by

external device s du rin g a resum e . Also, the register access for reading is possible only

afte r the Unlock Device command is executed.

After waking up from the suspend state, firmware must unlock registers and FIFOs using

this command, by writing the unlock code (AA37h) into the Lock register (8-bit bus: lower

byte first). The bit allocation of the Lock register is given in Table 39.

Code: B0h — unlock the device

Transaction — write 2 bytes (unlock code)

Table 38. Transaction error codes

Error code

(binary) Description

0000 no error

0001 PID encoding error; bits 7 to 4 are not the inverse of bits 3 to 0

0010 PID unknown; encoding is valid, but PID does not exist

0011 unexpected packet; packet is not of the expected type (token, data, or

acknowledge), or is a SETUP token to a non-control endpoint

0100 token CRC error

0101 data CRC error

0110 time-out error

0111 babble error

1000 unexpected end-of-packet

1001 sent or received NAK (Not AcKnowledge)

1010 sent stall; a token was received, but the endpoint was stalled

1011 overflow; the received packet was larger than the available buffer space

1100 sent empty packet (ISO only)

1101 bit stuffing error

1110 sync error

1111 wrong (unexpected) toggle bit in DATA PID; data was ignored

Table 39. Lock register: bit allocation

Bit 15 14 13 12 11 10 9 8

Symbol UNLOCKH[7:0] = AAh

Reset 10101010

Access WWWWWWWW

Bit 7 6 5 4 3 2 1 0

Symbol UNLOCKL[7:0] = 37h

Reset 00110111

Access WWWWWWWW

Product data sheet Rev. 04 — 29 September 2009 39 of 61

ISP1183

Low-power USB peripheral controller with DMA

12.4.3 Frame Number register (R: B4h)

This command returns the frame nu mber of the last successfully received SOF. It is

followed by reading one or two bytes from the Frame Number register, containing the

frame number (lower byte first). The Frame Number register is shown in Table 41.

Remark: After a bus reset, the value of the Frame Number register is undefined.

Code: B4h — read frame number

Transaction — read 1 byte or 2 byte s

[1] Reset value undefined after a bus reset.

12.4.4 Chip ID register (R: B5h)

This command reads th e chip identification code a nd hardware version numb er. Firmware

must check this info rm at ion to de te rm ine s upp or te d fu nct ion s an d fe at ur es. This

command accesses the Chip ID register, which is shown in Table 44.

Code: B5h — read chip ID

Transaction — read 2 bytes

Table 40. Lock register: bit description

Bit Symbol Description

15 to 0 UNLOCK[15:0] Sending data AA37h unlocks internal registers and FIFOs for writing,

following a resume.

Table 41. Frame Number register: bit allocation

Bit 15 14 13 12 11 10 9 8

Symbol reserved SOFRH[2:0]

Reset 00000000

Access RRRRRRRR

Bit 7 6 5 4 3 2 1 0

Symbol SOFRL[7:0]

Reset[1] 00000000

Access RRRRRRRR

Table 42. Frame Number register: bit desc ription

Bit Symbol Description

15 to 11 - reserved

10 to 8 SOFRH[2:0] SOF frame number (u pper byte)

7 to 0 SOFRL[7:0] SOF frame number (lower byte)

Table 43. Example of Frame Number register access

A0 Phase Bus lines Byte # Description

HIGH command D[7:0] - command code (B4h)

LOW data D[7:0] 0 frame number (lower byte)

LOW data D[7:0] 1 frame number (upper byte)

Product data sheet Rev. 04 — 29 September 2009 40 of 61

ISP1183

Low-power USB peripheral controller with DMA

12.4.5 Interrupt register (R: C0h)

This command in dicates the sources of interrupt s as stored in the 4- byte Interrupt register .

Each individual endp oint has its own interrupt bit. The bit allocation of the Interrup t register

is shown in Table 46. Bit BUSTATUS verifies the current bus st atus in th e interrupt service

routine. Interrupts are enabled through the Interrupt Enable register, see Section 12.1.5.

While reading the interrupt register, read all the 4 bytes completely.

Code: C0h — read Interrupt register

Transaction — read 4 bytes

[1] The reset value of this bit depends on the current USB bus status. If the bus is idle, the reset value will be 1.

Table 44. Chip ID register: bit allocation

Bit 15 14 13 12 11 10 9 8

Symbol CHIPIDH[7:0]

Reset 82h

Access RRRRRRRR

Bit 7 6 5 4 3 2 1 0

Symbol CHIPIDL[7:0]

Reset 11h

Access RRRRRRRR

Table 45. Chip ID register: bit description

Bit Symbol Description

15 to 8 CHIPIDH[7:0] chip ID code (82h)

7 to 0 CHIPIDL[7:0] silicon version (11h)

Table 46. Interrupt register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol reserved

Reset 00000000

Access RRRRRRRR

Bit 23 22 21 20 19 18 17 16

Symbol EP14 EP13 EP12 EP11 EP10 EP9 EP8 EP7

Reset 00000000

Access RRRRRRRR

Bit 15 14 13 12 11 10 9 8

Symbol EP6 EP5 EP4 EP3 EP2 EP1 EP0IN EP0OUT

Reset 00000000

Access RRRRRRRR

Bit 7 6 5 4 3 2 1 0

Symbol BUSTATUS SP_EOT PSOF SOF EOT SUSPND RESUME RESET

Reset 0[1] 0000000

Access RRRRRRRR

Product data sheet Rev. 04 — 29 September 2009 41 of 61

ISP1183

Low-power USB peripheral controller with DMA

Table 47. Interrupt register: bit description

Bit Symbol Description

31 to 24 - reserved

23 EP14 Logic 1 indicates the interrupt source: endpoint 14.

22 EP13 Logic 1 indicates the interrupt source: endpoint 13.

21 EP12 Logic 1 indicates the interrupt source: endpoint 12.

20 EP11 Logic 1 indicates the interrupt source: endpoint 11.

19 EP10 Logic 1 indicates the interrupt source: endpoint 10.

18 EP9 Logic 1 indicates the interrupt source: endpoint 9.

17 EP8 Logic 1 indicates the interrupt source: endpoint 8.

16 EP7 Logic 1 indicates the interrupt source: endpoint 7.

15 EP6 Logic 1 indicates the interrupt source: endpoint 6.

14 EP5 Logic 1 indicates the interrupt source: endpoint 5.

13 EP4 Logic 1 indicates the interrupt source: endpoint 4.

12 EP3 Logic 1 indicates the interrupt source: endpoint 3.

11 EP2 Logic 1 indicates the interrupt source: endpoint 2.

10 EP1 Logic 1 indicates the interrupt source: endpoint 1.

9 EP0IN Logic 1 indicates the interrupt source: control IN endpoint.

8 EP0OUT Logic 1 indicates the interrupt source: control OUT endpoint.

7 BUSTATUS It monitors the current USB bus status (0 = awake, 1 = suspend).

6 SP_EOT Logic 1 indicates that an EOT interrupt has occurred for a short packet.

5 PSOF Logic 1 indicates that an interrupt is issued every 1 ms because of the

pseudo SOF; after three missed SOFs, the suspend state is entered.

4 SOF Logic 1 indicates that a SOF condition was detected.

3 EOT Logic 1 indicates that an internal EOT condition was generated by the

DMA counter reaching zero.

2 SUSPND Logic 1 indicates that an awake to suspend change of state was detected

on the USB bus.

1 RESUME Logic 1 indicates that a resume state was detected.

0 RESET Logic 1 in dicates that a bus reset condition was detected.

Product data sheet Rev. 04 — 29 September 2009 42 of 61

ISP1183

Low-power USB peripheral controller with DMA

13. Limiting values

[1] Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor (Human Body Model).

14. Recommended operating conditions

Table 48. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VBUS bus supply voltage −0.5 +6.0 V

VDD(I/O) I/O supply voltage −0.5 +4.6 V

VIinput voltage digital −0.5 VDD(I/O) + 0.5 V

Ilu latch-up current VI< 0 V or VI> VBUS -100 mA

Vesd electrostatic discharge voltage ILI < 1 μA[1] −2000 +2000 V

Tstg storage temperature −60 +150 °C

Ptot total power dissipation VBUS = 5.5 V - 100 mW

Table 49. Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

VBUS bus supply voltage with regulator 4.0 5.0 5.5 V

VDD(I/O) I/O supply voltage 1.65 - 3.6 V

VIinput voltage 0 - VDD(I/O) V

VO(I/O) output I/O voltage 0 - VDD(I/O) V

VI(AI/O) input voltage on analog I/O

pins DP and DM 0- 3.6V

VO(od) open-drain output pull-up voltage 0 - VBUS V

Tamb ambient temperature −40 - +85 °C

Product data sheet Rev. 04 — 29 September 2009 43 of 61

ISP1183

Low-power USB peripheral controller with DMA

15. Static characteristics

[1] For 3.3 V operation, pin VREG(3V3) must be connected to pin VBUS.

[2] In suspend mode, the minimum voltage is 2.7 V.

[3] External loading is not included.

Table 50. Static characteristics: supply pins

VBUS = 4.0 V to 5.5 V; VDD(I/O) = 1.65 V to 3.6 V; VGND = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

VREG(3V3) 3.3 volt regulator voltage VBUS = 4.0 V to 5.5 V [1][2] 3.0 3.3 3.6 V

ICC supply current VBUS = 5.0 V; Tamb = 25 °C- 19 - mA

ICC(susp) suspend supply current VBUS = 5.0 V; Tamb = 25 °C[3] - - 250 μA

Iref(static) VDD(I/O) static I/O supply current suspend or no VBUS -- 10μA

Iref VDD(I/O) operating I/O supply

current -- 3.5mA

Table 51. Static characteristics: digital pins

VBUS = 4.0 V to 5.5 V; VDD(I/O) = 1.65 V to 3.6 V; VGND = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

VIL(I/O) LOW-level input voltage - - 0.2VDD(I/O) V

VIH(I/O) HIGH-level input voltage 0.7VDD(I/O) -- V

VOL LOW-level output voltage - - 0.22VDD(I/O) V

VOH HIGH-level output voltage 0.8VDD(I/O) -- V

ILI input leakage curren t −1-+1 μA

Ciinput capacitance - - 10 pF

Ziinput impedance 2 - - MΩ

Product data sheet Rev. 04 — 29 September 2009 44 of 61

ISP1183

Low-power USB peripheral controller with DMA

[1] DP is the USB positive data pin; DM is the USB negative data pin.

[2] Pull-up resistance on DP.

[3] Includes external resistors of 22 Ω± 1 % on both DP and DM.

[4] This voltage is available at pin VREG(3V3).

[5] In suspend mode, the minimum voltage is 2.7 V.

Table 52. Static characteristics: analog I/O pins DP and DM

VBUS = 4.0 V to 5.5 V; VDD(I/O) = 1.65 V to 3.6 V; VGND = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.[1]

Symbol Parameter Conditions Min Typ Max Unit

Input levels

VDI differential input sensitivity |VI(DP) −VI(DM)|0.2--V

VCM differential common mode

voltage includes VDI range 0.8 - 2.5 V

VIL LOW-level input voltage - - 0.8 V

VIH HIGH-level input voltage 2.0 - - V

Output levels

VOL LOW-level output voltage RL= 1.5 kΩ to +3.6 V - - 0.3 V

VOH HIGH-level output voltage RL= 15 kΩ to ground 2.8 - 3.6 V

Leakage current

ILZ OFF-state leakage current −10 - +10 μA

Capacitance

CIN transceiver capacitance pin to ground - - 2 0 pF

Resistance

RPU pull-up resistance SoftConnect = on [2] 1- 2kΩ

ZDRV driver output impedance steady-state drive [3] 29 - 44 Ω

ZINP input impedance 10 - - MΩ

Termination

VTERM termination voltage for

upstrea m fa ci ng po rt pu ll-up RPU [4][5] 3.0 - 3.6 V

Product data sheet Rev. 04 — 29 September 2009 45 of 61

ISP1183

Low-power USB peripheral controller with DMA

16. Dynamic characteristics

[1] Dependent on the crystal oscillator start-up time.

[1] Test circuit: see Figure 27.

[2] Excluding the first transition from Idle state.

[3] Characterized only, not tested. Limits guaranteed by design.

Table 53. Dynamic characteristics

VBUS = 4.0 V to 5.5 V; VDD(I/O) = 1.65 V to 3.6 V; VGND = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Reset

tW(RESET_N) external RESET_N pulse width crystal oscillator running 5 0 - - μs

crystal oscillator stopped [1] -3-ms

Crystal oscillator

fXTAL1 frequency on pi n XTAL1 - 6 - MHz

Table 54. Dynamic characteristics: analog I/O p ins DP and DM

VBUS = 4.0 V to 5.5 V; VDD(I/O) = 1.65 V to 3.6 V; VGND = 0 V; Tamb = −40 °C to +85 °C; CL= 50 pF; RPU = 1.5 kΩ on DP to

VTERM; unless otherwise specified.[1]

Symbol Parameter Conditions Min Typ Max Unit

Driver characteristics

tFR rise time CL= 50 pF ; 10 % to

90 % of |VOH − VOL|

4- 20ns

tFF fall time CL= 50 pF; 90 % to

10 % of |VOH − VOL|

4- 20ns

FRFM differential rise time/fall time

matching tFR/tFF [2] 90 - 111.11 %

VCRS output signal crossover volt age [2][3] 1.3 - 2.0 V

Data source timing

tFEOPT source SE0 interval of EOP [3] 160 - 175 ns

tFDEOP source jitter for differential

transition to SE0 transition [3] −2- +5ns

Receiver timing

tJR1 receiver jitter to next transition [3] −18.5 - +18.5 ns

tJR2 receiver jitter for paired

transitions [3] −9- +9ns

tFEOPR receiver SE0 interval of EOP accepted as EOP [3] 82--ns

tFST width of SE0 interval during

differential transition rejected as EOP [3] --14ns

Product data sheet Rev. 04 — 29 September 2009 46 of 61

ISP1183

Low-power USB peripheral controller with DMA

16.1 Timing

16.1.1 Parallel I/O timing

[1] The minimum value for data flow commands (see Table 13) is 180 ns.

Table 55. Dynamic character istics: parallel interface timing

VBUS = VREG(3V3) = 2.7 V to 3.9 V; VDD(I/O) = 1.8 V; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Read timing (see Figure 13)

tRHAX address hold time after RD_N HIGH CL= 30 pF 0 - - ns

tAVRL address setup time before RD_N LOW 0 - - ns

tRHDZ data outputs high-impedance time after

RD_N HIGH 0- -ns

tRHSH chip deselect time after RD_N HIGH −2- - ns

tRHRL RD_N LOW after RD_N HIGH 65 - - ns

tRLRH RD_N pulse width 25 - - ns

tSLRL CS_N time before RD_N LOW 0 - - ns

tRLDV data valid time after RD_N LOW - - 20 ns

tRC (tRHRL + tRLRH) read cycle time 90 - - ns

Write timing (see Figure 14)

tWHAX address hold time after WR_N HIGH 1 - - ns

tAVWL address setup time before WR_N LOW 0 - - ns

tSLWL CS_N time before WR_N LOW 0 - - ns

tWL (tWHWL +

tWLWH)write cycle time [1] 90/180 - - ns

tWLWH WR_N pulse width 22 - - ns

tWHWL WR_N LOW after WR_N HIGH [1] 68/158 - - ns

tWHSH chip deselect time after WR_N HIGH 0 - - ns

tDVWH data setup time before WR_N HIGH 2 - - ns

tWHDZ data hold time after WR_N HIGH 1 - - ns

Product data sheet Rev. 04 — 29 September 2009 47 of 61

ISP1183

Low-power USB peripheral controller with DMA

16.1.2 Access cycle timing

(1) If required, CS_N can be kept permanently asserted. There is no need to de-assert and assert in between the read and

write cycles.

Fig 13. Parallel interface read timing

004aaa256

tRHAX

tAVRL

tRLRH

tRLDV

tRHRL(1)

DATA

RD_N

CS_N

tRHSH

tSLRL

tRHDZ

(1) If required, CS_N can be kept permanently asserted. There is no need to de-assert and assert in between the read and

write cycles.

Fig 14. Parallel interface write timing

004aaa257

CS_N

DATA

WR_N

tWHAX

tAVWL

tWHDZ

tDVWH

tWLWH

tWHSH

tWHWL(1)

tSLWL

Table 56. Dynamic characteristics: access cycle timin g

VBUS = VREG(3V3) = 2.7 V to 3.9 V; VDD(I/O) = 1.8 V; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Write command + write data (see Figure 15 and Figure 16)

Tcy(WC-WD) cycle time for write command, then write data CL= 30 pF [1] 100 - - ns

Tcy(WD-WD) cycle time for write data 90 - - ns

Product data sheet Rev. 04 — 29 September 2009 48 of 61

ISP1183

Low-power USB peripheral controller with DMA

[1] The minimum value for data flow commands (see Table 13) is 180 ns.

Tcy(WD-WC) cycle time for write data, then write command 90 - - ns

Write command + read data (see Figure 17 and Figure 18)

Tcy(WC-RD) cycle time for write command, then read data [1] 100 - - ns

Tcy(RD-RD) cycle time for read data 90 - - ns

Tcy(RD-WC) cycle time for read data, then write command 90 - - ns

Table 56. Dynamic characteristics: access cycle timin g …continued

VBUS = VREG(3V3) = 2.7 V to 3.9 V; VDD(I/O) = 1.8 V; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Fig 15. Write command + write data cycle timing

(1) Example: read data.

Fig 16. Write data + write command cycle timing

Fig 17. Write command + read data cycle timing

004aaa425

Tcy(WC-WD) Tcy(WD-WD)

command

DATA

WR_N

datadata

CS_N

004aaa426

Tcy(WD-WC)

data

DATA

WR_N

datacommand

RD_N

CS_N

(1)

004aaa427

cy(WC-RD)

cy(RD-RD)

command

DATA

WR_N

datadata

RD_N

CS_N

Product data sheet Rev. 04 — 29 September 2009 49 of 61

ISP1183

Low-power USB peripheral controller with DMA

16.1.3 DMA timing: single-cycle mode

(1) Example: read data.

Fig 18. Read data + write command cycle timing

004aaa428

Tcy(RD-WC)

data

DATA

WR_N

data

(1)

command

RD_N

CS_N

Table 57. Dynamic characteristics: single-cycle DMA timing

VBUS = VREG(3V3) = 2.7 V to 3.9 V; VDD(I/O) = 1.8 V; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

8237 compatible mode (see Figure 19)

tASRP DREQ off after DACK on - 40 ns

Tcy(DREQ) cycle time signal DREQ 90 - ns

Read in DACK-only mode (see Figure 20)

tASRP DREQ off after DACK on - 40 ns

tASAP DACK pulse width 25 - ns

tASAP + tAPRS DREQ on after DACK off 90 - ns

tASDV data valid after DACK on - 22 ns

tAPDZ data hold after DACK off - 3 ns

Write in DACK-only mode (see Figure 21)

tASRP DREQ off after DACK on - 40 ns

tASAP + tAPRS DREQ on after DACK off 90 - ns

tDVAP data setup before DACK off 5 - ns

tAPDZ data hold after DACK off 3 - ns

Fig 19. DMA timing in 8237 compatible mode

004aaa429

DREQ

DACK

ASRP

cy(DREQ)

Product data sheet Rev. 04 — 29 September 2009 50 of 61

ISP1183

Low-power USB peripheral controller with DMA

16.1.4 DMA timing: burst mode

Fig 20. DMA read timing in DACK-only mode

004aaa430

DACK

DREQ

tASRP tAPRS

tASDV tAPDZ

DATA

tASAP

Fig 21. DMA write timing in DACK-only mode

004aaa431

DACK

DREQ

tASRP tAPRS

tDVAP tAPDZ

DATA

tASAP

Table 58. Dynamic characteristics: burst mode DMA timing

VBUS = VREG(3V3) = 2.7 V to 3.9 V; VDD(I/O) = 1.8 V; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Burst (see Figure 22)

tRSIH input RD_N or WR_N HIGH after DREQ on 22 - ns

tILRP DREQ off after input RD_N or WR_N LOW - 60 ns

tIHAP DACK off after input RD_N or WR_N HIGH 0 - ns

tIHIL DMA burst repeat interval (input RD_N or

WR_N HIGH to LOW) 90 - ns

Product data sheet Rev. 04 — 29 September 2009 51 of 61

ISP1183

Low-power USB peripheral controller with DMA

17. Application information

17.1 Bus-powered mode

In bus-powered mode, pin VBUSDET_N is not necessary. See Figure 23.

17.2 Hybrid-powered mode

In this mode:

•When the USB cable is pulled out, pin VBUSDET_N goes HIGH, thereby indicating to

the microcontroller that USB is disconnected. See Figure 24.

•When the USB cable is plugged in, pin VBUSDET_N goes LOW . This indi cates to the

microcontroller that the USB cable is plugged in. The microcontroller can then prepare

to reconfigure all re gis ter s of th e ISP118 3. See Figure 24.

Fig 22. Burst mod e DM A timing

004aaa432

DACK

DREQ

RSIH

ILRP

IHIL

IHAP

RD_N, WR_N

Fig 23. Bus-powered mode

004aaa451

MCU ISP1183

VBUS

VREG(3V3)

VDD(I/O) REGULATOR

VBUS

1.65 V to 3.6 V

VDD(I/O)

VCC

Product data sheet Rev. 04 — 29 September 2009 52 of 61

ISP1183

Low-power USB peripheral controller with DMA

17.3 Self-powered mode

In self-powered mode, pin VBUSDET_N cannot be used. The VBUS sensing can be done

in the following two ways:

•Connecting VBUS to the microprocessor; see Figure 25.

–When VBUSDET goes LOW, the microprocessor clears bit SOFTCT.

–When VBUSDET goes HIGH, the microprocessor sets bit SOFTCT.

•Connecting transistor switching; see Figure 26.

–When VBUS is HIGH, VREG(3V3) will bypass to pull up DP. This indicates that the

device is connected.

–When VBUS is LOW, pull up DP is switched off. This indicates that the device is

disconnected.

Remark: The above implementation is necessary to comply with USB-IF requir ements.

Fig 24. Hybrid-powered mode

004aaa452

MCU ISP1183

VBUS

VREG(3V3)

VDD(I/O)

VBUSDET_N

VBUS

VDD(I/O)

VCC

self-powered

self-powered (1.65 V to 3.6 V)

Product data sheet Rev. 04 — 29 September 2009 53 of 61

ISP1183

Low-power USB peripheral controller with DMA

Fig 25. VBUS connected to the micro processor

Fig 26. Transistor switching

004aaa454

MCU

ISP1183

VBUSDET

self-powered (3 V or 5 V)

100 kΩ

BUS

22 Ω

BUS

REG(3V3)

DD(I/O)

self-powered (1.65 V to 3.6 V)

004aaa453

MCU

ISP1183

VCC

self-powered (3 V or 5 V)

100 kΩ

VBUS

22 Ω

VBUS

VREG(3V3)

VDD(I/O)

self-powered (1.65 V to 3.6 V)

VBUSDET

VREG(3V3)

22 kΩ

1.5 kΩ

Product data sheet Rev. 04 — 29 September 2009 54 of 61

ISP1183

Low-power USB peripheral controller with DMA

18. Test information

The dynamic characteristics of the analog I/O ports (DP and DM) as listed in Table 54

were determined using the circuit shown in Figure 27.

Load capacitance:

(1) CL= 50 pF (full-speed mode)

Speed:

(1) Full-speed mode only: internal 1.5 kΩ pull-up resistor on DP

Fig 27. Load impedance for the DP and DM pins

test point

50 pF

22 Ω

15 kΩ

DUT

mgs784

Product data sheet Rev. 04 — 29 September 2009 55 of 61

ISP1183

Low-power USB peripheral controller with DMA

19. Package outline

Fig 28. Package outline SOT 617-1 (HVQFN32)

0.51

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 5.1

4.9

3.25

2.95

5.1

4.9 3.25

2.95

3.5

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT617-1 MO-220- - - - - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT617-1

HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;

32 terminals; body 5 x 5 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

916

32 25

terminal 1

index area

terminal 1

index area

01-08-08

02-10-18

1/2 e

1/2 e AC

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 04 — 29 September 2009 56 of 61

ISP1183

Low-power USB peripheral controller with DMA

20. Abbreviations

Table 59. Abbreviations

Acronym Description

ACK Acknowledge

ACPI Advanced Configuration and Power Interface

AT Advanced Technology

CMOS Complementary Metal-Oxide Semiconductor

CRC Cyclic Redundancy Check

DMA Direct Memory Access

ECR Endpoint Configuration Register

EMI ElectroMagnetic Interference

EOP End-Of-Packet

EOT End-Of-Transfer

ESR Endpoint Status Register

FIFO First In, First Out

I/O Input/Output

IR Interrupt Register

ISO Isochronous

MMU Memory Management Unit

NAK Not Acknowledge

PCB Printed Circu i t Boa rd

PID Packet Identifier

PIO Parallel I/O

PLL Phase-Locked Loop

POR Power-On Reset

PSOF Pseudo Start-Of-Frame

RISC Reduced Instruction Set Computer

SIE Serial Interface Engine

SOF Start-Of-Frame

USB Universal Serial Bus

Product data sheet Rev. 04 — 29 September 2009 57 of 61

ISP1183

Low-power USB peripheral controller with DMA

21. Revision history

Table 60. Revision history

Document ID Release date Data sheet status Change notice Supersedes

ISP1183_4 20090929 Product data sheet - ISP1183_3

Modifications: •Rebranded to the ST-Ericsson template.

•Section 4 “Ordering information”: updated.

•Removed soldering information.

ISP1183_3 20090120 Product data sheet - ISP1183_2

ISP1183_2 20070607 Product data sheet - ISP1183-01

ISP1183-01

(9397 750 11804) 20040224 Product data - -

Product data sheet Rev. 04 — 29 September 2009 58 of 61

ISP1183

Low-power USB peripheral controller with DMA

22. Tables

Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4

Table 3. ISP1183 operation modes . . . . . . . . . . . . . . . . .8

Table 4. Endpoint access and programmability . . . . . . .13

Table 5. Programmable FIFO size . . . . . . . . . . . . . . . . .14

Table 6. Memory configuration example . . . . . . . . . . . .14

Table 7. Endpoint selection for the DMA transfer . . . . .16

Table 8. 8237 compatible mode: pin functions . . . . . . .17

Table 9. DACK-only mode: pin functions . . . . . . . . . . . .18

Table 10. Summary of EOT conditions for a bulk

endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Table 11. Rec ommended EOT usage for isochronous

endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Table 12. Summary of control bits . . . . . . . . . . . . . . . . . .23

Table 13. Command and register overview . . . . . . . . . . .24

Table 14. Endpoint Configuration register: bit allocation .27

Table 15. Endpoint Configuration register: bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 16. Address register: bit allocation . . . . . . . . . . . .27

Table 17. Address register: bit description . . . . . . . . . . .27

Table 18. Mode register: bit allocation . . . . . . . . . . . . . . .28

Table 19. Mode register: bit description . . . . . . . . . . . . .28

Table 20. Hardware Configuration register: bit allocation 29

Table 21. Hardware Configuration re gister: bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 22. Interrupt Enable register: bit allocation . . . . . .30

Table 23. Interrupt Enable register: bit description . . . . .3 0

Table 24. Endpoint FIFO organization . . . . . . . . . . . . . . .3 2

Table 25. Example of endpoint FIFO access . . . . . . . . . .32

Table 26. Endpoint Status register: bit allocation . . . . . . .32

Table 27. Endpoint Status register: bit description . . . . .33

Table 28. Endpoint Status Image register: bit allocation .34

Table 29. Endpoint Status Image register: bit description 34

Table 30. DMA Function and Scratch register: bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 31. DMA Function and Scratch register: bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 32. DMA Configuration register: bit allocation . . . .36

Table 33. DMA Configuration register: bit description . . .36

Table 34. DMA Counter register: bit allocation . . . . . . . .3 7

Table 35. DMA Counter register: bit description . . . . . . .37

Table 36. Error Code register: bit allocation . . . . . . . . . .3 7

Table 37. Error Code register: bit description . . . . . . . . .37

Table 38. Transaction error codes . . . . . . . . . . . . . . . . . .38

Table 39. Lock register: bit allocation . . . . . . . . . . . . . . .38

Table 40. Lock register: bit description . . . . . . . . . . . . . .39

Table 41. Frame Number register: bit allocation . . . . . . .39

Table 42. Frame Number register: bit description . . . . . .39

Table 43. Example of Frame Number register access . .39

Table 44. Chip ID register: bit allocation . . . . . . . . . . . . .40

Table 45. Chip ID register: bit description . . . . . . . . . . . .40

Table 46. Interrupt register: bit allocation . . . . . . . . . . . .40

Table 47. Interrupt register: bit description . . . . . . . . . . .41

Table 48. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .42

Table 49. Recommended operating conditions . . . . . . . .42

Table 50. Static characteristics: supply pins . . . . . . . . . .43

Table 51. Static characteristics: digital pins . . . . . . . . . . 43

Table 52. Static characteristics: analog I/O pins DP

and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 53. Dynamic characteristics . . . . . . . . . . . . . . . . . 45

Table 54. Dynamic characteristics: analog I/O pins DP

and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 55. Dynamic characteristics: parallel interface

timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 56. Dynamic characteristics: access cycle timing . 47

Table 57. Dynamic characteristics: single-cycle DMA

timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 58. Dynamic characteristics: burst mode DMA

timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 59. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 60. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 57

Product data sheet Rev. 04 — 29 September 2009 59 of 61

ISP1183

Low-power USB peripheral controller with DMA

23. Figures

Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Fig 2. Pin configuration HVQFN32 . . . . . . . . . . . . . . . . .4

Fig 3. ISP1183 with a 4.0 V to 5.5 V supply. . . . . . . . . . .9

Fig 4. ISP1183 with a 3.0 V to 3.6 V supply. . . . . . . . . . .9

Fig 5. Typical oscillator circuit . . . . . . . . . . . . . . . . . . . .10

Fig 6. POR timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Fig 7. Clock with respect to the external POR. . . . . . . .11

Fig 8. Interrupt logic. . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Fig 9. ISP1183 in 8237-compatible DMA mode. . . . . . .17

Fig 10. ISP1183 in DACK-only DMA mode . . . . . . . . . . .19

Fig 11. Suspend and resume timing . . . . . . . . . . . . . . . .22

Fig 12. SUSPEND and WAKEUP signals in a powered-off

modem application. . . . . . . . . . . . . . . . . . . . . . . .22

Fig 13. Parallel interface read timing . . . . . . . . . . . . . . . .47

Fig 14. Parallel interface write timing. . . . . . . . . . . . . . . .47

Fig 15. Write command + write data cycle timing . . . . . .48

Fig 16. Write da ta + write co mma nd cycle timing . . . . . .48

Fig 17. Write command + read data cycle timing. . . . . . .48

Fig 18. Read data + write command cycle timing . . . . . .49

Fig 19. DMA timing in 8237 compatible mode. . . . . . . . .49

Fig 20. DMA read timing in DACK-only mode . . . . . . . . .50

Fig 21. DMA write timing in DACK-only mode. . . . . . . . .50

Fig 22. Burst mode DMA timing. . . . . . . . . . . . . . . . . . . .51

Fig 23. Bus-powered mode . . . . . . . . . . . . . . . . . . . . . . .51

Fig 24. Hybrid-powered mode . . . . . . . . . . . . . . . . . . . . .52

Fig 25. VBUS connected to the microprocessor . . . . . . . .5 3

Fig 26. Transistor switching. . . . . . . . . . . . . . . . . . . . . . .53

Fig 27. Load impedance for the DP and DM pins . . . . . .54

Fig 28. Package outline SOT617-1 (HVQFN32) . . . . . . .55

Product data sheet Rev. 04 — 29 September 2009 60 of 61

ISP1183

Low-power USB peripheral controller with DMA

24. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7 Funct ional description . . . . . . . . . . . . . . . . . . . 7

7.1 Analog transceiver . . . . . . . . . . . . . . . . . . . . . . 7

7.2 ST-Ericsson SIE . . . . . . . . . . . . . . . . . . . . . . . . 7

7.3 MMU and in tegrated RAM . . . . . . . . . . . . . . . . 7

7.4 SoftConnect . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

7.5 Bit clock recovery . . . . . . . . . . . . . . . . . . . . . . . 8

7.6 Voltage regulator. . . . . . . . . . . . . . . . . . . . . . . . 8

7.7 PLL clock multiplier. . . . . . . . . . . . . . . . . . . . . . 8

7.8 PIO and DMA interfaces. . . . . . . . . . . . . . . . . . 8

7.9 VBUS indicator. . . . . . . . . . . . . . . . . . . . . . . . . . 8

7.10 Operation modes . . . . . . . . . . . . . . . . . . . . . . . 8

7.11 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . 9

7.12 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . 9

7.13 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 10

8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

9 Endpoint description. . . . . . . . . . . . . . . . . . . . 13

9.1 Endpoint access . . . . . . . . . . . . . . . . . . . . . . . 13

9.2 Endpoint FIFO size. . . . . . . . . . . . . . . . . . . . . 13

9.3 Endpoint initialization . . . . . . . . . . . . . . . . . . . 14

9.4 Endpoint I/O mode access . . . . . . . . . . . . . . . 15

9.5 Special actions on control endpoints . . . . . . . 15

10 DMA transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 16

10.1 Selecting an endpoint for DMA transfer . . . . . 16

10.2 8237 compatible mode . . . . . . . . . . . . . . . . . . 17

10.3 DACK-only mode . . . . . . . . . . . . . . . . . . . . . . 18

10.4 EOT conditions. . . . . . . . . . . . . . . . . . . . . . . . 19

10.4.1 Bulk endpoints . . . . . . . . . . . . . . . . . . . . . . . . 19

10.4.1.1 DMA Counter register. . . . . . . . . . . . . . . . . . . 19

10.4.1.2 Short packet . . . . . . . . . . . . . . . . . . . . . . . . . . 19

10.4.2 Isochronous endpoints . . . . . . . . . . . . . . . . . . 20

11 Suspend and resume . . . . . . . . . . . . . . . . . . . 21

11.1 Suspend conditions . . . . . . . . . . . . . . . . . . . . 21

11.1.1 Powered-off application . . . . . . . . . . . . . . . . . 22

11.2 Resume conditions. . . . . . . . . . . . . . . . . . . . . 23

11.3 Control bits in suspend and resume. . . . . . . . 23

12 Commands and registers . . . . . . . . . . . . . . . . 24

12.1 Initialization commands . . . . . . . . . . . . . . . . . 26

12.1.1 Endpoint Configuration register (R/W:

30h to 3Fh/20h to 2Fh). . . . . . . . . . . . . . . . . . 26

12.1.2 Address register (R/W: B7h/B6h) . . . . . . . . . . 27

12.1.3 Mode register (R/W: B9h/B8h) . . . . . . . . . . . . 28

12.1.4 Hardware Configuration register

(R/W: BBh/BAh) . . . . . . . . . . . . . . . . . . . . . . . 28

12.1.5 Interrupt Enable register (R/W: C3h/C2h). . . . 29

12.1.6 Reset Device (F6h). . . . . . . . . . . . . . . . . . . . . 31

12.2 Data flow commands . . . . . . . . . . . . . . . . . . . 31

12.2.1 Endpoint Buffer (R/W: 10h,

12h to 1Fh/01h to 0Fh) . . . . . . . . . . . . . . . . . 31

12.2.2 Endpoint Status register (R: 50h to 5Fh) . . . . 32

12.2.3 Stall or Unstall Endpoint

(40h to 4Fh/80h to 8Fh) . . . . . . . . . . . . . . . . . 33

12.2.4 Validate Endpoint Buffer (61h to 6Fh) . . . . . . 33

12.2.5 Clear Endpoint Buffer (70h, 72h to 7Fh) . . . . 34

12.2.6 Check Endpoint Status (D0h to DFh). . . . . . . 34

12.2.7 Acknowledge Setup (F4h) . . . . . . . . . . . . . . . 35

12.3 DMA commands . . . . . . . . . . . . . . . . . . . . . . 35

12.3.1 DMA Function and Scratch register (R/W:

B3h/B2h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

12.3.2 DMA Configuration register (R/W: F1h/F0h) . 36

12.3.3 DMA Counter register (R/W: F3h/F2h). . . . . . 36

12.4 Gene ral commands . . . . . . . . . . . . . . . . . . . . 37

12.4.1 Endpoint Error Code (R: A0h to AFh) . . . . . . 37

12.4.2 Unlock Device (B0h) . . . . . . . . . . . . . . . . . . . 38

12.4.3 Frame Number register (R: B4h) . . . . . . . . . . 39

12.4.4 Chip ID register (R: B5h) . . . . . . . . . . . . . . . . 39

12.4.5 Interrupt register (R: C0h) . . . . . . . . . . . . . . . 40

13 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 42

14 Recommended operating conditions . . . . . . 42

15 Static characteristics . . . . . . . . . . . . . . . . . . . 43

16 Dynamic characteristics. . . . . . . . . . . . . . . . . 45

16.1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

16.1.1 Parallel I/O timing. . . . . . . . . . . . . . . . . . . . . . 46

16.1.2 Access cycle timing . . . . . . . . . . . . . . . . . . . . 47

16.1.3 DMA timing: single-cycle mode . . . . . . . . . . . 49

16.1.4 DMA timing: burst mode . . . . . . . . . . . . . . . . 50

17 Application information . . . . . . . . . . . . . . . . . 51

17.1 Bus-powered mode . . . . . . . . . . . . . . . . . . . . 51

17.2 Hybrid-powered mode . . . . . . . . . . . . . . . . . . 51

17.3 Self-powered mode . . . . . . . . . . . . . . . . . . . . 52

18 Test information . . . . . . . . . . . . . . . . . . . . . . . 54

19 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 55

20 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 56

21 Revision history . . . . . . . . . . . . . . . . . . . . . . . 57

22 Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

23 Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

24 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Product data sheet Rev. 04 — 29 September 2009 61 of 61

ISP1183

Low-power USB peripheral controller with DMA

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