LTC2451 Ultra-Tiny, 16-Bit ADC with I2C Interface FEATURES DESCRIPTION n The LTC(R)2451 is an ultra-tiny, 16-bit, analog-to-digital converter. The LTC2451 uses a single 2.7V to 5.5V supply, accepts a single-ended analog input voltage and communicates through an I2C interface. The converter is available in an 8-pin, 3mm x 2mm DFN or TSOT-23 package. It includes an integrated oscillator that does not require any external components. It uses a delta-sigma modulator as a converter core and provides single-cycle settling time for multiplexed applications. The LTC2451 includes a proprietary input sampling scheme that reduces the average input sampling current several orders of magnitude lower than conventional converters. n n n n n n n n n n n n n GND to VCC Single-Ended Input Range 0.02LSB RMS Noise 2LSB INL, No Missing Codes 1LSB Offset Error 4LSB Full-Scale Error Programmable 30/60 Conversions per Second Single Conversion Settling Time for Multiplexed Applications Single-Cycle Operation with Auto Shutdown 400A Supply Current 0.2A Sleep Current Internal Oscillator--No External Components Required Single Supply, 2.7V to 5.5V Operation 2-Wire I2C Interface Ultra-Tiny 3mm x 2mm DFN or TSOT-23 Package APPLICATIONS n n n n n n n System Monitoring Environmental Monitoring Direct Temperature Measurements Instrumentation Industrial Process Control Data Acquisition Embedded ADC Upgrades , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 6208279, 6411242, 7088280, 7164378. The LTC2451 is capable of up to 60 conversions per second and, due to the very large oversampling ratio, has extremely relaxed antialiasing requirements. In the 30Hz mode, the LTC2451 includes continuous internal offset calibration algorithms which are transparent to the user, ensuring accuracy over time and over the operating temperature range. The converter has external REF+ and REF - pins and the input voltage can range from VREF- to VREF+. If VREF+ = VCC and VREF- = GND, the input voltage can range from GND to VCC. Following a single conversion, the LTC2451 can automatically enter sleep mode and reduce its power to less than 0.2A. If the user reads the ADC once per second, the LTC2451 consumes an average of less than 50W from a 2.7V supply. TYPICAL APPLICATION Integral Nonlinearity, VCC = 3V 3 2.7V TO 5.5V 0.1F IN SENSOR 0.1F VCC LTC2451 REF - 1 SCL SDA GND 2-WIRE I2C INTERFACE INL (LSB) REF + 1k 2 10F 0 TA = 90C -1 TA = - 45C, 25C 2451 TA01a -2 -3 0 0.5 1 1.5 2 INPUT VOLTAGE (V) 2.5 3 2451 TA01b 2451fc 1 LTC2451 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (VCC) ................................... -0.3V to 6V Analog Input Voltage (VIN) ............ -0.3V to (VCC + 0.3V) Reference Voltage (VREF+, VREF -) ...-0.3V to (VCC + 0.3V) Digital Voltage (VSDA, VSCL) .......... -0.3V to (VCC + 0.3V) Storage Temperature Range................... -65C to 150C Operating Temperature Range LTC2451C ................................................ 0C to 70C LTC2451I.............................................. -40C to 85C PIN CONFIGURATION TOP VIEW TOP VIEW GND 1 REF- 2 REF+ 3 VCC 4 9 8 SDA 7 SCL 6 IN 5 GND GND 1 REF- 2 REF+ 3 VCC 4 8 SDA 7 SCL 6 IN 5 GND TS8 PACKAGE 8-LEAD PLASTIC TSOT-23 DDB PACKAGE 8-LEAD (3mm s 2mm) PLASTIC DFN C/I GRADE TJMAX = 125C, JA = 140C/W C/I GRADE TJMAX = 125C, JA = 76C/W EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION Lead Free Finish TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2451CDDB#TRMPBF LTC2451CDDB#TRPBF LDGQ 8-Lead Plastic (3mm x 2mm) DFN LTC2451IDDB#TRMPBF LTC2451IDDB#TRPBF LDGQ 8-Lead Plastic (3mm x 2mm) DFN LTC2451CDDB#TRMPBF LTC2451CTS8 LTDNS 8-Lead Plastic TSOT-23 LTC2451IDDB#TRMPBF LTC2451ITS8 LTDNS 8-Lead Plastic TSOT-23 TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 0C to 70C -40C to 85C 0C to 70C -40C to 85C ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 2) PARAMETER CONDITIONS Resolution (No Missing Codes) Integral Nonlinearity Offset Error Offset Error Offset Error Drift (Note 3) (Note 4) 30Hz Mode 60Hz Mode MIN l l l l l Gain Error Gain Error Drift Transition Noise TYP MAX UNITS 2 0.08 0.5 0.02 10 0.5 2 Bits LSB mV mV LSB/C 0.01 0.02 0.02 16 % of FS LSB/C 1.4 VRMS Power Supply Rejection DC 30Hz Mode 80 dB Power Supply Rejection DC 60Hz Mode 80 dB 2451fc 2 LTC2451 ANALOG INPUT AND REFERENCES The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 2) SYMBOL VIN VREF+ VREF- CIN IDC_LEAK(VIN) PARAMETER Input Voltage Range Positive Reference Voltage Range Negative Reference Voltage Range IN Sampling Capacitance IN DC Leakage Current IDC_LEAK(REF+, REF-) REF+, REF- DC Leakage Current Input Sampling Current (Note 5) ICONV CONDITIONS MIN l VREF- l VCC - 2.5 l 0 VREF+ - VREF- 2.5V VREF+ - VREF- 2.5V l l VIN = GND (Note 8) VIN = VCC (Note 8) VREF = 5V (Note 8) -10 -10 -10 l TYP 0.35 1 1 1 50 MAX VREF+ VCC VCC - 2.5 10 10 10 UNITS V V V pF nA nA nA nA POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 2) SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current Conversion Sleep CONDITIONS MIN 2.7 l l l TYP MAX 5.5 UNITS V 400 0.2 700 0.5 A A I2C INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.7V to 5.5V. (Note 2) SYMBOL VIH VIL VHYS VOL IIN CI CB PARAMETER High Level Input Voltage Low Level Input Voltage Hysteresis of Schmidt Trigger Inputs Low Level Output Voltage (SDA) Input Leakage Capacitance for Each I/O Pin Capacitance Load for Each Bus Line CONDITIONS MIN 0.7VCC l TYP l l (Note 3) I = 3mA 0.1VCC VIN 0.9VCC MAX 0.3VCC 0.05VCC l l 0.4 1 -1 10 l l 400 UNITS V V V V A pF pF I2C TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.7V to 5.5V. (Notes 2, 7) SYMBOL tCONV tCONV fSCL tHD(SDA) PARAMETER Conversion Time Conversion Time SCL Clock Frequency Hold Time (Repeated) Start Condition CONDITIONS 30Hz Mode 60Hz Mode l MIN 26 13 0 0.6 tLOW Low Period of the SCL Pin l 1.3 s tHIGH High Period of the SCL Pin l 0.6 s tSU(STA) Set-Up Time for a Repeated Start Condition l 0.6 s tHD(DAT) Data Hold Time l 0 0.9 tSU(DAT) tr tf tSU(STO) Data Set-Up Time Rise Time for SDA/SCL Signals Fall Time for SDA/SCL Signals Set-Up Time for Stop Condition l 300 300 l 100 20 + 0.1CB 20 + 0.1CB 0.6 tBUF Bus Free Time Between a Stop and Start Condition l 1.3 l l l (Note 6) (Note 6) l l TYP 33.2 16.6 MAX 46 23 400 UNITS ms ms kHz s s ns ns ns s s 2451fc 3 LTC2451 I2C TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 2, 7) SYMBOL tOF PARAMETER Output Fall Time VIH(MIN) to VIL(MAX) tSP Input Spike Suppression CONDITIONS Bus Load CB 10pF to 400pF (Note 6) l MIN 20 + 0.1CB TYP MAX 250 l Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2. All voltage values are with respect to GND. VCC = 2.7V to 5.5V, unless otherwise specified. Specifications apply to both 30Hz and 60Hz modes unless otherwise specified. VREF = VREF+ - VREF-, VREFCM = (VREF+ + VREF-)/2, FS = VREF+ - VREF-; VREF- VIN VREF+ Note 3. Guaranteed by design, not subject to test. UNITS ns 50 ns Note 4. Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Guaranteed by design, test correlation and 3-point transfer curve measurement. Note 5. Input sampling current is the average input current drawn from the input sampling network while the LTC2451 is actively sampling the input. CB = capacitance of one bus line in pF. Note 6. CB = capacitance of one bus line in pF. Note 7. All values refer to VIH(MIN) and VIL(MAX) levels. Note 8. A positive current is flowing into the DUT pin. TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C; graphs apply to both 30Hz and 60Hz modes, unless otherwise noted. Integral Nonlinearity VCC = 5V, VREF+ = 3V Integral Nonlinearity VCC = VREF+ = 3V 3 3 2 2 2 1 1 1 0 TA = - 45C, 25C, 90C -1 INL (LSB) 3 INL (LSB) INL (LSB) Integral Nonlinearity VCC = VREF+ = 5V 0 TA = - 45C, 25C, 90C 0 -1 -1 -2 -2 TA = 90C TA = - 45C, 25C -2 -3 0 1 2 3 INPUT VOLTAGE (V) 4 5 2451 G01 -3 0 0.5 1 1.5 2 INPUT VOLTAGE (V) 2.5 3 2451 G02 -3 0 0.5 1 1.5 2 INPUT VOLTAGE (V) 2.5 3 2451 G03 2451fc 4 LTC2451 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C; graphs apply to both 30Hz and 60Hz modes, unless otherwise noted. Offset Error vs Temperature 30Hz Mode Offset Error vs Temperature 60Hz Mode 0.50 0.50 4.5 0.45 0.45 4.0 0.40 0.40 3.5 0.35 0.35 3.0 2.5 VCC = 4.1V 2.0 VCC = 5V 0.30 0.25 0.20 1.5 0.15 1.0 0.10 VCC = 3V VCC = 4.1V -25 25 50 0 TEMPERATURE (C) 75 0.00 -50 100 VCC = 5V 0.30 0.25 -25 VCC = 5V, 4.1V, 3V 0.20 0.15 0.10 VCC = 3V 0.05 0.5 0 -50 OFFSET (mV) 5.0 OFFSET (V) INL (LSB) Maximum INL vs Temperature 0.05 25 50 0 TEMPERATURE (C) 75 0.00 -50 100 -25 25 50 0 TEMPERATURE (C) 2451 G05 2451 G04 Gain Error vs Temperature 2451 G06 Transition Noise vs Temperature 10 100 75 Transition Noise vs Output Code 3.0 3.0 2.5 2.5 GAIN ERROR (LSB) 8 7 VCC = 3V 6 5 4 VCC = 4.1V 3 VCC = 5V 2 TRANSITION NOISE RMS (V) TRANSITION NOISE RMS (V) 9 2.0 1.5 VCC = 5V 1.0 VCC = 3V 0.5 2.0 1.5 VCC = 5V 1.0 VCC = 3V 0.5 1 0 -50 -25 25 50 0 TEMPERATURE (C) 75 0 -50 100 0 -25 0 25 50 TEMPERATURE (C) 75 2451 G07 VCC = 4.1V VCC = 5V -25 0 25 50 TEMPERATURE (C) 75 100 2451 G10 1000 150 VCC = 4.1V 100 50 100 AVERAGE POWER DISSIPATION (W) VCC = 3V 200 0 -50 10000 200 SLEEP CURRENT (nA) CONVERSION CURRENT (A) 500 0 -50 65536 Average Power Dissipation vs Temperature VCC = 3V, 30Hz Mode 250 600 300 32768 49152 OUTPUT CODE 2451 G09 Sleep Mode Power Supply Current vs Temperature VCC = 5V 16384 2451 G08 Conversion Mode Power Supply Current vs Temperature 400 0 100 VCC = 3V -25 0 25 50 TEMPERATURE (C) 75 100 2451 G11 25Hz OUTPUT SAMPLE RATE 10Hz OUTPUT SAMPLE RATE 100 1Hz OUTPUT SAMPLE RATE 10 1 -50 -25 0 25 50 TEMPERATURE (C) 75 100 2451 G12 2451fc 5 LTC2451 TYPICAL PERFORMANCE CHARACTERISTICS modes, unless otherwise noted. Average Power Dissipation vs Temperature VCC = 3V, 60Hz Mode Power Supply Rejection vs Frequency at VCC 0 10000 -20 1000 25Hz OUTPUT SAMPLE RATE REJECTIOIN (dB) AVERAGE POWER DISSIPATION (W) TA = 25C; graphs apply to both 30Hz and 60Hz 10Hz OUTPUT SAMPLE RATE 100 1Hz OUTPUT SAMPLE RATE -40 -60 -80 30Hz MODE, 60Hz MODE 10 -100 1 -50 -25 0 25 50 TEMPERATURE (C) 75 -120 100 1 10 100 1k 10k 100k FREQUENCY AT VCC (Hz) 1M 2451 G13 2451 G14 Conversion Period vs Temperature 60Hz Mode 44 22 42 21 CONVERSION TIME (ms) CONVERSION TIME (ms) Conversion Period vs Temperature 30Hz Mode 40 VCC = 5.5V, 4.1V, 2.7V 38 36 34 32 30 -45 -25 10M 20 VCC = 5.5V, 4.1V, 2.7V 19 18 17 16 35 15 55 -5 TEMPERATURE (C) 75 95 2451 G15 15 -45 -25 35 15 55 -5 TEMPERATURE (C) 75 95 2451 G16 2451fc 6 LTC2451 PIN FUNCTIONS GND (Pin 1, 5): Ground. Connect to a ground plane through a low impedance connection. REF- (Pin 2), REF+ (Pin 3): Differential Reference Input. The voltage on these pins can have any value between GND and VCC as long as the reference positive input, REF+, remains more positive than the negative reference input, REF-, by at least 2.5V. The differential reference voltage (VREF = REF+ to REF-) sets the full-scale range. VCC (Pin 4): Positive Supply Voltage. Bypass to GND (Pin 1) with a 10F capacitor in parallel with a low series inductance 0.1F capacitor located as close to the part as possible. IN (Pin 6): Analog Input. IN's single-ended input range is VREF- to VREF+. SCL (Pin 7): Serial Clock Input of the I2C Interface. The LTC2451 can only act as a slave and the SCL pin only accepts an external serial clock. Data is shifted into the SDA pin on the rising edges of SCL and output through the SDA pin on the falling edges of SCL. SDA (Pin 8): Bidirectional Serial Data Line of the I2C Interface. The conversion result is output through the SDA pin. The pin is high impedance unless the LTC2451 is in the data output mode. While the LTC2451 is in the data output mode, SDA is an open-drain pull-down (which requires an external 1.7k pull-up resistor to VCC). Exposed Pad (Pin 9): Ground. Must be soldered to PCB ground. BLOCK DIAGRAM 3 REF + 4 VCC I2C INTERFACE 6 IN 16-BIT A/D CONVERTER SCL SDA 7 8 INTERNAL OSCILLATOR 2 REF - 1 GND 1, 5, 9 2451 BD APPLICATIONS INFORMATION CONVERTER OPERATION Converter Operation Cycle The LTC2451 is a low power, delta-sigma analog-todigital converter with an I2C interface. Its operation, as shown in Figure 1, is composed of three successive states: conversion, sleep, and data input/output. Initially, at power-up, the LTC2451 is set to its default 60Hz mode and performs a conversion. Once the conversion is complete, the device enters the sleep state. While in the sleep state, power consumption is reduced by several orders of magnitude. The part remains in the sleep state as long it is not addressed for a Read or Write operation. The conversion result is held indefinitely in a static shift register while the part is in the sleep state. The device will not acknowledge an external request during the conversion state. After a conversion is finished, the device is ready to accept a Read/Write request. The LTC2451's address is hardwired at 0010100. Once the LTC2451 is addressed for a Read operation, the device 2451fc 7 LTC2451 APPLICATIONS INFORMATION POWER-ON RESET CONVERSION SLEEP NO READ/WRITE ACKNOWLEDGE YES if the power supply voltage, VCC, is restored within the operating range (2.7V to 5.5V) before the end of the POR time interval. Ease of Use The LTC2451 data output has no latency, filter settling delay, or redundant results associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog input voltages requires no special actions. DATA INPUT/OUTPUT NO STOP OR READ 16 BITS YES 2451 F01 Figure 1. State Diagram begins outputting the conversion result under the control of the serial clock (SCL). There is no latency in the conversion result. The data output is 16 bits long and outputs from MSB to LSB. Data is updated on the falling edges of SCL, allowing the user to reliably latch data on the rising edge of SCL. In Write operation, the device accepts one configuration byte and the data is shifted in on the rising edges of SCL. A new conversion is initiated by a Stop condition following a valid Read or Write operation, or by the conclusion of a complete Read cycle (all 16 bits read out of the device). Power-Up Sequence In the 30Hz mode, the LTC2451 performs offset calibrations during every conversion. This calibration is transparent to the user and has no effect upon the cyclic operation previously described. The advantage of continuous calibration is stability of the ADC performance with respect to time and temperature. The LTC2451 includes a proprietary input sampling scheme that reduces the average input current by several orders of magnitude when compared to traditional delta-sigma architectures. This allows external filter networks to interface directly to the LTC2451. Since the average input sampling current is 50nA, an external RC lowpass filter using a 1k and 0.1F results in less than 1LSB additional error. Reference Voltage Range This converter accepts a truly differential external reference voltage. The voltage range for the REF+ and REF- pins covers the entire operating range of the device (GND to VCC). For correct converter operation, VREF+ - VREF- 2.5V. The LTC2451 differential reference input range is 2.5V to VCC. For the simplest operation, REF+ can be shorted to VCC and REF- can be shorted to GND. When the power supply voltage, VCC, applied to the converter is below approximately 2.1V, the ADC performs a power-on reset. This feature guarantees the integrity of the conversion result. Input Voltage Range When VCC rises above this threshold, the converter generates an internal power-on reset (POR) signal for approximately 0.5ms. The POR signal clears all internal registers. Following the POR signal, the LTC2451 starts a conversion cycle and follows the succession of states described in Figure 1. The first conversion result following POR is accurate within the specifications of the device Ignoring offset and full-scale errors, the converter will theoretically output an "all zero" digital result when the input is at VREF- (a zero scale input) and an "all one" digital result when the input is at VREF+ (a full-scale input). In an underrange condition, for all input voltages less than the voltage corresponding to output code 0, the converter will generate the output code 0. In an overrange condition, 2451fc 8 LTC2451 APPLICATIONS INFORMATION for all input voltages greater than the voltage corresponding to output code 65535, the converter will generate the output code 65535. finished, a Stop (P) condition is generated by transitioning SDA from low to high while SCL is pulled high. The bus is free after a Stop is generated. Start and Stop conditions are always generated by the master. I2C INTERFACE When the bus is in use, it stays busy if a Repeated Start (Sr) is generated instead of a Stop condition. The Repeated Start (Sr) conditions are functionally identical to the Start (S). The LTC2451 communicates through an I2C interface. The I2C interface is a 2-wire open-drain interface supporting multiple devices and masters on a single bus. The connected devices can only pull the data line (SDA) low and never drive it high. SDA is externally connected to the supply through a pull-up resistor. When the data line is free, it is pulled high through this resistor. Data on the I2C bus can be transferred at rates up to 100k/s in the standard mode and up to 400k/s in the fast mode. Each device on the I2C bus is recognized by a unique address stored in that device and can operate either as a transmitter or receiver, depending on the function of the device. In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. Devices addressed by the master are considered a slave. The address of the LTC2451 is 0010100. The LTC2451 can only be addressed as a slave. It can only transmit the last conversion result. The serial clock line, SCL, is always an input to the LTC2451 and the serial data line, SDA, is bidirectional. Figure 2 shows the definition of the I2C timing. The Start and Stop Conditions A Start (S) condition is generated by transitioning SDA from high to low while SCL is high. The bus is considered to be busy after the Start condition. When the data transfer is Data Transferring After the Start condition, the I2C bus is busy and data transfer can begin between the master and the addressed slave. Data is transferred over the bus in groups of nine bits, one byte followed by one acknowledge (ACK) bit. The master releases the SDA line during the ninth SCL clock cycle. The slave device can issue an ACK by pulling SDA low or issue a Not Acknowledge (NAK) by leaving the SDA line high impedance (the external pull-up resistor will hold the line high). Change of data only occurs while the clock line (SCL) is low. Data Format After a Start condition, the master sends a 7-bit address (factory set at 0010100), followed by a Read request (R) or Write request (W) bit. The bit R is 1 for a Read request and 0 for a Write request. If the 7-bit address agrees with the LTC2451's address, the device is selected. When the device is addressed during the conversion state, it does not accept the request and issues a NAK by leaving the SDA line high. If the conversion is complete, the LTC2451 issues an ACK by pulling the SDA line low. The user can send one byte of data into the LTC2451 following a Write request and an ACK. The sequence is shown in Figure 3. The Write sequence is used solely to set the SDA tf tLOW tSU(DAT) tr tf tHD(SDA) tSP tr tBUF SCL tHD(STA) S tHD(DAT) tHIGH tSU(STA) tSU(STO) Sr P S 2451 F02 Figure 2. Definition of Timing for Fast/Standard Mode Devices on the I2C Bus 2451fc 9 LTC2451 APPLICATIONS INFORMATION OPERATION SEQUENCE conversion speed. The default conversion speed is 60Hz. The user can specify a 30Hz conversion speed by setting the eighth bit (S30) = 1, or specify a 60Hz conversion speed by setting the eighth bit (S30) = 0. Continuous Read Conversions from the LTC2451 can be continuously read (see Figure 7). At the end of a Read operation, a new conversion automatically begins. At the conclusion of the conversion cycle, the next result may be read using the method described above. If the conversion cycle is not concluded and a valid address selects the device, the LTC2451 generates a NAK signal indicating the conversion cycle is in progress. After a Read request and an ACK, the LTC2451 can output data, as shown in Figure 4. The data output stream is 16 bits long and is shifted out on the falling edges of SCL. The first bit is the MSB (D15) and is followed by successively less significant bits (D14, D13 ...) until the LSB (D0) is output by the LTC2451. This sequence is summarized in Figure 5. 1 7 8 9 1 2 3 4 5 6 7 8 9 SCL 7-BIT ADDRESS SDA W ACK BY LTC2451 START BY MASTER S30 = 1: 30Hz MODE S30 = 0: 60Hz MODE S30 ACK BY MASTER SLEEP DATA INPUT 2451 F03 Figure 3. Timing Diagram for Write Sequence 1 7 8 9 1 2 3 8 D15 D14 D13 9 1 2 3 8 D7 D6 D5 D0 9 SCL SDA 7-BIT ADDRESS R D8 MSB LSB ACK BY LTC2451 START BY MASTER ACK BY MASTER SLEEP NACK BY MASTER DATA OUTPUT CONVERT 2451 F04 Figure 4. Timing Diagram for Read Sequence S CONVERSION 7-BIT ADDRESS (0010100) SLEEP R ACK READ DATA OUTPUT P CONVERSION 2451 F05 Figure 5. Conversion Sequence 2451fc 10 LTC2451 APPLICATIONS INFORMATION Continuous Read/Write Once the conversion cycle is concluded, the LTC2451 can be written to, and then read from, using the Repeated Start (Sr) command. Figure 7 shows a cycle which begins with a data Write, a Repeated Start, followed by a Read, and concluded with a Stop command. The following conversion begins after all 16 bits are read out of the device, or after the Stop command, and uses the newly programmed configuration. Discarding a Conversion Result and Initiating a New Conversion with Optional Configuration Updating At the conclusion of a conversion cycle, a Write cycle can be initiated. Once the Write cycle is acknowledged, a Stop (P) command initiates a new conversion. If a new configuration is required, this data can be written into the device and a Stop command initiates a new conversion (see Figure 8). Synchronizing the LTC2451 with the Global Address Call The LTC2451 can also be synchronized with the global address call (see Figure 9). To achieve this, the LTC2451 must first have completed the conversion cycle. The S CONVERSION 7-BIT ADDRESS (0010100) R ACK READ PRESERVING THE CONVERTER ACCURACY The LTC2451 is designed to dramatically reduce the conversion result's sensitivity to device decoupling, PCB layout, antialiasing circuits, line and frequency perturbations. Nevertheless, in order to preserve the high accuracy capability of this part, some simple precautions are desirable. Digital Signal Levels Due to the nature of CMOS logic, it is advisable to keep input digital signals near GND or VCC. Voltages in the P S DATA OUTPUT SLEEP master issues a Start, followed by the LTC2451 global address 1110111, and a Write request. The LTC2451 will be selected and acknowledge the request. If desired, the master then sends the Write byte to program the 30Hz or 60Hz mode. After the optional Write byte, the master ends the Write operation with a Stop. This will update the configuration registers (if a Write byte was sent) and initiate a new conversion on the LTC2451, as shown in Figure 9. In order to synchronize the start of the conversion without affecting the configuration registers, the Write operation can be aborted with a Stop. This initiates a new conversion on the LTC2451 without changing the configuration registers. 7-BIT ADDRESS (0010100) CONVERSION R ACK READ DATAOUTPUT SLEEP P CONVERSION 2451 F06 Figure 6. Consecutive Reading at the Same Configuration 7-BIT ADDRESS (0010100) S CONVERSION W ACK WRITE 7-BIT ADDRESS (0010100) Sr DATA INPUT SLEEP R ACK ADDRESS READ P DATA OUTPUT CONVERSION 2451 F05 Figure 7. Write, Read, Start Conversion S CONVERSION 7-BIT ADDRESS (0010100) W ACK WRITE (OPTIONAL) DATA INPUT SLEEP P CONVERSION 2451 F08 Figure 8. Start a New Conversion without Reading Old Conversion Result S GLOBAL ADDRESS (1110111) SLEEP W ACK WRITE (OPTIONAL) DATA INPUT P CONVERSION 2451 F09 Figure 9. Synchronize the LTC2451 with the Global Address Call 2451fc 11 LTC2451 APPLICATIONS INFORMATION range of 0.5V to VCC - 0.5V may result in additional current leakage from the part. Driving VCC and GND In relation to the VCC and GND pins, the LTC2451 combines internal high frequency decoupling with damping elements, which reduce the ADC performance sensitivity to PCB layout and external components. Nevertheless, the very high accuracy of this converter is best preserved by careful low and high frequency power supply decoupling. A 0.1F, high quality, ceramic capacitor in parallel with a 10F ceramic capacitor should be connected between the VCC and GND pins, as close as possible to the package. The 0.1F capacitor should be placed closest to the ADC. It is also desirable to avoid any via in the circuit path, starting from the converter VCC pin, passing through these two decoupling capacitors, and returning to the converter GND pin. The area encompassed by this circuit path, as well as the path length, should be minimized. Very low impedance ground and power planes, and star connections at both VCC and GND pins, are preferable. The VCC pin should have three distinct connections: the first to the decoupling capacitors described above, the second to the ground return for the input signal source, and the third to the ground return for the power supply voltage source. Driving REF+ and REF - A simplified equivalent circuit for REF+ and REF - is shown in Figure 10. Like all other A/D converters, the LTC2451 is only as accurate as the reference it is using. Therefore, it is important to keep the reference line quiet by careful low and high frequency power supply decoupling. The LT6660 reference is an ideal match for driving the LTC2451's REF+ pin. The LTC6660 is available in a 2mm x 2mm DFN package with 2.5V, 3V, 3.3V and 5V options. A 0.1F, high quality, ceramic capacitor in parallel with a 10F ceramic capacitor should be connected between the REF +/ REF - and GND pins, as close as possible to the package. The 0.1F capacitor should be placed closest to the ADC. VCC ILEAK RSW 15k (TYP) REF + ILEAK VCC ILEAK CEQ 0.35pF (TYP) RSW 15k (TYP) IN ILEAK VCC ILEAK REF - RSW 15k (TYP) 2451 F10 ILEAK Figure 10. LTC2451 Analog Input and Reference Pins Equivalent Circuit Driving IN The input drive requirements can best be analyzed using the equivalent circuit of Figure 11. The input signal, VSIG, is connected to the ADC input pin (IN) through an equivalent source resistance RS. This resistor includes both the actual generator source resistance and any additional optional resistors connected to the input pin. An optional input capacitor, CIN, is also connected between the ADC input pin and GND. This capacitor is placed in parallel with the ADC input parasitic capacitance, CPAR. Depending on the PCB layout, CPAR has typical values between 2pF and 15pF. In addition, the equivalent circuit of Figure 11 includes the converter equivalent internal resistor, RSW, and sampling capacitor, CEQ. There are some immediate trade-offs in RS and CIN without needing a full circuit analysis. Increasing RS and CIN can provide the following benefits: 1. Due to the LTC2451's input sampling algorithm, the input current drawn by the input pin (IN) over a conversion cycle is 50nA. A high RS * CIN attenuates the high frequency components of the input current, and RS values up to 1k result in <1LSB additional INL. 2451fc 12 LTC2451 APPLICATIONS INFORMATION 2. The bandwidth from VSIG is reduced at the input pin. This bandwidth reduction isolates the ADC from high frequency signals, and as such provides simple antialiasing and input noise reduction. 3. Switching transients generated by the ADC are attenuated before they go back to the signal source. 4. A large CIN gives a better AC ground at the input pin, helping reduce reflections back to the signal source. 5. Increasing RS protects the ADC by limiting the current during an outside-the-rails fault condition. There is a limit to how large RS * CIN should be for a given application. Increasing RS beyond a given point increases the voltage drop across RS due to the input current, to the point that significant measurement errors exist. Additionally, for some applications, increasing the RS * CIN product too much may unacceptably attenuate the signal at frequencies of interest. For most applications, it is desirable to implement CIN as a high quality 0.1F ceramic capacitor and RS 1k. This capacitor should be located as close as possible to the input pin. Furthermore, the area encompassed by this circuit path, as well as the path length, should be minimized. In the case of a 2-wire sensor that is not remotely grounded, it is desirable to split RS and place series resistors in the ADC input line and in the sensor ground return line, which should be tied to the ADC GND pin using a star connection topology. Figure 12 shows the measured LTC2451 INL versus the input voltage as a function of RS value with an input capacitor CIN = 0.1F. In some cases, RS can be increased above these guidelines. The input current is negligible when the ADC is either in sleep or I/O modes. Thus, if the time constant of the input RC circuit = RS * CIN, is of the same order of magnitude or longer than the time periods between actual conversions, then one can consider the input current to be reduced correspondingly. These considerations need to be balanced out by the input signal bandwidth. The 3dB bandwidth 1/(2RSCIN). Finally, if the recommended choice for CIN is unacceptable for the user's specific application, an alternate strategy is to eliminate CIN and minimize CPAR and RS. In practical terms, this configuration corresponds to a low impedance sensor directly connected to the ADC through minimum length VCC ILEAK RS RSW 15k (TYP) IN + - VSIG CIN CPAR CEQ 0.35pF (TYP) ILEAK ICONV 2451 F11 16 8 12 6 8 4 4 INL (LSB) INL(LSB) Figure 11. LTC2451 Input Drive Equivalent Circuit RS = 1k 0 RS = 0 -4 2 RS = 1k 0 -2 RS = 10k RS = 0 -8 -4 -12 -6 -16 RS = 10k -8 0 1 2 3 INPUT VOLTAGE (V) 4 5 2451 F12 Figure 12. Measured INL vs Input Voltage, CIN = 0.1F, VCC = 5V, TA = 25C 0 0.5 1 1.5 2 2.5 3 3.5 INPUT VOLTAGE (V) 4 4.5 5 2451 F13 Figure 13. Measured INL vs Input Voltage, CIN = 0, VCC = 5V, TA = 25C 2451fc 13 LTC2451 APPLICATIONS INFORMATION traces. Actual applications include current measurements through low value sense resistors, temperature measurements, low impedance voltage source monitoring, and so on. The resultant INL versus VIN is shown in Figure 13. The measurements of Figure 13 include a capacitor CPAR corresponding to a minimum sized layout pad and a minimum width input trace of about 1" length. Signal Bandwidth and Noise Equivalent Input Bandwidth The LTC2451 includes a sinc1 type digital filter with the first notch located at f0 = 60Hz. As such, the 3dB input signal bandwidth is 26.54Hz. The calculated LTC2451 input signal attenuation versus frequency over a wide frequency range is shown in Figure 14. The calculated LTC2451 input signal attenuation with low frequencies is shown in Figure 15. The converter noise level is about 1.4VRMS , and can be modeled by a white noise source connected at the input of a noise-free converter. For a simple system noise analysis, the input drive circuit can be modeled as a single-pole equivalent circuit characterized by a pole location, fi, and a noise spectral density, ni. If the converter has an unlimited bandwidth, or at least a bandwidth substantially larger than fi, then the total noise contribution of the external drive circuit would be: Vn = ni / 2 * fi The total system noise level can then be estimated as the square root of the sum of (Vn2) and the square of the LTC2451 noise floor (~2V2). 0 INPUT SIGNAL ATTENUATIOIN (dB) INPUT SIGNAL ATTENUATION (dB) 0 -20 -40 -60 -80 -5 -10 -15 -20 -25 -30 -35 -40 -45 -100 -50 0 2.5 5.0 7.5 1.00 1.25 1.50 INPUT SIGNAL FREQUENCY (MHz) 0 60 120 180 240 300 360 420 480 540 600 INPUT SIGNAL FREQUENCY (Hz) 2451 F14 2451 F15 Figure 14. LTC2451 Input Signal Attentuation vs Frequency Figure 15. LTC2451 Input Signal Attenuation vs Frequency (Low Frequencies) TYPICAL APPLICATIONS Easy Active Input Easy Passive Input PRECONDITIONED SENSOR WITH VOLTAGE OUTPUT V+ RS < 1k 1k VOUT LTC2451 LTC2451 GND 100nF 100nF 2451 TA02 2451 TA03 2451fc 14 LTC2451 PACKAGE DESCRIPTION DDB Package 8-Lead Plastic DFN (3mm x 2mm) (Reference LTC DWG # 05-08-1702 Rev B) 0.61 p0.05 (2 SIDES) 3.00 p0.10 (2 SIDES) R = 0.115 TYP 5 R = 0.05 TYP 0.40 p 0.10 8 0.70 p0.05 2.55 p0.05 1.15 p0.05 PACKAGE OUTLINE 2.00 p0.10 (2 SIDES) PIN 1 BAR TOP MARK (SEE NOTE 6) 0.25 p 0.05 0.56 p 0.05 (2 SIDES) 0.75 p0.05 0.200 REF 0.50 BSC 2.20 p0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 4 0.25 p 0.05 1 PIN 1 R = 0.20 OR 0.25 s 45o CHAMFER (DDB8) DFN 0905 REV B 0.50 BSC 0 - 0.05 2.15 p0.05 (2 SIDES) BOTTOM VIEW--EXPOSED PAD TS8 Package 8-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1637) 0.52 MAX 2.90 BSC (NOTE 4) 0.65 REF 1.22 REF 1.4 MIN 3.85 MAX 2.62 REF 2.80 BSC 1.50 - 1.75 (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.22 - 0.36 8 PLCS (NOTE 3) 0.65 BSC 0.80 - 0.90 0.20 BSC 0.01 - 0.10 1.00 MAX DATUM `A' 0.30 - 0.50 REF 0.09 - 0.20 (NOTE 3) 1.95 BSC TS8 TSOT-23 0802 NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 2451fc Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC2451 TYPICAL APPLICATION Thermistor Measurement 5k 10k REF + IN THERMISTOR 1k TO 10k 100nF VCC SCL LTC2451 REF - SDA GND 2451 TA04 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1236A-5 Precision Bandgap Reference, 5V 0.05% Max, 5ppm/C Drift LT1461 Micropower Series Reference, 2.5V 0.04% Max, 3ppm/C Drift LT1790 Micropower Precision Reference in TSOT-23-6 Package 60A Max Supply Current, 10ppm/C Max Drift, 1.25V, 2.048V, 2.5V, 3V, 3.3V, 4.096V and 5V Options LTC1860/LTC1861 12-Bit, 5V, 1-/2-Channel 250ksps SAR ADC in MSOP 850A at 250ksps, 2A at 1ksps, SO-8 and MSOP Packages LTC1860L/LTC1861L 12-Bit, 3V, 1-/2-Channel 150ksps SAR ADC 450A at 150ksps, 10A at 1ksps, SO-8 and MSOP Packages LTC1864/LTC1865 16-Bit, 5V, 1-/2-Channel 250ksps SAR ADC in MSOP 850A at 250ksps, 2A at 1ksps, SO-8 and MSOP Packages LTC1864L/LTC1865L 16-Bit, 3V, 1-/2-Channel 150ksps SAR ADC 450A at 150ksps, 10A at 1ksps, SO-8 and MSOP Packages LTC2440 24-Bit No Latency TMADC 200nVRMS Noise, 8kHz Output Rate, 15ppm INL LTC2480 16-Bit, Differential Input, No Latency ADC, with PGA, Temperature Sensor, SPI Easy DriveTM Input Current Cancellation, 600nVRMS Noise, Tiny 10-Lead DFN Package LTC2481 16-Bit, Differential Input, No Latency ADC, with PGA, Temperature Sensor, I2C Easy Drive Input Current Cancellation, 600nVRMS Noise, Tiny 10-Lead DFN Package LTC2482 16-Bit, Differential Input, No Latency ADC, SPI Easy Drive Input Current Cancellation, 600nVRMS Noise, Tiny 10-Lead DFN Package LTC2483 16-Bit, Differential Input, No Latency ADC, I2C Easy Drive Input Current Cancellation, 600nVRMS Noise, Tiny 10-Lead DFN Package LTC2484 24-Bit, Differential Input, No Latency ADC, SPI Easy Drive Input Current Cancellation, 600nVRMS Noise, Tiny 10-Lead DFN Package LTC2485 24-Bit, Differential Input, No Latency ADC, I2C Easy Drive Input Current Cancellation, 600nVRMS Noise, Tiny 10-Lead DFN Package LTC6241 Dual, 18MHz, Low Noise, Rail-to-Rail Op Amp 550nVP-P Noise, 125V Offset Max LT6660 Micropower References in 2mm x 2mm DFN Package, 2.5V, 3V, 3.3V, 5V 20ppm/C Maximum Drift, 0.2% Max LTC2450 Easy-to-Use, Ultra-Tiny 16-Bit ADC 2 LSB INL, 50nA Sleep Current, Tiny 2mm x 2mm DFN-6 Package, 30Hz Output Rate LTC2450-1 Easy-to-Use, Ultra-Tiny 16-Bit ADC 2 LSB INL, 50nA Sleep Current, Tiny 2mm x 2mm DFN-6 Package, 60Hz Output Rate LTC2453 I2C, Differential, Ultra-Tiny 16-Bit ADC 2 LSB INL, 50nA Sleep Current, 3mm x 2mm DFN-8 and TSOT-8 Packages, 60Hz Output Rate No Latency and Easy Drive are trademarks of Linear Technology Corporation. 2451fc 16 Linear Technology Corporation LT 0808 REV C * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com (c) LINEAR TECHNOLOGY CORPORATION 2008