CYRF69103 Programmable Radio on Chip Low Power 1. PRoCTM LP Features Programmable output power up to +4 dBm Auto Transaction Sequencer (ATS) Framing CRC and Auto ACK Received Signal Strength Indication (RSSI) Automatic Gain Control (AGC) Single Device, Two Functions 8-bit Flash based MCU function and 2.4 GHz radio transceiver function in a single device. Flash Based Microcontroller Function M8C based 8-bit CPU, optimized for Human Interface Devices (HID) applications 256 Bytes of SRAM 8 Kbytes of Flash memory with EEPROM emulation In-System reprogrammable CPU speed up to 12 MHz 16-bit free running timer Low power wakeup timer 12-bit Programmable Interval Timer with interrupts Watchdog timer Industry leading 2.4 GHz Radio Transceiver Function Operates in the unlicensed worldwide Industrial, Scientific, and Medical (ISM) band (2.4 GHz to 2.483 GHz) DSSS data rates of up to 250 Kbps GFSK data rate of 1 Mbps -97 dBm receive sensitivity Component Reduction Integrated 1.8V boost converter GPIOs that require no external components Operates off a single crystal Flexible I/O 2 mA source current on all GPIO pins. Configurable 8 mA or 50 mA/pin current sink on designated pins Each GPIO pin supports high impedance inputs, configurable pull up, open drain output, CMOS/TTL inputs, and CMOS output Maskable interrupts on all I/O pins Operating Voltage from 1.8V to 3.6V DC Operating Temperature from 0 to 70C Pb-free 40-Pin QFN Package Advanced Development Tools based on Cypress's PSoC(R) Tools 2. Logic Block Diagram nSS VCC SCK MOSI 47F VCC 470nF VIO VCC3 VCC2 VReg VCC1 L/D VBat0 VBat1 VBat2 VDD_MICRO RST 10 F RFbias RFp RFn Microcontroller Function Radio Function IRQ/GPIO P1.5/MOSI P0_1,3,4,7 4 MISO/GPIO P1.4/SCK P1_0:2,6:7 XOUT/GPIO P1.3/nSS 5 12 MHz Cypress Semiconductor Corporation Document #: 001-07611 Rev *F * 198 Champion Court * ..... GND GND Xtal GND RESV P2_0:1 2 ....... Vdd PACTL/GPIO 470 nF San Jose, CA 95134-1709 * 408-943-2600 Revised February 26, 2010 [+] Feedback CYRF69103 3. Contents PRoCTM LP Features......................................................... 1 Logic Block Diagram........................................................ 1 Contents ............................................................................ 2 Applications ...................................................................... 3 Functional Description..................................................... 3 Functional Overview ......................................................... 3 2.4 GHz Radio Function .............................................. 3 Data Transmission Modes........................................... 3 Microcontroller Function .............................................. 3 Backward Compatibility ............................................... 4 DDR Mode................................................................... 4 SDR Mode.................................................................. 5 Pinouts .............................................................................. 6 Functional Block Overview.............................................. 7 2.4 GHz Radio............................................................. 7 Frequency Synthesizer................................................ 7 Baseband and Framer................................................. 7 Packet Buffers and Radio Configuration Registers ..... 8 Auto Transaction Sequencer (ATS) ............................ 8 Interrupts ..................................................................... 9 Clocks.......................................................................... 9 GPIO Interface ............................................................ 9 Power On Reset/Low Voltage Detect.......................... 9 Timers ......................................................................... 9 Power Management .................................................... 9 Low Noise Amplifier (LNA) and Received Signal Strength Indication (RSSI) ............................... 11 SPI Interface.................................................................... 11 3-Wire SPI Interface .................................................. 11 4-Wire SPI Interface .................................................. 11 SPI Communication and Transactions ...................... 12 SPI I/O Voltage References ...................................... 12 SPI Connects to External Devices ............................ 12 CPU Architecture............................................................ 12 CPU Registers........................................................... 13 Flags Register ........................................................... 13 Accumulator Register ................................................ 13 Index Register ........................................................... 14 Stack Pointer Register............................................... 14 CPU Program Counter High Register ....................... 14 CPU Program Counter Low Register ........................ 14 Addressing Modes .......................................................... 15 Source Immediate ..................................................... 15 Source Direct ............................................................. 15 Source Indexed ......................................................... 15 Destination Direct ...................................................... 15 Destination Indexed................................................... 16 Destination Direct Source Immediate........................ 16 Destination Indexed Source Immediate ..................... 16 Document #: 001-07611 Rev *F Destination Direct Source Direct ............................... 16 Source Indirect Post Increment ................................. 17 Destination Indirect Post Increment .......................... 17 Instruction Set Summary ............................................... 18 Memory Organization ................................................. 19 Flash Program Memory Organization ....................... 19 Data Memory Organization ....................................... 20 Flash.......................................................................... 20 SROM........................................................................ 20 SROM Function Descriptions .................................... 21 Clocking .......................................................................... 24 SROM Table Read Description ................................. 25 Clock Architecture Description .................................. 26 CPU Clock During Sleep Mode ................................. 30 Reset................................................................................. 31 Power On Reset ........................................................ 32 Watchdog Timer Reset.............................................. 32 Sleep Mode...................................................................... 32 Sleep Sequence ........................................................ 32 Low Power in Sleep Mode......................................... 33 Wakeup Sequence .................................................... 33 Low Voltage Detect Control........................................... 35 POR Compare State ................................................. 36 ECO Trim Register .................................................... 36 General Purpose I/O Ports............................................. 37 Port Data Registers ................................................... 37 GPIO Port Configuration ........................................... 38 GPIO Configurations for Low Power Mode ............... 43 Serial Peripheral Interface (SPI)................................ 44 SPI Data Register...................................................... 45 SPI Configure Register.............................................. 45 SPI Interface Pins...................................................... 47 Timer Registers .............................................................. 47 Registers ................................................................... 47 Interrupt Controller......................................................... 50 Architectural Description ............................................ 50 Interrupt Processing .................................................. 51 Interrupt Latency ....................................................... 51 Interrupt Registers..................................................... 51 Microcontroller Function Register Summary ............. 55 Radio Function Register Summary............................... 57 Absolute Maximum Ratings .......................................... 58 DC Characteristics (T = 25xC) ....................................... 58 AC Characteristics ........................................................ 60 RF Characteristics.......................................................... 64 Ordering Information...................................................... 66 Package Handling........................................................... 66 Package Diagram............................................................ 66 Document History Page ................................................. 67 Sales, Solutions, and Legal Information ...................... 68 Worldwide Sales and Design Support....................... 68 Page 2 of 68 [+] Feedback CYRF69103 4. Applications The CYRF69103 PRoC LP is targeted for the following applications: Wireless HID devices: Mice Remote Controls Presenter tools Barcode scanners POS terminal General purpose wireless applications: Industrial applications Home automation White goods Consumer electronics Toys The radio meets requirements: Communication between the microcontroller and the radio is through the radio's SPI interface. 6. Functional Overview The CYRF69103 is a complete Radio System-on-Chip device, providing a complete RF system solution with a single device and a few discrete components. The CYRF69103 is designed to implement low cost wireless systems operating in the worldwide 2.4 GHz Industrial, Scientific, and Medical (ISM) frequency band (2.400 GHz to 2.4835 GHz). 6.1 2.4 GHz Radio Function The SoC contains a 2.4 GHz 1 Mbps GFSK radio transceiver, packet data buffering, packet framer, DSSS baseband controller, Received Signal Strength Indication (RSSI), and SPI interface for data transfer and device configuration. The radio supports 98 discrete 1 MHz channels (regulations may limit the use of some of these channels in certain jurisdictions). In DSSS modes the baseband performs DSSS spreading/despreading, while in GFSK Mode (1 Mb/s - GFSK) the baseband performs Start of Frame (SOF), End of Frame (EOF) detection, and CRC16 generation and checking. The baseband may also be configured to automatically transmit Acknowledge (ACK) handshake packets whenever a valid packet is received. When in receive mode, with packet framing enabled, the device is always ready to receive data transmitted at any of the supported bit rates, except SDR, enabling the implementation of mixed-rate systems in which different devices use different data rates. This also enables the implementation of dynamic data rate systems, which use high data rates at shorter distances and/or in a low moderate interference environment, and change to lower data rates at longer distances and/or in high interference environments. Document #: 001-07611 Rev *F following Europe: ETSI EN 301 489-1 V1.4.1 ETSI EN 300 328-1 V1.3.1 North America: FCC CFR 47 Part 15 Japan: ARIB STD-T66 worldwide regulatory 6.2 Data Transmission Modes The radio supports four different data transmission modes: In GFSK mode, data is transmitted at 1 Mbps, without any DSSS In 8DR mode, 1 byte is encoded in each PN code symbol transmitted In DDR mode, 2 bits are encoded in each PN code symbol transmitted In SDR mode, a single bit is encoded in each PN code symbol transmitted 5. Functional Description PRoC LP devices are integrated radio and microcontroller functions in the same package to provide a dual-role single-chip solution. the Both 64-chip and 32-chip data PN codes are supported. The four data transmission modes apply to the data after the Start of Packet (SOP). In particular, the packet length, data and CRC are all sent in the same mode. 6.3 Microcontroller Function The MCU function is an 8-bit Flash-programmable microcontroller. The instruction set is optimized specifically for HID and a variety of other embedded applications. The MCU function has up to 8 Kbytes of Flash for user's code and up to 256 bytes of RAM for stack space and user variables. In addition, the MCU function includes a Watchdog timer, a vectored interrupt controller, a 16-bit Free Running Timer, and 12-bit Programmable Interrupt Timer. The microcontroller has 15 GPIO pins grouped into multiple ports. With the exception of the four radio function GPIOs, each GPIO port supports high impedance inputs, configurable pull up, open drain output, CMOS/TTL inputs and CMOS output. Up to two pins support programmable drive strength of up to 50 mA. Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller. Each GPIO port has its own GPIO interrupt vector with the exception of GPIO Port 0. GPIO Port 0 has two dedicated pins that have independent interrupt vectors (P0.3 - P0.4). The microcontroller features an internal oscillator. The PRoC LP includes a Watchdog timer, a vectored interrupt controller, a 12-bit programmable interval timer with configurable 1 ms interrupt and a 16-bit free running timer. In addition, the CYRF69103 IC has a Power Management Unit (PMU), which enables direct connection of the device to any battery voltage in the range 1.8V to 3.6V. The PMU conditions the battery voltage to provide the supply voltages required by the device and may supply external devices. Page 3 of 68 [+] Feedback CYRF69103 6.4 Backward Compatibility The CYRF69103 IC is fully interoperable with the main modes of the first generation Cypress radios namely the CYWUSB6934 -LS and CYWWUSB6935-LR devices. The 62.5 kbps mode is supported by selecting 32 chip DDR mode. Similarly, the 15.675 kbps mode is supported by selecting 64 chip SDR mode In this method, a suitably configured CYRF69103 IC device may transmit data to or receive data from a first generation device, or both. Backwards compatibility requires disabling the SOP, length, and CRC16 fields. This section provides the different configurations of the registers and firmware that enable a new generation radio to communicate with a first generation radio. There are two possible modes: SDR and DDR mode (8-DR and GFSK modes are not present in the first generation radio). The second generation radio must be initialized using the RadioInitAPI of the LP radio driver and then the following registers' bits need to be configured to the given Byte values. Essentially, the following deactivates the added features of the second generation radio and takes it down to the level of the first generation radio. The data format, data rates, and the PN codes used are recognizable by the first generation radio. 6.5 DDR Mode Table 6-1. DDR Mode Register Value Description TX_CFG_ADR 0X16 32 chip PN Code, DDR, PA = 6 RX_CFG_ADR 0X4B AGC is enabled. LNA and attenuator are disabled. Fast turnaround is disabled, the device uses high side receive injection and Hi-Lo is disabled. Overwrite to receive buffer is enabled and the RX buffer is configured to receive eight bytes maximum. XACT_CFG_ADR 0X05 AutoACK is disabled. Forcing end state is disabled. The device is configured to transition to Idle mode after a Receive or Transmit. ACK timeout is set to 128 s. FRAMING_CFG_ADR 0X00 All SOP and framing features are disabled. Disable LEN_EN=0 if EOP is needed. TX_OVERRIDE_ADR 0X04 Disable Transmit CRC-16. RX_OVERRIDE_ADR 0X14 The receiver rejects packets with a zero seed. The Rx CRC-16 Checker is disabled and the receiver accepts bad packets that do not match the seed in CRC_seed registers. This helps in communication with the first generation radio that does not have CRC capabilities. ANALOG_CTRL_ADR 0X01 Set ALL SLOW. When set, the synthesizer settle time for all channels is the same as the slow channels in the first generation radio. DATA32_THOLD_ADR 0X03 Sets the number of allowed corrupted bits to 3. EOP_CTRL_ADR 0x01 Sets the number of consecutive symbols for non-correlation to detect end of packet. PREAMBLE_ADR 0xAAAA05 AAAA are the two preamble bytes. Any other byte can also be written into the preamble register file. Recommended counts of the preamble bytes to be sent must be >4. Document #: 001-07611 Rev *F Page 4 of 68 [+] Feedback CYRF69103 6.6 SDR Mode Table 6-2. SDR Mode Register Value Description TX_CFG_ADR 0X3E 64 chip PN code, SDR mode, PA = 6 RX_CFG_ADR 0X4B AGC is enabled. LNA and attenuator are disabled. Fast turnaround is disabled, the device uses high side receive injection and Hi-Lo is disabled. Overwrite to receive buffer is enabled and RX buffer is configured to receive eight bytes maximum. Enables RXOW to allow new packets to be loaded into the receive buffer. This also enables the VALID bit which is used by the first generation radio's error correction firmware. XACT_CFG_ADR 0X05 AutoACK is disabled. Forcing end state is disabled. The device is configured to transition to Idle mode after Receive or Transmit. ACK timeout is set to 128 s. FRAMING_CFG_ADR 0X00 All SOP and framing features are disabled. Disable LEN_EN=0 if EOP is needed. TX_OVERRIDE_ADR 0X04 Disable Transmit CRC-16. RX_OVERRIDE_ADR 0X14 The receiver rejects packets with a zero seed. The RX CRC-16 checker is disabled and the receiver accepts bad packets that do not match the seed in the CRC_seed registers. This helps in communication with the first generation radio that does not have CRC capabilities. ANALOG_CTRL_ADR 0X01 Set ALL SLOW. When set, the synthesizer settle time for all channels is the same as the slow channels in the first generation radio, for manual ACK consistency DATA64_THOLD_ADR 0X07 Sets the number of allowed corrupted bits to 7 which is close to the recommended 12% value. EOP_CTRL_ADR 0xA1 Sets the number of consecutive symbols for non-correlation to detect end of packet. PREAMBLE_ADR 0xAAAA09 Document #: 001-07611 Rev *F AAAA are the two preamble bytes. Any other byte can also be written into the preamble register file. Recommended counts of the preamble bytes to be sent must be >8. Page 5 of 68 [+] Feedback CYRF69103 7. Pinouts Figure 7-1. Pin Diagram PACTL / GPIO 31 P1.6 32 VIO 33 RST 34 P1.7 35 VDD_1.8 36 L/D 37 P0.7 38 VREG 40 VBAT0 39 Corner tabs 30 XOUT / GPIO P0.4 1 XTAL 2 VCC 3 P0.3 4 P0.1 5 26 P1.4 / SCK VBAT1 6 25 P1.3 / SS VCC 7 24 P1.2 P2.1 8 VBAT2 9 29 MISO / GPIO CYRF69103 WirelessUSB LP 28 P1.5 / MOSI 27 IRQ / GPIO 23 VDD_Micro 22 P1.1 * E-PAD Bottom Side 21 P1.0 RFBIAS 10 20 NC 19 RESV 18 NC 17 NC 16 VCC 15 P2.0 14 NC 13 RFN 12 GND 11 RFP Table 7-1. Pin Definitions Pin Name Description 1 P0.4 Individually configured GPIO 2 XTAL 12 MHz crystal 3, 7, 16 VCC 2.4V to 3.6V supply. Connected to pin 40 (0.047 F bypass) 4 P0.3 Individually configured GPIO 5 P0.1 Individually configured GPIO 6 Vbat1 Connect to 1.8V to 3.6V power supply, through 47 ohm series/1 F shunt C 8 P2.1 GPIO. Port 2 Bit 1 9 Vbat2 Connected to1.8V to 3.6V main power supply, through 0.047 F bypass C 10 RFbias RF pin voltage reference 11 RFp Differential RF to or from antenna 12 GND GND 13 RFn Differential RF to or from antenna 14, 17, 18, 20 NC 15 P2.0 19 RESV 21 P1.0 22 P1.1 23 VDD_micro GPIO Reserved. Must connect to GND GPIO GPIO MCU supply connected to pin 40, max CPU 12 MHz 24 P1.2 25 P1.3 / nSS 26 P1.4 / SCK 27 IRQ 28 P1.5 / MOSI 29 MISO 3-wire SPI mode configured as Radio GPIO. In 4-wire SPI mode sends data to MCU function 30 XOUT Buffered CLK, PACTL_n or Radio GPIO Document #: 001-07611 Rev *F GPIO Slave Select SPI Clock Radio Function Interrupt output, configure High, Low or as Radio GPIO MOSI pin from microcontroller function to radio function Page 6 of 68 [+] Feedback CYRF69103 Table 7-1. Pin Definitions (continued) Pin Name 31 PACTL 32 P1.6 Description Control for external PA or Radio GPIO GPIO 33 VIO 1.8V to 3.6V to main power supply rail for Radio I/O 34 RST Radio Reset. Connected to pin 40 with 0.47 F. Must have a RST=HIGH event the very first time power is applied to the radio otherwise the state of the radio control registers is unknown 35 P1.7 GPIO 36 VDD1.8 37 L/D Regulated logic bypass. Connected to 0.47 F to GND Inductor/Diode connection for Boost. When Internal PMU is not being used connect L/D to GND. 38 P0.7 GPIO 39 Vbat0 Connected to1.8V to 3.6V main power supply, through 0.047 F bypass C 40 VREG Boost regulator output voltage feedback 41 E-pad Must be connected to ground 42 Corner Tabs Do Not connect corner tabs 8. Functional Block Overview 8.3 Baseband and Framer All the blocks that make up the PRoC LP are presented in this section. The baseband and framer blocks provide the DSSS encoding and decoding, SOP generation and reception and CRC16 generation and checking, and EOP detection and length field. 8.1 2.4 GHz Radio 8.3.1 Data Transmission Modes and Data Rates The radio transceiver is a dual conversion low IF architecture optimized for power and range/robustness. The radio employs channel matched filters to achieve high performance in the presence of interference. An integrated Power Amplifier (PA) provides up to +4 dBm transmit power, with an output power control range of 34 dB in seven steps. The supply current of the device is reduced as the RF output power is reduced. The SoC supports four different data transmission modes: Table 8-1. Internal PA Output Power Step Table PA Setting Typical Output Power (dBm) 7 +4 6 0 In GFSK mode, data is transmitted at 1 Mbps, without any DSSS. In 8DR mode, 8 bits are encoded in each DATA_CODE_ADR derived code symbol transmitted. In DDR mode, 2 bits are encoded in each DATA_CODE_ADR derived code symbol transmitted (as in the CYWUSB6934 DDR mode). In SDR mode, 1 bit is encoded in each DATA_CODE_ADR derived code symbol transmitted (as in the CYWUSB6934 standard modes). 5 -5 4 -10 3 -15 2 -20 Both 64-chip and 32-chip DATA_CODE_ADR codes are supported. The four data transmission modes apply to the data after the SOP. In particular the length, data, and CRC16 are all sent in the same mode. In general, lower data rates reduces packet error rate in any given environment. 1 -25 The CYRF69103 IC supports the following data rates: 0 -30 1000 kbps (GFSK) 8.2 Frequency Synthesizer 250 kbps (32-chip 8DR) Before transmission or reception may commence, it is necessary for the frequency synthesizer to settle. The settling time varies depending on channel; 25 fast channels are provided with a maximum settling time of 100 s. 125 kbps (64-chip 8DR) 62.5 kbps (32-chip DDR) 31.25 kbps (64-chip DDR) 15.625 kbps (64-chip SDR) 3rd The "fast channels" (<100 s settling time) are every frequency, starting at 2400 MHz up to and including 2472 MHz (that is, 0,3,6,9.......69 and 72). Document #: 001-07611 Rev *F Lower data rates typically provide longer range and/or a more robust link. Page 7 of 68 [+] Feedback CYRF69103 8.3.2 Link Layer Modes The CYRF69103 IC device supports the following data packet framing features: SOP - Packets begin with a 2-symbol Start of Packet (SOP) marker. This is required in GFSK and 8DR modes, but is optional in DDR mode and is not supported in SDR mode. If framing is disabled then an SOP event is inferred whenever two successive correlations are detected. The SOP_CODE_ADR code used for the SOP is different from that used for the "body" of the packet, and if desired may be a different length. SOP must be configured to be the same length on both sides of the link. EOP - There are two options for detecting the end of a packet. If SOP is enabled, then a packet length field may be enabled. GFSK and 8DR must enable the length field. This is the first 8 bits after the SOP symbol, and is transmitted at the payload data rate. If the length field is enabled, an End of Packet (EOP) condition is inferred after reception of the number of bytes defined in the length field, plus two bytes for the CRC16 (if enabled). The alternative to using the length field is to infer an EOP condition from a configurable number of successive non correlations; this option is not available in GFSK mode and is only recommended when using SDR mode. CRC16 - The device may be configured to append a 16-bit CRC16 to each packet. The CRC16 uses the USB CRC polynomial with the added programmability of the seed. If enabled, the receiver verifies the calculated CRC16 for the payload data against the received value in the CRC16 field. The starting value for the CRC16 calculation is configurable, and the CRC16 transmitted may be calculated using either the loaded seed value or a zero seed; the received data CRC16 is checked against both the configured and zero CRC16 seeds. CRC16 detects the following errors: Any one bit in error Any two bits in error (no matter how far apart, which column, and so on) Any odd number of bits in error (no matter where they are) An error burst as wide as the checksum itself Figure 8-1. shows an example packet with SOP, CRC16 and lengths fields enabled. Figure 8-1. Example Default Packet Format P re a m b le n x 16us P 2 n d F ra m in g S y m b o l* SOP 1 SOP 2 1 s t F ra m in g S y m b o l* L e n g th P a y lo a d D a ta Packet le n g th 1 B y te P e rio d C R C 16 * N o te :3 2 o r 6 4 u s 8.4 Packet Buffers and Radio Configuration Registers 8.5 Auto Transaction Sequencer (ATS) Packet data and configuration registers are accessed through the SPI interface. All configuration registers are directly addressed through the address field in the SPI packet (as in the CYWUSB6934). Configuration registers are provided to allow configuration of DSSS PN codes, data rate, operating mode, interrupt masks, interrupt status, and others. The CYRF69103 IC provides automated support for transmission and reception of acknowledged data packets. 8.4.1 Packet Buffers All data transmission and reception use the 16-byte packet buffers: one for transmission and one for reception. The transmit buffer allows a complete packet of up to 16 bytes of payload data to be loaded in one burst SPI transaction, and then transmitted with no further MCU intervention. Similarly, the receive buffer allows an entire packet of payload data up to 16 bytes to be received with no firmware intervention required until packet reception is complete. The CYRF69103 IC supports packet length of up to 40 bytes; interrupts are provided to allow an MCU to use the transmit and receive buffers as FIFOs. When transmitting a packet longer than 16 bytes, the MCU can load 16 bytes initially, and add further bytes to the transmit buffer as transmission of data creates space in the buffer. Similarly, when receiving packets longer than 16 bytes, the MCU must fetch received data from the FIFO periodically during packet reception to prevent it from overflowing. Document #: 001-07611 Rev *F When transmitting a data packet, the device automatically starts the crystal and synthesizer, enters transmit mode, transmits the packet in the transmit buffer, and then automatically switches to receive mode and waits for a handshake packet--and then automatically reverts to sleep mode or idle mode when either an ACK packet is received, or a time out period expires. Similarly, when receiving in transaction mode, the device waits in receive mode for a valid packet to be received, then automatically transitions to transmit mode, transmits an ACK packet, and then switches back to receive mode to await the next packet. The contents of the packet buffers are not affected by the transmission or reception of ACK packets. In each case, the entire packet transaction takes place without any need for MCU firmware action; to transmit data the MCU simply needs to load the data packet to be transmitted, set the length, and set the TX GO bit. Similarly, when receiving packets in transaction mode, firmware simply needs to retrieve the fully received packet in response to an interrupt request indicating reception of a packet. Page 8 of 68 [+] Feedback CYRF69103 8.6 Interrupts 8.9 Power On Reset/Low Voltage Detect The radio function provides an interrupt (IRQ) output, which is configurable to indicate the occurrence of various different events. The IRQ pin may be programmed to be either active high or active low, and be either a CMOS or open drain output. The power on reset circuit detects logic when power is applied to the device, resets the logic to a known state, and begins executing instructions at Flash address 0x0000. When power falls below a programmable trip voltage, it generates reset or may be configured to generate interrupt. There is a low voltage detect circuit that detects when VCC drops below a programmable trip voltage. It may be configurable to generate an LVD interrupt to inform the processor about the low voltage event. POR and LVD share the same interrupt. There is not a separate interrupt for each. The Watchdog timer can be used to ensure the firmware never gets stalled in an infinite loop. The radio function features three sets of interrupts: transmit, receive, and system interrupts. These interrupts all share a single pin (IRQ), but can be independently enabled/disabled. In transmit mode, all receive interrupts are automatically disabled, and in receive mode all transmit interrupts are automatically disabled. However, the contents of the enable registers are preserved when switching between transmit and receive modes. If more than one radio interrupt is enabled at any time, it is necessary to read the relevant status register to determine which event caused the IRQ pin to assert. Even when a given interrupt source is disabled, the status of the condition that would otherwise cause an interrupt can be determined by reading the appropriate status register. It is therefore possible to use the devices without making use of the IRQ pin by polling the status register(s) to wait for an event, rather than using the IRQ pin. 8.7 Clocks A 12 MHz crystal (30 ppm or better) is directly connected between XTAL and GND without the need for external capacitors. A digital clock out function is provided, with selectable output frequencies of 0.75, 1.5, 3, 6, or 12 MHz. This output may be used to clock an external microcontroller (MCU) or ASIC. This output is enabled by default, but may be disabled. The requirements for the crystal to be directly connected to XTAL pin and GND are: Nominal Frequency: 12 MHz Operating Mode: Fundamental Mode Resonance Mode: Parallel Resonant Frequency Initial Stability: 30 ppm Series Resistance: <60 ohms Load Capacitance: 10 pF Drive Level: l00 W The MCU function features an internal oscillator. The clock generator provides the 12 MHz and 24 MHz clocks that remain internal to the microcontroller. 8.8 GPIO Interface The MCU function features up to 15 general purpose I/O (GPIO) pins.The I/O pins are grouped into three ports (Port 0 to 2). The pins on Port 0 and Port 1 may each be configured individually while the pins on Port 2 may only be configured as a group. Each GPIO port supports high-impedance inputs, configurable pull up, open drain output, CMOS/TTL inputs, and CMOS output with up to two pins that support programmable drive strength of up to 50 mA sink current. Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller. Each GPIO port has its own GPIO interrupt vector with the exception of GPIO Port 0. GPIO Port 0 has three dedicated pins that have independent interrupt vectors (P0.1, P0.3-P0.4). Document #: 001-07611 Rev *F 8.10 Timers The free running 16-bit timer provides two interrupt sources: the programmable interval timer with 1-s resolution and the 1.024 ms outputs. The timer can be used to measure the duration of an event under firmware control by reading the timer at the start and at the end of an event, then calculating the difference between the two values. 8.11 Power Management The operating voltage of the device is 1.8V to 3.6V DC, which is applied to the VBAT pin. The device can be shut down to a fully static sleep mode by writing to the FRC END = 1 and END STATE = 000 bits in the XACT_CFG_ADR register over the SPI interface. The device enters sleep mode within 35 s after the last SCK positive edge at the end of this SPI transaction. Alternatively, the device may be configured to automatically enter sleep mode after completing packet transmission or reception. When in sleep mode, the on-chip oscillator is stopped, but the SPI interface remains functional. The device wakes from sleep mode automatically when the device is commanded to enter transmit or receive mode. When resuming from sleep mode, there is a short delay while the oscillator restarts. The device may be configured to assert the IRQ pin when the oscillator has stabilized. The output voltage (VREG) of the Power Management Unit (PMU) is configurable to several minimum values between 2.4V and 2.7V. VREG may be used to provide up to 15 mA (average load) to external devices. It is possible to disable the PMU, and to provide an externally regulated DC supply voltage to the device in the range 2.4V to 3.6V. The PMU also provides a regulated 1.8V supply to the logic. The PMU has been designed to provide high boost efficiency (74-85% depending on input voltage, output voltage and load) when using a Schottky diode and power inductor, eliminating the need for an external boost converter in many systems where other components require a boosted voltage. However, reasonable efficiencies (69-82% depending on input voltage, output voltage and load) may be achieved when using low-cost components such as SOT23 diodes and 0805 inductors. The current through the diode must stay within the linear operating range of the diode. For some loads the SOT23 diode is sufficient, but with higher loads it is not and a SS12 diode must be used to stay within this linear range of operation. Along with the diode, the inductor used must not saturate its core. In higher loads, a lower resistance/higher saturation coil like the inductor from Sumida must be used. Page 9 of 68 [+] Feedback CYRF69103 Figure 8-3. PMU Disabled - Linear Regulator VCC 0.047F The following three figures show different examples of how to use PRoC LP with and without the PMU. Figure 8-2. shows the most common circuit making use of the PMU to boost battery voltage up to 2.7V. Figure 8-3. is an example of the circuit used when the supply voltage is always above 2.7V. This could be three 1.5V battery cells in series along with a linear regulator, or some similar power source. Figure 8-4. shows an example of using the PRoC LP with its PMU disabled and an external boost to supply power to the device. This might be required when the load is much greater than the 15 mA average load that PRoC can support. 0.047F 0.047F 0.047F 0.047F VCC3 VCC2 VCC1 VReg VIO VBat0 VBat2 0.047F VDD Figure 8-2. PMU Enabled VBat 0.047F 0.047F VBat1 The PMU also provides a configurable low battery detection function which may be read over the SPI interface. One of seven thresholds between 1.8V and 2.7V may be selected. The interrupt pin may be configured to assert when the voltage on the VBAT pin falls below the configured threshold. LV IRQ is not a latched event. Battery monitoring is disabled when the device is in sleep mode. PRoC LP VDD_MICRO VCC 1 Ohm 1% 10 F 6.3V L/D 0.047 F 1 F 6.3V 0.047 F 0.047F 0.047 F Figure 8-4. PMU Disabled - External Boost Converter VCC VCC3 VCC2 VCC1 VReg VIO VBat0 VBat1 VBat2 0.047 F VDD 1 Ohm 1% 10F 6.3V 47 Ohm PRoC LP VDD_MICRO 0.047F 0.047F 1F 6.3V 0.1F 0.047F 0.047F L/D 0.047F 10 H BAT400D VCC2 VCC1 VReg VIO VBat0 VBat2 VCC VBat1 0.047F VBat 100 F 10V V Bat External DC-DC Boost Converter VCC3 47 Ohm 0.1F 0.047 F 10 F 6.3V VDD VDD_MICRO PRoC LP L/D 0.1F Document #: 001-07611 Rev *F Page 10 of 68 [+] Feedback CYRF69103 MOSI The gain of the receiver may be controlled directly by clearing the AGC EN bit and writing to the Low Noise Amplifier (LNA) bit of the RX_CFG_ADR register. When the LNA bit is cleared, the receiver gain is reduced by approximately 20 dB, allowing accurate reception of very strong received signals (for example when operating a receiver very close to the transmitter). An additional 20 dB of receiver attenuation can be added by setting the Attenuation (ATT) bit; this allows data reception to be limited to devices at very short ranges. Disabling AGC and enabling LNA is recommended unless receiving from a device using external PA. Figure 9-1. 3-Wire SPI Mode Radio Function MCU Function P1.5/MOSI The RSSI register returns the relative signal strength of the on-channel signal power. When receiving, the device may be configured to automatically measure and store the relative strength of the signal being received as a 5-bit value. When enabled, an RSSI reading is taken and may be read through the SPI interface. An RSSI reading is taken automatically when the start of a packet is detected. In addition, a new RSSI reading is taken every time the previous reading is read from the RSSI register, allowing the background RF energy level on any given channel to be easily measured when RSSI is read when no signal is being received. A new reading can occur as fast as once every 12 s. SCK nSS 8.12 Low Noise Amplifier (LNA) and Received Signal Strength Indication (RSSI) MOSI MOSI/MISO multiplexed on one MOSI pin P1.4/SCK SCK P1.3/nSS nSS 9.2 4-Wire SPI Interface The 4-wire SPI communications interface consists of MOSI, MISO, SCK, and SS. The radio function receives a clock from the MCU function on the SCK pin. The MOSI pin is multiplexed with the MISO pin. Bidirectional data transfer takes place between the MCU function and the radio function through this multiplexed MOSI pin. When using this mode the user firmware must ensure that the MOSI pin on the MCU function is in a high impedance state, except when the MCU is actively transmitting data. Firmware must also control the direction of data flow and switch directions between MCU function and radio function by setting the SWAP bit [Bit 7] of the SPI Configure Register. The SS pin is asserted before initiating a data transfer between the MCU function and the radio function. The IRQ function may be optionally multiplexed with the MOSI pin; when this option is enabled the IRQ function is not available while the SS pin is low. When using this configuration, user firmware must ensure that the MOSI function on MCU function is in a high-impedance state whenever SS is high. SCK Figure 9-2. 4-Wire SPI Mode nSS 9.1 3-Wire SPI Interface MOSI The SPI interface between the MCU function and the radio function is a 3-wire SPI Interface. The three pins are MOSI (Master Out Slave In), SCK (Serial Clock), SS (Slave Select). There is an alternate 4-wire MISO Interface that requires the connection of two external pins. The SPI interface is controlled by configuring the SPI Configure Register. (SPICR Addr: 0x3D). The device receives SCK from the MCU function on the SCK pin. Data from the MCU function is shifted in on the MOSI pin. Data to the MCU function is shifted out on the MISO pin. The active low SS pin must be asserted for the two functions to communicate. The IRQ function may be optionally multiplexed with the MOSI pin; when this option is enabled the IRQ function is not available while the SS pin is low. When using this configuration, user firmware must ensure that the MOSI function on MCU function is in a high-impedance state whenever SS is high. 9. SPI Interface Radio Function MCU Function P1.6/MISO P1.5/MOSI MOSI P1.4/SCK SCK P1.3/nSS nSS MISO This connection is external to the PRoC LP Chip Document #: 001-07611 Rev *F Page 11 of 68 [+] Feedback CYRF69103 9.3 SPI Communication and Transactions The SPI transactions can be single byte or multi-byte. The MCU function initiates a data transfer through a Command/Address byte. The following bytes are data bytes. The SPI transaction format is shown in Figure 9-1. The DIR bit specifies the direction of data transfer. 0 = Master reads from slave. 1 = Master writes to slave. The INC bit helps to read or write consecutive bytes from contiguous memory locations in a single burst mode operation. If Slave Select is asserted and INC = 1, then the master MCU function reads a byte from the radio, the address is incremented by a byte location, and then the byte at that location is read, and so on. If Slave Select is asserted and INC = 0, then the MCU function reads/writes the bytes in the same register in burst mode, but if it is a register file then it reads/writes the bytes in that register file. The SPI interface between the radio function and the MCU is not dependent on the internal 12 MHz oscillator of the radio. Therefore, radio function registers can be read from or written into while the radio is in sleep mode. 9.4 SPI I/O Voltage References The SPI interfaces between MCU function and the radio and the IRQ and RST have a separate voltage reference VIO. For CYRF69103 VIO is normally set to VCC. 9.5 SPI Connects to External Devices The three SPI wires, MOSI, SCK, and SS are also drawn out of the package as external pins to allow the user to interface their own external devices (such as optical sensors and others) through SPI. The radio function also has its own SPI wires MISO and IRQ, which can be used to send data back to the MCU function or send an interrupt request to the MCU function. They can also be configured as GPIO pins. Table 9-1. SPI Transaction Format Byte 1 Bit # Bit Name Byte 1+N 7 6 [5:0] [7:0] DIR INC Address Data 10. CPU Architecture This family of microcontrollers is based on a high-performance, 8-bit, Harvard architecture microprocessor. Five registers control the primary operation of the CPU core. These registers are affected by various instructions, but are not directly accessible through the register space by the user. Table 10-1. CPU Registers and Register Name Register Register Name Flags CPU_F Program Counter CPU_PC Accumulator CPU_A Stack Pointer CPU_SP Index CPU_X The 16-bit Program Counter Register (CPU_PC) allows for direct addressing of the full eight Kbytes of program memory space. Document #: 001-07611 Rev *F The Accumulator Register (CPU_A) is the general-purpose register that holds the results of instructions that specify any of the source addressing modes. The Index Register (CPU_X) holds an offset value that is used in the indexed addressing modes. Typically, this is used to address a block of data within the data memory space. The Stack Pointer Register (CPU_SP) holds the address of the current top-of-stack in the data memory space. It is affected by the PUSH, POP, LCALL, CALL, RETI, and RET instructions, which manage the software stack. It can also be affected by the SWAP and ADD instructions. The Flag Register (CPU_F) has three status bits: Zero Flag bit [1]; Carry Flag bit [2]; Supervisory State bit [3]. The Global Interrupt Enable bit [0] is used to globally enable or disable interrupts. The user cannot manipulate the Supervisory State status bit [3]. The flags are affected by arithmetic, logic, and shift operations. The manner in which each flag is changed is dependent upon the instruction being executed (for example, AND, OR, XOR). See Table 13-1 on page 18. Page 12 of 68 [+] Feedback CYRF69103 11. CPU Registers 11.1 Flags Register The Flags Register can only be set or reset with logical instruction. Table 11-1. CPU Flags Register (CPU_F) [R/W] Bit # 7 Field 6 5 4 3 2 1 0 XIO Super Carry Zero Global IE Read/Write - Reserved - - R/W R RW RW RW Default 0 0 0 0 0 0 1 0 Bits 7:5 Bit 4 Reserved XIO Set by the user to select between the register banks. 0 = Bank 0 1 = Bank 1 Bit 3 Super Indicates whether the CPU is executing user code or Supervisor Code (This code cannot be accessed directly by the user). 0 = User Code 1 = Supervisor Code Bit 2 Carry Set by CPU to indicate whether there has been a carry in the previous logical/arithmetic operation. 0 = No Carry 1 = Carry Bit 1 Zero Set by CPU to indicate whether there has been a zero result in the previous logical/arithmetic operation. 0 = Not Equal to Zero 1 = Equal to Zero Bit 0 Global IE Determines whether all interrupts are enabled or disabled. 0 = Disabled 1 = Enabled Note This register is readable with explicit address 0xF7. The OR F, expr and AND F, expr must be used to set and clear the CPU_F bits. 11.2 Accumulator Register Table 11-2. CPU Accumulator Register (CPU_A) Bit # 7 6 5 Field 4 3 2 1 0 CPU Accumulator [7:0] Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Bits 7:0 CPU Accumulator [7:0] 8-bit data value holds the result of any logical/arithmetic instruction that uses a source addressing mode. Document #: 001-07611 Rev *F Page 13 of 68 [+] Feedback CYRF69103 11.3 Index Register Table 11-3. CPU X Register (CPU_X) Bit # 7 6 5 4 Field 3 2 1 0 X [7:0] Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 2 1 0 Bits 7:0 X [7:0] 8-bit data value holds an index for any instruction that uses an indexed addressing mode. 11.4 Stack Pointer Register Table 11-4. CPU Stack Pointer Register (CPU_SP) Bit # 7 6 5 4 Field 3 Stack Pointer [7:0] Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 3 2 1 0 Bits 7:0 Stack Pointer [7:0] 8-bit data value holds a pointer to the current top-of-stack. 11.5 CPU Program Counter High Register Table 11-5. CPU Program Counter High Register (CPU_PCH) Bit # 7 6 5 Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 3 2 1 0 Field 4 Program Counter [15:8] Bits 7:0 Program Counter [15:8] 8-bit data value holds the higher byte of the program counter. 11.6 CPU Program Counter Low Register Table 11-6. CPU Program Counter Low Register (CPU_PCL) Bit # 7 6 5 Field 4 Program Counter [7:0] Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Bit 7:0 Program Counter [7:0] 8-bit data value holds the lower byte of the program counter. Document #: 001-07611 Rev *F Page 14 of 68 [+] Feedback CYRF69103 12. Addressing Modes 12.3 Source Indexed Examples of the different addressing modes are discussed in this section and example code is given. 12.1 Source Immediate The result of an instruction using this addressing mode is placed in the A register, the F register, the SP register, or the X register, which is specified as part of the instruction opcode. Operand 1 is an immediate value that serves as a source for the instruction. Arithmetic instructions require two sources. Instructions using this addressing mode are two bytes in length. The result of an instruction using this addressing mode is placed in either the A register or the X register, which is specified as part of the instruction opcode. Operand 1 is added to the X register forming an address that points to a location in either the RAM memory space or the register space that is the source for the instruction. Arithmetic instructions require two sources; the second source is the A register or X register specified in the opcode. Instructions using this addressing mode are two bytes in length. Table 12-3. Source Indexed Opcode Table 12-1. Source Immediate Opcode Operand 1 Instruction Examples ADD A, Immediate Value X, 8 In this case, the immediate value of 8 is moved to the X register. AND F, 9 In this case, the immediate value of 9 is logically ANDed with the F register and the result is placed in the F register. 12.2 Source Direct The result of an instruction using this addressing mode is placed in either the A register or the X register, which is specified as part of the instruction opcode. Operand 1 is an address that points to a location in either the RAM memory space or the register space that is the source for the instruction. Arithmetic instructions require two sources; the second source is the A register or X register specified in the opcode. Instructions using this addressing mode are two bytes in length. Table 12-2. Source Direct Opcode Operand 1 Instruction MOV X, Source Index Examples ADD A, [X+7] 7 In this case, the immediate value of 7 is added with the Accumulator, and the result is placed in the Accumulator. MOV Examples ADD A, Operand 1 Instruction MOV X, In this case, the value in the memory location at address X + 7 is added with the Accumulator, and the result is placed in the Accumulator. REG[X+8] In this case, the value in the register space at address X + 8 is moved to the X register. 12.4 Destination Direct The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is an address that points to the location of the result. The source for the instruction is either the A register or the X register, which is specified as part of the instruction opcode. Arithmetic instructions require two sources; the second source is the location specified by Operand 1. Instructions using this addressing mode are two bytes in length. Table 12-4. Destination Direct Opcode Operand 1 Instruction Destination Address Source Address Examples ADD [7], [7] A In this case, the value in the memory location at address 7 is added with the Accumulator, and the result is placed in the memory location at address 7. The Accumulator is unchanged. A In this case, the Accumulator is moved to the register space location at address 8. The Accumulator is unchanged. In this case, the value in the RAM memory location at address 7 is added with the Accumulator, and the result is placed in the Accumulator. REG[8] In this case, the value in the register space at address 8 is moved to the X register. Document #: 001-07611 Rev *F MOV REG[8], Page 15 of 68 [+] Feedback CYRF69103 12.5 Destination Indexed 12.7 Destination Indexed Source Immediate The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is added to the X register forming the address that points to the location of the result. The source for the instruction is the A register. Arithmetic instructions require two sources; the second source is the location specified by Operand 1 added with the X register. Instructions using this addressing mode are two bytes in length. The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is added to the X register to form the address of the result. The source for the instruction is Operand 2, which is an immediate value. Arithmetic instructions require two sources; the second source is the location specified by Operand 1 added with the X register. Instructions using this addressing mode are three bytes in length. Table 12-5. Destination Indexed Table 12-7. Destination Indexed Source Immediate Opcode Operand 1 Instruction Destination Index Example ADD [X+7], A Opcode Instruction In this case, the value in the memory location at address X+7 is added with the Accumulator, and the result is placed in the memory location at address x+7. The Accumulator is unchanged. Examples ADD [X+7], MOV REG[X+8], 12.6 Destination Direct Source Immediate The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is the address of the result. The source for the instruction is Operand 2, which is an immediate value. Arithmetic instructions require two sources; the second source is the location specified by Operand 1. Instructions using this addressing mode are three bytes in length. Table 12-6. Destination Direct Source Immediate Opcode Instruction Operand 1 Destination Address Examples ADD [7], MOV REG[8], Operand 2 Immediate Value 6 In this case, value in the memory location at address 7 is added to the immediate value of 5, and the result is placed in the memory location at address 7. In this case, the immediate value of 6 is moved into the register space location at address 8. Document #: 001-07611 Rev *F Operand 2 Immediate Value 5 In this case, the value in the memory location at address X+7 is added with the immediate value of 5 and the result is placed in the memory location at address X+7. 6 In this case, the immediate value of 6 is moved into the location in the register space at address X+8. 12.8 Destination Direct Source Direct The result of an instruction using this addressing mode is placed within the RAM memory. Operand 1 is the address of the result. Operand 2 is an address that points to a location in the RAM memory that is the source for the instruction. This addressing mode is only valid on the MOV instruction. The instruction using this addressing mode is three bytes in length. Table 12-8. Destination Direct Source Direct Opcode 5 Operand 1 Destination Index Instruction Example MOV [7], Operand 1 Destination Address Operand 2 Source Address [8] In this case, the value in the memory location at address 8 is moved to the memory location at address 7. Page 16 of 68 [+] Feedback CYRF69103 12.9 Source Indirect Post Increment 12.10 Destination Indirect Post Increment The result of an instruction using this addressing mode is placed in the Accumulator. Operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) for the source of the instruction. The indirect address is incremented as part of the instruction execution. This addressing mode is only valid on the MVI instruction. The instruction using this addressing mode is two bytes in length. Refer to the PSoC Designer: Assembly Language User Guide for further details on MVI instruction. The result of an instruction using this addressing mode is placed within the memory space. Operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) for the destination of the instruction. The indirect address is incremented as part of the instruction execution. The source for the instruction is the Accumulator. This addressing mode is only valid on the MVI instruction. The instruction using this addressing mode is two bytes in length. Table 12-9. Source Indirect Post Increment Opcode Operand 1 Instruction Example MVI A, Source Address Address [8] In this case, the value in the memory location at address 8 is an indirect address. The memory location pointed to by the indirect address is moved into the Accumulator. The indirect address is then incremented. Document #: 001-07611 Rev *F Table 12-10. Destination Indirect Post Increment Opcode Operand 1 Instruction Example MVI [8], Destination Address Address A In this case, the value in the memory location at address 8 is an indirect address. The Accumulator is moved into the memory location pointed to by the indirect address. The indirect address is then incremented. Page 17 of 68 [+] Feedback CYRF69103 13. Instruction Set Summary Cycles Bytes Opcode Hex Cycles Bytes Opcode Hex Cycles Bytes Opcode Hex The instruction set is summarized in Table 13-1 numerically and serves as a quick reference. If more information is needed, the Instruction Set Summary tables are described in detail in the PSoC Designer Assembly Language User Guide (available on www.cypress.com). Table 13-1. Instruction Set Summary Sorted Numerically by Opcode Order[1, 2] 00 15 1 SSC 2D 8 2 OR [X+expr], A Z 5A 5 2 MOV [expr], X 01 4 2 ADD A, expr C, Z 2E 9 3 OR [expr], expr Z 5B 4 1 MOV A, X 02 6 2 ADD A, [expr] C, Z 2F 10 3 OR [X+expr], expr Z 5C 4 1 MOV X, A 03 7 2 ADD A, [X+expr] C, Z 30 9 1 HALT 5D 6 2 MOV A, reg[expr] Z 04 7 2 ADD [expr], A C, Z 31 4 2 XOR A, expr Z 5E 7 2 MOV A, reg[X+expr] Z 05 8 2 ADD [X+expr], A C, Z 32 6 2 XOR A, [expr] Z 5F 10 3 MOV [expr], [expr] 06 Instruction Format Flags Instruction Format Flags Instruction Format Flags Z 9 3 ADD [expr], expr C, Z 33 7 2 XOR A, [X+expr] Z 60 5 2 MOV reg[expr], A 07 10 3 ADD [X+expr], expr C, Z 34 7 2 XOR [expr], A Z 61 6 2 MOV reg[X+expr], A 08 4 1 PUSH A 35 8 2 XOR [X+expr], A Z 62 8 3 MOV reg[expr], expr 09 4 2 ADC A, expr C, Z 36 9 3 XOR [expr], expr Z 63 9 3 MOV reg[X+expr], expr 0A 6 2 ADC A, [expr] C, Z 37 10 3 XOR [X+expr], expr Z 64 4 1 ASL A C, Z 0B 7 2 ADC A, [X+expr] C, Z 38 5 2 ADD SP, expr 65 7 2 ASL [expr] C, Z 0C 7 2 ADC [expr], A C, Z 39 5 2 CMP A, expr 8 2 ASL [X+expr] C, Z 0D 8 2 ADC [X+expr], A C, Z 3A 7 2 CMP A, [expr] if (A=B) Z=1 66 if (A