19-6261; Rev 7; 11/18
Benets and Features
●High Integration Saves Space and BOM Cost
• Ecient, Integrated DC-DC Converter (with
Integrated Switches)
• Built-In Output-Voltage Monitoring
• Protects Against Overload, Output Short Circuit,
Output Overvoltage, and Overtemperature
• Integrated TVS Diode Withstands Cable
Discharge Event (CDE)
• Internal LDO Regulator with Up to 100mA Load
(MAX5987A)
●IEEE 802.3af-Compliant Features Reduce Design Time
• PoE Class 1/Class 2 Classication Set with
Single Resistor
• Intelligent Maintain Power Signature (MPS)
Complies with IEEE 802.3af Specication
• Simplied Wall Adapter Interface
• Pass 2kV, 200m CAT-6 Cable Discharge Event
● High Efficiency During Light Loads Reduces Power
Consumption
• Sleep and Ultra-Low-Power Mode (MAX5986A/
MAX5986B/MAX5986C)
• Frequency Foldback for High-Eciency Light-Load
Operation
• Back-Bias Capability to Optimize the Eciency
● Robust Performance
• 8.7V to 60V Wide Input Voltage Range
• Hiccup-Mode Runaway Current Limit
• 49mA (typ) Inrush Current Limit
• Open-Drain RESET Output (MAX5987A)
● Flexible and Easy to Design With
• 3.0V to 14V Programmable Output Voltage Range
• Internal Compensation
• Fixed 215kHz/430kHz Switching Frequency
• Fixed 3.3V or Adjustable Output Voltage through
an External Resistive Divider
General Description
The MAX5986A–MAX5986C/MAX5987A provide a
complete power-supply solution as IEEE® 802.3af-
compliant Class 1/Class 2 Powered Devices (PDs) in a
Power-over-Ethernet (PoE) system. The devices integrate
the PD interface with an efficient DC-DC converter, offering
a low external part count PD solution. The MAX5987A
includes a low-dropout regulator and the MAX5986A–
MAX5986C include sleep and ultra-low power modes.
The PD interface provides a detection signature and
a Class 1/Class 2 classification signature with a single
external resistor. The PD interface also provides an
isolation power MOSFET, a 60mA (max) inrush current
limit, and a 323mA operating current limit.
The integrated step-down DC-DC converter uses a peak
current-mode control scheme and provides an easy-to-
implement architecture with a fast transient response.
The step-down converter operates in a wide input voltage
range from 8.7V to 60V and supports up to 6.49W
of input power. The MAX5986A/MAX5986B/MAX5987A
operate at a fixed 215kHz switching frequency and
the MAX5986C operates at a fixed 430kHz switching
frequency. The DC-DC converter operates at a fixed
switching frequency, with an efficiency-boosting
frequency foldback that reduces the switching frequency
by half at light loads.
The devices feature an input undervoltage-lockout
(UVLO) with wide hysteresis and long deglitch time
to compensate for twisted-pair cable resistive drop
and to assure glitch-free transition during power-on/off
conditions. The devices also feature overtemperature
shutdown, short-circuit protection, output overvoltage
protection, and hiccup current limit for enhanced perfor-
mance and reliability.
The MAX5986A–MAX5986C/MAX5987A are available
in a 16-pin, 5mm x 5mm, TQFN power package and
operate over the -40°C to +85°C temperature range.
Ordering Information appears at end of data sheet.
Applications
● IEEE 802.3af-Powered Devices
●IP Phones
● Wireless Access Nodes
● IP Security Cameras
● WiMAX® Base Stations
Click here for production status of specic part numbers.
IEEE is a registered service mark of the Institute of Electrical
and Electronics Engineers, Inc.
WiMAX is a registered certification mark and registered service
mark of WiMAX Forum.
MAX5986A–MAX5986C/
MAX5987A
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, PDs with Integrated
DC-DC Converter
EVALUATION KIT AVAILABLE
(Note 2)
Junction-to-Ambient Thermal Resistance (qJA) ..............35°C/W
Junction-to-Case Thermal Resistance (qJC) ..................2.7°C/W
(All voltages referenced to GND, unless otherwise noted.)
VDD to GND ...........................................................-0.3V to +70V
(100V, 100ms, RTEST = 3.3kω) (Note 1)
VCC, WAD, RREF to GND ........................ -0.3V to (VDD + 0.3V)
AUX, LDO_IN, LED to GND .................................... -0.3V to 16V
LDO_OUT to GND .............................. -0.3V to (LDO_IN + 0.3V)
LDO_FB to GND ...................................................... -0.3V to +6V
LX to GND ................................................ -0.3V to (VCC + 0.3V)
LDO_OUT, VDRV, FB, RESET, WK, SL, ULP,
MPS, CLASS2 to GND .........................................-0.3V to +6V
VDRV to VDD ............................................. -0.3V to (VDD + 0.3V)
PGND to GND ......................................................-0.3V to +0.3V
LX Total RMS Current ...........................................................1.6A
Continuous Power Dissipation (TA = + 70NC)
TQFN (derate 28.6mW/NC above +70NC) ..............2285.7mW
Operating Temperature Range .......................... -40NC to +85NC
Junction Temperature .....................................................+150NC
Storage Temperature Range ............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
(VDD = 48V, RSIG = 24.9kω, LED, VCC, SL, ULP, WK, RESET, LDO_OUT unconnected, WAD = LDO_EN = LDO_IN = PGND = GND,
C1 = 68nF, C2 = 10µF, C3 = 1µF (see Figure 3), VFB = VAUX = 0V, LX unconnected. VCLASS2 = 0V, VMPS = 0V. All voltages are
referenced to GND, unless otherwise noted. TA = TJ = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
(Note 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER DEVICE (PD) INTERFACE
DETECTION MODE
Input Offset Current IOFFSET VVDD = 1.4V to 10.1V (Note 4) 10 FA
Effective Differential Input
Resistance dR VVDD = 1.4V to 10.1V with 1V step,
(Note 5) 23.95 25.5 kI
CLASSIFICATION MODE
Classification Enable Threshold VTH,CLS,EN VDD rising 10.2 11.5 12.5 V
Classification Disable Threshold VTH,CLS,DIS VDD rising 22 23 23.8 V
Classification Stability Time 2 ms
Classification Current ICLASS VDD = 12.6V
to 20V
CLASS2 = GND 9.12 10.5 11.88 mA
CLASS2 = VDRV 16.1 18 20.9
POWER MODE
VDD Supply Voltage Range VDD 60 V
VDD Supply Current IDD VDD = 60V
MAX5986A/B/
MAX5987A 3.6 4.5 mA
MAX5986C 4.8 6.6
MAX5986A–MAX5986C/
MAX5987A
IEEE 802.3af-Compliant, High-Eciency,
Class 1/Class 2, PDs with Integrated
DC-DC Converter
www.maximintegrated.com Maxim Integrated
│
2
Electrical Characteristics
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Package Thermal Characteristics
Note 1: See Figure 1, Test Circuit.
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-lay-
er board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
(VDD = 48V, RSIG = 24.9kω, LED, VCC, SL, ULP, WK, RESET, LDO_OUT unconnected, WAD = LDO_EN = LDO_IN = PGND = GND,
C1 = 68nF, C2 = 10µF, C3 = 1µF (see Figure 3), VFB = VAUX = 0V, LX unconnected. VCLASS2 = 0V, VMPS = 0V. All voltages are
referenced to GND, unless otherwise noted. TA = TJ = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
(Note 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VDD Turn-On Voltage VON VDD rising MAX5986A/B/C 34.3 35.7 37.6 V
MAX5987A 37.2 38.7 40
VDD Turn-Off Voltage VOFF VDD falling 30 31.4 V
VDD Turn-On/Off Hysteresis VHYST_UVLO (Note 6) MAX5986A/B/C 3.4 4.2 V
MAX5987A 7.2
VDD Deglitch Time tOFF_DLY VDD falling from 40V to 20V (Note 5) 150 Fs
Inrush to Operating Mode Delay tDELAY tDELAY = time from a (VDD - VCC) 1.5V
to 0V 123 ms
Isolation Power MOSFET
On-Resistance RON_ISO IVCC = 100mA TJ = +25NC 1.2 I
TJ = +85NC 1.5
MAINTAIN POWER SIGNATURE (MPS = VDRV)
PoE MPS Current Rising Threshold IMPS_RISE 18 28.7 40 mA
PoE MPS Current Falling
Threshold IMPS_FALL 14 24 35 mA
PoE MPS Current Threshold
Hysteresis IMPS_HYS 4.3 mA
PoE MPS Output Average Current IMPS_AVE 4.8 mA
PoE MPS Peak Output Current IMPS_PEAK 10 12.6 mA
PoE MPS Time High tMPS_HIGH 95 ms
PoE MPS Time Low tMPS_LOW 190 ms
CURRENT LIMIT
Inrush Current Limit IINRUSH During initial turn-on period,
VDD - VCC = 4V, measured at VCC 39 49 60 mA
Current Limit During Normal
Operation ILIM After inrush completed, VCC = VDD -
1.5V, measured at VCC
290 323 360 mA
WAD Detection Rising Threshold VWAD_RISE (Note 9) 8.8 V
WAD Detection Falling Threshold VWAD_FALL (Note 9) 5.8 V
WAD Detection Hysteresis 0.6 V
WAD Input Current IWAD VWAD = 24V 125 FA
MAX5986A–MAX5986C/
MAX5987A
IEEE 802.3af-Compliant, High-Eciency,
Class 1/Class 2, PDs with Integrated
DC-DC Converter
www.maximintegrated.com Maxim Integrated
│
3
Electrical Characteristics (continued)
(VDD = 48V, RSIG = 24.9kω, LED, VCC, SL, ULP, WK, RESET, LDO_OUT unconnected, WAD = LDO_EN = LDO_IN = PGND = GND,
C1 = 68nF, C2 = 10µF, C3 = 1µF (see Figure 3), VFB = VAUX = 0V, LX unconnected. VCLASS2 = 0V, VMPS = 0V. All voltages are
referenced to GND, unless otherwise noted. TA = TJ = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
(Note 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
LOGIC
CLASS2, MPS Voltage Rising
Threshold 2.9 V
CLASS2, MPS Voltage Falling
Threshold 0.4 V
RESET Output Voltage Low
(MAX5987A Only) ISINK = 1mA 0.2 V
CLASS2, MPS Leakage -10 +10 FA
INTERNAL REGULATOR WITH BACK BIAS
VAUX Input Voltage Range VAUX Inferred from VAUX input current 4.75 14 V
VAUX Input Current VAUX from 4.75V to 14V 0.65 3.1 mA
VDRV Output Voltage 4.2 5.5 V
SLEEP MODE (MAX5986A–MAX5986C)
WK and ULP Logic Threshold VTH VWK falling and VULP rising and falling 1.6 2.9 V
SL Logic Threshold Falling 0.55 0.8 V
SL Current V SL = 0V 62.5 FA
LED Current Amplitude ILED
R SL = 121kI, VLED = 6.5V 5.3
mA
R SL = 60.4kI, VLED = 6.5V 9.2 10.6 12
R SL = 30.2kI, VLED = 6.5V 19.2 21.2 23.5
R SL = 30.2kI, VLED = 3.5V 21.2
LED Current Programmable Range 10 20 mA
LED Current with Grounded SL V SL = 0V 20.6 26.4 31.4 mA
LED Current Frequency fILED Sleep and ultra-low
power modes MAX5986B/C 250 Hz
LED Current Duty Cycle DILED Sleep and ultra-low
power modes MAX5986B/C 25 %
VDD Current Amplitude IVDD Sleep mode, VLED = 6.5V 10 12 14.5 mA
Internal Current Duty Cycle DIVDD Sleep and ultra-low power modes 75 %
Internal Current Enable Time tMPS Ultra-low power mode 76 87 98 ms
Internal Current Disable Time tMPDO Ultra-low power mode 205 235 265 ms
THERMAL SHUTDOWN
Thermal Shutdown Threshold TSD TJ rising 151 NC
Thermal Shutdown Hysteresis TSD,HYS 16 NC
MAX5986A–MAX5986C/
MAX5987A
IEEE 802.3af-Compliant, High-Eciency,
Class 1/Class 2, PDs with Integrated
DC-DC Converter
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│
4
Electrical Characteristics (continued)
(VDD = 48V, RSIG = 24.9kω, LED, VCC, SL, ULP, WK, RESET, LDO_OUT unconnected, WAD = LDO_EN = LDO_IN = PGND = GND,
C1 = 68nF, C2 = 10µF, C3 = 1µF (see Figure 3), VFB = VAUX = 0V, LX unconnected. VCLASS2 = 0V, VMPS = 0V. All voltages are
referenced to GND, unless otherwise noted. TA = TJ = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
(Note 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
LDO (MAX5987A)
Input Voltage Range Inferred from line regulation 4.5 14 V
Output Voltage LDO_FB = VDRV 3.3 V
Max Output Voltage Setting With external divider to LDO_FB 5.5 V
LDO FB Regulation Voltage 1.2 1.227 1.25 V
LDO FB Leakage Current ±1 FA
Dropout VLDO_IN = 5V, VLDO_FB = VDRV,
ILOAD = 80mA 300 mV
Load Regulation ILOAD from 1mA to 80mA 0.5 mV/mA
Line Regulation VLDO_IN from 4.5V to 14V 1.4 mV/V
Overcurrent Protection Threshold IOVC 85 mA
LDO_FB Rising Threshold 3.2 4.2 V
LDO_FB Falling Threshold 2.0 2.4 V
DC-DC CONVERTER INPUT SUPPLY
VDD Voltage Range VDD,RISING VCC = VDD = VWAD - 0.3V, rising 8 60 V
VDD,FALLING VCC = VDD = VWAD - 0.3V, falling 7.7 60
POWER MOSFETs
High-Side pMOS On-Resistance RDSON-H ILX = 0.5A (sourcing) 0.54 I
Low-Side nMOS On-Resistance RDSON-L ILX = 0.5A (sinking) 0.16 I
LX Leakage Current ILX-LKG VDD = VCC = 28V,
VLX = (VPGND + 1V) to (VCC - 1V) -5 +5 FA
SOFT-START (SS)
Soft-Start Time tSS-TH 10 ms
FEEDBACK (FB)
FB Regulation Voltage VFB-RG 1.203 1.225 1.252 V
FB Input Bias Current IFB VFB = 1.224V 10 200 nA
OUTPUT VOLTAGE
Output Voltage Range VOUT
MAX5986A/MAX5987A 3.0 5.6 V
MAX5986B/MAX5986C 5.4 14
MAX5986A–MAX5986C/
MAX5987A
IEEE 802.3af-Compliant, High-Eciency,
Class 1/Class 2, PDs with Integrated
DC-DC Converter
www.maximintegrated.com Maxim Integrated
│
5
Electrical Characteristics (continued)
(VDD = 48V, RSIG = 24.9kω, LED, VCC, SL, ULP, WK, RESET, LDO_OUT unconnected, WAD = LDO_EN = LDO_IN = PGND = GND,
C1 = 68nF, C2 = 10µF, C3 = 1µF (see Figure 3), VFB = VAUX = 0V, LX unconnected. VCLASS2 = 0V, VMPS = 0V. All voltages are
referenced to GND, unless otherwise noted. TA = TJ = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
(Note 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Cycle-by-Cycle Overvoltage
Protection VOUT-OV
Rising (Note 7) 100.5 100.3 108 %
Falling (Note 7) 98.5
INTERNAL COMPENSATION NETWORK
Compensation Network Zero-
Resistance RZERO 200 kI
Compensation Network Zero-
Capacitance CZERO 150 pF
CURRENT LIMIT
Peak Current-Limit Threshold IPEAK-LIMIT
MAX5986B/
MAX5986C
CLASS2 = GND 0.75 0.81
A
CLASS2 = VDRV 0.85 0.94
MAX5986A/
MAX5987A
CLASS2 = GND 1.45 1.64
CLASS2 = VDRV 1.66 1.79
Runaway Current-Limit Threshold
MAX5986B/
MAX5986C
CLASS2 = GND 0.93
CLASS2 = VDRV 1.07
MAX5986A/
MAX5987A
CLASS2 = GND 1.9
CLASS2 = VDRV 2.2
Valley Current-Limit Threshold IVALLEY-
LIMIT
MAX5986A/MAX5987A 1.5 A
MAX5986B/MAX5986C 0.75
ZX Threshold IZX 25 mA
TIMINGS
Switching Frequency fSW
MAX5986A/MAX5986B/MAX5987A 190 215 238 kHz
MAX5986C 380 430 475
Frequency Foldback fSW-FOLD
MAX5986A/MAX5986B/MAX5987A 95 107.5 119 kHz
MAX5986C 195 215 238
Consecutive ZX Events for Entering
Foldback 8 Events
Consecutive ZX Events for Exiting
Foldback 8 Events
VOUT Undervoltage Trip Level to
Cause HICCUP VOUT-HICF After soft-start completed (Note 7) 55 60 65 %
HICCUP Timeout MAX5986A/MAX5986B/MAX5987A 154 ms
MAX5986C 77
Minimum On-Time tON-MIN 113 140 ns
LX Dead Time 14 ns
MAX5986A–MAX5986C/
MAX5987A
IEEE 802.3af-Compliant, High-Eciency,
Class 1/Class 2, PDs with Integrated
DC-DC Converter
www.maximintegrated.com Maxim Integrated
│
6
Electrical Characteristics (continued)
(VDD = 48V, RSIG = 24.9kω, LED, VCC, SL, ULP, WK, RESET, LDO_OUT unconnected, WAD = LDO_EN = LDO_IN = PGND = GND,
C1 = 68nF, C2 = 10µF, C3 = 1µF (see Figure 3), VFB = VAUX = 0V, LX unconnected. VCLASS2 = 0V, VMPS = 0V. All voltages are
referenced to GND, unless otherwise noted. TA = TJ = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
(Note 3)
Note 3: All devices are 100% production tested at TA = +25°C. Limits over temperature are guaranteed by design.
Note 4: The input offset current is illustrated in Figure 2.
Note 5: Effective differential input resistance is defined as the differential resistance between VDD and GND, see Figure 2.
Note 6: A 20V glitch on input voltage, which takes VDD below VON shorter than or equal to tOFF_DLY does not cause the device to
exit power-on mode.
Note 7 Referred to feedback regulation voltage.
Note 8: Referred to LDO feedback regulation voltage.
Note 9: The WAD Detection Rising and Falling Thresholds control the isolation power MOS transistor. To turn the DC-DC on in
WAD mode, the WAD must be detected and the VDD must be within the VDD voltage range.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
RESET (MAX5987A)
VFB Threshold for RESET Assertion VFB-OKF VFB falling (Note 7) 87 90 93 %
VFB Threshold for RESET
Deassertion VFB-OKR VFB rising (Note 7) 91.5 95 98 %
VLDO_FB Threshold for RESET
Assertion VLDO_FB-OKF VLDO_FB falling, LDO_FB = VDRV
(Note 8) 90 %
VLDO_FB Threshold for RESET
Deassertion VFB rising 95 %
for RESET Deassertion Delay 4.8 ms
RESET Output Voltage Low ISINK = 1mA 0.1 V
RESET Leakage Current ±10 FA
MAX5986A–MAX5986C/
MAX5987A
IEEE 802.3af-Compliant, High-Eciency,
Class 1/Class 2, PDs with Integrated
DC-DC Converter
www.maximintegrated.com Maxim Integrated
│
7
Electrical Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
Figure 2. Effective Differential Resistance and Offset Current
Figure 1. MAX5986A/MAX5987A Internal TVS Test Setup
IIN
IINi + 1
IINi
IOFFSET
dRi
1VVINi VINi + 1
IOFFSET = IINi - VINi
dRi
dRi = (VINi + 1 - VINi) = 1V
(IINi + 1 - IINi) (IINi + 1 - IINi)
VIN
EVALUATION
BOARD
1ms/10ms/100ms
RTEST
MAX5986A
100V
DETECTION CURRENT vs. INPUT VOLTAGE
MAX5986A toc01
INPUT VOLTAGE (V)
DETECTION CURRENT (mA)
8.97.45.94.42.9
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0
1.4 10.1
QUIESCENT CURRENT vs. SUPPLY
VOLTAGE (ULTRA-LOW POWER MODE)
MAX5986A toc02
SUPPLY VOLTAGE (V)
QUIESCENT CURRENT (mA)
55504540
2.75
3.00
3.25
3.50
3.75
4.00
2.50
35 60
SIGNATURE RESISTANCE
vs. SUPPLY VOLTAGE
MAX5986A toc03
SUPPLY VOLTAGE (V)
DIFFERENTIAL RESISTANCE (k
I)
7.45.94.42.9
23
24
25
26
27
28
22
1.4 10.18.9
INPUT OFFSET CURRENT
vs. INPUT VOLTAGE
MAX5986A toc04
SUPPLY VOLTAGE (V)
OFFSET CURRENT (µA)
7.45.94.42.9
-2
-1
0
1
2
3
-3
1.4 10.18.9
Maxim Integrated
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MAX5986A–MAX5986C/
MAX5987A
IEEE 802.3af-Compliant, High-Eciency,
Class 1/Class 2, PDs with Integrated
DC-DC Converter
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
CLASSIFICATION SETTLING TIME
MAX5986A toc06
VDD
10V/div
GND
IDD
10mA/div
0mA
400µs/div
CLASSIFICATION CURRENT
vs. INPUT VOLTAGE
MAX5986A toc05
INPUT VOLTAGE (V)
CLASSIFICATION CURRENT (mA)
18.617.115.614.1
10.42
10.44
10.46
10.48
10.50
10.52
10.54
10.56
10.58
10.60
10.40
12.6 20.0
LED CURRENT vs. RSL
MAX5986A toc08
RSL (kI)
LED CURRENT (mA)
706050403020
12
18
20
24
28
8
10 80
LED CURRENT vs. LED VOLTAGE
MAX5986A toc09
LED VOLTAGE (V)
LED CURRENT (mA)
5.253.501.75
10
15
20
25
5
0 7.00
RSL = 30.2kI
RSL = 60.4kI
EFFICIENCY vs. LOAD CURRENT
(MAX5986C, VOUT = 12V)
MAX5986A toc10
LOAD CURRENT (A)
EFFICIENCY (%)
0.60.50.1 0.2 0.3 0.4
65
70
75
80
85
90
95
100
60
0 0.7
VIN = 36V
VIN = 48V
VIN = 57V
INRUSH CURRENT LIMIT vs. VCC VOLTAGE
MAX5986A toc07
VCC (V)
INRUSH CURRENT (mA)
4236302418126
44
48
52
56
60
40
04
8
Maxim Integrated
│
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MAX5986A–MAX5986C/
MAX5987A
IEEE 802.3af-Compliant, High-Eciency,
Class 1/Class 2, PDs with Integrated
DC-DC Converter
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
5V LOAD TRANSIENT
(0% TO 50%)
MAX5986A toc13
VOUT
AC-COUPLED
50mV/div
IOUT
500mA/div
0A
100µs/div
DC-DC CONVERTER STARTUP
IOUT = 0A
MAX5986A toc15
VOUT
1V/div
VGND
2ms/div
5V LOAD TRANSIENT
(50% TO 100%)
MAX5986A toc14
VOUT
AC-COUPLED
50mV/div
IOUT
500mA/div
0A
100µs/div
DC-DC CONVERTER STARTUP
ROUT = 6.67I
MAX5986A toc16
VOUT
1V/div
VGND
2ms/div
EFFICIENCY vs. LOAD CURRENT
(MAX5986B, VOUT = 12V)
MAX5986A toc11
LOAD CURRENT (mA)
EFFICIENCY (%)
0.70.60.4 0.50.2 0.30.1
60
65
70
75
80
85
90
95
100
0
VIN = 36V
VIN = 48V
VIN = 57V
EFFICIENCY vs. LOAD CURRENT
(MAX5986A/MAX5987A, VOUT = 5V)
MAX5986A toc12
LOAD CURRENT (A)
EFFICIENCY (%)
1.0 1.1 1.20.90.80.70.5 0.6
0.2 0.3 0.40.1
60
65
70
75
80
85
90
95
100
0
VIN = 12V
VIN = 36V
VIN = 57V
VIN = 48V
MAX5986A–MAX5986C/
MAX5987A
IEEE 802.3af-Compliant, High-Eciency,
Class 1/Class 2, PDs with Integrated
DC-DC Converter
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│
10
Typical Operating Characteristics (continued)
PIN
NAME FUNCTION
MAX5986A/MAX5986B/
MAX5986C MAX5987A
1 1 AUX
Auxiliary Voltage Input. Auxiliary input to the internal regulator (VDRV). Connect
AUX to the output of the buck converter if the output voltage is greater than
4.75V to back bias the internal circuitry and increase efficiency. Connect to a
clean ground when not used.
2 2 LX Inductor Connection. Inductor connection for the internal DC-DC converter.
3 — LED LED Driver Output. In sleep mode, LED sources a periodic current (ILED) at
250Hz with 25% duty cycle.
— 3 LDO_IN LDO Input Voltage. Connect LDO_IN to output when used, otherwise connect to
GND. Connect a minimum 1FF bypass capacitor between LDO_IN and GND.
4 — WK
Wake Mode Enable Input. WK has an internal 50kI pullup resistor to the
internal 5V bias rail. A falling edge on WK brings the device out of sleep mode
and into the normal operating mode (wake mode).
— 4 LDO_OUT LDO Output Voltage. Connect a minimum 1FF output capacitor between
LDO_OUT and GND.
5 5 FB Feedback. Feedback input for the DC-DC buck converter. Connect FB to a
resistive divider from the output to GND to adjust the output voltage.
15
16
14
13
6
5
7
LX
WK
8
AUX
MPS
ULP
WAD
12
VCC
4
12 11 9
PGND
RREF *EP *EP
*EXPOSED PAD, CONNECT TO GND
*EXPOSED PAD, CONNECT TO GND
SL
VDRV
GND
FB
+
LED CLASS2
3
10
VDD
TQFN
MAX5986A
MAX5986B
MAX5986C
TOP VIEW
15
16
14
13
6
5
7
LX
LDO_OUT
8
AUX
RESET
CLASS2
WAD
12
VCC
4
12 11 9
PGND
RREF
LDO_FB
VDRV
GND
FB
+
LDO_IN MPS
3
10
VDD
TQFN
MAX5987A
MAX5986A–MAX5986C/
MAX5987A
IEEE 802.3af-Compliant, High-Eciency,
Class 1/Class 2, PDs with Integrated
DC-DC Converter
www.maximintegrated.com Maxim Integrated
│
11
Pin Description
Pin Conguration
PIN
NAME FUNCTION
MAX5986A/MAX5986B/
MAX5986C MAX5987A
6 6 GND Ground. Reference rail for the device. It is also the “quiet” ground for all
voltage reference (e.g., FB is referenced to this GND).
7 7 VDRV
Internal 5V Regulator Voltage Output. The internal voltage regulator provides
5V to the MOSFET driver and other internal circuits. VDRV is referenced to
GND. Do not use VDRV to drive external circuits. Connect a 1FF bypass
capacitor between VDRV and GND.
8 — SL
Sleep Mode Enable Input. A falling edge on SL brings the device into sleep
mode. An external resistor (RSL) connected between SL and GND sets the
LED current (ILED).
— 8 LDO_
FB
LDO Regulator Feedback Input. Connect to VDRV to get the preset LDO
output voltage of 3.3V, or connect to a resistive divider from the LDO_OUT to
GND for an adjustable LDO output voltage.
9 — ULP
Ultra-Low-Power Mode Enable Input. ULP has an internal 50kI pullup resistor to
the internal 5V bias rail. A falling edge on SL while ULP is asserted low enables
ultra-low power mode. When ultra-low power mode is enabled, the power
consumption of the device is reduced even lower than sleep mode to comply
with ultra-low power sleep power requirements while still supporting MPS.
10 9 CLASS2 Class 2 Selection Input. Connect to VDRV for Class 2 operation. Connect to
GND for Class 1 operation.
11 10 MPS MPS Enable Input. Connect to VDRV to turn the MPS function on. Connect to
GND to turn MPS off.
— 11 RESET
Open-Drain RESET Output. The RESET output is driven low if either LDO_OUT
or FB drops below 90% of its set value. RESET goes high 100Fs after both
LDO_OUT and FB rise above 95% of their set values. Leave unconnected
when not used.
12 12 WAD
Wall Power Adapter Detector Input. Wall adapter detection is enabled when
the voltage from WAD to GND is greater than 8.8V. When a wall power
adapter is present, the isolation p-channel power MOSFET turns off. Connect
WAD directly to GND when the wall power adapter or other auxiliary power
source is not used.
13 13 VDD Positive Supply Input. Connect a 68nF (min) bypass capacitor between VDD
and PGND.
14 14 VCC
DC-DC Converter Power Input. VDD is connected to VCC by an isolation
p-channel MOSFET. Connect a 10FF capacitor in parallel with a 1FF ceramic
capacitor between VCC and PGND.
15 15 PGND
Power Ground. Power ground of the DC-DC converter power stage. Connect
PGND to GND with a star connection. Do not use PGND as reference for
sensitive feedback circuit.
16 16 RREF Signature Resistor Connection. Connect a 24.9kI resistor (RSIG) to GND.
— — EP Exposed Pad. Connect the exposed pad to ground.
MAX5986A–MAX5986C/
MAX5987A
IEEE 802.3af-Compliant, High-Eciency,
Class 1/Class 2, PDs with Integrated
DC-DC Converter
www.maximintegrated.com Maxim Integrated
│
12
Pin Description (continued)
Detailed Description
PD Interface
The devices include complete interface functions for
a PD to comply with the IEEE 802.3af standard as a
Class 1/Class 2 PD. The devices provide the detection
and classification signatures using a single external
signature resistor. An integrated MOSFET provides
isolation from the buck converter when the PSE has
not applied power. The devices guarantee a leakage
current offset of less than 10µA during the detection
phase. The devices feature power-mode undervoltage-
lockout (UVLO) with wide hysteresis and long deglitch
time to compensate for twisted-pair-cable resistive drop
and to ensure glitch-free transitions between detection,
classification, and power-on/-off modes.
Operating Modes
The devices operate in three different modes depend-
ing on VDD. The three modes are detection mode,
classification mode, and power mode. The device is in
detection mode when VDD is between 1.4V and 10.1V,
classification mode when VDD is between 12.6V and 20V,
and power mode when the input voltage exceeds VON.
Detection Mode (1.4V < VDD < 10.1V)
In detection mode, the devices provide a signature
differential resistance to VDD. During detection, the
power-sourcing equipment (PSE) applies two voltages
to VDD, both between 1.4V and 10.1V with a mini-
mum 1V increment. The PSE computes the differential
resistance to ensure the presence of the 24.9kω signature
resistor. Connect the 24.9kω signature resistor (RSIG)
from RREF to GND for proper signature detection. The
device applies VDD to RREF when in detection mode,
and the VDD offset current due to the device is less than
10µA. The DC offset due to protection diodes does not
significantly affect the signature resistance measurement.
Classication Mode (12.6V < VDD < 20V)
In classification mode, the devices sink Class 1/Class 2
classification currents. The PSE applies a classification
voltage between 12.6V and 20V, and measures the clas-
sification currents. The devices use the external 24.9kω
resistor (RSIG) and the CLASS2 pin to set the classifica-
tion current at 10.5mA (Class 1) or 18.5mA (Class 2). The
devices provide either Class 1 (CLASS2 = GND) or Class
2 (CLASS2 = VDRV). The PSE uses this to determine
the maximum power to deliver. The classification current
includes current drawn by the supply current of the device
so the total current drawn by the PD is within the IEEE
802.3af standard. The classification current is turned off
when the device leaves classification mode.
Power Mode (VDD > VON)
In power mode, the devices have the isolation MOSFET
between VDD and VCC fully on. The MAX5987A has
the buck regulator enabled and the LDO enabled. The
MAX5986A–MAX5986C can be in either wake mode,
sleep mode, or ultra-low power mode. The buck regulator
is enabled when the MAX5986A–MAX5986C is in wake
mode.
The devices enter power mode when VDD rises above
the undervoltage lockout threshold (VON). When VDD
rises above VON, the device turns on the internal
p-channel isolation MOSFET to connect VCC to VDD
with inrush current limit internally set to 49mA (typ). The
isolation MOSFET is fully turned on when VCC is near
VDD and the inrush current is below the inrush limit.
Once the isolation MOSFET is fully turned on, the device
changes the current limit to 323mA. The buck converter
turns on 123ms after the isolation MOSFET turns on fully.
Undervoltage Lockout
The devices operate with up to a 60V supply voltage with
a turn-on UVLO threshold (VON) at 35.4V/38.7V (typ),
and a turn-off UVLO threshold (VOFF) at 31.4V (typ).
When the input voltage is above VON, the device enters
power mode and the internal isolation MOSFET is turned
on. When the input voltage is below VOFF for more than
tOFF_DLY, the MOSFET and the buck converter are off.
LED Driver (MAX5986A–MAX5986C)
The MAX5986A–MAX5986C drive an LED, or multiple
LEDs in series, with a maximum LED voltage of 6.5V.
In sleep mode and ultra-low power mode, the LED
current is pulse width modulated with a duty cycle of 25%
and the amplitude is set by R SL. The LED driver current
amplitude is programmable from 10mA to 20mA using R
SL according to the formula:
ILED = 646/R SL (mA)
where R SL is in kω.
MAX5986A–MAX5986C/
MAX5987A
IEEE 802.3af-Compliant, High-Eciency,
Class 1/Class 2, PDs with Integrated
DC-DC Converter
www.maximintegrated.com Maxim Integrated
│
13
Sleep and Ultra-Low Power Modes
(MAX5986A–MAX5986C)
The MAX5986A–MAX5986C feature a sleep mode and
an ultra-low power mode in which the internal p-channel
isolation MOSFET is kept on and the buck regulator is off.
In sleep mode, the LED driver output (LED) pulse width
of the MAX5986B/MAX5986C modulates the LED current
with a 25% duty cycle, while the MAX5986A does 100%
only. The peak LED current (ILED) is set by an external
resistor R SL. To enable sleep mode, apply a falling edge
to SL with ULP disconnected or high impedance. Sleep
mode can only be entered from wake mode.
Ultra-low power mode allows the devices to reduce power
consumption lower than sleep mode, while maintaining
the power signature of the IEEE standard. The ultra-low
power-mode enable input ULP is internally held high
with a 50kω pullup resistor to the internal 5V bias of the
device. To enable ultra-low power mode, apply a falling
edge to SL with ULP = LOW. Ultra-low power mode can
only be entered from wake mode.
To exit from sleep mode or ultra-low power mode and
resume normal operation, apply a falling edge on the
wake-mode enable input (WK).
Thermal-Shutdown Protection
If the devices’ die temperature reaches 151°C, an over-
temperature fault is generated and the device shuts
down. The die temperature must cool down below +135°C
to remove the overtemperature fault condition. After a
thermal shutdown condition clears, the device is reset.
WAD Description
For applications where an auxiliary power source such as
a wall power adapter is used to power the PD, the devices
feature wall power adapter detection.
The wall power adapter is connected from WAD to PGND.
The devices detect the wall power adapter when the volt-
age from WAD to PGND is greater than 8.8V. When a wall
power adapter is detected, the internal isolation MOSFET
is turned off, classification current is disabled.
Connect the auxiliar power source to WAD, connect a
diode from WAD to VDD, and connect a diode from WAD
to VCC. See the typical application circuit in Figure 2.
The application circuit must ensure that the auxiliary
power source can provide power to VDD and VCC by
means of external diodes. The voltage on VDD must
be within the VDD voltage range to allow the DC-DC to
operate. To allow operation of the DC-DC converter, the
VDD and VCC voltage must be greater than 8V on the ris-
ing edge, while on the falling edge the VDD and VCC may
fall down to 7.3V, keeping the DC-DC converter on.
Note: When operating solely with a wall power adapter,
the WAD voltage must be able to meet the condition VDD
> 8V, that likely results in WAD > 8.8V.
Internal Linear Regulator and Back Bias
An internal voltage regulator provides VDRV to internal
circuitry. The VDRV output is filtered by a 1µF capacitor
connected from VDRV to GND. The regulator is for
internal use only and cannot be used to provide power to
external circuits. VDRV can be powered by either VDD or
VAUX, depending on VAUX. The internal regulator is used
for both PD and buck converter operations.
VOUT can be used to back bias the VDRV voltage regu-
lator if VOUT is greater than 4.75V. Back biasing VDRV
increases device efficiency by drawing current from VOUT
instead of VDD. If VOUT is used as back bias, connect
AUX directly to VOUT. In this configuration, the VDRV
source switches from VDD to VAUX after the buck con-
verter’s output has reached its regulation voltage.
Cable Discharge Event Protection (CDE)
A 70V voltage clamp is integrated to protect the internal
circuits from a cable discharge event.
DC-DC Buck Converter
The DC-DC buck converter uses a PWM, peak
current-mode, fixed-frequency control scheme
providing an easy-to-implement architecture without
sacrificing a fast transient response. The buck converter
operates in a wide input voltage range from 8V to 60V
and supports up to 6.49W of input power. The devices
provide a wide array of protection features including
UVLO, overtemperature shutdown, short-circuit
protection with hiccup runaway current limit, cycle-by-
cycle peak current protection, and cycle-by-cycle output
overvoltage protection, for enhanced performance and
reliability. A frequency foldback scheme is implemented
to reduce the switching frequency to half at light loads to
increase the efficiency.
MAX5986A–MAX5986C/
MAX5987A
IEEE 802.3af-Compliant, High-Eciency,
Class 1/Class 2, PDs with Integrated
DC-DC Converter
www.maximintegrated.com Maxim Integrated
│
14
Frequency Foldback Protection for
High-Eciency Light-Load Operation
The devices enter frequency foldback mode when eight
consecutive inductor current zero-crossings occur.
The switching frequency is 215kHz or 430kHz under
loads large enough that the inductor current does not
cross zero. In frequency foldback mode, the switching
frequency is reduced to 107.5kHz or 215kHz to increase
power conversion efficiency. The device returns to
normal mode when the inductor current does not cross
zero for eight consecutive switching periods. Frequency
foldback mode is forced during startup until 50% of the
soft-start is completed.
Hiccup Mode
The devices include a hiccup protection feature. When
hiccup protection is triggered, the devices turn off the
high-side and turn on the low-side MOSFET until the
inductor current reaches the valley current limit. The
control logic waits 154ms (77ms for the MAX5986C) until
attempting a new soft-start sequence. Hiccup mode is
triggered if the current in the high-side MOSFET exceeds
the runaway current-limit threshold, both during soft-start
and during normal operating mode. Hiccup mode can
also be triggered in normal operating mode in the case
of an output undervoltage event. This happens if the
regulated feedback voltage drops below 60% (typ).
RESET Output (MAX5987A)
The MAX5987A features an open-drain RESET output
that indicates if either the LDO or the switching regula-
tor drop out of regulation. The RESET output goes low if
either regulator drops below 92% of its regulated feed-
back value. RESET goes high impedance 100µs after both
regulators are above 95% of their value.
Maintain Power Signature (MPS)
The devices feature the MPS to comply to the
IEEE 802.3af standard. They are able to maintain a
minimum current (10mA) of the port to avoid the power
disconnection from the PSE. The devices enter the MPS
when the port current is lower than 14mA and also exit the
MPS mode when the port current is geater than 40mA.
The feature is enabled by connecting the MPS pin to
VDRV, or disagbled by connecting the MPS pin to GND.
RSL is required in MPS mode
Applications Information
Operation with Wall Adapter
For applications where an auxiliary power source, such
as a wall power adapter, is used to power the PD, the
devices feature wall power adapter detection. The device
gives priority to the WAD supply over VDD supply, and
smoothly switches the power supply to WAD when it is
detected. The wall power adapter is connected from WAD
to PGND. The devices detect the wall power adapter
when the voltage from WAD to PGND is greater than
8.8V. When a wall power adapter is detected, the internal
isolation MOSFET is turned off, classification current is
disabled and the device draws power from the auxiliary
power source through VCC. Connect the auxiliary power
source to WAD, connect a diode from WAD to VCC. See
the typical application circuit in Figure 2.
Adjusting LDO Output Voltage (MAX5987A)
An uncommitted LDO regulator is available to provide
a supply voltage to external circuits. A preset voltage of
3.3V is set by connecting LDO_FB directly to VDRV. For
different output voltages connect a resistor divider from
LDO_OUT and LDO_FB to GND. The total feedback
resistance should be in the range of 100kω. The maxi-
mum output current is 85mA and thermal considerations
must be taken to prevent triggering thermal shutdown.
The LDO regulator can be powered by VOUT, a differ-
ent power supply, or grounded when not used. The LDO
is enabled once the buck converter has reached the
regulation voltage. The LDO is disabled when the buck
converter is turned off or not regulating.
Adjusting Buck Converter Output Voltage
The buck converter output voltage is set by changing
the feedback resistor-divider ratio. The output voltage
can be set from 3.0V to 5.6V (MAX5986A/MAX5987A)
or 5.4V to 14V (MAX5986B/MAX5986C). The FB voltage
is regulated to 1.225V. Keep the trace from the FB pin to
the center of the resistive divider short, and keep the total
feedback resistance around 100kω.
MAX5986A–MAX5986C/
MAX5987A
IEEE 802.3af-Compliant, High-Eciency,
Class 1/Class 2, PDs with Integrated
DC-DC Converter
www.maximintegrated.com Maxim Integrated
│
15
Inductor Selection
Choose an inductor with the following equation:
where LIR is the ratio of the inductor ripple current to
full load current at the minimum duty cycle. Choose LIR
between 20% to 40% for best performance and stability.
Use an inductor with the lowest possible DC resistance
that fits in the allotted dimensions. Powdered iron ferrite
core types are often the best choice for performance. With
any core material, the core must be large enough not to
saturate at the current limit of the devices.
VCC Input Capacitor Selection
The input capacitor reduces the current peaks drawn from
the input power supply and reduces switching noise in the
IC. The total input capacitance must be equal or greater
than the value given by the following equation to keep the
input-ripple voltage within specification and minimize the
high-frequency ripple current being fed back to the input
source:
where VIN-RIPPLE is the maximum allowed input ripple
voltage across the input capacitors and is recommended
to be less than 2% of the minimum input voltage. D is the
duty cycle (VOUT/VIN) and TS is the switching period (1/
fS).
The impedance of the input capacitor at the switching
frequency should be less than that of the input source so
high-frequency switching currents do not pass through
the input source, but are instead shunted through the
input capacitor. The input capacitor must meet the ripple
current requirement imposed by the switching currents.
The RMS input ripple current is given by:
where IRIPPLE is the input RMS ripple current.
Output Capacitor Selection
The key selection parameters for the output capacitor are
capacitance, ESR, ESL, and voltage-rating requirements.
These affect the overall stability, output ripple voltage, and
transient response of the DC-DC converter. The output
ripple occurs due to variations in the charge stored in
the output capacitor, the voltage drop due to the capaci-
tor’s ESR, and the voltage drop due to the capacitor’s
ESL. Estimate the output-voltage ripple due to the output
capacitance, ESR, and ESL:
VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR) +VRIPPLE(ESL)
where the output ripple due to output capacitance, ESR,
and ESL is:
or whichever is larger. The peak-to-peak inductor current
(IP-P)
Use these equations for initial output capacitor selec-
tion. Determine final values by testing a prototype or an
evaluation circuit. A smaller ripple current results in less
output-voltage ripple. Since the inductor ripple current is
a factor of the inductor value, the output-voltage ripple
decreases with larger inductance. Use ceramic capacitors
for low ESR and low ESL at the switching frequency of
the converter. The ripple voltage due to ESL is negligible
when using ceramic capacitors.
Load-transient response depends on the selected output
capacitance. During a load transient, the output instantly
changes by ESR x ILOAD. Before the controller can
respond, the output deviates further, depending on the
inductor and output capacitor values. After a short time,
the controller responds by regulating the output voltage
back to its predetermined value. The controller response
time depends on the closed-loop bandwidth. A higher
bandwidth yields a faster response time, preventing the
output from deviating further from its regulating value.
MAX5986A–MAX5986C/
MAX5987A
IEEE 802.3af-Compliant, High-Eciency,
Class 1/Class 2, PDs with Integrated
DC-DC Converter
www.maximintegrated.com Maxim Integrated
│
16
PCB Layout
Careful PCB layout is critical to achieve clean and stable
operation. It is highly recommended to duplicate the
MAX5986A EV kit layout for optimum performance. If
deviation is necessary, follow these guidelines for good
PCB layout:
1) Connect input and output capacitors to the power
ground plane; connect all other capacitors to the signal
ground plane.
2) Place capacitors on VDD, VCC, AUX, VDRV as close
as possible to the IC and its corresponding pin using
direct traces. Keep power ground plane (connected to
PGND) and signal ground plane (connected to GND)
separate.
3) Keep the high-current paths as short and wide as
possible. Keep the path of switching current short
and minimize the loop area formed by LX, the output
capacitors, and the input capacitors.
4) Connect VDD, VCC, and PGND separately to a large
copper area to help cool the IC to further improve effi-
ciency and long-term reliability.
5) Ensure all feedback connections are short and direct.
Place the feedback resistors and compensation com-
ponents as close as possible to the IC.
6) Route high-speed switching nodes, such as LX, away
from sensitive analog areas (FB).
7) Place enough vias in the pad for the EP of the
MAX5986A–MAX5986C/MAX5987A so that heat gen-
erated inside can be effectively dissipated by the
PCB copper. The recommended spacing for the vias
is 1mm to 1.2mm pitch. The thermal vias should be
plated (1oz copper) and have a small barrel diameter
(0.3mm to 0.33mm).
Table 1. Design Selection Table
*100μH/0.8A is recommendedfor with the MAX5986C.
OUTPUT CIN COUT L CLASS
3.3V CERAMIC ELECTROLYTIC CERAMIC
2.2FF/100V 10FF/63V 3x22FF/6.3V 33FH/1.4A 1
5V 2.2FF/100V 10FF/63V 3x22FF/6.3V 47FH/1.6A 1 or 2
12V 2.2FF/100V 10FF/63V 2x10FF/16V 220F/0.8A* 1 or 2
MAX5986A–MAX5986C/
MAX5987A
IEEE 802.3af-Compliant, High-Eciency,
Class 1/Class 2, PDs with Integrated
DC-DC Converter
www.maximintegrated.com Maxim Integrated
│
17
Figure 3. MAX5986A 5V Output with Back Bias
MAX5986A
VDD VCC
VDRV
WAD
WK
SL
RREF
GND PGND
ULP
AUX
LX
FB
LED
L0
47µH
C2
10µF
C1
68nF
C3
1µF
1µF
R1
75kI
RSL
60.4kI
0I
TO µP OPEN-DRAIN OUTPUTS
OR PULLDOWN SWITCHES
RSIG
24.9kI
R2
24.9kI
5V
OUTPUT
CLASS2
MPS
RJ-45 AND
BRIDGE
RECTIFIER
C4
47µF
MAX5986A–MAX5986C/
MAX5987A
IEEE 802.3af-Compliant, High-Eciency,
Class 1/Class 2, PDs with Integrated
DC-DC Converter
www.maximintegrated.com Maxim Integrated
│
18
Typical Application Circuits
Figure 4. MAX5986B/MAX5986C 12V Output with Back Bias
MAX5986B
MAX5986C
VDRV
CLASS2
MPS
VDD VCC WAD
WK
SL
RREF
GND PGND
ULP
AUX
LX
FB
LED
L0
220µH*
C2
10µF
C1
68nF
C3
1µF
1µF
R1
215kI
RSL
60.4kI
0I
TO µP OPEN-DRAIN OUTPUTS
OR PULLDOWN SWITCHES
RSIG
24.9kI
R2
24.9kI
12V
OUTPUT
RJ-45 AND
BRIDGE
RECTIFIER
*USE 110µH FOR MAX5986C
C4
10µF
MAX5986A–MAX5986C/
MAX5987A
IEEE 802.3af-Compliant, High-Eciency,
Class 1/Class 2, PDs with Integrated
DC-DC Converter
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│
19
Typical Application Circuits (continued)
Figure 5. MAX5987A 5V Buck Regulator Output and 3.3V LDO Output
MAX5987A
LDO_FB
VDD VCC WAD
RREF
GND PGND
AUX
LX
FB
LED
L0
47µH
C2
10µF
C1
68nF
C3
1µF
1µF
R1
75kI
0
RSIG
24.9kI
R2
24.9kI
5V
OUTPUT
RJ-45 AND
BRIDGE
RECTIFIER
VDRV
TO 5V OUTPUT LDO_IN
C6
1µF
LDO_OUT
C5
1µF
CLASS2
MPS
C4
47µF
MAX5986A–MAX5986C/
MAX5987A
IEEE 802.3af-Compliant, High-Eciency,
Class 1/Class 2, PDs with Integrated
DC-DC Converter
www.maximintegrated.com Maxim Integrated
│
20
Typical Application Circuits (continued)
CONTROL
CLK
1.5V
VREF
DRIVER
FB
PGND
LX
VDRV
AUX
WAD
VCC
5V
HOT-SWAP
CONTROLLER
PD VOLTAGE
MONITOR
5V
5V
1
0
5V
5V
REGULATOR
OPEN-DRAIN
(MAX5987A ONLY)
(MAX5986A/B/C ONLY)
RESET
5V
DETECTION
CLASSIFICATION
TVS
GND
VDD
RREF
VREF
LDO_IN
LDO_OUT
LDO_FB
CLASS2
MPS
LDO
LOGIC
50kI50kI
WK
SL
ULP
LED
5VVDD
BANDGAP
CLASS
MPS
MAX5986A
MAX5986B
MAX5986C
MAX5987A
VDD
(MAX5987A ONLY)
MAX5986A–MAX5986C/
MAX5987A
IEEE 802.3af-Compliant, High-Eciency,
Class 1/Class 2, PDs with Integrated
DC-DC Converter
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│
21
Functional Diagram
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
16 TQFN-EP T1655-4 21-0140 90-0121
PART PIN-PACKAGE SLEEP/ULP
MODE
LED CURRENT
DUTY CYCLE LDO UVLO (V) RESET fSW
(kHz)
MAX5986AETE+ 16 TQFN-EP* Yes 100% No 35.7 No 215
MAX5986BETE+ 16 TQFN-EP* Yes 25% No 35.7 No 215
MAX5986CETE+ 16 TQFN-EP* Yes 25% No 35.7 No 430
MAX5987AETE+ 16 TQFN-EP* No n/a Yes 38.7 Yes 215
MAX5986A–MAX5986C/
MAX5987A
IEEE 802.3af-Compliant, High-Eciency,
Class 1/Class 2, PDs with Integrated
DC-DC Converter
www.maximintegrated.com Maxim Integrated
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Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages. Note that
a “+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
Ordering Information
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 4/12 Initial release —
1 12/12 Added MAX5986B and MPS and CLASS2 features 1–20
2 4/13 Corrected error in Pin Configurations and replaced TOC12 10, 11
3 1/14 Added MAX5986C 1–23
4 12/14 Changed fSW of MAX5986A to 215kHz and changed LED current of
MAX5986A 1–23
5 1/15 Updated Benefits and Features section 1
6 11/16 Updated Electrical Characteristics table 5
7 11/18 Updated Maintain Power Signature (MPS) 15
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2018 Maxim Integrated Products, Inc.
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MAX5986A–MAX5986C/
MAX5987A
IEEE 802.3af-Compliant, High-Eciency,
Class 1/Class 2, PDs with Integrated
DC-DC Converter
Revision History
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
