MR0A08B
128K x 8 MRAM
FEATURES
• 3.3Voltpowersupply
• Fast35nsread/writecycle
• SRAMcompatibletiming
• Nativenon-volatility
• Unlimitedread&writeendurance
• Dataalwaysnon-volatilefor>20-yearsattemperature
• Commercialandindustrialtemperatures
• RoHS-CompliantTSOP2,BGAandSOICpackages
BENEFITS
• OnememoryreplacesFLASH,SRAM,EEPROMandBBSRAMin
systemforsimpler,moreecientdesign
• Improvesreliabilitybyreplacingbattery-backedSRAM
INTRODUCTION
TheMR0A08Bisa1,048,576-bitmagnetoresistiverandomaccess
memory(MRAM)deviceorganizedas131,072wordsof8bits.The
MR0A08BoersSRAMcompatible35nsread/writetimingwithun-
limitedendurance.
Dataisalwaysnon-volatileforgreaterthan20-years.Dataisautomaticallyprotectedonpowerlossby
low-voltageinhibitcircuitrytopreventwriteswithvoltageoutofspecication.TheMR0A08Bistheideal
memorysolutionforapplicationsthatmustpermanentlystoreandretrievecriticaldataandprograms
quickly.
TheMR0A08Bisavailableinsmallfootprint400-mil,44-leadplasticsmall-outlineTSOPtype-2package,
8mmx8mm,48-pinballgridarray(BGA)packagewith0.75mmballcentersora32-leadSOICpackage.
Thesepackagesarecompatiblewithsimilarlow-powerSRAMproductsandothernon-volatileRAMprod-
ucts.
TheMR0A08Bprovideshighlyreliabledatastorageoverawiderangeoftemperatures.Theproductisof-
feredwithcommercialtemperature(0to+70°C)andindustrialtemperature(-40to+85°C).
MR0A08BRev.5,12/20111
RoHS
CONTENTS
1.DEVICEPINASSIGNMENT.........................................................................2
2.ELECTRICALSPECIFICATIONS.................................................................4
3.TIMINGSPECIFICATIONS.......................................................................... 7
4.ORDERINGINFORMATION.......................................................................12
5.MECHANICALDRAWING..........................................................................13
6.REVISIONHISTORY......................................................................................16
HowtoReachUs..........................................................................................16
EverspinTechnologies©2011
MR0A08BRev.5,12/20112
CHIP
ENABLE
BUFFER
OUTPUT
ENABLE
BUFFER
ADDRESS
BUFFER
WRITE
ENABLE
BUFFER
G
E
17
OUTPUT ENABLE
128k x 8
BIT
MEMORY
ARRAY
ROW
DECODER
COLUMN
DECODER
SENSE
AMPS
OUTPUT
BUFFER
WRITE
DRIVER
FINAL
WRITE
DRIVERS
WRITE ENABLE
W
A[16:0]
10
7
88
8
8
8
8
DQ[7:0]
1. DEVICE PIN ASSIGNMENT
Figure 1.1 Block Diagram
Table 1.1 Pin Functions
Signal Name Function
A AddressInput
E ChipEnable
W WriteEnable
G OutputEnable
DQ DataI/O
VDD PowerSupply
VSS Ground
DC DoNotConnect
NC NoConnection
MR0A08B
EverspinTechnologies©2011
A
A
A
A
DQ0
DQ1
VDD
E
VSS
DQ2
DQ3
W
A
A
A
DC
A
DC 22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44 DC
NC
NC
NC
DC
A
G
DQ7
DQ6
VSS
A
VDD
DQ5
DQ4
DC
A
A
A
A
A
DC
DC
A
A
DC
NC
123456
GA0A1A2A
A3
A5
A4EB
A6C
VDD
VDD
D
DC
NC
A14
VSS
VSS
E
A12 A13
DQ7
DQ2
DQ3
DQ1
DQ0DQ4
DQ5
DQ6
F
NC
NC
A10 A11
WG
NC
NC
A7
A9NC H
NC
NCNC
NC
NC
DCDC
DCDC
A16
A15
A8
MR0A08BRev.5,12/20113
Figure 1.2 Pin Diagrams for Available Packages (Top View)
44 Pin TSOP2 32 Pin SOIC 48 Pin FBGA
Table 1.2 Operating Modes
E1G1W1Mode VDD Current DQ[7:0]2
HX X Notselected ISB1,ISB2 Hi-Z
L H H Outputdisabled IDDR Hi-Z
L L H ByteRead IDDR DOut
LXL ByteWrite IDDW Din
1H=high,L=low,X=don’tcare
2Hi-Z=highimpedance
DEVICE PIN ASSIGNMENT MR0A08B
EverspinTechnologies©2011
1
DC
2
A16
3
A14
4
A12
5
A7
6
A6
7
A5
8
A4
9
A3
10
A2
11
A1
12
A0
13
DQ0
14
DQ1
VDD
A15
A13
A8
A9
A11
NC
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
15
DQ2
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
W
G
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Thisdevicecontainscircuitrytoprotecttheinputsagainstdamagecausedbyhighstaticvoltagesor
electricelds;however,itisadvisedthatnormalprecautionsbetakentoavoidapplicationofany
voltagegreaterthanmaximumratedvoltagestothesehigh-impedance(Hi-Z)circuits.
Thedevicealsocontainsprotectionagainstexternalmagneticelds.Precautionsshouldbetaken
toavoidapplicationofanymagneticeldmoreintensethanthemaximumeldintensityspecied
inthemaximumratings.
MMR0A08BRev.5,12/20114
Parameter Symbol Value Unit
Supplyvoltage2VDD -0.5to4.0 V
Voltageonanypin2VIN -0.5toVDD+0.5 V
Outputcurrentperpin IOUT ±20 mA
Packagepowerdissipation3PD0.600 W
Temperatureunderbias
MR0A08B(Commercial)
MR0A08BC(Industrial)
TBIAS -10to85
-45to95
°C
StorageTemperature Tstg -55to150 °C
Leadtemperatureduringsolder(3minutemax) TLead 260 °C
Maximummagneticeldduringwrite
MR0A08B(AllTemperatures) Hmax_write 2000 A/m
Maximummagneticeldduringreadorstandby Hmax_read 8000 A/m
1Permanentdevicedamagemayoccurifabsolutemaximumratingsareexceeded.Functionalopera-
tionshouldberestrictedtorecommendedoperatingconditions.Exposuretoexcessivevoltagesor
magneticeldscouldaectdevicereliability.
2AllvoltagesarereferencedtoVSS.
3 Powerdissipationcapabilitydependsonpackagecharacteristicsanduseenvironment.
Table 2.1 Absolute Maximum Ratings1
MR0A08B
EverspinTechnologies©2011
MMR0A08BRev.5,12/20115
Parameter Symbol Min Typical Max Unit
Powersupplyvoltage VDD 3.013.3 3.6 V
Writeinhibitvoltage VWI 2.5 2.7 3.0i V
Inputhighvoltage VIH 2.2 - VDD+0.32 V
Inputlowvoltage VIL -0.53- 0.8 V
Temperatureunderbias
MR0A08B(Commercial)
MR0A08BC(Industrial)
TA0
-40
70
85
°C
1 Thereisa2msstartuptimeonceVDDexceedsVDD,(max).SeePower Up and Power Down Sequencing below.
2 VIH(max)=VDD+0.3VDC;VIH(max)=VDD+2.0VAC(pulsewidth≤10ns)forI≤20.0mA.
3V
IL(min)=-0.5VDC;VIL(min)=-2.0VAC(pulsewidth≤10ns)forI≤20.0mA.
Table 2.2 Operating Conditions
Power Up and Power Down Sequencing
TheMRAMisprotectedfromwriteoperationswheneverVDDislessthanVWI.AssoonasVDDexceedsVDD(min),
thereisastartuptimeof2msbeforereadorwriteoperationscanstart.Thistimeallowsmemorypower
suppliestostabilize.
TheEandWcontrolsignalsshouldtrackVDDonpoweruptoVDD-0.2VorVIH(whicheverislower)andremain
highforthestartuptime.Inmostsystems,thismeansthatthesesignalsshouldbepulledupwitharesis-
torsothatsignalremainshighifthedrivingsignalisHi-Zduringpowerup.AnylogicthatdrivesEandW
shouldholdthesignalshighwithapower-onresetsignalforlongerthanthestartuptime.
DuringpowerlossorbrownoutwhereVDDgoesbelowVWI,writesareprotectedandastartuptimemustbe
observedwhenpowerreturnsaboveVDD(min).
BROWNOUT or POWER LOSS
NORMAL
OPERATION
VDD
READ/WRITE
INHIBITED
VWIDD
2 ms
READ/WRITE
INHIBITED
VIH
STARTUP
NORMAL
OPERATION
2 ms
E
W
RECOVER
VIH
Figure 2.1 Power Up and Power Down Diagram
MR0A08B
Electrical Specications
EverspinTechnologies©2011
MR0A08BRev.5,12/20116
Parameter Symbol Min Typical Max Unit
Inputleakagecurrent Ilkg(I) - - ±1 μA
Outputleakagecurrent Ilkg(O) - - ±1 μA
Outputlowvoltage
(IOL=+4mA)
(IOL=+100μA)
VOL - - 0.4
VSS+0.2
V
Outputhighvoltage
(IOL=-4mA)
(IOL=-100μA)
VOH 2.4
VDD-0.2
--V
Table 2.3 DC Characteristics
Table 2.4 Power Supply Characteristics
MR0A08B
Electrical Specications
EverspinTechnologies©2011
Parameter Symbol Typical Max Unit
ACactivesupplycurrent-readmodes1
(IOUT=0mA,VDD=max) IDDR 25 30 mA
ACactivesupplycurrent-writemodes1
(VDD=max)
MR0A08B(Commercial)
MR0A08BC(Industrial)
IDDW 55
55
65
70
mA
ACstandbycurrent
(VDD=max,E=VIH)
no other restrictions on other inputs
ISB1 6 7 mA
CMOSstandbycurrent
(E≥VDD-0.2VandVIn≤VSS+0.2Vor≥VDD-0.2V)
(VDD=max,f=0MHz)
ISB2 5 6 mA
1 Allactivecurrentmeasurementsaremeasuredwithoneaddresstransitionpercycleandatminimumcycletime.
MR0A08BRev.5,12/20117
MR0A08B
3. TIMING SPECIFICATIONS
Table 3.1 Capacitance1
Parameter Symbol Typical Max Unit
Addressinputcapacitance CIn - 6 pF
Controlinputcapacitance CIn - 6 pF
Input/Outputcapacitance CI/O - 8 pF
1 f=1.0MHz,dV=3.0V,TA=25°C,periodicallysampledratherthan100%tested.
Table 3.2 AC Measurement Conditions
Figure 3.1 Output Load Test Low and High
Figure 3.2 Output Load Test All Others
Parameter Value Unit
Logicinputtimingmeasurementreferencelevel 1.5 V
Logicoutputtimingmeasurementreferencelevel 1.5 V
Logicinputpulselevels 0or3.0 V
Inputrise/falltime 2 ns
Outputloadforlowandhighimpedanceparameters SeeFigure3.1
Outputloadforallothertimingparameters SeeFigure3.2
V
Output
L= 1.5 V
RL= 50 Ω
ZD= 50 Ω
Output
435 Ω
590 Ω
5 pF
3.3 V
EverspinTechnologies©2011
MR0A08B
Timing Specications
MR0A08BRev.5,12/20118
Parameter Symbol Min Max Unit
Readcycletime tAVAV 35 - ns
Addressaccesstime tAVQV - 35 ns
Enableaccesstime2tELQV - 35 ns
Outputenableaccesstime tGLQV - 15 ns
Outputholdfromaddresschange tAXQX 3- ns
Enablelowtooutputactive3tELQX 3- ns
Outputenablelowtooutputactive3tGLQX 0 - ns
EnablehightooutputHi-Z3tEHQZ 0 15 ns
OutputenablehightooutputHi-Z3tGHQZ 0 10 ns
1 Wishighforreadcycle.Powersuppliesmustbeproperlygroundedanddecoupled,andbuscontentionconditionsmustbe
minimizedoreliminatedduringreadorwritecycles.
2 AddressesvalidbeforeoratthesametimeEgoeslow.
3 Thisparameterissampledandnot100%tested.Transitionismeasured±200mVfromthesteady-statevoltage.
Table 3.3 Read Cycle Timing1
Read Mode
Figure 3.3A Read Cycle 1
Figure 3.3B Read Cycle 2
A (ADDRESS)
Q (DATA OUT)
tAVAV
tAXQX
tAVQV
Previous Data Valid
Note: Device is continuously selected (E≤VIL, G≤VIL).
Data Valid
A (ADDRESS)
E (CHIP ENABLE)
G (OUTPUT ENABLE)
Q (DATA OUT) Data Valid
tAVAV
tAVQV
tELQV
tELQX
tGHQZ
tEHQZ
tGLQV
tGLQX
EverspinTechnologies©2011
MR0A08B
Timing Specications
MR0A08BRev.5,12/20119
Table 3.4 Write Cycle Timing 1 (W Controlled)1
Parameter Symbol Min Max Unit
Writecycletime2tAVAV 35 - ns
Addressset-uptime tAVWL 0 - ns
Addressvalidtoendofwrite(Ghigh) tAVWH 18 - ns
Addressvalidtoendofwrite(Glow) tAVWH 20 - ns
Writepulsewidth(Ghigh) tWLWH
tWLEH
15 - ns
Writepulsewidth(Glow) tWLWH
tWLEH
15 - ns
Datavalidtoendofwrite tDVWH 10 - ns
Dataholdtime tWHDX 0 - ns
WritelowtodataHi-Z3tWLQZ 0 12 ns
Writehightooutputactive3tWHQX 3- ns
Writerecoverytime tWHAX 12 - ns
1 AllwriteoccursduringtheoverlapofElowandWlow.Powersuppliesmustbeproperlygroundedanddecoupledandbus
contentionconditionsmustbeminimizedoreliminatedduringreadandwritecycles.IfGgoeslowatthesametimeorafter
Wgoeslow,theoutputwillremaininahighimpedancestate.AfterWorEhasbeenbroughthigh,thesignalmustremainin
steady-statehighforaminimumof2ns.TheminimumtimebetweenEbeingassertedlowinonecycletoEbeingasserted
lowinasubsequentcycleisthesameastheminimumcycletimeallowedforthedevice.
2 Allwritecycletimingsarereferencedfromthelastvalidaddresstothersttransitionaddress.
3 Thisparameterissampledandnot100%tested.Transitionismeasured±200mVfromthesteady-statevoltage.Atanygiven
voltageortemperate,tWLQZ(max)<tWHQX(min)
W (WRITE ENABLE)
A (ADDRESS)
E (CHIP ENABLE)
t
AVAV
t
AVWH
t
WHAX
t
AVWL
t
WLEH
t
WLWH
DATA VALID
t
DVWH
t
WHDX
Q (DATA OUT)
D (DATA IN)
t
WLQZ
t
WHQX
Hi -Z Hi -Z
Figure 3.4 Write Cycle Timing 1 (W Controlled)
EverspinTechnologies©2011
MR0A08B
Timing Specications
EverspinTechnologies©2011 MR0A08BRev.5,12/201110
Table 3.5 Write Cycle Timing 2 (E Controlled)1
Figure 3.5 Write Cycle Timing 2 (E Controlled)
Parameter Symbol Min Max Unit
Writecycletime2tAVAV 35 - ns
Addressset-uptime tAVEL 0 - ns
Addressvalidtoendofwrite(Ghigh) tAVEH 18 - ns
Addressvalidtoendofwrite(Glow) tAVEH 20 - ns
Enabletoendofwrite(Ghigh) tELEH
tELWH
15 - ns
Enabletoendofwrite(Glow)3tELEH
tELWH
15 - ns
Datavalidtoendofwrite tDVEH 10 - ns
Dataholdtime tEHDX 0 - ns
Writerecoverytime tEHAX 12 - ns
1 AllwriteoccursduringtheoverlapofElowandWlow.Powersuppliesmustbeproperlygroundedanddecoupledandbus
contentionconditionsmustbeminimizedoreliminatedduringreadandwritecycles.IfGgoeslowatthesametimeorafter
Wgoeslow,theoutputwillremaininahighimpedancestate.AfterWorEhasbeenbroughthigh,thesignalmustremainin
steady-statehighforaminimumof2ns.TheminimumtimebetweenEbeingassertedlowinonecycletoEbeingasserted
lowinasubsequentcycleisthesameastheminimumcycletimeallowedforthedevice.
2 Allwritecycletimingsarereferencedfromthelastvalidaddresstothersttransitionaddress.
3 IfEgoeslowatthesametimeorafterWgoeslow,theoutputwillremaininahigh-impedancestate.IfEgoeshighatthe
sametimeorbeforeWgoeshigh,theoutputwillremaininahigh-impedancestate.
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
Q (DATA OUT)
D (DATA IN)
tAVAV
tAVEH
tAVEL
tEHAX
tEHDX
tDVEH
Hi-Z
Data Valid
tELEH
tELWH
MR0A08B
Timing Specications
MR0A08BRev.5,12/201111
Table 3.6 Write Cycle Timing 3 (Shortened tWHAX, W and E Controlled)1
Table 3.6 Write Cycle Timing 3 (Shortened tWHAX, W and E Controlled)
Parameter Symbol Min Max Unit
Writecycletime2tAVAV 35 - ns
Addressset-uptime tAVWL 0 - ns
Addressvalidtoendofwrite(Ghigh) tAVWH 18 - ns
Addressvalidtoendofwrite(Glow) tAVWH 20 - ns
Writepulsewidth tWLWH
tWLEH
15 - ns
Datavalidtoendofwrite tDVWH 10 - ns
Dataholdtime tWHDX 0 - ns
Enablerecoverytime tEHAX -2 - ns
Writerecoverytime3tWHAX 6 - ns
Writetoenablerecoverytime3tWHEL 12 - ns
1 AllwriteoccursduringtheoverlapofElowandWlow.Powersuppliesmustbeproperlygroundedanddecoupledandbus
contentionconditionsmustbeminimizedoreliminatedduringreadandwritecycles.IfGgoeslowatthesametimeorafter
Wgoeslow,theoutputwillremaininahighimpedancestate.AfterW,orEhasbeenbroughthigh,thesignalmustremainin
steady-statehighforaminimumof2ns.TheminimumtimebetweenEbeingassertedlowinonecycletoEbeingasserted
lowinasubsequentcycleisthesameastheminimumcycletimeallowedforthedevice.
2 Allwritecycletimingsarereferencedfromthelastvalidaddresstothersttransitionaddress.
3 IfEgoeslowatthesametimeorafterWgoeslowtheoutputwillremaininahighimpedancestate.IfEgoeshighatthesame
timeorbeforeWgoeshightheoutputwillremaininahighimpedancestate.Emustbebroughthigheachcycle.
tAVWL
tAVAV
tAVWH
tWLWH
t
WLEH
t
DVWH
t
WHDX
tWHAX
t
tEHAX
WHEL
W (WRITE ENABLE)
A (ADDRESS)
E (CHIP ENABLE)
D (DATA IN)
EverspinTechnologies©2011
MR0A08BRev.5,12/201112
MR0A08B
4. ORDERING INFORMATION
Figure 4.1 Part Numbering System
Part Number Description Package Ship Pack Temp Range
MR0A08BYS35 3.3V128Kx8MRAMCommercial 44-TSOP Tray 0to70°C
MR0A08BCYS35 3.3V128Kx8MRAMIndustrial 44-TSOP Tray -40to+85°C
MR0A08BYS35R 3.3V128Kx8MRAMCommercial 44-TSOP Tape&Reel 0to70°C
MR0A08BCYS35R 3.3V128Kx8MRAMIndustrial 44-TSOP Tape&Reel -40to+85°C
MR0A08BMA35 3.3V128Kx8MRAMCommercial 48-BGA Tray 0to70°C
MR0A08BCMA35 3.3V128Kx8MRAMIndustrial 48-BGA Tray -40to+85°C
MR0A08BMA35R 3.3V128Kx8MRAMCommercial 48-BGA Tape&Reel 0to70°C
MR0A08BCMA35R 3.3V128Kx8MRAMIndustrial 48-BGA Tape&Reel -40to+85°C
MR0A08BSO35 3.3V128Kx8MRAMCommercial 32-SOIC Tray 0to70°C
MR0A08BCSO3513.3V128Kx8MRAMIndustrial 32-SOIC Tray -40to+85°C
Table 4.1 Available Parts
EverspinTechnologies©2011
Carrier Blank = Tray, R = Tape & Reel
Speed 35 ns
Package YS = TSOP2, MA = FBGA, SO=SOIC
Temperature Range
Blank= 0 to +70 °C, C= -40 to +85 °C
Revision
Data Width 08 = 8-Bit
Type A = Asynchronous
Density 0 = 1Mb
Magnetoresistive RAM
MR
MR 0 A 08 B C YS 35 R
1PreliminaryProduct:ThisproductisclassiedasPreliminaryuntilthecompletionofallqualicationtests.Thespeci-
cationsinthisdatasheetareintendedtobenalbutaresubjecttochange.PleasechecktheEverspinwebsitewww.
everspin.comforthelatestinformationonproductstatus.
MR0A08BRev.5,12/201113
Figure 5.1 TSOP2
MR0A08B
5. MECHANICAL DRAWING
Print Version Not To Scale
1. DimensionsandtolerancesperASMEY14.5M-1994.
2. DimensionsinMillimeters.
3. Dimensionsdonotincludemoldprotrusion.
4. DimensiondoesnotincludeDAMbarprotrusions.
DAMBarprotrusionshallnotcausetheleadwidthtoexceed0.58.
EverspinTechnologies©2011
MR0A08BRev.5,12/201114
Figure 5.2 FBGA
MR0A08B
Mechanical Drawings
EverspinTechnologies©2009
TOP VIEW
BOTTOM VIEW SIDE VIEW
0.41
0.31 0.32
0.22
Print Version Not To Scale
1. DimensionsinMillimeters.
2. DimensionsandtolerancesperASMEY14.5M-1994.
3. MaximumsolderballdiametermeasuredparalleltoDATUMA
4. DATUMA,theseatingplaneisdeterminedbythesphericalcrowns
ofthesolderballs.
5. Parallelismmeasurementshallexcludeanyeectofmarkontop
surfaceofpackage.
MR0A08BRev.5,12/201115
MR0A08B
Mechanical Drawings
EverspinTechnologies©2011
Figure 5.3 SOIC
Unit A B C D E F G H I J K
mm-Min
-Max
20.574
20.878
1.00
1.50
0.355
0.508
0.66
0.81
0.101
0.254
2.286
2.540
Radius
0.101
0.533
1.041
0.152
0.304
7.416
7.594
10.287
10.642
inch-Min
-Max
0.810
0.822
0.04
0.06
0.14
0.02
0.026
0.032
0.004
0.010
0.09
0.10
Radius
0.0040
0.021
0.041
0.006
0.012
0.292
0.299
0.405
0.419
1 16
32 17
PIN 1 ID
A
BC
D
E F
G
H
J
K
I
Reference JEDEC MO-119
Print Version Not To Scale
MR0A08B
MR0A08BRev.5,12/201116
Revision Date Description of Change
0 Sep12,2008 InitialAdvanceInformationRelease
1 May8,2009
Revisedformat;AddTable3.6WriteTimingCycle3;AddFigure3.6WriteTim-
ingCycle3;AddTSOPIILeadWidthInfo;ChangedtoPreliminaryfromProd-
uctConcept.
2 June18,2009 ChangedfromdatasheetfromPreliminarytoProductionexceptwhere
noted.
3Apr12,2011 AddedSOICpackageoption.
4August15,
2011
CorrectedSOICPin1toreadDC.Updatedcontactinformation.Revised
copyrightyear.
5 Dec16,2011
ChangedTSOP-IItoTSOP2.ChangedlogotonewESTLogo.AddedIndustri-
alTempGradeoptioninSOICpackage,Table4.1.DeletedTape&Reelpack
optionforallSOICpackagedparts.Figure2.1cosmeticupdate.Figure5.2
BGApackageoutlinedrawingrevisedforballsize.
6. REVISION HISTORY
Information in this document is provided solely to enable system and software implementers to use
Everspin Technologies products. There are no express or implied licenses granted hereunder to design or
fabricate any integrated circuit or circuits based on the information in this document. Everspin Technolo-
gies reserves the right to make changes without further notice to any products herein. Everspin makes no
warranty, representation or guarantee regarding the suitability of its products for any particular purpose,
nor does Everspin Technologies assume any liability arising out of the application or use of any product or
circuit, and specically disclaims any and all liability, including without limitation consequential or inci-
dental damages. “Typical” parameters, which may be provided in Everspin Technologies data sheets and/
or specications can and do vary in dierent applications and actual performance may vary over time. All
operating parameters including “Typicals” must be validated for each customer application by customer’s
technical experts. Everspin Technologies does not convey any license under its patent rights nor the rights
of others. Everspin Technologies products are not designed, intended, or authorized for use as compo-
nents in systems intended for surgical implant into the body, or other applications intended to support
or sustain life, or for any other application in which the failure of the Everspin Technologies product
could create a situation where personal injury or death may occur. Should Buyer purchase or use Everspin
Technologies products for any such unintended or unauthorized application, Buyer shall indemnify and
hold Everspin Technologies and its ocers, employees, subsidiaries, aliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or
indirectly, any claim of personal injury or death associated with such unintended or unauthorized use,
even if such claim alleges that Everspin Technologies was negligent regarding the design or manufacture
of the part. Everspin™ and the Everspin logo are trademarks of Everspin Technologies, Inc. All other
product or service names are the property of their respective owners.
©Everspin Technologies, Inc. 2011
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File Name:
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EverspinTechnologies©2011