Preliminary Data Sheet
October 2001
L9214A/G
Low-Cost Ringing SLIC
Introduction
The Agere Systems Inc. L9214 is a subscriber line
interface circuit that is optimized to provide a very
low-cost solution for short- and medium-loop applica-
tions. This device provides the complete set of line
interface functionality, including power ringing
needed to interface to a subscriber loop. This device
has the capability to operate with a VCC supply of
3.3 V or 5 V and is designed to minimize external
components required at all device interfaces.
Features
■Low-cost solution
■Onboard ringing generation with software adjust-
able crest factor switching
■Flexible VCC opti on s:
— 3.3 V or 5 V VCC
— No –5 V required
■Power control options:
— Power control resistor
— Automatic battery switch to minimize off-hook
power
■Eight operating states:
— Scan mode for minimal power dissipation
— Forward and reverse battery active
— On-hook transmission states
— Ring mode
— Disconnect mode
■Low on-hook power:
— 25 mW scan mode
— 165 mW active mode
■Two SLIC gain options to minimize external com-
ponents in codec interface
■Loop start, ring trip, and ground key detectors
■Programmable current limit
■On-hook and scan mode line voltage clamp
■Thermal protection
■48-pin MLCC, 32-pin PLCC, and 28-pin SOG
(Please contact your Agere Sales Representative
for availability) packages
Applications
■Voice over Internet Protocol (VoIP)
■Cable Modems
■Terminal Adapters (TA)
■Wireless Local Loop ( WLL)
■Telcordia Technologies™ GR-9 09 Ac ce ss
■Network Termination (NT)
■PBX
■Key Sy st ems
Description
This device is optimized to provide battery feed, ring-
ing, and supervision on short- and medium-loop plain
old telephone service (POTS) loops. Supported
round trip loop length is up to 1000 Ω.
This device provides power ring to the subscriber by
the use of line reversal to create either a sine wave
ringing signal with a PWM input or a trapezoidal ring-
ing signal with a selectable crest factor from a square
wave input. It provides forward and reverse battery
feed states, on-hook transmission, a low-power scan
state, and a forward disconnect state.
The devic e requi re s a VCC and line feed battery to
operate. VCC may be either a 3.3 V or a 5 V supply.
The ringing signal is derived from the high-voltage
battery. An automatic battery switch is included to
allow for use of a second lower voltage battery in the
off-hook mode, thus minimizing short-loop off-hook
power consumption and dissipation. If the user
desires single battery operation, a power resistor is
required to reduce the power dissipation in the SLIC.
Loop closure, ring trip, and ground key detectors are
available. The loop closure detector has a fixed
threshold with hysteresis. The ring trip detector and
ground key detector threshold and time constants are
externall y set.
The dc current limit is programmed by an external
resistor , the maximum current limit determined by the
Vcc supply.
The overhead voltage for this device is fixed and the
device is capable of supporting 3.17 dB into a 600 Ω
load with minimal overhead.
The device is offered with two gain options. This
allows for an optimized codec interface, with minimal
external components regardless of whether a first-
generation or a programmable third-generation
codec is used.
Prel iminary Data Sheet
October 2001
Low-Cost Ringing SLIC
L9214A/G
2 Agere Systems Inc.
Table of Contents
Contents Page
Introduction..................................................................1
Features....................................................................1
Applications...............................................................1
Description................................................................1
Features ......................................................................4
Description...................................................................4
Architecture Diagram...................................................7
Pin Information ............................................................8
Operating Sta tes........... ................... ...... ....... ............. 12
State Definitions ........................................................12
Forward Acti ve (Fast Pol arit y Rever sal) .................12
Off-hook................................................................12
On-hook................................................................12
Forward Active (Slow Polarity Reversal).................12
Off-hook................................................................12
On-hook................................................................12
Reverse Active (Fast Polarity Reversal) .................13
Off-hook................................................................13
On-hook................................................................13
Reverse Active (Slow Polarity Reversal) ................13
Off-hook................................................................13
On-hook................................................................13
Scan........................................................................13
Disconnect..............................................................13
Ring.........................................................................13
Thermal Shutdown..................................................13
Absolute Maximum Ratings.......................................14
Electrical Characteristics...........................................15
Test Configurations ...................................................22
Applications...............................................................24
Power Control .........................................................24
dc Loop Current Limit..............................................25
Overhead Voltage...................................................25
Active Mode .........................................................25
Scan Mode...........................................................25
On-Hook Transmission Mode...............................25
Ring Mode............................................................26
Contents Page
Loop Range ........... ...... ....... ................... ....... ...... ... 26
Battery Reversal Rate............................................ 26
Supervision............................................................... 27
Loop Closure.......... ...... ....... ...... ....... ...... ....... ......... 27
Ring Trip ................ ................... ....... ...... ....... ......... 27
Tip or Ring Ground Detector.................................. 27
Power Ring ............................................................ 27
Periodic Pulse Metering (PPM) ................................ 29
ac Applications ......................................................... 29
ac Parameters........................................................ 29
Codec Types.......................................................... 29
First-Generation Codecs..................................... 29
Third-Generation Codecs.................................... 29
ac Interface Network.............................................. 29
Design Examp le s...................... ....... ...... ....... ...... ... 30
First-Generation Codec ac Interface
Network—Resistiv e Term in ation ...................... 30
Example 1, Real Termination.............................. 31
First-Generation Codec ac Interface
Network—Complex Termination....................... 34
Complex Termination Impedance Design
Example............................................................ 34
ac Interface Using First-Generation Codec......... 33
Transmit Gain......................... .................... ...... ... 35
Receive Gain.................... ...... .................... ...... ... 36
Hybrid Balance.................................................... 36
Blocking Capacitors............................................. 37
Third-Generation Codec ac Interface
Network—Complex Termination....................... 40
Outline Diagram........................................................ 41
28-Pin SOG............................................................ 42
32-Pin PLCC.......................................................... 43
48-Pin MLCC.......................................................... 44
48-Pin MLCC, JEDEC MO-220 VKKD-2................ 45
Ordering Information................................................. 46
Preliminary Data Sheet
October 2001 Low-Cost Ringing SLIC
L9214A/G
Agere Systems Inc. 3
Table of Contents (continued)
Figures Page
Figure 1. Architecture Diagram ...................................7
Figure 2. 28-Pin SOG Diagram ..................................8
Figure 3. 32-Pin PLCC Diagram .................................8
Figure 4. 48-Pin MLCC Dia gr am........... ....... ...... ....... ..9
Figure 5. Basic Test Circuit (3 REN Configuration) ..22
Figure 6. Metallic PSRR ...........................................23
Figure 7. Longitudinal PSRR ....................................23
Figure 8. Longitudinal Balance .................................23
Figure 9. ac Gains ....................................................23
Figure 10. Ringing Waveform Crest Factor = 1.6 .....27
Figure 11. Ringing Waveform Crest Factor = 1.2 .....27
Figure 12. Ring Operation ........................................28
Figure 13. ac Equivalent Circuit ................................31
Figure 14. Agere T7504 First-Generation Codec;
Resistive Termination (5 REN
Configuration)...........................................32
Figure 15. Interface Circuit Using First-Generation
Codec (Blocking Capacitors
Not Shown) ....... ...... ....... ...... ....... ...... .......35
Figure 16. ac Interface Using First-Generation
Codec (Including Blocking Capacitors)
for Complex Termination Impedance ......37
Figure 17. Agere T7504 First-Generation Codec;
Complex Termination with Power Control
Resistor (3 REN Configu ratio n)......... ....... 38
Figure 18. Third-Generation Codec ac Interface
Network; Complex Termination (3 REN
Configuration)...........................................40
Tables Page
Table 1. Pin Descriptions ......................................... 10
Table 2. Control States ............................................ 12
Table 3. Typical Operating Characteristics .............. 14
Table 4. Thermal Characteristics.............................. 14
Table 5. Environmental Characteristics ................... 15
Table 6. 5.0 V Supply Currents ............................... 15
Table 7. 5. 0 V Powering .......................................... 15
Table 8. 3.3 V Supply Currents ................................ 16
Table 9. 3.3 V Powering .......................................... 16
Table 10. Two-Wire Port .......................................... 17
Table 11. Analog Pin Characteristics ...................... 18
Table 12. ac Feed Characteristics ........................... 19
Table 13. Logic Inputs and Outputs
(VCC = 5.0 V) .............................................. 20
Table 14. Logic Inputs and Outputs
(VCC = 3.3 V) ............................................ 20
Table 15. Ringing Specifications ............................. 20
Table 16. Ring Trip (3 REN Configuration) .............. 21
Table 17. Ring Trip (5 REN Configuration)............... 21
Table 18. Typical Active Mode On- to Off-Hook
Tip/Ring Current-Limit Transient
Response ................................................ 25
Table 19. FB1/FB2 Values vs. Typical Ramp Time
at VBAT1 = –65 V ....................................... 26
Table 20. L9214 Parts List for Agere T7504
First-Generation Codec; Resistive
Termination .............................................. 33
Table 21. L9214 Parts List for Agere T7504 First-
Generation Codec; Complex Termination
with Power Control Resistor .................... 38
Table 22. L9214 Parts List for Agere T8536
Third-Generation Codec Meter Pulse
Applic ati on ac and dc Para mete r s;
Fully Programmable ................................ 41
Prel iminary Data Sheet
October 2001
Low-Cost Ringing SLIC
L9214A/G
4 Agere Systems Inc.
Features
■Onboard balanced trapezoidal ringing generation,
40 Vrms, 1.2 crest factor:
— 3 RE N ring load (2330 Ω + 24 µF), 600 Ω loop
— 2 RE N ring load (3500 Ω + 16 µF), 1000 Ω loop
— 2 RE N ring load (3500 Ω + 1.8 µF), 500 Ω loop
— No ring relay
— No bulk ring generator required
— 15 Hz to 70 Hz ring frequency supported
■Power supplies requirements:
— VCC talk battery and ringing battery required
— No –5 V supply required
— No high-voltage positive supply required
■Flexible Vcc options:
— 3.3 V or 5 V VCC operation
— 3.3 V or 5 V VCC interchangeable and transparent
to users
■Power control options:
— Automatic battery switch
— Power control resistor
■Minimal external components required
■Ten operating states:
— Forward active, fast polarity reversal
— Reverse active, fast polarity reversal
— Forward active, slow polarity reversal
— Reverse active, slow polarity reversal
— Scan
— Disconnect
— Ringing, line forward with high slope
— Ringing, line reverse with high slope
— Ringing, line forward with low slope
— Ringing, line reverse with low slope
■Unlatched parallel data control interface
■Low SLIC power:
— Scan 24 mW (VCC = 5.0 V)
— Forward/reverse active 148 mW (VCC = 5.0 V)
— Scan 17 mW (VCC = 3.3 V)
— Forward/reverse on-hook 135 mW (VCC = 3.3 V)
■Supervision:
— Loop start, fixed threshold with hysteresis
— Ring trip filtering, fixed threshold not a function of
battery voltage, user adjustable with an external
resistor
— Common-mode current for ground key applica-
tio ns, user-adjustable threshold
■Adjustable current limit:
— 10 mA to 45 mA programming range at 5 V Vcc
— 10 mA to 35 mA programming range at 3.3 V Vcc
■Overhead voltage:
— Automatically adjusted in active mode
— Clamped <56.5 V in scan and on-hook modes
■Thermal shutdown protection with hysteresis
■Longitudinal balance:
— ETSI/ITU-T balance
— GR-909
■Meter pulse compatible
■ac interface:
— Two SLIC gain options to minimize external com-
ponents required for interface to first- or third-gen-
eration codecs
— Sufficient dynamic range for direct coupling to
codec output
■28-pin SOG, 32-pin PLCC, and 48-pin MLCC pack-
age options
■90 V CBIC-S technology
Description
The L9214 is designed to provide battery feed, ringing,
and supervision functions on short and medium plain
old telephone service (POTS) loops. Supported round-
trip loop length is up to 1000 Ω of wir ing res istan ce plus
handset or ringing load. This device is designed to min-
imize power in all operating states.
The L9214 offers eight operating states. The device
assumes use of a lower-voltage talk battery, a higher-
voltage ringing battery and a single VCC supply.
The L9214 requires only a positive VCC supply. No
–5 V supply is needed. The L9214 can operate with a
VCC of either 5.0 V or 3.3 V, allowing for greater user
flexibility. The choice of VCC voltage is transparent to
the user; the device will function with either supply volt-
age connected.
Two batteries may be used:
1. A high-voltage ring battery (VBAT1). VBAT1 is a maxi-
mum –70 V and is used for power ringing, scan, and
on-hook transmission modes. This supply is current
limited to the maximum power ringing current of
approximately 90 mApeak.
2. A lower-voltage talk battery (VBAT2). VBAT2 is nor-
mally used for active mode powering.
Alternatively, operation may be from a single high-volt-
age battery supply with a power control resistor to
reduce the powe r diss ipatio n in the SLIC.
Preliminary Data Sheet
October 2001 Low-Cost Ringing SLIC
L9214A/G
Agere Systems Inc. 5
Description (continued)
Forward and reverse battery active modes are used for
off-hook conditions. Since this device is designed for
short- and medium-loop applications, the lower-voltage
VBAT2 is normally applied during the forward and
rever se activ e states . Battery reversal is quiet, without
breaking the ac path. The rate of battery reversal may
be ramped to control switching time.
The magnitude of the overhead voltage in the forward
and reverse active modes allows for an undistorted sig-
nal of 3.17 dBm into 600 Ω. The ring trip detector is
turned off during active modes to conserve power.
On-hook transmission is not permitted in the scan
mode. In this mode, the tip ring voltage is derived from
the higher VBAT1 rather than VBAT2.
In the scan and active modes, the overhead voltage is
set such that the tip/ring open loop voltage is 42.5 V
minimum for a primary battery of 63 V to 70 V for com-
patibility with maintenance termination units (MTUs).
Also, the maximum voltage with respect to ground
(tip or ring to ground) is 56.5 V to comply with UL™
1950/60950 ANNEX M.2 method B and IEC® 60950
(quiet interval of ringing). If the primary battery is below
–63 V, the magnitude of the tip/ring open circuit voltage
is approximately 17 V less than the battery.
To minimize on-hook power , a low-power scan mode is
available. In this mode, all functions except off-hook
supervision are turned off to conserve power. On-hook
transmission is not allowed in the scan mode.
A forward disconnect mode is provided, where all cir-
cuits are turned off and power is denied to the loop.
The device offers a ring mode, in which a power ring
signal is provided to the tip/ring pair. During the ring
mode, the user, by use of the input states, performs
line reve rsal s at the requ ired frequ enc y, whi ch gen er-
ates the power ringing signal. This signal may be
applied continuously but is normally cadenced to meet
country-specific requirements. The input states are
normally set to an active state when power ringing is
halted to enable on-hook transmission. The ring trip
detector and common-mode current detector are active
during the ring mode. The user may adjust the crest
factor of the ring signal by selecting one of the two slew
rates. The two rates, high or low, allow the designer to
chose one set of external capacitors to meet the crest
factor range of 1.2 to 1.6 over a 3:1 frequency range by
software control alone. For increased power efficiency,
the crest factor should be kept as low as possible.
With maxi mum V BAT1, the L9214 has sufficient power to
ring a 3 REN (2310 Ω + 24 µF) ringing load into 600 Ω
of physical wiring resistance. With maximum VBAT1, the
L9214 has sufficient power to ring a 2 REN (3500 Ω +
16 µF) ringing load into <1000 Ω of physical wiring
resistance. Loop ranges may be expanded by applying
a lower crest factor trapezoidal input waveform.
This feature eliminates the need for a separate external
ring relay, associated external circuitry, and a bulk ring-
ing generator. See the Applications section of this data
sheet for more information.
Where PPM is required, it is injected into the audio
receive pins (ac-coupled). PPM shaping must be
done externally and the PPM level must be within the
1.12 Vrms (3.17 dBm, 600 Ω) level set by the amplifier
overhead in the active state.
Both the ring trip and loop closure supervision func-
tions are included. The loop closure has a fixed typical
10 mA on- to off-hook threshold in the active and scan
mode. In either case, there is a 2 mA hysteresis. The
ring trip detector requires a simple filter at the input.
The ring trip thres hol d interna lly at a given batter y volt-
age is fixed, but the threshold can be adjusted through
an external voltage divider . Typical ring trip threshold is
20.1 mA for a –65 V VBAT1.
A common-mode current detector for tip or ring ground
detection is included for ground key applications. The
threshold is user programmable via external resistors.
See the Applications section of this data sheet for more
information on supervision functions.
Prel iminary Data Sheet
October 2001
Low-Cost Ringing SLIC
L9214A/G
6 Agere Systems Inc.
Description (continued)
Longitudinal balance is consistent with European ETSI
and North American GR-909 requirements. Specifica-
tions are given in Table 10.
Data control is via a parallel unlatched control scheme.
The dc current limit is programmable in the active
modes by use of an external resistor connected
between DCOUT and IPROG. Design equations for this
feature are given in the dc Loop Current Limit section
within the Applications section of this data sheet.
Programming range is 15 mA to 45 mA with VCC =
5.0 V and 15 mA to 35 mA with VCC = 3.3 V. Program-
ming accuracy is ±10% over this current range.
Circuitry is added to the L9214 to minimize the inrush
of current from the VCC supply and to the battery supply
during an on- to off-hook transition, thus saving in
power supply design cost. See the Applications section
of this data sheet for more information.
Transmit and receive gains have been chosen to mini-
mize the number of external components required in
the SLIC-codec ac interface, regardless of the choice
of codec.
The L9214 uses a voltage feed-current sense architec-
ture; thus, the transmit gain is a transconductance. The
L9214 transconductance is set via a single external
resistor, and this device is designed for optimal perfor-
mance wi th a transconductance set at 300 V/A.
The L9214 offers an option for a single-ended to differ-
ential receive gain of either 8 or 2. These options are
mask programmable at the factory and are selected by
choice of product code.
A receive gain of 8 is more appropriate when choosing
a first-generation type codec where termination imped-
ance, hybrid balance, and overall gains are set by
external analog filters. The higher gain is typically
required for synthesization of complex termination
impedance.
A receive gain of 2 is more appropriate when choosing
a third-generation type codec. Third-generation codecs
will synthesize termination impedance and set hybrid
balance and overall gains. To accomplish these func-
tions, thir d-generation codecs typ ical ly have both ana-
log and digital gain filters. For optimal signal to noise
performance, it is best to operate the codec at a higher
gain level. If the SLIC then provides a high gain, the
SLIC output may be saturated causing clipping distor-
tion of the signal at tip and ring. To avoid this situation,
with a higher gain SLIC, external resistor dividers are
used. These external components are not necessary
with the lower gain offered by the L9214. See the Appli-
cations section of this data sheet for more information.
The L9214 is internally referenced to 1.5 V. The SLIC
output VITR is referenced to AGND; therefore, it must
be ac-coupled to the codec input. However, the SLIC
inputs RCVP/RCVN are floating inputs. If there is not
feedback from RCVP/RCVN to VITR, RCVP/RCVN
may be directly coupled to the codec output. If there is
feedback from RCVP/RCVN to VITR, RCVP/RCVN
must be ac coupled to the codec output.
The L9214 is therma ll y protec ted to guard aga ins t
faults. Upon reaching the thermal shutdown tempera-
ture, the device will enter an all-off mode. Upon cool-
ing, the device will re-enter the state it was in prior to
thermal shutdown. Hysteresis is built in to prevent
oscillation.
The L9214 is packaged in the 28-pi n SOG, 32- pi n
PLCC and 48-pin MLCC surface-mount packages. The
L9214A is set for gain of eight applications, and the
L9214G is set for gain of two applications.
Preliminary Data Sheet
October 2001 Low-Cost Ringing SLIC
L9214A/G
Agere Systems Inc. 7
Architecture Diagram
12-3530.C (F)
Figure 1. Architecture Diagram
IREF
VITR
TXI
ITR
VTX
PT
PR
ICM
TRGDET
CF2
CF1
FB2
FB1
POWER/BATTERY SWIT CH
AGND VCC BGND VBAT2 VBAT1 IPROG NSTAT RTFLT DCOUT
REFERENCE
AAC
X20
(ITR/308)
TIP/RING
CURRENT
SENSE
ITR
ITR
RFT
18 Ω
RFR
18 Ω
VBAT1 PARALLEL
DATA
INTERFACE
B0 B1 B2 B3
X1
X1
RCVN
RCVP
CURRENT
LIMIT
AND
INRUSH
CONTROL
RING
LOOP
RECTIFIERVTX
COMMON-
MODE
CURRENT
DETECTOR
TRIP
CLOSURE
–
+
9214A GAIN = 4
+
–
+
–
–
+
GAIN
AX
9214G GAIN = 1
ac INTERFACE
CIRCUIT
VBAT2
VBAT1 VBAT2
VREF
Prel iminary Data Sheet
October 2001
Low-Cost Ringing SLIC
L9214A/G
8 Agere Systems Inc.
Pin Information
12-3568 (F)
Figure 2. 28-Pin SOG Diagram
Figure 3. 32-Pin PLCC Diagram
5
6
7
8
9
10
11
25
24
23
22
21
20
19
DCOUT
IPROG
CF2
CF1
RTFLT
IREF
AGND
B0
B1
B2
B3
FB1
PR
PT
L9214
4RCVN
3RCVP
2VITR
1NSTAT
26 ITR
27 VTX
28 TXI
12VCC
13VBAT1
14VBAT2
18 FB2
17 ICM
16 TRGDET
15 BGND
28-PIN SOG
1430
5
13 21
29
14 20
32 3132
28
27
26
25
24
23
22
15 16 17 18 19
12
11
10
9
8
7
6
IREF
AGND
VCC
VBAT1
VBAT2
BGND
TRGDET
RTFLT
CF1
CF2
IPROG
DCOUT
NC
NC
NC
RCVN
RCVP
VITR
NC
NSTAT
TXI
VTX
ITR
ICM
FB2
FB1
PT
PR
B3
B2
B1
B0
L9214
32-PIN PLCC
Preliminary Data Sheet
October 2001 Low-Cost Ringing SLIC
L9214A/G
Agere Systems Inc. 9
Pin Information (continued)
12-3361f(F)
Figure 4. 48-Pin MLCC Diagram
1
3
4
6
7
8
9
10
11
12
2
48 46 45 44 43 42 41 40 38 3747
13 16 17 18 19 20 21 22 23 2414
36
33
32
31
30
29
28
27
26
25
35
B3
PT
FB1
NC
I
REF
NC
PR
RCVN
NC
RCVP
NC
NC
FB2
TRGDET
NC
V
BAT2
VITR
34
VTX
39
15
5
NC
I
PROG
CF2
RTFLT
AGND
NC
ICM
B2
B0
35
L9214A/G
48-PIN MLCC
DCOUT
CF1
B1
BGND
NC
NC
NC
NC
VCC
NC
NC
NC
NC
NC
NC
NC
ITR
TXI
NSTAT
NC
V
BAT1
Prel iminary Data Sheet
October 2001
Low-Cost Ringing SLIC
L9214A/G
10 Agere Systems Inc.
Pin Information (continued)
Table 1. Pin Descriptions
28-Pin
SOG 32-Pin
PLCC 48-Pin
MLCC Symbol Type Name/Function
1143NSTATOLoop Closure Detector Output—Ring Trip Detector
Output. When low, this logic output indicates that an off-
hook condition exists or ringing is tripped.
——5, 14, 18,
28, 32, 39,
42, 44
NC —No Connection. May be used as a tie point.
—2, 6, 7, 8 1—4, 8,
1 1, 17, 21,
27, 30, 37,
46
NC —No Connection. May not be used as a tie point.
2345VITROTransmit ac Output Voltage. Output of internal AAC
amplifier. This output is a voltage that is directly propor-
tional to the differential ac tip/ring current.
3 4 47 RCVP I Receive ac Signal Input (Noninverting). This high-
impedance input controls to ac differential voltage on tip
and ring. This node is a floating input.
4 5 48 RCVN I Receive ac Signal Input (Inverting). This high-imped-
ance input controls to ac differential voltage on tip and
ring. This node is a floating input.
5 9 6 DCOUT O dc Output Voltage. This output is a voltage that is
directly proportional to the absolute value of the differen-
tial tip/ring current. This is used to set the dc current limit
and the ring trip threshol d.
610 7 I
PROG ICurrent-Limit Program Input. A resistor is connected
from this pin to DCOUT to program the dc current limit for
the device.
711 9 CF2—Filter Capacitor. Connect a capacitor from this node to
ground.
81210 CF1—Filter Capacitor. Connect a capacitor from this node to
CF2.
91312RTFLT—Ring Trip Filter. Connect this lead to DCOUT via a resis-
tor and to AGND with a capacitor or a resistor capacitor
combination, depending on the ringing type, to filter the
ring trip circuit to prevent spu r iou s respo ns es.
10 14 13 IREF ISLIC Internal Reference Current. Connect a resistor
between this pin and AGND to generate an internal refer-
ence current.
11 15 15 AGND GND Analog Signal Ground.
12 16 16 VCC PWR Analog Power Supply. User choice of 5 V or 3.3 V nom-
in al power supply.
13 17 19 VBAT1 PWR Battery Supply 1. High-voltage battery.
14 18 20 VBAT2 PWR Battery Supply 2. Low-voltage battery or power control
resistor.
15 19 22 BGND GND Battery Ground. Ground return for the battery supplies.
Preliminary Data Sheet
October 2001 Low-Cost Ringing SLIC
L9214A/G
Agere Systems Inc. 11
Pin Information (continued)
Table 1. Pin Descriptions (continued)
28-Pin
SOG 32-Pin
PLCC 48-Pin
MLCC Symbol Type Name/Function
16 20 23 TRGDET O Tip/Ring Ground De tect. When high, this open collector
output indicates the presence of a ring ground or a tip
ground. This supervision output may be used in ground
key or common-mode fault detection applications.
17 21 24 ICM I Common-Mode Current Sense. To program tip or ring
ground sense threshold, connect a resistor to VCC and
connect a capacitor to AGND to filter 50/60 Hz. If unused,
the pin is connected to ground.
18 22 25 FB2 —Polarity Reversal Slowdown Capacitor. Connect a
capacitor from this node for controlling rate of battery
reversal. Also used for ringing, this pin cannot be left
open.
19 23 26 FB1 —Polarity Reversal Slowdown Capacitor. Connect a
capacitor from this node for controlling rate of battery
reversal. Also used for ringing, this pin cannot be left
open.
20 24 29 PT I/O Protected Tip. The input to the loop sensing circuit and
output drive of the tip amplifier. Connect to loop through
overvoltage and overcurrent protection.
21 25 31 PR I/O Protected Ring. The input to the loop sensing circuit and
output drive of the ring amplifier. Connect to loop through
overvoltage and overcurrent protection.
22 26 33 B3 I State Control Input.
23 27 34 B2 I State Control Input.
24 28 35 B1 I State Control Input.
25 29 36 B0 I State Control Input.
26 30 38 ITR I Transmit Gain. Input to AX amplifier. Connect a resistor
from this node to VTX to set transmit gain. Gain shaping
for termination impedance with a COMBO I codec is also
achieved with a network from this node to VTX.
27 31 40 VTX O ac/dc Output Voltage. Output of internal AX amplifier.
The voltage at this pin is directly proportional to the differ-
ential tip/ring current.
28 32 41 TXI I ac/dc Separation . Input to internal AAC amplifier. Con-
nect a 0.1 µF capacitor from this pin to VTX.
Prel iminary Data Sheet
October 2001
Low-Cost Ringing SLIC
L9214A/G
12 Agere Systems Inc.
Operating States
Table 2. Control States
* In this state, all supervision functions are disabled, on hook transmission is disabled, pin PT is posit ive with respect to PR, VBAT1 is applied to
tip/ring, and the tip to ring voltage will be equivalent to the scan state.
B3 B2 B1 B0 State
0 0 0 0 Disconnect
0 0 0 1 Ringing, (line reverse with high slope)
0 0 1 0 Unused*
0 0 1 1 Ringing, (line forward with high slope)
0 1 0 0 Disconnect
0 1 0 1 Reverse active and on-hook, fast polarity reversal
0110Scan
0 1 1 1 Forward active and on-hook, fast polarity reversal
1 0 0 0 Disconnect
1 0 0 1 Ringing, (line reverse with low slope)
1 0 1 0 Unused*
1 0 1 1 Ringing, (line forward with low slope)
1 1 0 0 Disconnect
1 1 0 1 Reverse active and on-hook, slow polarity reversal
1110Scan
1 1 1 1 Forward active and on-hook, slow polarity reversal
State Definition s
Forward Active (Fast Polarity Reversal)
Off-hook
■Pin PT is positive with respect to PR.
■VBAT2 is applied to tip/ring drive amplifiers for the
majority of loop lengths. This may also be derived
from VBAT1 through a power control resistor.
■Loop closure and common-mode detect are active.
■Ring trip detector is turned off to conserve power.
■Overhead is set for undistorted transmission of
+3.17 dBm into 600 Ω.
On-hook
■Pin PT is positive with respect to PR.
■VBAT1 is applied to tip/ring drive amplifiers. The tip to
ring on-hook differential voltage will be between
–42.5 V and –56.5 V with a primary battery of –65 V.
■Loop closure and common-mode detect are active.
■Ring trip detector is turned off to conserve power.
■On-hook transmission is enabled.
■Overhead is set to nominal 17.0 V for undistorted
transmission of 0 dBm into 600 Ω.
Forward Active (Slow Polarity Reversal)
Off-hook
■Same as the forward active (fast polarity reversal)
state, but with slower polarity reversal.
On-hook
■Same as the forward active (fast polarity reversal)
state, but with slower polarity reversal.
Preliminary Data Sheet
October 2001 Low-Cost Ringing SLIC
L9214A/G
Agere Systems Inc. 13
State Definition s (continued)
Reverse Active (Fast Polarity Reversal)
Off-hook
■Pin PR is positive with respect to PT.
■VBAT2 is applied to tip/ring drive amplifiers via the soft
battery switch for the majority of loop lengths. This
may also be derived from VBAT1 through a power
control resistor.
■Loop closure and common-mode detect are active.
■Ring trip detector is turned off to conserve power.
■Overhead is set to nominal 4.0 V for undistorted
transmission of 0 dBm into 600 Ω and may be
increased automatically for larger signal levels.
On-hook
■Pin PR is positive with respect to PT.
■VBAT1 is applied to tip/ring drive amplifiers. The tip to
ring on-hook differential voltage will be between
–42.5 V and –56.5 V with a primary battery of –65 V.
■Loop closure and common-mode detect are active.
■Ring trip detector is turned off to conserve power.
■On-hook transmission is enabled.
■Overhead is set to nominal 17.0 V for undistorted
transmission of 0 dBm into 600 Ω.
Reverse Active (Slow Polarity Reversal)
Off-hook
■Same as the reverse active (fast polarity reversal)
state, but with slower polarity reversal.
On-hook
■Same as the reverse active (fast polarity reversal)
state, but with slower polarity reversal.
Scan
■Except for loop closure, all circuits (including ring trip
and common-mode detector) are powered down.
■On-hook transmission is disabled.
■Pin PT is positive with respect to PR, and VBAT1 is
applied to tip/ring.
■The tip to ring on-hook differential voltage will be
between –42.5 V and –56.5 V with a –65 V primary
battery.
Disconnect
■The tip/ring amplifiers and all supervision are turned
off.
■The SLIC goes into a high-impedance state.
■NSTAT is forced high (on-hook).
Ring
■Ringing controlled digitally or by a PWM input signal
■Power ring signal is applied to tip and ring.
■Software-selectable slew rate, fast or slow.
■Ring trip supervision and common-mode current
supervision are active; loop closure is inactive.
■Overhead voltage is reduced to typically 2.5 V and
current limit set at IPROG is disabled.
■Current is limi ted by sa turati on cu rren t of the ampli fi-
ers themselves, typically 72 mA peak at 125 °C.
Thermal Shutdown
■Not controlled via truth table inputs.
■This mode is caused by excessive heating of the
device, such as may be encountered in an extended
power-cross situation.
Prel iminary Data Sheet
October 2001
Low-Cost Ringing SLIC
L9214A/G
14 Agere Systems Inc.
Absolute Maximum Ratings (at TA = 25 °C)
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
Note: The IC can be damaged unless all ground connections are applied before, and removed after, all other connections. Furthermore, when
powering the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds the
device ratings. For example, inductance in a supply lead could resonate with the supply filter capacitor to cause a destructive overvoltage.
Table 3. Typical Operating Characteristics
Table 4. Thermal Characteristics
1. This parameter is not tested in production. It is guaranteed by design and device characterization.
2. Airflow, PCB board layers, and other factors can greatly affect this parameter.
Parameter Symbol Min Typ Max Unit
dc Supply (VCC) —–0.5 —7.0 V
Battery Supply (VBAT1)———–80 V
Battery Supply (VBAT2)———VBAT1 V
Logic Input Voltage —–0.5 —VCC + 0.5 V
Logic Output Voltage —–0.5 —VCC + 0.5 V
Operating Temperature Range —–40 —125 °C
Storage Temperature Range —–40 —150 °C
Relative Humidity Range —5—95 %
Ground Potential Difference (BGND to AGND) ———±1 V
Parameter Min Typ Max Unit
5 V dc Supplies (VCC)—5.0 5.25 V
3 V dc Supplies (VCC)2.973.3—V
High Office Battery Supply (VBAT1)–63 –65 –70 V
Auxiliary Office Battery Supply (VBAT2)–15 –21 VBAT1 V
Operating Temperature Range (28-pin SOG) 0 25 70 °C
Operating Temperature Range (32-pin PLCC) –40 25 85 °C
Parameter Min Typ Max Unit
Thermal Protection Shutdown (Tjc) 150 165 —°C
28-pin SOG Thermal Resistance Junction to Ambient (θJA)1, 2:
Natural Convection 2S2P Board
Wind Tunnel 200 Linear Feet per Minute (LFPM) 2S2P Board —
—70
59 —
—°C/W
°C/W
32-pin PLCC Thermal Resistance Junction to Ambient (θJA)1, 2:
Natural Convection 2S2P Board
Natural Convection 2S0P Board
Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S2P Board
Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S0P Board
—
—
—
—
35.5
50.5
31.5
42.5
—
—
—
—
°C/W
°C/W
°C/W
°C/W
48-pin MLCC Thermal Resistance Junction to Ambient (θJA)1, 2 —38 —°C/W
Preliminary Data Sheet
October 2001 Low-Cost Ringing SLIC
L9214A/G
Agere Systems Inc. 15
Electrical Characteristics
Table 5. Environmental Characteristics
1. Not to exceed 26 grams of water per kilogram of dry air.
Table 6. 5.0 V Supply Currents
VBAT1 = –65 V, VBAT2 = –21 V, VCC = 5.0 V.
Table 7. 5.0 V Powering
VBAT1 = –65 V, VBAT2 = –21 V, VCC = 5.0 V.
Note: Refer to the power control description in the Applications section to calculate power dissipation in the forward/reverse off-hook state.
Parameter Min Typ Max Unit
Temperature Range (28-pin SOG) 0 —70 °C
Temperature Range (32-pin PLCC and 48-pin MLCC) –40 —85 °C
Humidi ty Rang e15—951%RH
Parameter Min Typ Max Unit
Supply Currents (scan state; no loop current):
IVCC
IVBAT1
IVBAT2
—
—
—
2.90
0.09
0.04
3.80
0.20
0.07
mA
mA
mA
Supply Currents (forward/reverse active; no loop current, VBAT1 applied):
IVCC
IVBAT1
IVBAT2
—
—
—
4.8
1.5
1.0
6.00
1.95
1.20
mA
mA
mA
Supp ly Curr en ts (disco nne ct mode):
IVCC
IVBAT1
IVBAT2
—
—
—
1.60
0.02
0.01
2.20
0.10
0.02
mA
mA
mA
Supply Currents (ringing mode, no load applied):
IVCC
IVBAT1
IVBAT2
—
—
—
4.40
1.70
0.57
5.0
2.2
0.7
mA
mA
mA
Parameter Min Typ Max Unit
Power Dissipation (scan state; no loop current) —21 33 mW
Power Dissipation (forward/reverse active; no loop current, VBAT1 applied) —143 182 mW
Power Dissipation (disconnect mode) —10 18 mW
Power Dissipation (ring mode; no load applied) —144 183 mW
Prel iminary Data Sheet
October 2001
Low-Cost Ringing SLIC
L9214A/G
16 Agere Systems Inc.
Electrical Characteristics (continued)
Table 8. 3.3 V Supply Currents
VBAT1 = –65 V, VBAT2 = –21 V, VCC = 3.3 V.
Table 9. 3.3 V Powering
VBAT1 = –65 V, VBAT2 = –21 V, VCC = 3.3 V.
Note: Refer to the power control description in the Applications section to calculate power dissipation in the forward/reverse off- hook state.
Parameter Min Typ Max Unit
Supply Currents (scan state; no loop current):
IVCC
IVBAT1
IVBAT2
—
—
—
2.30
0.09
0.04
3.00
0.18
0.07
mA
mA
mA
Supply Currents (forward/reverse active; no loop current, VBAT1 applied):
IVCC
IVBAT1
IVBAT2
—
—
—
4.40
1.50
0.97
5.30
1.90
1.20
mA
mA
mA
Supply Currents (disconnect mode):
IVCC
IVBAT1
IVBAT2
—
—
—
1.20
0.02
0.01
1.70
0.10
0.02
mA
mA
mA
Supply Currents (ringing mode, no load applied):
IVCC
IVBAT1
IVBAT2
—
—
—
4.00
1.64
0.54
4.75
2.16
0.60
mA
mA
mA
Parameter Min Typ Max Unit
Power Dissipation (scan state; no loop current) —14 23 mW
Power Dissipation (forward/reverse active; no loop current, VBAT1 applied) —132 166 mW
Power Dissi pation (dis co nne ct mod e) —513mW
Power Dissipation (ring mode; no loop current) —131 169 mW
Preliminary Data Sheet
October 2001 Low-Cost Ringing SLIC
L9214A/G
Agere Systems Inc. 17
Electrical Characteristics (continued)
Table 10. Two-Wire Port
* Values guaranteed by design, not subject to production test.
†Corresponds to 55 dB minimum with 1%, 30 Ω re sistors per Q552 (11/ 96) Sec tion 2.1.2 and IEEE® 455.
Parameter Min Typ Max Unit
Tip or Ring Drive Current = dc + Longitudinal + Signal Currents 72 ——mApeak
Tip or Ring Drive Current = Ringing + Longitudinal 37 ——mApeak
Signal Current 5 ——mArms
Longitudinal Current Capability per Wire (Longitudinal current is indepen-
dent of dc loop cur rent.) 8.5 15 —mArms
Ringing Current (RLOAD = 2330 Ω + 24 µF) 25 ——mApeak
Ringing Current (RLOAD = 3500 Ω + 1.8 µF) 12 ——mApeak
Ringing Current Limit (RLOAD = 100 Ω)——90 mApeak
dc Loop Current —ILIM (RLOOP = 500 Ω):
Programming Range (VCC = 5.0 V)
Programming Range (VCC = 3.3 V) 15
15 —
—45
35 mA
mA
dc Current Variation (current limit 15 mA to 45 mA) ——±10 %
dc Loop Current (RLOOP = 100 Ω, on to off hook transition)
t < 20 ms —
——
—350
100 mApeak
mA
dc Loop Current (RLOOP = 100 Ω, on to off hook transition)
t < 50 ms —
——
——
150% ILIM
dc Feed Resistance, 2 x RF (excluding protection resistors) 25 36 50 Ω
Loop Resistance Range*, (0 dB overload into 600 Ω)
ILOOP = 20 mA, V BAT2 = –24 V, 50 Ω (2 x RF), 60 Ω (2 x RP), 300 Ω RLOOP plus
Handset
ILOOP = 25 mA, VBAT1 = –65 V, 50 Ω (2 x RF), 60 Ω (2 x RP), 1000 Ω RLOOP
plus Handset
840
1540
—
—
—
—
Ω
Ω
Open Loop Voltages, |VBAT1| = –63 V to –70 V:
Scan/On-Hook Transmission Mode:
|PT – PR| – Differen tia l
|PT| or |PR| Referenced to BGND 42.5
—48
——
56.5 V
V
Ring Mode, |VBAT1| = –63 V to –70 V:
|PT – PR| – Differential, (open loop ring voltage) 40 ——Vrms
Loop Closure Threshold:
Scan/Active/On-hook Transmission Modes —10 —mA
Loop Closure Threshold Hysteresis: —2—mA
Ground Key:
Differential Detector Threshold
Detection 5
50 8
—10
—mA
ms
Longitudinal to Metallic Balance at PT/PR
Test Method per Figure 8, 1 kHz† 58 dB minimum, 60 dB typical:
300 Hz to 600 Hz
600 Hz to 3.4 kHz 55
55 58
58 —
—dB
dB
Metallic to Longitudinal (harm) Balance:
200 Hz to 1000 Hz
100 Hz to 4000 Hz 40
40 —
——
—dB
dB
PSRR 500 Hz—3000 Hz:
VBAT1, VBAT2
VCC (3.3 V operation) 40
25 —
——
—dB
dB
Prel iminary Data Sheet
October 2001
Low-Cost Ringing SLIC
L9214A/G
18 Agere Systems Inc.
Electrical Characteristics (continued)
Table 11. Analog Pin Characteristics
Parameter Min Typ Max Unit
TXI (input impedance) —100 —kΩ
Output Offset (VTX)
Output Offset (VITR)
Output Drive Current (VTX)
Output Drive Current (VITR)
Output Voltage Swing (VTX) (VCC = 5.0 V)
Output Voltage Swing (VITR) (VCC = 5.0 V)
Output Short-circuit Current (VTX)
Output Short-circuit Current (VITR)
Output Load Resistance (VT X and VITR)
Output Load Capacitance (VTX)
Output Load Capacitance (VITR)
—
—
—
—
±3.7
—
—
—
10
—
—
±5
±70
±500
±250
—
—
±5
±6
—
—
—
—
—
—
—
+5/–8
±3.1
—
—
—
20
50
mV
mV
µA
µA
V
V
mA
mA
kΩ
pF
pF
RCVN and RCVP:
Input Voltage Range (VCC = 5.0 V)
Input Voltage Range (VCC = 3.3 V)
Input Bias Current
0
0
—
—
—
—
VCC – 0.5
VCC – 0.3
±1.5
V
V
µA
Preliminary Data Sheet
October 2001 Low-Cost Ringing SLIC
L9214A/G
Agere Systems Inc. 19
Electrical Characteristics (continued)
Table 12. ac Feed Characteristics
1. S et externally either by discrete external components or a third- or fourth-generation codec. Any complex impedance R1 + R2 || C between
150 Ω and 1400 Ω can be synthesized.
2. This parameter is not tested in production. It is guaranteed by design and device characterization.
3. VITR transconductance depends on the resistor from ITR to VTX. This gain assumes an ideal 4750 Ω, the recommended value. Positive cur-
rent is defined as the differential current flowing from PT to PR.
4. Tested per Figure 9. The gain reading is adjusted by the ratio of 696/660 to account for the 36 Ω nominal ac feed resistance.
Parameter Min Typ Max Unit
ac Term ina tio n Imped anc e1150 600 1400 Ω
Total Harmonic Distortion (200 Hz—4 kHz)2:
Off-hook
On-hook —
——
—0.3
1.0 %
%
Transmit Gain (f = 1004 Hz, 1020 Hz)3:
PT/PR Current to VITR 291 300 309 V/A
Receive Gain4 (f = 1004 Hz to 1020 Hz):
RCVP or RCVN to PT—PR (gain of 8 option, L9214A)
RCVP or RCVN to PT—PR (gain of 2 option, L9214G) 7.6
1.9 8
28.4
2.1 —
—
Gain vs. Frequency (transmit and receive)2, 600 Ω Te rm in ation
(Q.552), 1004 Hz, 1020 Hz reference:
200 Hz—300 Hz
300 Hz—3.4 kHz
3.4 kHz—3.6 kHz
3.6 kHz—20 kHz
20 kHz—266 kHz
–0.30
–0.05
–1.50
–3.00
—
0
0
0
–0.1
—
0.05
0.05
0.05
–0.05
–2.0
dB
dB
dB
dB
dB
Gain vs. Level (transmit and receive)2, 0 dBV Reference (Q.552):
–55 dB to +3.0 dB –0.05 0 0.05 dB
Idle-channel Noise (tip/ring) 600 Ω Termination:
Psophometric
C-Message
3 kHz Flat
—
—
—
–82
8
—
–77
13
20
dBmp
dBrnC
dBrn
Idle-channel Noise (VTX) 600 Ω Termination:
Psophometric
C-Message
3 kHz Flat
—
—
—
–82
8
—
–77
13
20
dBmp
dBrnC
dBrn
Prel iminary Data Sheet
October 2001
Low-Cost Ringing SLIC
L9214A/G
20 Agere Systems Inc.
Electrical Characteristics (continued)
Table 13. Logic Inputs and Outputs (VCC = 5.0 V)
Table 14. Logic Inputs and Outputs (VCC = 3.3 V)
Table 15. Ringing Specifications
1. Voltage is measured across both resistive and capacitive elements of the ringer load.
2. Voltage is measured only across the resistive element of the ringer load.
Parameter Symbol Min Typ Max Unit
Input Voltages:
Low Level
High Level
VIL
VIH –0.5
2.0 0.4
2.4 0.7
VCC V
V
Input Current:
Low Level (VCC = 5.25 V, VI = 0.4 V)
High Level (VCC = 5.25 V, VI = 2.4 V) IIL
IIH —
——
—±250
±250 µA
µA
Output Voltages (open collector with internal pull-up resistor):
Low Level (VCC = 4.75 V, IOL = 200 µA)
High Level (VCC = 4.75 V, IOH = –10 µA) VOL
VOH 0
2.4 0.2
—0.4
VCC V
V
Parameter Symbol Min Typ Max Unit
Input Voltages:
Low Level
High Level
VIL
VIH –0.5
2.0 0.2
2.5 0.5
VCC V
V
Input Current:
Low Level (VCC = 3.46 V, VI = 0.4 V)
High Level (VCC = 3.46 V, VI = 2.4 V) IIL
IIH —
——
—±250
±250 µA
µA
Output Voltages (open collector with internal pull-up resistor):
Low Level (VCC = 3.13 V, IOL = 200 µA)
High Level (VCC = 3.13 V, IOH = –5 µA) VOL
VOH 0
2.2 0.2
—0.5
VCC V
V
Parameter Min Typ Max Unit
Ring Signal Isolation:
PT/PR to VITR
Ring Mode
—60 —dB
Ringing V oltage (5 REN 1386 Ω + 40 µF load, 200 Ω loop, 2 x 30 Ω protection
resistors, –69 V battery, 1.2 crest factor)140 ——Vrms
Ringing V oltage (3 REN 2330 Ω + 24 µF load, 600 Ω loop, 2 x 30 Ω protection
resistors, –69 V battery, 1.2 crest factor)140 ——Vrms
Ringing Voltage (2 REN 3500 Ω + 16 µF load, 1000 Ω loop, 2 x 30 Ω protec -
tion re si st or s, –69 V battery, 1.2 crest factor)140 ——Vrms
Ringing V oltage (2 REN 3500 Ω + 1.8 µF load, 500 Ω loop, 2 x 30 Ω protection
resistors, –69 V battery, 1.2 crest factor)240 ——Vrms
Ring Signal Distortion:
5 REN 1386 Ω, 40 µF Load, 200 Ω Loop
3 REN 2330 Ω, 24 µF Load, 600 Ω Loop
2 REN 3500 Ω, 16 µF Load, 1000 Ω Loop
2 REN 3500 Ω, 1.8 µF Load, 500 Ω Loop
—
—
—
—
5
5
5
5
—
—
—
10
%
%
%
%
Preliminary Data Sheet
October 2001 Low-Cost Ringing SLIC
L9214A/G
Agere Systems Inc. 21
Electrical Characteristics (continued)
Table 16. Ring Trip (3 REN Configuration)
Ringing will not be tripped by the following loads:
■100 Ω resistor in series with a 2 µF capacitor applied across tip and ring. Ring frequency = 17 Hz to 23 Hz.
■10 kΩ resistor in parallel with a 4 µF capacitor applied across tip and ring. Ring frequency = 17 Hz to 23 Hz.
Table 17. Ring Trip (5 REN Configuration)
Ringing will not be tripped by the following loads:
■100 Ω resistor in series with a 2 µF capacitor applied across tip and ring. Ring frequency = 17 Hz to 23 Hz.
■10 kΩ resistor in parallel with a 6 µF capacitor applied across tip and ring. Ring frequency = 17 Hz to 23 Hz.
Note: Refer to the application section for further description of the 3 REN configuration vs. 5 REN configuration.
Parameter Min Typ Max Unit
Ring Trip (NSTAT = 0): Loop Resistance (total) 0 —1000 Ω
Ring Trip (NSTAT = 1): Loop Resistance (total) 10 ——kΩ
Ringer Load ——2330 Ω + 24 µF—
Trip Time (f = 20 Hz) —— 130 ms
Parameter Min Typ Max Unit
Ring Trip (NSTAT = 0): Loop Resistance (total) 0 —600 Ω
Ring Trip (NSTAT = 1): Loop Resistance (total) 10 ——kΩ
Ringer Load ——1386 Ω + 40 µF—
Trip Time (f = 20 Hz) —— 150 ms
Prel iminary Data Sheet
October 2001
Low-Cost Ringing SLIC
L9214A/G
22 Agere Systems Inc.
Test Configurations
12-3531.j (F)
Figure 5. Basic Test Circuit, VCC = 3.3 V (3 REN Configuration)
VBAT2 VBAT1 BGND VCC AGND ICM TRGDET
0.1 µF
0.1 µF
0.1 µF
RTFLT
DCOUT
PR
PT
30 Ω
30 Ω
CF1
CF2
B0
B1
B2
B3
0.1 µF
VITR
RCVP
RCVN
ITR
VTX
TXI
VBAT2 VBAT1 VCC
RLOOP
100 Ω/600 Ω
TIP
RING
FB2
FB1
0.47 µF
L9214
NSTAT
B0
B1
B2
B3
4750 Ω
0.1 µF
600 kΩ
0.1 µFVCC
IPROG
IREF
28.7 kΩ
5.76 kΩ
75 kΩ
133 kΩ
1 µF
0.047 µF
0.047 µF
RCVP
RCVN
VITR
Preliminary Data Sheet
October 2001 Low-Cost Ringing SLIC
L9214A/G
Agere Systems Inc. 23
Test Configurations (continued)
12-2582.c (F)
Figure 6. Metallic PSRR
12-2583.b (F)
Figure 7. Longitudinal PSRR
12-2584.D (F)
Figure 8. Longitudinal Balance
12-2587.J (F)
Figure 9. ac Gains
VS
4.7 µF
100 Ω
VBAT OR
VCC
DISCONNECT
VT/R
VBAT OR VCC
TIP
RING
BASIC
TEST CIRCUIT
+
–
PSRR = 20log VS
VT/R
600 Ω
BYPASS CAPACITOR
VS
4.7 µF
100 Ω
VBAT OR
VCC
DISCONNECT
BYPASS CAPACITOR
56.3 Ω
VBAT OR VCC
TIP
RING
BASIC
TEST CIRCUIT
PSRR = 20log VS
VM
67.5 Ω
10 µF
10 µF
67.5 Ω
VM
+
–
TIP
RING
BASIC
TEST CIRCUIT
LONGITUDINAL BALANCE = 20log VS
VITR
368 Ω
100 µF
100 µF
368 Ω
VS
VITR
PT
PR
BASIC
TEST CIRCUIT
600 ΩVT/R
+
–
RCVN
VS
VITR
RCVN OR
RCVP
OR
RCVP
GXMT VXMT
VTR⁄
-------------
=
GRCV VTR⁄
VRCVP OR VRCVN
-------------------------------------------------
=
Prel iminary Data Sheet
October 2001
Low-Cost Ringing SLIC
L9214A/G
24 Agere Systems Inc.
Applications
Power Con trol
Under normal device operating conditions, power dissi-
pation must be controlled to prevent the device temper-
ature from rising too close to the thermal shutdown
point. Power dissipation is highest with higher battery
voltages, higher current limit, and under shorter dc loop
conditions. Additionally, higher ambient temperature
will reduce thermal margin. Increasing the number of
PC board layers and increasing airflow around the
device are typical ways of improving thermal margin.
The maximum recommended junction temperature for
the L9214 is 150 °C. The junction temperature is:
Tj = TAMBIENT + θJA * PSLIC
The thermal impedance of this device depends on the
package type as well as number of PCB layers and air-
flow. The thermal impedance of the 28-pin SOG pack-
age is somewhat higher than the 32-pin PLCC
package. The 28-pin SOG package in still air with a
single-sided PCB is rated at 70 °C/W. The 32-pin
PLCC package thermal impedance with no airflow on a
four-l ayer PCB is estimated at 37 °C/W.
The power handling capability of the package is:
PSLIC = (150 °C – TAMBIENT)/θJA
which is a minimum of 0.93 W for the 28-pin SOG
package with a single-sided PCB and no airflow and as
much as 2.15 W for the 32-pin PLCC package with a
mult ilayer PCB.
This device is intended to operate with a high-voltage
primar y batte ry of –63 V to –70 V. Unde r sh ort-lo o p
conditions, an internal soft battery switch shunts most
(all but IBIAS = 3.5 mA) of the loop current to an auxiliary
battery of lower absolute voltage (typically –21 V).
Where single battery operation is required, an external
power control resistor can be connected from the VBAT2
pin to VBAT1 and all but 3.5 mA of the loop current will
flow through the power control re si st or.
The power dissipated in the device is best illustrated by
an example. As su me VBAT1 is –65 V, VBAT2 is –21 V,
and the current limit is is ILOOP.
Let IQ1 and IQ2 be the quiescent currents drawn from
VBAT1 and VBAT2 respectively (the current drawn from
the battery when the phone is on-hook). Let IBIAS be
the additional current drawn from VBAT1 when the
phone is off-hook.
IBIAS = IVBAT1(off-hook) – IQ1
Typically IBIAS is 3.5 mA. This additional VBAT1 current
contributes to the loop current and the remaining loop
current is supplied by VBAT2, so that
IVBAT2 = IQ2 + ILOOP – IBIAS
IVCC is the current drawn from VCC and is relatively con-
stant as the phone goes off hook.
The total power from the power suppl ies is:
PTOTAL = {[(IQ1 + IBIAS) * VBAT1] + [(IQ2 + ILOOP – IBIAS) *
VBAT2] + [(IVCC) * VCC]}
The maximu m va lue s of IQ1 and IQ2 are 1.95 mA and
1.20 mA respectively from Table 4.
If the current limit is set to 25 mA, given the current limit
tolerance of 10%, the maximum current limit is
27.5 mA. Also, assume 20 Ω of wire resistance, 30 Ω
of protection resistance, and 200 Ω for the handset
PTOTAL = {[(1.95 mA + 3.5 mA) * (65 V)] + [(1.20 mA +
27.5 mA – 3.5 mA) * (21 V)] + [(6 mA) * (5 V)]
= 913.45 mW
The power delivered to the loop and the protection
resistors (PLOOP) is:
PLOOP = {(ILOOP)2 * [(2 * RPROTECTION) + (RWIRE) +
(RPHONE)]} = {(27.5 mA)2 * [(2 * 30 Ω) + (20 Ω) +
200 Ω)]} = 212 mW
Thus, the total power diss ipated by the SLIC is:
PD of SLIC = Total power (PTOTAL) – power delivered to
loop and protection resistors (PLOOP).
PD = 913.45 mW – 212 mW
= 701.45 mW for this example.
Since the minimum power handling capability of the
28-pin SOG package is 0.93 W, in this case either
package type is acceptable even with a single-sided
PCB. At higher battery voltages, higher ambient tem-
perature, and higher current limit, the required thermal
impedance drops and the 32-pin PLCC package, more
PCB layers, or some airflow might be required.
Another case to consider is the case of the power con-
trol resistor. In this case, the effective VBAT2 voltage is:
VBAT2 = VBAT1 – RPWR * (ILOOP – IBIAS + IQ2)
For the case of the 27.5 mA maximum current limit,
choosing RPWR = 1.75 k Ω would give VBAT2 = –21 V and
the same SLIC power as above. The power in the
resistor would be:
PRPWR = (ILOOP – IBIAS + IQ2)2 * RPWR = 1.11 W
Choo sing a larg er RPWR would result in lower V BAT2 and
lower SLIC power, but more power in the resistor. Simi-
larly, choosing a smaller RPWR resul ts in higher VBAT2,
higher SLIC power, and less power in the resistor.
Preliminary Data Sheet
October 2001 Low-Cost Ringing SLIC
L9214A/G
Agere Systems Inc. 25
Applications (continued)
dc Loop Cu rrent Limit
In the active modes, dc current limit is programmable
via an external resistor. The resistor is connected
between IPROG and DCOUT. The loop current limit
(ILOOP) with 100 Ω load is related to the RIPROG pro-
gramming resistor by:
ILOOP (mA) = 4 mA/kΩ * RIPROG (kΩ) + 2 mA
Note that the overall current-limit accuracy achieved
will be affected by the specified accuracy of the internal
SLIC current-limit circuit and the accuracy of the exter-
nal resistor.
The above equation describes the active mode steady-
state current-limit response. There will be a transient
response of the current-limit circuit upon an on- to off-
hook transition. Typical active mode transient current-
limit response is given in Table 18.
Table 18. Typical Active Mode On- to Off-Hook Tip/
Ring Current-Limit Transient Response
Overhead Voltage
Active Mode
The overhead is preprogrammed in the active mode.
Note that overhead is not symmetrical with respect to
tip and ring. Under default conditions, the tip to ground
voltage is 2.1 V to 2.6 V and the ring to battery over-
head is 14.5 V typical.
The default overhead provides sufficient headroom for
on-hook transmission of a +3.17 dBm signal into
600 Ω.
+3.17 dBm = 10 log (Vrms2 / P0 * R600 Ω)
dBm = 10 log (Vrms2 / 0.001 W * 600 Ω)
+3.17 dBm = 10 log
Vrms = 1.12 V and Vpeak = 1.58 V are supported.
Scan Mode
If the magnitude of the primary battery is greater than
a nominal –63 V, the magnitude of the open-loop tip
to ring voltage is clamped to between –42.5 V and
–56.5 V.
Again, the overhead is not symmetrical with respect to
tip and ring. With the magnitude of the primary battery
greater than a nominal –63 V, the tip to ground voltage
is clamped between –0.1 V and –0.6 V and the ring to
ground voltage is clamped between –42.5 V and
–56.5 V. If the magnitude of the primary battery is less
than a nominal –63 V, the tip to ground voltage is
–0.1 V to –0.6 V and the ring to battery voltage is typi-
cally 17 V less than VBAT1.
On-Hook Transmission Mode
If the magnitude of the primary battery is greater than
63 V, the magnitude of the open-loop tip to ring voltage
will be greater than 42.5 V. If the magnitude of the pri-
mary battery is less than 63 V, the open-loop voltage
may be less than 42.5 V and is approximately 17 V less
than the magnitude of the primary battery voltage. For
primary battery voltages less than 70 V, the magnitude
of the ring to ground voltage will be less than 56.5 V.
Again, the overhead is not symmetrical with respect to
tip and ring. The tip voltage to ground is between –2 V
and –4.5 V and the ring to primary voltage is 14.5 V
typical.
Parameter Value Unit
dc Loop Current: Ac tive Mode
RLOOP = 100 Ω On- to Off-hook
Transition t < 20 ms
ILOOP + 60 mA
dc Loop Current: Ac tive Mode
RLOOP = 100 Ω On- to Off-hook
Transition t < 30 ms
ILOOP + 20 mA
dc Loop Current: Ac tive Mode
RLOOP = 100 Ω On- to Off-hook
Transition t < 50 ms
ILOOP mA
Vrms2
0.6 IV R×()
--------------------------------
Prel iminary Data Sheet
October 2001
Low-Cost Ringing SLIC
L9214A/G
26 Agere Systems Inc.
Applications (continued)
Overhead Voltage (continued)
Ring Mode
In the ring mode, to maximize ringing loop length, the
overhead is decreased to the saturation of the tip ring
drive amplifiers, a nominal 4 V. The tip to ground volt-
age is 1 V, and the ring to VBAT1 voltage is 3 V.
The AX amplifier at VTX is active during the ring mode,
differential ring current may be sensed at VTX during
the ring mode.
Loop Range
The dc loop range for medium-loop applications is cal-
culated using:
The dc loop range for short-loop applications is calcu-
lated using:
where:
VOHH = 19.5 (2.5 V + 17 V) and
VOHL = 3.4 V (2.5 V + 0.9 V)
and where:
RL = loop resistance, not including protection resistors.
RP = protection resistor value.
Rdc = SLIC internal dc feed resistance.
|VBAT1| and |VBAT2| = battery voltage magnitude.
ILOOP = loop current.
VOHH = overhead voltage when power is drawn from
VBAT1.
VOHL = overhead voltage when power is drawn from
VBAT2.
The point of change over between VBAT2 and VBAT1
occurs at:
|VBAT2| – (0.9 + 2.5) V > [(2RP + RDC + RL) * ILOOP] V
VBAT2 is typically applied under off-hook conditions for
power conservation and SLIC thermal considerations.
The L9214 is intende d for sho rt- and medium -loo p
applications and, therefore, will always be in current
limit during off-hook conditions. However, note that the
ringing loop length rather than the dc loop length will be
the factor to determine operating loop length. Where
VBAT2 is insufficient to support the loop length, the
power will be taken from VBAT1.
Battery Reversal Rate
The rate of battery reverse is controlled or ramped by
capacitors FB1 and FB2. A chart showing FB1/FB2 val-
ues versus typical ramp time is given below. Leave
FB1 and FB2 open if it is not desired to ramp the rate of
battery reversal.
Table 19. FB1/FB2 Values vs. Typical Ramp Time at
VBAT1 = –65 V
RLVBAT1 VOHH–()
ILOOP
-----------------------------------------------2RP–Rdc–=
RLVBAT2 VOHL–()
ILOOP
---------------------------------------------- 2RP–Rdc–=CFB1/CFB2 Transition Time
Fast, B3 = 0 Transition Time
Slow, B3 = 1
0.01 µF 7 ms 20 ms
0.1 µF 75 ms 220 ms
0.22 µF 145 ms 440 ms
0.47 µF 300 ms 900 ms
1.0 µF 600 ms 1.8 s
1.22 µF 750 ms 2.25 s
1.3 µF 830 ms 2.5 s
1.4 µF 900 ms 2.7 s
1.6 µF 1070 ms 3.2 s
Preliminary Data Sheet
October 2001 Low-Cost Ringing SLIC
L9214A/G
Agere Systems Inc. 27
Supervision
The L9214 offers the loop closure and ring trip supervi-
sion functions. Internal to the device, the outputs of
these detectors are multiplexed into a single package
output, NSTAT. Additionally, a common-mode current
detector for tip or ring ground detection is included for
ground key applications.
Loop Closure
The loop closure has a fixed typical 10 mA on- to off-
hook threshold in the active mode and a fixed 10 mA
on- to off-hook threshold from the scan mode. In either
case, there is a 2 mA hysteresis with VCC = 5.0 V and
with VCC = 3.3 V.
Ring Trip
The ring trip detector requires an external filter at the
input, minimizing external components. An R + R//C
combination of 75 kΩ and 133 kΩ // 1 µF, for a filter
pole at 3.3 Hz, is recommended for a 3 REN config-
uration. For a 5 REN configuration, a 150 kΩ and
100 kΩ // 1 µF (for a filter pole at 2.65 Hz) combination
is recommended.
The ring trip threshold is internally fixed and is indepen-
dent of battery voltage. The threshold, IRT = 20.1 mA .
Tip or Ring Ground Detector
In the ground key or ground start applications a com-
mon-mode current de tector is used to indicate either a
tip- or ring-ground has occurred (ground key) or an off-
hook has occurred (ground start). The detection thresh-
old is set by connecting a resistor from ICM to VCC.
1000 * VCC/RICM (kΩ) = ITH (mA)
where:
RICM > 80 kΩ @ VCC = 3.3 V
RICM > 150 kΩ @ VCC = 5.0 V
Additionally, a filter capacitor across RICM wil l set the
time constant of the detector. No hysteresis is associ-
ated with this detector.
Power Ring
The device offers a ring mode, in which a power ring
signal is provided to the tip/ring pair. The standard
method of ringing is to perform trapezoidal ringing by
use of the state input pins. It is possible to select either
fast or slow slew rates to alter the crest factor of the
ringing signal. This allows designers to set the external
capacitors to a specific factor and change the ringing
frequency under software control while maintaining the
crest factor between 1.2 and 1.6 for the trapezoidal sig-
nal.
During the ring mode, it is also possible to supply a
pulse-width modulated, PWM, signal into the device’s
B1 input. This signal is used to produce the power ring
signal. This signal must be removed during nonring
mode states. The user may input any crest factor ring
signal using this method; thus, the device will support a
sine wave (crest factor 1.414) or a lower or higher crest
factor input for increased power efficiency ring signal.
Various crest factors are shown below.
12-3346a (F)
Note: Slew rate = 5.65 V/ms; trise = tfall = 23 ms; pwidth = 2 ms;
period = 50 ms.
Figure 10. Ringing Waveform Crest Factor = 1.6
12-3347a (F)
Note: Slew rate = 10.83 V/ms; trise = tfall = 12 ms; pwidth = 13 ms;
period = 50 ms.
Figure 11. Ringing Waveform Crest Factor = 1.2
TIME (s)
–80
–60
–40
–20
0
20
40
60
80
0.00
0.02 0.06
0.04 0.08
0.10
0.12
0.14
0.16
0.18
0.20
VOLTS (V)
TIME (s)
–80
–60
–40
–20
0
20
40
60
80
0.00
0.02 0.06
0.04 0.08
0.10
0.12
0.14
0.16
0.18
0.20
VOLTS (V)
Prel iminary Data Sheet
October 2001
Low-Cost Ringing SLIC
L9214A/G
28 Agere Systems Inc.
Supervision (continued)
Power Ring (continued)
The ring signal will appear balanced on tip and ring.
That is, the ring signal is applied on both tip and ring,
with the signal on tip 180° out of phase from the signal
on ring. This operation is shown in Figure 12 below.
Ringing loop range is calculated as follows:
VRINGLOAD = {(VBATTERY – 4)/Crest Factor} *
{RLOAD/(RLOAD + RLOOP + 2 x RPROTECTION)}
As a practical example, calculate the maximum dc loop
length, assuming the following conditions:
Minimum required ring voltage = 40 Vrms
VBATTERY = –67 V
Trapezoidal ringing, crest factor = 1.2
Protection resistors = 30 Ω each
Ring Load = 2 North American REN = 3500 Ω + 16 µF
Ringing frequency = 25 Hz
First, calculate the equivalent ringing load resistance at
25 Hz.
RLOAD = {(35 00 Ω)2 + (2 * π * 25 * 16E–6)–2}0.5
RLOAD = 3522 Ω
40 Vrms = {(67 – 4)/1.2)} {3522 Ω/(RLOOP + 3522 Ω +
60 Ω)}
RLOOP = 1040 Ω
Effects such as power supply tolerance and crest factor
tolerance can affect this calculation.
Crest factor is estimated by the formula:
Where:
f = ringing frequency; CFB = (CFB1 + CFB2)/2;
Ics = 30 µA with B3 = 1 and 90 µA with B3 = 0;
VOHH = 4 V
1
14fC
FB VBAT1 VOHH–〈〉)×××( 3ICS×
-----------------------------------------------------------------------------------------
–
-------------------------------------------------------------------------------------------------------
=
12-3532.B (F)
Figure 12. Ring Operation
GND
VBAT
RING
LOAD
1/2 RLOOP + RPROTECTION
1/2 RLOOP + RPROTECTION
PT +1
PR
B1 SQUARE WAVE OR
PWM SIGNAL
L9214
VTIP
VRING
–1
3 V
1 V
Preliminary Data Sheet
October 2001 Low-Cost Ringing SLIC
L9214A/G
Agere Systems Inc. 29
Periodic Pulse Metering (PPM)
Periodic pulse metering (PPM), also referred to as tele-
tax (TTX), is applied to the audio input of the L9214.
When in the active state, this signal is presented to the
tip/ring subscriber loop along with the audio signal. The
L9214 assumes that a shaped PPM signal is applied to
the audio input.
ac Applications
ac Parameters
There are four key ac design parameters. Termination
impedance is the impedance looking into the 2-wire
port of the line card. It is set to match the impedance of
the telephone loop in order to minimize echo return to
the telephone set. T ransmit gain is measured from the
2-wire port to the PCM highway, while receive gain is
done from the PCM highway to the transmit port.
Transmit and receiv e gains may be spe c ified in terms
of an actual gain, or in terms of a transmission level
point (TLP), that is the actual ac transmission level in
dBm. Finally, the hybrid balance network cancels the
unwanted amount of the receive signal that appears at
the transmit port.
Codec Types
At this point in the design, the codec needs to be
selected. The interface network between the SLIC and
codec can then be designed. Below is a brief codec
feature summary.
First-Generation Codecs
These perform the basic filtering, A/D (transmit), D/A
(receive), and µ-law/A-law companding. They all have
an op amp in front of the A/D converter for transmit
gain setting and hybrid balance (cancellation at the
summing node). Depending on the type, some have
differential analog input and output stages, +5 V only or
±5 V operation, and µ-law/A-law selectability. These
are available in single and quad designs. This type of
codec requires continuous time analog filtering via
external resistor/capacitor networks to set the ac
design parameters. An example of this type of codec is
the Agere T7504 quad 5 V only codec.
This type of codec tends to be the most economical in
terms of piece part price, but tends to require more
external components than a third-generation codec.
The ac parameters are fixed by the external R/C net-
work so software control of ac parameters is difficult.
Third-Generation Codecs
This class of devices includes all ac parameters set
digitally under microprocessor control. Depending on
the device, it may or may not have data control latches.
Additional functionality sometimes offered includes
tone plant gener ati on and rece pti on, PP M generation,
test algorithms, and echo cancellation. Again, this type
of codec may be 3.3 V, 5 V only, or ±5 V operation, sin-
gle-, quad-, or 16-channel, and µ-law/A-law or 16-bit
linear coding selectable. Examples of this type of
codec are the Agere T8535/6 (5 V only, quad, standard
features), T8537/8 (3.3 V only, quad, standard fea-
tures), T8533/4 (5 V only, quad with echo cancellation),
and the T8531/32 (5 V only, eight- or 16-channel).
ac Interface Network
The ac interface network between the L9214 and the
codec will vary depending on the codec selected. With
a first-generation codec, the interface between the
L9214 and codec actually sets the ac parameters. With
a third-generation codec, all ac parameters are set dig-
itally, internal to the codec; thus, the interface between
the L9214 and this type of codec is designed to avoid
overload at the codec input in the transmit direction
and to optimize signal to noise ratio (S/N) in the receive
direction.
Because the design requirements are very different
with a first- or third-generation codec, the L9214 is
offered with two di fferent receive gains. Each r eceive
gain was chosen to optimize, in terms of external com-
ponents required, the ac interface between the L9214
and codec.
With a first-generation codec, the termination imped-
ance is set by providing gain shaping through a feed-
back network from the SLIC VITR output to the SLIC
RCVN/RCVP inputs. The L9214 provides a transcon-
ductance from T/R to VITR in the transmit direction and
a single-ended to differential gain from either RCVN or
RCVP to T/R in the receive direction. Assuming a short
from VITR to RCVN or RCVP, the maximum imped-
ance that is seen looking into the SLIC is the product of
the SLIC transc on duc tance tim es the SLI C rec eive
gain, plus the protection resistors. The various speci-
fied termination impedance can range over the voice-
band as low as 300 Ω up to over 1000 Ω. Thus, if the
SLIC gains are too low, it will be impossible to synthe-
size the higher termination impedances. Further, the
termination that is achieved will be far less than what is
calculated by assuming a short for SLIC output to SLIC
input.
Prel iminary Data Sheet
October 2001
Low-Cost Ringing SLIC
L9214A/G
30 Agere Systems Inc.
ac Applications (continued)
ac Interface Network (continued)
In the receive direction, in order to control echo, the
gain is typically a loss, which requires a loss network at
the SLIC RCVN/RCVP inputs, which will reduce the
amount of gain that is available for termination imped-
ance. For this reason, a high-gain SLIC is required with
a first-generation codec.
With a third-generation codec, the line card designer
has different concerns. To design the ac interface, the
designer must first decide upon all termination imped-
ance, hybrid balances, and transmission level point
(TLP) requirements that the line card must meet. In the
transmit direction, the only concern is that the SLIC
does not provide a signal that is too hot and overloads
the codec input. Thus, for the highest TLP that is being
designed to, given the SLIC gain, the designer, as a
function of voiceband frequency, must ensure the
codec is not overloaded. With a given TLP and a given
SLIC gain, if the signal will cause a codec overload, the
designer must insert some sort of loss, typically a resis-
tor divider, between the SLIC output and codec input.
Note also that some third-generation codecs require
the designer to provide an inherent resistive termina-
tion via external networks. The codec will then provide
gain shaping, as a function of frequency, to meet the
return loss requirements. This feedback will increase
the signal at the codec input and increase the likeli-
hood that a resistor divider is needed in the transmit
direction. Further stability issues may add external
components or excessive ground plane requirements
to the design.
In the receive direction, the issue is to optimize the
S/N. Again, the designer must consider all the TLPs.
The idea is, for all desired TLPs, to run the codec at or
as close as possible to its maximum output signal, to
optimize the S/N. Remember noise floor is constant, so
the hotter the signal from the codec, the better the S/N.
The problem is if the codec is feeding a high-gain SLIC,
either an external resistor divider is needed to knock
the gain down to meet the TLP requirements, or the
codec is not operated near maximum signal levels,
thus compromising the S/N.
Thus, it appears that the solution is to have a SLIC with
a low gain, especially in the receive direction. This will
allow the codec to operate near its maximum output
signal (to optimize S/N), without an external resistor
divider (to minimize cost).
To meet the unique requirements of both type of
codecs, the L9214 offers two receive gain choices.
These receive gains are mask programmable at the
factory and are offered as two different code variations.
For interface with a first-generation codec, the L9214 is
offered with a receive gain of 8. For interface with a
third-generation codec, the L9214 is offered with a
receive gain of 2. In either case, the transconductance
in the transmit direction or the transmit gain is 300 Ω,
(300 V/A).
This selection of receive gain gives the designer the
flexibility to maximize performance and minimize exter-
nal components, regardless of the type of codec cho-
sen.
Design Examples
First-Generation Codec ac In terface Network—
Resistive Termin ation
The following reference circuit shows the complete
SLIC schematic for interface to the Agere T7504 first-
generation codec for a resistive termination imped-
ance. For this example, the ac interface was designed
for a 600 Ω resistive termination and hybrid balance
with transmit gain and receive gain set to 0 dBm. For
illustration purposes, no PPM injection was assumed in
this example.
This is a lower feature application example and uses
single battery operation, fixed overhead, current limit,
and loop closure threshold.
Resistor RGN is optional. It compensates for any mis-
match of input bias voltage at the RCVN/RCVP inputs.
If it is not used, there may be a slight offset at tip and
ring due to mismatch of input bias voltage at the
RCVN/RCVP inputs. It is very common to simply tie
RCVN directly to ground in this particular mode of oper-
ation. If used, to calculate RGN, the impedance from
RCVN to ac ground should equal the impedance from
RCVP to ac ground.
Preliminary Data Sheet
October 2001 Low-Cost Ringing SLIC
L9214A/G
Agere Systems Inc. 31
ac Applications (continued)
Design Examples (continued)
Example 1, Real Termination
The following design equations refer to the circuit in
Figure 13. Use these to synthesize real termination
impedance.
Termination Impedance:
zT =
Receive Gain:
VT/R
IT/R–
------------
zT36 Ω2+RP2400
1RT1
RGP
---------RT1
RRCV
------------
++
-----------------------------------
+=
grcv VT/R
VFR
------------
=
grcv 8
1RRCV
RT1
----------- RRCV
RGP
------------
++
1ZT
ZT/R
---------
+
------------------------------------------------------------------
=
Transmit Gain:
Hybrid Balance:
hbal = 20log
hbal = 20log
To optimize the hybrid balance, the sum of the currents
at the VFX input of the codec op amp should be set to
0. The expression for ZHB becomes the following:
gtx VGSX
VT/R
-----------
=
gtx RX–
RT2
--------- 300
ZT/R
---------
×=
RX
RHB
------------gtx–grcv×
VGSX
VFR
---------------
RHB kΩ() RX
gtx grcv×
-------------------
=
12-3569 (F)
Figure 13. ac Equivalent Circuit
RP
ZT+
–
RP
VT/R
IT/R
VS
ZT/R
+
–
RING AV = –1
AV = 1
VITR
CURRENT
SENSE
TIP
+
–
RT1
RRCV
RHB1
RT2
RCVN
RCVP
RXVGSX
VFXIN
VFR
1/4 T7504 CODEC
RGP
+2.4 V
–0.300 V/mA
AV = 4
L9214
VFXIP
18 Ω
18 Ω
+
–
+
–
Prel iminary Data Sheet
October 2001
Low-Cost Ringing SLIC
L9214A/G
32 Agere Systems Inc.
ac Applications (continued)
Design Examples (continued)
Example 1, Real Termination (continued)
12-3533.L (F)
Figure 14. Agere T7504 First-Generation Codec; Resistive Termination (5 REN Configuration)
VBAT1 BGND VBAT2 VCC AGND ICM TRGDET
ground key
not used
CVBAT1
0.1 µF
CVBAT2
0.1 µF
CCC
0.1 µF
PR
PT
AGERE
L7591
VBAT1
FUSIBLE RESISTOR
30 Ω
30 Ω
CF1 CF2 FB1 FB2 NSTAT B3 B2 B1 B0
CF1
0.22 µFCF2
0.1 µF
VITR
RCVP
RCVN
ITR
VTX
TXI
RGX
4750 Ω
VBAT1 VBAT2 VCC
CTX
0.1 µF
1/4 T7504
CODEC
RT6 CC1
RX
GSX
+2.4 V
RHB1 VFXIN
RRCV
RT3
RGP
CC2 VFRO
DX
DR
FSE
FSEP
MCLK
ASEL CONTROL
INPUTS
SYNC
AND
PCM
HIGHWAY
CLOCK
RGN
–
+
49.9 kΩ
100 kΩ
100 kΩ
60.4 kΩ0.1 µF
17.65 kΩ
26.7 kΩ
69.8 kΩ
0.1 µF
L9214A
FUSIBLE RESISTOR
OR PTC
OR PTC
RTFLT
DCOUT
IPROG (ILOOP = 25 mA)
IREF
RRT2
RRT1
100 kΩ
CRT
1 µF
150 kΩ
RIPROG
5.76 kΩ
RIREF
28.7 kΩ
CFB1
0.01 µFCFB2
0.01 µFFROM/TO
CONTROL
RCR
5 kΩ
CCC1
150 nF
DBAT1
Preliminary Data Sheet
October 2001 Low-Cost Ringing SLIC
L9214A/G
Agere Systems Inc. 33
ac Applications (continued)
Design Examples (continued)
Example 1, Real Termination (continued)
Table 20. L9214 Parts List for Agere T7504 First-Generation Codec; Resistive Termination
Note: TX = 0 dBm, RX = 0 dBm, termination impedance = 600 Ω, hybrid balance = 600 Ω.
Name Value Tolerance Rating Function
Fault Protection
RPT 30 Ω1% Fusible or PTC Protection resistor.
RPR 30 Ω1% Fusible or PTC Protection resistor.
Protector Agere
L7591 — — Second ary pr otecti on.
Power Supply
CVBAT1 0.1 µF20% 100 V VBAT filter capacitor.
CVBAT2 0.1 µF20% 50 V VBAT filter capacitor. |VBAT2| < |VBAT1|.
DBAT1 1N4004 — — Re ve rs e curren t .
CCC 0.1 µF20% 10 V VCC filter capacitor.
CF1 0.22 µF20% 100 V Filter capacitor.
CF2 0.1 µF20% 100 V Filter capacitor.
dc Profile
RIPROG 5.76 kΩ1% 1/16 W With RIREF, fixe s d c cur r en t limit .
RIREF 28.7 kΩ1% 1/16 W With RIPROG, fixe s dc cu rr ent limi t.
Ringing/Ring Trip
CRT 1.0 µF20% 10 V Ring trip filter capacitor.
RRT1 100 kΩ1% 1/16 W Ring trip filter resistor.
RRT2 150 kΩ1% 1/16 W Ring trip filter resistor.
CFB1 0.01 µF20% 100 V With CFB2, slows rate of battery reversal. Sets crest factor
of balanced power ring signal.
CFB2 0.01 µF20% 100 V With CFB1, slows rate of battery reversal. Sets crest factor
of balanced power ring signal.
ac Interface
RGX 4750 Ω1% 1/16 W Sets T/R to VITR transconductance.
RCR 5 kΩ5% 1/16 W Compensation resistor.
CCC1 150 pF 20% 10 V Compensation capacitor.
CTX 0.1 µF20% 10 V ac/d c se para ti on.
CC1 0.1 µF20% 10 V dc blocking ca pacitor.
CC2 0.1 µF20% 10 V dc blocking ca pacitor.
RT3 69.8 kΩ1% 1/16 W With RGP and RRCV, sets termination impedance and
receive gain.
RT6 49.9 kΩ1% 1/16 W With RX, sets transmit gain.
RX100 kΩ1% 1/16 W With RT6, sets transmit gain.
RHB1 100 kΩ1% 1/16 W With RX, sets hybrid balance.
RRCV 60.4 kΩ1% 1/16 W With RGP and RT3, sets termination impedance and
receive gain.
RGP 26.7 kΩ1% 1/16 W With RRCV and RT3, sets terminati on im peda nc e and
receive gain.
RGN Optional 17.6 kΩ1% 1/16 W Optional. Compensates for input offset at RCVN/RCVP.
Prel iminary Data Sheet
October 2001
Low-Cost Ringing SLIC
L9214A/G
34 Agere Systems Inc.
ac Applications (continued)
Design Examples (continued)
First-Generation Codec ac Interface Network—
Complex Terminatio n
The following reference circuit shows the complete
SLIC schematic for interface to the Agere T7504 first-
generation codec for the German complex termination
impedance. For this example, the ac interface was
designed for a 220 Ω + (820 Ω || 115 nF) complex ter-
mination and hybrid balance with transmit gain and
receive gain set to 0 dBm.
Complex Terminat ion Im pedance Desig n Exa mple
The gain shaping necessary for a complex termination
impedance may be done by shaping across the Ax
amplifier at nodes ITR and VTX.
Complex termination is specified in the form:
5-6396(F)
To work with this application, convert termination to the
form:
5-6398(F)
where:
R1´ = R1 + R2
R2´ = (R1 + R2)
C´ = C
ac Interface Using First-Generation Codec
RGX/RTGS/CGS (ZTG): These components give gain
shaping to get good gain flatness. These components
are a scaled version of the specified complex termina-
tion impedance.
Note for pure (600 Ω) resistive terminations, compo-
nents RTGS and CGS are not used. Resistor RGX is us ed
and is still 4750 Ω.
RX/RT6: With other components set, the transmit gain
(for complex and resistive terminations) RX and RT6 are
varied to give specified transmit gain.
RT3/RRCV/RGP: For both complex and resistive termina-
tions, the ratio of these resistors sets the receive gain.
For resistive terminations, the ratio of these resistors
sets the return loss characteristic. For complex termi-
nations, the ratio of these resistors sets the low-fre-
quency return loss characteristic.
CN/RN1/RN2: For complex terminations, these compo-
nents provide high-frequency compensation to the
return loss characteristic.
For resistive terminations, these components are not
used and RCVN is connected to ground via a resistor.
RHB: Sets hybrid balance for all terminations.
Set Z TG—gain shaping:
ZTG = RGX || RTGS + CGS which is a scaled version of
ZT/R (the specified termination resistance) in the
R1´ || R2´ + C´ form.
RGX must be 4750 Ω to set SLIC transconductance to
300 V/A.
RGX = 4750 Ω
At dc, CGS and C´ are open.
RGX = M x R1´
where M is the scale factor.
M =
It can be shown:
RTGS = M x R2´
and
CTGS =
R2
C
R1
R1´
C´R2´
R1
R2
-------
R2
R1R2+
---------------------
24750
R1′
--------------
C′
M
------
Preliminary Data Sheet
October 2001 Low-Cost Ringing SLIC
L9214A/G
Agere Systems Inc. 35
ac Applications (continued)
Design Examples (continued)
ac Interface Using First-Generation Codec (continued)
5-6400.H (F)
Figure 15. Interface Circuit Using First-Generation Codec (Blocking Capacitors Not Shown)
0.1 µF
RTGS
VTX
RGX = 4750 Ω
TXI VITR
RT6
Rx
RT3 RHB
CODEC
OUTPUT
DRIVE
AMP
CODEC
OP AMP
–
+
20
CN
RN1
RN2 RGP
RRCV
–IT/R
318.25
CGS
RCVN
RCVP
Transmit Gain
Transmit gain will be specified as a gain from T/R to
PCM, TX (dB). Since PCM is referenced to 600 Ω and
assumed to be 0 dB, and in the case of T/R being refer-
enced to some complex impedance other than 600 Ω
resistive, the effects of the impedance transformation
must be taken into account.
Again, specified complex termination impedance at T/R
is of the form:
5-6396(F)
First, calculate the equivalent resistance of this network
at the midband frequency of 1000 Hz.
REQ =
Using REQ, calculate the desired transmit gain, taking
into account the impedance transformation:
TX (dB) = TX (specified[dB]) + 20log
TX (specified[dB]) is the specified transmit gain. 600 Ω is the
impedance at the PCM, and REQ is the impedance at
Tip and ring. 20log represents the power
loss/gain due to the impedance transformation.
Note in the case of a 600 Ω pure resistive termination
at T/R 20log = 20log = 0.
Thus, there is no power loss/gain due to impedance
transformation and TX (dB) = TX (specified [dB] ).
Finall y, co nv er t TX (dB) to a ratio, gtx:
TX (dB) = 20log gtx
The ratio of RX/RT6 is used to set the transmit gain:
= gtx • • with a quad Agere codec
such as T7504:
RX < 200 kΩ
R2
C
R1
2πf()
2C12R1R22R1R2++
12πf()
2R22C12
+
-----------------------------------------------------------------------------
22πfR22C12
12πf()
2R22C12
+
---------------------------------------------------
2
+
600
REQ
-----------
600
REQ
-----------
600
REQ
-----------600
600
----------
RX
RT6
---------- 318.25
20
------------------1
M
-----
Prel iminary Data Sheet
October 2001
Low-Cost Ringing SLIC
L9214A/G
36 Agere Systems Inc.
ac Applications (continued)
Design Examples (continued)
ac Interface Using First-Generation Codec (contin-
ued)
Receive Gain
Ratios of RRCV, R T3, RGP will set both the low-frequency
termination and receive gain for the complex case. In
the complex case, additional high-frequency compen-
sation, via CN, RN1, and RN2, is needed for the return
loss characteristic. For resistive termination, CN, RN1,
and RN2 are not used and RCVN is tied to ground via a
resistor.
Determine the receive gain, grcv, taking into account the
impedance transformation in a manner similar to trans-
mit gain.
RX (dB) = RX (specified[dB]) + 20log
RX (dB) = 20log grcv
Then:
grcv =
and low-frequency termination
ZTER(low) = + 2RP + 36 Ω
ZTER(low) is the specified termination impedance assum-
ing low frequency (C or C´ is open).
RP is t he series protect ion resistor.
36 Ω is the typical internal feed resistance.
These two equations are best solved using a computer
spreadsheet.
Next, solve for the high-frequency return loss compen-
sation circuit, CN, RN1, and RN2:
CNRN2 = CG RTGP
RN1 = RN2
There is an input offset voltage associated with nodes
RCVN and RCVP. To minimize the effect of mismatch
of this voltage at T/R, the equivalent resistance to ac
ground at RCVN should be approximately equal to that
at RCVP. Refer to Figure 16 (with dc blocking capaci-
tors). To meet this requirement, RN2 = RGP || RT3.
Hybrid Balance
Set the hybrid cancellation via RHB.
RHB =
If a 5 V only codec such as the Agere T7504 is used,
dc blocking capacitors must be added as shown in Fig-
ure 16. This is because the codec is referenced to
2.5 V and the SLIC to ground—with the ac coupling, a
dc bias at T/R is eliminated and power associated with
this bias is not consumed.
Typically, values of 0.1 µF to 0.47 µF capacitors are
used for dc blocking. The addition of blocking capaci-
tors will cause a shift in the return loss and hybrid bal-
ance frequency response toward higher frequencies,
degrading the lower-frequency response. The lower
the value of the blocking capacitor, the more pro-
nounced the effect is, but the cost of the capacitor is
lower. It may be necessary to scale resistor values
higher to compensate for the low-frequency response.
This eff ect is bes t evalua ted via simulat ion. A PSPICE®
model for the L9214 is available.
Design equation calculations seldom yield standard
component values. Conversion from the calculated
value to standard value may have an effect on the ac
parameters. This effect should be evaluated and opti-
mized via simulation.
REQ
600
-----------
4
1RRCV
RT3
--------------- RRCV
RGP
---------------
++
------------------------------------------------
2400
1RT3
RGP
------------RT3
RRCV
---------------
++
--------------------------------------------
2RP
2400
-------------
2400
2RP
-------------RTGS
RTGP
--------------
1–
RX
grcv gtx×
-------------------------
Preliminary Data Sheet
October 2001 Low-Cost Ringing SLIC
L9214A/G
Agere Systems Inc. 37
ac Applications (continued)
Design Examples (continued)
ac Interface Using First-Generation Codec (continued)
Blocking Capacitors
5-6401.G (F)
Figure 16. ac Interface Using First-Generation Codec (Including Blocking Capacitors) for Complex
Termination Impedance
0.1 µF
RTGS
VTX
RGX = 4750 Ω
TXI VITR
RT6
Rx
RT3 RHB
CODEC
OUTPUT
DRIVE
AMP
CODEC
OP AMP
–
+
20
CN
RN1
RN2 RGP
RRCV
RCVN
RCVP
–IT/R
318.25
CGS
CB1
2.5 V
CB2
Prel iminary Data Sheet
October 2001
Low-Cost Ringing SLIC
L9214A/G
38 Agere Systems Inc.
ac Applications (continued)
Design Examples (continued)
ac Interface Using First-Generation Codec (continued)
12-3535.m (F)
Figure 17. Agere T7504 First-Generation Code c; Complex Termination with Power Contr ol Resistor (3 REN
Configuration)
Table 21. L9214 Parts List for Agere T7504 First-Generation Codec; Complex Termination with Power
Control Resistor
Name Value Tolerance Rating Function
Fault Protection
RPT 30 Ω1% Fusible or
PTC Prote cti on resi stor.
RPR 30 Ω1% Fusible or
PTC Prote cti on resi stor.
Protector Agere
L7591 — — Secondary protection.
VBAT1 BGND VBAT2 VCC AGND ICM TRGDET
ground key
not used
CVBAT1
0.1 µF
CVBAT2
0.1 µF
CCC
0.1 µF
PR
PT
AGERE
L7591
VBAT1
FUSIBLE RESISTOR
30 Ω
VITR
RCVP
RCVN
ITR
VTX
TXI
RGX
4750 Ω
RTGS
CGS
VBAT1 VCC
CTX
0.1 µF
1/4 T7504
CODEC
RT6 GSX
+2.4 V
RHB1
RT3
RRCV
CN
RGP
DX
DR
FSE
FSEP
MCLK
ASEL CONTROL
INPUTS
SYNC
AND
PCM
HIGHWAY
CLOCK
RN2
–
+
30 Ω CC2
L9214A
CC1
CF1 CF2 FB1 FB2 NSTAT B3 B2 B1 B0
CF1
0.22 µFCF2
0.1 µFFROM/ TO CONTROL
FUSIBLE RESISTOR
47.5 kΩ
54.9 kΩ
127 kΩ
RN1
49.9 kΩ113 kΩ
120 pF
0.1 µF
0.1 µF40.6 kΩ
CFB1
0.01 µFCFB2
0.01 µF
OR PTC
OR PTC
RTFLT
DCOUT
IPROG (ILOOP = 25 mA)
IREF
RRT2
RRT1
133 kΩ
CRT
1 µF
75 kΩ
RIPROG
5.76 kΩ
RIREF
28.7 kΩ
VFXIN
RX
115 kΩ
VFRO
1.74 kΩ
12 nF
RPWR
2.0 kΩ
59.0 kΩ
DBAT1
Preliminary Data Sheet
October 2001 Low-Cost Ringing SLIC
L9214A/G
Agere Systems Inc. 39
Applications (continued)
Design Examples (continued)
ac Interface Using First-Generation Codec (continued)
Table 21. L9214 Parts List for Agere T7504 First-Generation Codec; Complex Termination with Power Con-
trol Resist or (continued)
Note: TX = 0 dBm, RX = 0 dBm, termination impedance = 220 Ω + (820 Ω || 115 nF), hybrid balance = 220 Ω + (820 Ω || 115 nF).
Name Value Tolerance Rating Function
Power Supply
CVBAT1 0.1 µF20% 100 V VBAT filter capacitor.
CVBAT2 0.1 µF20% 50 V VBAT filter capacitor. |VBAT2| < |VBAT1|.
DBAT1 1N4004 — — Reverse current.
CCC 0.1 µF20% 10 V VCC filter capacitor.
CF1 0.22 µF20% 100 V Filter capacitor.
CF2 0.1 µF20% 100 V Filter capacitor.
RPWR 2.0 kΩ5% 2 W Power control resistor, provides single battery supply operation.
dc Profile
RIPROG 5.76 kΩ1% 1/16 W Wi th RIREF, fixes dc current limit.
RIREF 28.7 kΩ1% 1/16 W With R IPROG, fixes dc current limit.
Ringing/Ring Trip
CRING 1.0 µF20% 10 V Ring trip filter capacitor.
RRT1 133 kΩ1% 1/16 W Ring trip filter resistor.
RRT2 75 kΩ1% 1/16 W Ring trip filter resistor.
CFB1 0.01 µF20% 100 V With CFB2, slows rate of battery reversal. Sets crest factor of bal-
anced power ring signal.
CFB2 0.01 µF20% 100 V With CFB1, slows rate of battery reversal. Sets crest factor of bal-
anced power ring signal.
ac Interface
RGX 4750 Ω1% 1/16 W Sets T/R to VITR transconductance.
RTGS 1.74 k Ω1% 1/16 W Gain shaping for complex termination.
CGS 12 nF 5% 10 V Gain shaping for complex termination.
CTX 0.1 µF20% 10 V ac/dc separation.
CC1 0.1 µF20% 10 V dc blocking capacitor.
CC2 0.1 µF20% 10 V dc blocking capacitor.
RT3 49.9 kΩ1% 1/16 W With RGP and RRCV, sets termination impedance and receive gain.
RT6 40.2 kΩ1% 1/16 W With RX, sets transmit gain.
RX115 kΩ1% 1/16 W With RT6, sets transmit gain.
RHB1 113 kΩ1% 1/16 W With RX, sets hybrid bal anc e.
RRCV 59.0 kΩ1% 1/16 W With RGP and RT3, sets termination impedance and receive gain.
RGP 54.9 kΩ1% 1/16 W With R RCV and RT3, sets termination impedance and receive gain.
CN120 pF 20% 10 V High frequency compensation.
RN1 127 kΩ1% 1/16 W High frequency compensation.
RN2 47.5 kΩ1% 1/16 W High frequency compensation, compensate for dc offset at
RCVP/RCVN.
Prel iminary Data Sheet
October 2001
Low-Cost Ringing SLIC
L9214A/G
40 Agere Systems Inc.
ac Applications (continued)
Design Examples (continued)
Third-Generation Codec ac Interface Network—Complex Termination
The following reference circuit shows the complete SLIC schematic for interface to the Agere T8536 third-genera-
tion codec. All ac parameters are programmed by the T8536. Note this codec differentiates itself in that no external
components are required in the ac interface to provide a dc termination impedance or for stability. Please see the
T8535/6 data sheet for information on coefficient programming.
12-3534.Z1 (F)
Figure 18. Third-Generation Codec ac Interface Network; Complex Termination (3 REN Configuration)
VBAT1 BGND VBAT2 VCC AGND ICM TRGDET
ground key
not used
CVBAT1
0.1 µF
CVBAT2
0.1 µF
CCC
0.1 µF
PR
PT
AGERE
L7591
VBAT1
50 Ω
50 Ω
CF1 CF2 FB1 FB2 NSTAT B3 B2 B1 B0
CF1
0.22 µFCF2
0.1 µF
VITR
RCVP
RCVN
ITR
VTX
TXI
RGX
4750 Ω
VBAT1 VBAT2 VCC
CTX
0.1 µF
CC1
PCM
HIGHWAY
DX0
DR0
DX1
DR1
FS
BCLK
DGND
VDD
SYNC
AND
VDD
VFXI
VFROP
VFRON
SLIC5a
SLIC4a
SLIC3a
SLIC2a
SLIC0a
CLOCK
L9214G
FROM/TO
CONTROL
B3
B2
B0
NSTAT
B1
0.1 µF
FUSIBLE RESISTOR
OR PTC
OR PTC
FUSIBLE RESISTOR
RTFLT
DCOUT
IPROG (ILOOP = 25 mA)
IREF
RRT2
RRT1
133 kΩ
CRT
1 µF
75 kΩ
RIPROG
5.76 kΩ
RIREF
28.7 kΩ
CFB1
0.01 µFCFB2
0.01 µF
RCR CCC1
DBAT1 820 pF
2 kΩ
1/4 T8536
CODEC
Preliminary Data Sheet
October 2001 Low-Cost Ringing SLIC
L9214A/G
Agere Systems Inc. 41
ac Applications (continued)
Design Examples (continued)
Third-Generation Codec ac Interface Network—Complex Termination (continued)
Table 22. L9214 Parts List for Agere T8536 Third-Generation Codec Meter Pulse Application ac and dc
Parameters; Fully Programmable
* For loop stability, increase to 50 Ω minimum if synthesizing 900 Ω or 900 Ω + 2.16 µF termination impedance.
Name Value Tolerance Rating Function
Fault Protection
RPT 30 Ω1% Fusible or PTC Protection resistor*.
RPR 30 Ω1% Fusible or PTC Protection resistor*.
Protector Agere L7591 — — Secondary protection.
Power Supply
CVBAT1 0.1 µF20% 100 V VBAT filter capacitor.
CVBAT2 0.1 µF20% 50 V VBAT filter capacitor. |VBAT2| < |VBAT1|.
DBAT1 1N4004 — — Reverse current.
CCC 0.1 µF20% 10 V VCC filter capacitor.
CF1 0.22 µF20% 100 V Filter capacitor.
CF2 0.1 µF20% 100 V Filter capacitor.
dc Profile
RIPROG 5.76 kΩ1% 1/16 W With RIREF, fixes dc current limi t.
RIREF 28.7 kΩ1% 1/16 W With RIPROG, fixes dc current limit.
Ringing/Ring Trip
CRT 1.0 µF20% 10 V Ring trip filter capacitor.
RRT1 133 kΩ1% 1/16 W Ring trip filter resistor.
RRT2 75 kΩ1% 1/16 W Ring trip filter resistor.
CFB1 0.01 µF20% 100 V With CFB2, slows rate of battery reversal. Sets crest fac-
tor of balanced power ring si gna l.
CFB2 0.01 µF20% 100 V With CFB1, slows rate of battery reversal. Sets crest fac-
tor of balanced power ring si gna l.
ac Interface
RGX 4750 Ω1% 1/16 W Sets T/R to VITR transconductance.
RCR 10 kΩ5% 1/16 W Compensation resistor.
CCC1 270 pF 20% 10 V Compensation capacitor.
CTX 0.1 µF20% 10 V ac/dc separation.
CC1 0.1 µF20% 10 V dc blocki ng capaci tor.
Prel iminary Data Sheet
October 2001
Low-Cost Ringing SLIC
L9214A/G
42 Agere Systems Inc.
Outline Diagrams
28-Pin SOG
Note: The dimensions in these outline diagrams are intended for informational purposes only. For detailed draw-
ings to assist your design efforts, please contact your Agere Sales Representative.
5-4414
Package Dimensions
Package
Description Number
of Pins
N
Maximum
Length
L
Maximum Width
Without Leads
B
Maximum Width
Including Leads
W
Maximum Height
Above Board
H
SOG (small outline gull-wing) 28 18.11 7.62 10.64 2.67
W
0.61
0.51 MAX
H
0.28 MAX
0.10
SEATING PLANE
1.27 TYP
N
L
B
1
PIN #1 IDENTI F IER Z ONE
Preliminary Data Sheet
October 2001 Low-Cost Ringing SLIC
L9214A/G
Agere Systems Inc. 43
Outline Diagrams (continued)
32-Pin PLCC
Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schemat-
ics to assist your design efforts, please contact your Agere Sales Representative.
5-3813r2 (F)
0.10
SEATING PLA NE
0.38 MIN
TYP
1.27 TYP
0.330/0.533
1430
5
13 21
29
14 20
12.446 ± 0.127
11.430 ± 0.076
PIN #1 IDENTIFIER
ZONE
14.986
± 0.127
13.970
± 0.076
3.175/3.556
Prel iminary Data Sheet
October 2001
Low-Cost Ringing SLIC
L9214A/G
44 Agere Systems Inc.
Outline Diagrams (continued)
48-Pin MLCC
Dimensions are in millimeters.
Notes: The dimensions in this outline diagram are intended for informational purposes only. For detailed schemat-
ics to assist your design efforts, please contact your Agere Sales Representative.
The exposed pad on the bottom of the package will be at VBAT1 potential.
0195
PIN #1
IDENTIFIER ZONE
1
7.00
6.75
SEATING PLANE
0.08
0.65/0.80
0.20 REF
DETAIL A
7.00
5.10
± 0.15
3
3.50
3.375
6.75
0.00/0.05
SECTION C–C
11 SP ACES @
0.50 = 5.50
0.50 BSC
0.13/0.23
0.18/0.30
0.30/0.45
0.01/0.05
1.00 MAX
12°
0.18/0.30
0.24/0.60
0.24/0.60
2
1
3
2
0.20/0.45
0.50 BSC
DETAIL A
CC
VIEW FOR EVEN TERMINAL/SIDE
CL
EXPOSED PAD
Preliminary Data Sheet
October 2001 Low-Cost Ringing SLIC
L9214A/G
Agere Systems Inc. 45
Outline Diagrams (continued)
48-Pin MLCC, JEDEC MO-220 VKKD-2
Dimensions are in millimeters.
Notes: The dimensions in this outline diagram are intended for informational purposes only. For detailed schemat-
ics to assist your design efforts, please contact your Agere Sales Representative.
The exposed pad on the bottom of the package will be at VBAT1 potential.
0195
INDEX AREA
7.00
3.50
SEATI N G PLA N E
0.08
0.20 REF
DETAIL A
7.00
5.00/5.25
3.50
11 SPACES @
0.50 = 5.50
0.50 BSC
0.18/0.30
0.02/0.05
1.00 MAX 0.23
0.30/0.50
1
3
2
(7.00/2 x 7.00/2)
PIN #1
IDEN TIFIER ZONE
TOP VIEW
SIDE VIEW DETAIL B
0.23
0.18
0.18
BOTTOM VIEW
2.50/2.625
EXPOSED PAD
DETAIL B
0.50 BSC
DETAIL A
VIEW FOR EVEN TE R M INAL/S ID E
CL
Prel iminary Data Sheet
October 2001
Low-Cost Ringing SLIC
L9214A/G
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Copyright © 2001 Agere Systems Inc.
All Rights Reserved
October 2001
DS01-144ALC (Replaces DS00-342ALC)
For additional information, contact your Agere Systems Account Manager or the following:
INTERNET: http://www.agere.com
E-MAIL: docmaster@agere.com
N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286
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Ordering Information
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Device Part No. Description Package Comco de
LUCL9214AAJ-D SLIC Gain = 8 28-Pin SOG*, Dry-bagged 108553892
LUCL9214AAJ-DT SLIC Gain = 8 28-Pin SOG*, Dry-bagged, Tape and Reel 108553900
LUCL9214AAU-D SLIC Gain = 8 32-Pin PLCC, Dry-bagged 108697905
LUCL9214AAU-DT SLIC Gain = 8 32-Pin PLCC, Dry-bagged, Tape and Reel 108697913
LUCL9214ARG-D SLIC Gain = 8 48-Pin MLCC, Dry-bagged 109058636
LUCL9214ARG-DT SLIC Gain = 8 48-Pin MLCC, Dry-bagged, Tape and Reel 109058644
LUCL9214GAJ-D SLIC Gain = 2 28-Pin SOG*, Dry-bagged 108560723
LUCL9214GAJ-DT SLIC Gain = 2 28-Pin SOG*, Dry-bagged, Tape and Reel 108560731
LUCL9214GAU-D SLIC Gain = 2 32-Pin PLCC, Dry-bagged 108698309
LUCL9214GAU-DT SLIC Gain = 2 32-Pin PLCC, Dry-bagged, Tape and Reel 108698317
LUCL9214GRG-D SLIC Gain = 2 48-Pin MLCC, Dry-bagged 109058651
LUCL9214GRG-DT SLIC Gain = 2 48-Pin MLCC, Dry-bagged, Tape and Reel 109058669
