First Release
Features
• Built using the advantages and compatibility
of CMOS and IXYS HDMOSTM processes
• Latch-Up Protected up to 2 Amps
• High 2A Peak Output Current
• Wide Operating Range: 4.5V to 25V
• -55°C to +125°C Extended Operating
Temperature
• High Capacitive Load Drive Capability: 1000pF
in <10ns
• Matched Rise And Fall Times
• Low Propagation Delay Time
• Low Output Impedance
• Low Supply Current
Applications
• Driving MOSFETs and IGBTs
• Motor Controls
• Line Drivers
• Pulse Generators
• Local Power ON/OFF Switch
• Switch Mode Power Supplies (SMPS)
• DC to DC Converters
• Pulse Transformer Driver
• Class D Switching Amplifiers
• Power Charge Pumps
General Description
The IXDR502, and IXDS502 each consist of a single 2A
CMOS high speed gate driver for driving the latest IXYS
MOSFETs & IGBTs. Each type can source and sink 2
Amps of peak current while producing voltage rise and
fall times of less than 15ns. The input of each driver is
TTL or CMOS compatible and is virtually immune to
latch up. Patented* design innovations eliminate cross
conduction and current "shoot-through". Improved
speed and drive capabilities are further enhanced by
very quick & matched rise and fall times.
The IXDR502 is configured as a single inverting gate
driver, and the IXDS502 is configured as a single non-
inverting gate driver.
The IXDR502, and IXDS502 are available in the 6-Lead
DFN (D1) package, which occupies less than 20% of
the board area of a typical 8-Pin SOIC package.
*United States Patent 6,917,227
Ordering Information
DS99909(10/07)
NOTE: All parts are lead-free and RoHS Compliant
Copyright © 2007 IXYS CORPORATION All rights reserved
IXDR502 / IXDS502
2 Ampere Single Low-Side Ultrafast MOSFET Drivers
Preliminary Technical Information
Part Number Description Package
Typ e Packing Style Pack
Qty Configuration
IXDR502D1B 2A Low Side Gate Driver I.C. 6-Lead DFN 2” x 2” Waffle Pack 121
IXDR502D1BT/R 2A Low Side Gate Driver I.C. 6-Lead DFN 7” Tape and Reel 2500 Single Inverting
Driver
IXDS502D1B 2A Low Side Gate Driver I.C. 6-Lead DFN 2” x 2” Waffle Pack 121
IXDS502D1BT/R 2A Low Side Gate Driver I.C. 6-Lead DFN 7” Tape and Reel 2500 Single Non-
Inverting Driver
2
Copyright © 2007 IXYS CORPORATION All rights reserved
IXDR502 / IXDS502
Figure 2 - IXDR502 Inverting 2A Gate Driver Functional Block Diagram
Figure 1 - IXDS502 Non-Inverting 2A Gate Driver Functional Block Diagram
* United States Patent 6,917,227
N
P
OUT
Vcc
IN ANTI-CROSS
CONDUCTION
CIRCU IT *
GND GND
N
P
OUT
Vcc
IN ANTI-CROSS
CONDUCTION
CIRCUIT *
GND GND
3
IXDR502 / IXDS502
Unless otherwise noted, 4.5V ≤ VCC ≤ 25V .
All voltage measurements with respect to GND. IXD_502 configured as described in Test Conditions .
Electrical Characteristics @ TA = 25 oC (3)
Symbol Parameter Test Conditions Min Typ Max Units
VIH High input voltage 4.5V ≤ VCC ≤ 18V 2.5 V
VIL Low input voltage 4.5V ≤ VCC ≤ 18V 1.0 V
VIN Input voltage range -5 VCC + 0.3 V
IIN Input current 0V ≤ VIN ≤ VCC -10 10
µA
VOH High output voltage
V
CC - 0.025 V
VOL Low output voltage
0.025 V
ROH High state output
resistance VCC = 15V
3 4
Ω
ROL Low state output
resistance VCC = 15V 2.2 3 Ω
IPEAK Peak output current
VCC = 1 5 V 2 A
IDC Continuous output
current 0.5 A
tR Rise time CLOAD = 1000pF VCC = 15V 7.5 12 ns
tF Fall time CLOAD = 1000pF VCC = 15V 6.5 10 ns
tONDLY ON propagation delay CLOAD = 1000pF VCC = 15V 25 35 ns
tOFFDLY OFF propagation delay
CLOAD = 1000pF VCC = 15V 20 30 ns
VCC Power supply voltage
4.5 15 25 V
ICC
Power supply current VIN = 3.5V
VIN = 0V
VIN = +VCC, (4.5V≤ VCC ≤ 18V)
1
0 2
15
15
mA
µA
µA
Absolute Maximum Ratings (1) Operating Ratings (2)
Parameter Value
Supply Voltage 35V
All Other Pins -0.3 V to VCC + 0.3V
Junction Temperature 150 °C
Storage Temperature -65 °C to 150 °C
Lead Temperature (10 Sec) 300 °C
Parameter Value
Operating Supply Voltage 4.5V to 25V
Operating Temperature Range -55 °C to 125 °C
(4)
IXYS reserves the right to change limits, test conditions, and dimensions.
Package Thermal Resistance *
6-Lead DFN (D1) θJ-A(typ) 125-200 °C/W
6-Lead DFN (D1) θJ-C(max)3.3 °C/W
6-Lead DFN (D1) θJ-S(typ) 7.3 °C/W
4
Copyright © 2007 IXYS CORPORATION All rights reserved
IXDR502 / IXDS502
Unless otherwise noted, 4.5V ≤ VCC ≤ 22V , Tj < 150oC
All voltage measurements with respect to GND. IXD_502 configured as described in Test Conditions .
Electrical Characteristics @ temperatures over -55 oC to 125 oC (3)
Symbol Parameter Test Conditions Min Typ Max Units
VIH High input voltage 4.5V ≤ VCC ≤ 15V 3.5 V
VIL Low input vol t age 4.5V ≤ VCC ≤ 15V 0.8 V
VIN Input voltage range -5 VCC + 0.3 V
IIN Input current 0V ≤ VIN ≤ V CC -20 20
µA
VOH High output voltage VCC - 0.05 V
VOL Low output voltage 0.05 V
ROH Output resistance
@ Output high VCC = 15V
6
Ω
ROL Output resistance
@ Output Low VCC = 15V 4 Ω
IDC Continuous output
current 0.3 A
tR Rise time CL=1000pF Vcc=15V 14 ns
tF Fall time CL=1000pF Vcc=15V 12 ns
tONDLY On-time propagation
delay CL=1000pF Vcc=15V 40 ns
tOFFDLY Off-time propagation
delay CL=1000pF Vcc=15V 35 ns
VCC Power supply voltage 4.5 15 22 V
ICC
Pow er supply curren t VIN = 3.5V
VIN = 0V
VIN = + VCC, (4.5 V≤ VCC ≤ 18V)
1
0 3
10
10
mA
µA
µA
Notes:
1. Operating the device beyond the parameters listed as “Absolute Maximum Ratings” may cause permanent
damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
2. The device is not intended to be operated outside of the Operating Ratings.
3. Electrical Characteristics provided are associated with the stated Test Conditions.
4. Typical values are presented in order to communicate how the device is expected to perform, but not necessarily
to highlight any specific performance limits within which the device is guaranteed to function.
* The following notes are meant to define the conditions for the θJ-A, θJ-C and θJ-S values:
1) The θJ-A (typ) is defined as junction to ambient. The θJ-A of the standard single die 8-Lead PDIP and 8-Lead SOIC are dominated
by the resistance of the package, and the IXD_5XX are typical. The values for these packages are natural convection values with
vertical boards and the values would be lower with forced convection. For the 6-Lead DFN package, the θJ-A value supposes the DFN
package is soldered on a PCB. The θJ-A (typ) is 200 °C/W with no special provisions on the PCB, but because the center pad
provides a low thermal resistance to the die, it is easy to reduce the θJ-A by adding connected copper pads or traces on the PCB.
These can reduce the θJ-A (typ) to 125 °C/W easily, and potentially even lower. The θJ-A for DFN on PCB without heatsink or thermal
management will vary significantly with size, construction, layout, materials, etc. This typical range tells the user what they are likely
to get if no thermal management is done.
2) θJ-C (max) is defined as juction to case, where case is the large pad on the back of the DFN package. The θJ-C values are generally
not published for the PDIP and SOIC packages. The θJ-C for the DFN packages are important to show the low thermal resistance from
junction to the die attach pad on the back of the DFN, -- and a guardband has been added to be safe.
3) The θJ-S (typ) is defined as junction to heatsink, where the DFN package is soldered to a thermal substrate that is mounted on a
heatsink. The value must be typical because there are a variety of thermal substrates. This value was calculated based on easily
available IMS in the U.S. or Europe, and not a premium Japanese IMS. A 4 mil dialectric with a thermal conductivity of 2.2W/mC was
assumed. The result was given as typical, and indicates what a user would expect on a typical IMS substrate, and shows the potential
low thermal resistance for the DFN package.
5
IXDR502 / IXDS502
Pin Description
Figure 3 - Characteristics Test Diagram
CAUTION: Follow proper ESD procedures when handling and assembling this component.
1
2
34
5
6
IN GND
Vcc
OUT GND
GND
10uF
Vcc
1000 pF
Agilent 1147A
Current Probe
0.01uF
PIN NUMBER SYMBOL FUNCTION DESCRIPTION
1 IN Signal Input Input signal-TTL or CMOS compatible.
2 Vcc Supply Voltage
Positive power supply voltage input. This pin provides power to the
entire chip. The range for this voltage is from 4.5V to 25V.
3 OUT Drive Output Driver output. For application purposes, this pin is connected via a
resistor to the gate of a MOSFET or IGBT.
4,5,6 GND Ground
The drivers ground pins. Internally connected to all circuitry, these
pins provide ground reference for the entire device. These pins
should be connected to a low noise analog ground plane for
optimum performance.
IXYS reserves the right to change limits, test conditions, and dimensions.
IXDS 6 Lead DFN (D1B)
(Bottom View)
NOTE: Solder tabs on bottoms of DFN packages are grounded
5
6
43
2
1GND
GND
GND
IN
OUT
Vcc
5
6
43
2
1GND
GND
GND
IN
OUT
Vcc
IXDR 6 Lead DFN (D1B)
(Bottom View)
Pin Configuration
6
Copyright © 2007 IXYS CORPORATION All rights reserved
IXDR502 / IXDS502
Typical Performance Characteristics
Fig. 5
Fig. 7
Fig. 9
Fig. 4
Fig. 6
Fig. 8
Rise Time vs. Supply Volta ge
0
10
20
30
40
50
60
70
80
0 5 10 15 20 25 30 35 40
Supply Voltage (V)
Rise Time (ns)
560pF
1000pF
10000pF
5400pF
Fall Time vs. Supply Voltage
0
10
20
30
40
50
60
70
0 5 10 15 20 25 30 35 40
Supply Voltage (V)
Fall Time (ns)
560pF
1000pF
10000pF
5400pF
Rise / Fall Time vs. Temperature
VSUPPLY = 15V CLOAD = 1000pF
0
2
4
6
8
10
12
-50 0 50 100 150
Temperature (C)
Rise / Fall Time (ns)
Rise time
Fall time
Rise Time vs. Capacitive Load
0
10
20
30
40
50
60
70
80
90
100 1000 10000
Load Capacitance (pF)
Rise Time (ns)
5V
15V
10V
20V
Fall Time vs. Capacitive Load
0
10
20
30
40
50
60
70
100 1000 10000
Load Capacitance (pF)
Fall Time (ns)
20V
15V
10V
5
Input Threshold Levels vs. Supply Voltage
0
0.5
1
1.5
2
2.5
0 5 10 15 20 25 30 35 40
Supply Voltage (V)
Threshold Level (V)
Positive going input
Negative going input
7
IXDR502 / IXDS502
Fig. 10 Input Threshold Levels vs. Temperature
0
0.5
1
1.5
2
2.5
3
-50 0 50 100 150
Temperature (C)
Input Threshold Level (V)
Positive going input
Nega tive going inpu t
Propagation Delay vs. Supply Voltage
Rising Input, CLOAD = 1000pF
0
5
10
15
20
25
30
35
40
0 5 10 15 20 25 30 35 40
Supply Voltage (V)
Propagation Delay Time (ns)
Non-Inverting
Inverting
Propagation Delay vs. Supply Voltage
Falling Input, CLOAD = 1000pF
0
5
10
15
20
25
30
35
40
45
0 5 10 15 20 25 30 35 40
Supply Voltage (V)
Propagation Delay Time (ns)
Inverting
Non-Inverting
Propagation Delay vs. Temperature
VSUPPLY = 15V CLOAD = 1000pF
0
5
10
15
20
25
30
35
40
-50 0 50 100 150
Temeprature (C)
Propagation Delay Time (ns)
Positve going input
Negative going input
Qu iesc e nt C u rrent vs. Sup p ly Volt a g e
0.1
1
10
100
1000
10000
0 5 10 15 20 25 30 35 40
Supply Voltage (V)
Quiesent Current (uA)
Inverting
Input = "0"
Non-inverting
Input = "0"
Inverting/Non-inverting
Input = "1"
Quiescent Current vs. Temperature
VSUPPLY = 15V
0.1
1
10
100
1000
10000
100000
1000000
-50 0 50 100 150
Temperature (C)
Quiescent Current (uA)
Non-inverting, Input= "0"
Inverting, Input= "1"
Non-inverting, Input= "1"
Inverting, Input= "0"
Fig. 11
Fig. 12 Fig. 13
Fig. 14 Fig. 15
8
Copyright © 2007 IXYS CORPORATION All rights reserved
IXDR502 / IXDS502
Supply Current vs. Frequency
VSUPPLY = 15V
0
50
100
150
200
250
300
100 1000 10000
Frequency (kHz)
Supply Current (mA)
560pF
1000pF
10000pF
5400pF
Supply Current vs. Frequency
VSUPPLY = 10V
0
20
40
60
80
100
120
140
160
180
200
100 1000 10000
Frequency (kHz)
Supply Current (mA)
560pF
1000pF
10000pF
5400pF
Fig. 16
Fig. 19
Fig. 21
Fig. 18
Fig. 20
Supply Current vs. Capacitive Load
VSUPPLY = 10V
0
20
40
60
80
100
120
140
160
180
200
100 1000 10000
Load Capacitance (pF)
Supply Current (mA)
100kHz
1MHz
2MHz
Supply Current vs. Capacitive Load
VSUPPLY = 15V
0
50
100
150
200
250
300
100 1000 10000
Load Capacitance (pF)
Supply Current (mA)
100kHz
1MHz
2MHz
Supply Current vs. Capacitive Load
VSUPPLY = 5V
0
10
20
30
40
50
60
70
80
90
100
100 1000 10000
Load Capacitance (pF)
Supply Current (mA)
100kHz
1MHz
2MHz
Supply Current vs. Frequency
VSUPPLY = 5V
0
10
20
30
40
50
60
70
80
90
100
100 1000 10000
Frequency (kHz)
Supply Current (mA)
560pF
1000pF
10000pF
5400pF
Fig. 17
9
IXDR502 / IXDS502
Output Sink Current vs. Temperature
VSUPPLY = 15V
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
0
-50 0 50 100 150
Temperature (C)
Output Sink Current (A)
Supply Current vs. Frequency
VSUPPLY = 20V
0
50
100
150
200
250
300
350
400
100 1000 10000
Frequency (kHz)
Supply Current (mA)
560pF
1000pF
10000pF
5400pF
Output Sink Current vs. Supply Voltage
-7
-6
-5
-4
-3
-2
-1
0
0 5 10 15 20 25 30 35 40
Supply Voltage (V)
Sink Current (A)
Fig. 23
Fig. 24 Fig. 25
Fig. 27
Supply Current vs. Capacitive Load
VSUPPLY = 20V
0
50
100
150
200
250
300
350
400
100 1000 10000
Load Capacitance (pF)
Supply Current (mA)
100kHz
1MHz
2MHz
Ou tput Source C urrent vs. Su pply Voltage
0
1
2
3
4
5
6
7
0 5 10 15 20 25 30 35 40
Supply Voltage (V)
Source Current (A)
Output Source Current vs. Temperature
VSUPPLY = 15V
0
0.5
1
1.5
2
2.5
3
3.5
-50 0 50 100 150
Temp erature (C)
Output Source Current (A)
Fig. 22
Fig. 26
10
Copyright © 2007 IXYS CORPORATION All rights reserved
IXDR502 / IXDS502
Low State Output Resistance vs. Supply Voltage
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0 5 10 15 20 25 30 35 40
Supply Voltage (V)
Output Resistance (ohms)
Fig. 29
Fig. 28 High State Output Resistance vs. Supply Voltage
0
1
2
3
4
5
6
0 5 10 15 20 25 30 35 40
Supply Voltage (V)
Output Rsistance (ohms)
Supply Bypassing, Grounding Practices And Output Lead Inductance
When designing a circuit to drive a high speed MOSFET
utilizing the IXD_502, it is very important to observe certain
design criteria in order to optimize performance of the driver.
Particular attention needs to be paid to Supply Bypassing,
Grounding, and minimizing the Output Lead Inductance.
Say, for example, we are using the IXD_502 to charge a 1500pF
capacitive load from 0 to 25 volts in 25ns.
Using the formula: I= ∆V C / ∆t, where ∆V=25V C=1500pF &
∆t=25ns, we can determine that to charge 1500pF to 25 volts in
25ns will take a constant current of 1.5A. (In reality, the charging
current won’t be constant, and will peak somewhere around
2A).
SUPPLY BYPASSING
In order for our design to turn the load on properly, the IXD_502
must be able to draw this 1.5A of current from the power supply
in the 25ns. This means that there must be very low impedance
between the driver and the power supply. The most common
method of achieving this low impedance is to bypass the power
supply at the driver with a capacitance value that is an order of
magnitude larger than the load capacitance. Usually, this would
be achieved by placing two different types of bypassing
capacitors, with complementary impedance curves, very close
to the driver itself. (These capacitors should be carefully selected
and should have low inductance, low resistance and high-pulse
current-service ratings). Lead lengths may radiate at high
frequency due to inductance, so care should be taken to keep
the lengths of the leads between these bypass capacitors and
the IXD_502 to an absolute minimum.
GROUNDING
In order for the design to turn the load off properly, the IXD_502
must be able to drain this 1.5A of current into an adequate
grounding system. There are three paths for returning current
that need to be considered: Path #1 is between the IXD_502
and its load. Path #2 is between the IXD_502 and its power
supply. Path #3 is between the IXD_502 and whatever logic is
driving it. All three of these paths should be as low in resistance
and inductance as possible, and thus as short as practical. In
addition, every effort should be made to keep these three
ground paths distinctly separate. Otherwise, the returning ground
current from the load may develop a voltage that would have a
detrimental effect on the logic line driving the IXD_502.
OUTPUT LEAD INDUCTANCE
Of equal importance to Supply Bypassing and Grounding are
issues related to the Output Lead Inductance. Every effort
should be made to keep the leads between the driver and its
load as short and wide as possible. If the driver must be placed
farther than 2” (5mm) from the load, then the output leads should
be treated as transmission lines. In this case, a twisted-pair
should be considered, and the return line of each twisted pair
should be placed as close as possible to the ground pin of the
driver, and connected directly to the ground terminal of the load.
11
IXDR502 / IXDS502
IXYS Semiconductor GmbH
Edisonstrasse15 ; D-68623; Lampertheim
Tel: +49-6206-503-0; Fax: +49-6206-503627
e-mail: marcom@ixys.de
IXYS Corporation
3540 Bassett St; Santa Clara, CA 95054
Tel: 408-982-0700; Fax: 408-496-0670
e-mail: sales@ixys.net
www.ixys.com
0.079±0.004 [2.00±0.10]
0.079±0.004 [2.00±0.10]
0.035±0.004 [0.90±0.10]
S0.002^0.000; o S0.05^0.00;o
[]
0.013 [0.32]
0.044 [1.12]
0.008 [0.20]
0.012 [0.30]
0.020 [0.50]
0.012 [0.30]
0.010 [0.26]
0.054 [1.36]
0.008 [0.20]
