RT9199
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DS9199-10 May 2011 www.richtek.com
Pin Configurations
Cost-Effective, 2A Peak Sink/Source Bus Termination Regulator
Ordering Information
General Description
The RT9199 is a simple, cost-effective and high-speed
linear regulator designed to generate termination voltage
in Double Data Rate (DDR) memory system to comply
with the devices requirements. The regulator is capable of
actively sinking or sourcing up to peak 2A for DDRII or
1.5A for DDRIII while regulating an output voltage to within
20mV. The output termination voltage can be tightly
regulated to track 1/2VDDQ by two external voltage divider
resistors or the desired output voltage can be pro-grammed
by externally forcing the REFEN pin voltage.
The RT9199 also incorporates a high-speed differential
amplifier to provide ultra-fast response in line/load transient.
Other features include extremely low initial offset voltage,
excellent load regulation, current limiting in bi-directions
and on-chip thermal shut-down protection.
The RT9199 are available in both SOP-8 and SOP-8
(Exposed Pad) surface mount packages.
Features
zz
zz
zIdeal for DDRII / DDRIII VTT Applications
zz
zz
zSink and Source Current :
Peak 2A for DDRII
Peak 1.5A for DDRIII
zz
zz
zIntegrated Power MOSFETs
zz
zz
zGenerate Termination Voltage for DDR Memory
Interfaces
zz
zz
zHigh Accuracy Output Voltage at Full-Load
zz
zz
zOutput Adjustment by T wo External Re sistors
zz
zz
zLow External Component Count
zz
zz
zShutdown for Suspend to RAM (STR) Functionality
with High-Impedance Output
zz
zz
zCurrent Limiting Protection
zz
zz
zOn-Chip Thermal Protection
zRoHS Compliant and Halogen Free
Applications
zDesktop PCs, Notebooks, and Workstations
zGraphics Card Memory Termination
zSet Top Boxes, Digital TVs, Printers
zEmbedded Systems
zActive Termination Buses
zDDR/II Memory Systems
(TOP VIEW)
SOP-8
SOP-8 (Exposed Pad)
Note :
Richtek products are :
RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
VIN
GND
REFEN
VOUT
NC
NC
NC
VCNTL
GND
2
3
45
6
7
8
9
Package Type
S : SOP-8
SP : SOP-8 (Exposed Pad-Option 2)
RT9199
Lead Plating System
P : Pb Free
G : Green (Halogen Free and Pb Free)
Z : ECO (Ecological Element with
Halogen Free and Pb free)
VIN
GND
REFEN
VOUT
VCNTL
2
3
45
6
7
8
VCNTL
VCNTL
VCNTL
RT9199
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DS9199-10 May 2011www.richtek.com
Typical Application Circuit
R1 = R2 = 100kΩ, RTT = 50Ω / 33Ω / 25Ω
COUT(MIN) = 10μF (Ceramic) + 1000μF under the worst case testing condition
RDUMMY = 1kΩ as for VOUT discharge when VIN is not presented but VCNTL is presented
CSS = 1μF, CIN = 470μF (Low ESR), CCNTL = 47μF
Test Circuit
Figure 1. Output Voltage Tolerance, ΔVLOAD
VIN
REFEN
GND
VCNTL
VOUT
RT9199
EN
2N7002
R1
R2
CSS
VIN = 1.8V/1.5V
VCNTL = 5V
CCNTL
CIN
RTT
COUT RDUMMY
VIN
REFEN
GND
VCNTL
VOUT
RT9199
0.9V/0.75V
COUT
IL
VOUT
V
VIN = 1.8V/1.5V VCNTL = 5V
Marking Information
RT9199xS : Product Number
x : P or G or Z
YMDNN : Date Code
RT9199xSP : Product Number
x : P or G or Z
YMDNN : Date Code
RT9199xS RT9199xSP
RT9199
xSYMDNN
RT9199
xSPYMDNN
RT9199
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DS9199-10 May 2011 www.richtek.com
Figure 2. Current in Shutdown Mode, ISTBY
VIN
REFEN
GND
VCNTL
VOUT
RT9199
VIN = 1.8V/1.5V
0.9V/0.75V
COUT
VOUT
V
RL
0.9V
0V
RL and COUT
Time deleay
0.15V
AVCNTL = 5V
Figure 3. Current Limit for High Side, ILIM
Figure 4. Current Limit for Low Side, ILIM
Figure 5. REFEN Pin Shutdown Threshold, VIH & VIL
VIN
REFEN
GND
VCNTL
VOUT
RT9199
0.9V/0.75V
COUT
IL
VOUT
V
A
VIN = 1.8V/1.5V VCNTL = 5V
VIN
REFEN
GND
VCNTL
VOUT
RT9199
VIN = 1.8V/1.5V
0.9V/0.75V
COUT
IL
VOUT
V
A
Power Supply
with Current Limit VCNTL = 5V
VIN
REFEN
GND
VCNTL
VOUT
RT9199
VIN = 1.8V/1.5V
COUT
VOUT
V
RL
0.9V/0.75V
0V
RL and COUT
Time deleay
0.9V/0.75V
0.15V
VOUT
VREFEN
VOUT would be low if VREFEN < 0.15V
VOUT would be high if VREFEN > 0.6V
VCNTL = 5V
RT9199
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DS9199-10 May 2011www.richtek.com
Functional Pin Description
VIN
Input voltage which supplies current to the output pin.
Connect this pin to a well-decoupled supply voltage. To
prevent the input rail from dropping during large load
transient, a large, low ESR capacitor is recommended to
use. The capacitor should be placed as close as possible
to the VIN pin.
GND (Exposed Pad)
Common Ground. The exposed pad must be soldered to
a large PCB and connected to GND for maximum power
dissipation.
VCNTL
VCNTL supplies the internal control circuitry and provides
the drive voltage. The driving capability of output current is
proportioned to the VCNTL. Connect this pin to 5V bias
supply to handle large output current with at least 1μF
capacitor from this pin to GND. An important note is that
VIN should be kept lower or equal to VCNTL.
Function Block Diagram
GND
VCNTL
REFEN
Current Limit
Thermal Protection
VOUT
EA
+
-
VIN
REFEN
Reference voltage input and active low shutdown control
pin. Two resistors dividing down the VIN voltage on the pin
to create the regulated output voltage. Pulling the pin to
ground turns off the device by an open-drain, such as
2N7002, signal N-MOSFET.
VOUT
Regulator output. VOUT is regulated to REFEN voltage
that is used to terminate the bus resistors. It is capable of
sinking and sourcing current while regulating the output
rail. To maintain adequate large signal transient response,
typical value of 1000μF Al electrolytic capacitor with 10μF
ceramic capacitors are recommended to reduce the effects
of current transients on VOUT.
RT9199
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DS9199-10 May 2011 www.richtek.com
Electrical Characteristics
(VIN = 1.8V/1.5V, VCNTL = 5V, VREFEN = 0.9V/0.75V, COUT = 10μF (Ceramic), TA = 25°C, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Input
VCNTL Operation Current ICNTL I
OUT = 0A -- 1 2.5 mA
Standby Current (Note 5) ISTBY VREFEN < 0.2V (Shutdown),
RLOAD = 180Ω -- 2 90 μA
Output (DDR II)
Output Offset Voltage (Note 6) VOS I
OUT = 0A −10 -- 10 mV
VIN = 1.8V, VREFIN = 0.9V, IOUT = ±1.8A −20 -- 20
Load Regulation (Note 7) ΔVLOAD
VIN = 1.5V, VREFIN = 0.75V, IOUT = ±1.4A −10 -- 10
mV
Prote ctio n
VIN = 1.8V, VREFIN = 0.9V 2 -- 3.5
Current li mit ILIMIT VIN = 1.5V, VREFIN = 0.75V 1.5 -- 3.5 A
Thermal Shutdown Temperature TSD V
CNTL = 5V 125 170 -- °C
Thermal Shutdown Hysteresis ΔTSD V
CNTL = 5V -- 35 -- °C
REFEN Shutdown
VIH Enable 0.6 -- --
Shutdown Threshold
VIL Shutdown -- -- 0.15
V
Absolute Maximum Ratings (Note 1)
zInput Voltage, VIN ---------------------------------------------------------------------------------------------------------- 6V
zControl Voltage, VCNTL --------------------------------------------------------------------------------------------------- 6V
z Power Dissipation, PD @ TA = 25°C
SOP-8 ----------------------------------------------------------------------------------------------------------------------- 0.909W
SOP-8 (Exposed Pad) -------------------------------------------------------------------------------------------------- 1.176W
zPackage Thermal Resistance (Note 2)
SOP-8, θJA ------------------------------------------------------------------------------------------------------------------ 110°C/W
SOP-8, θJC ------------------------------------------------------------------------------------------------------------------ 60°C/W
SOP-8 (Exposed Pad), θJA ---------------------------------------------------------------------------------------------- 86°C/W
SOP-8 (Exposed Pad), θJC --------------------------------------------------------------------------------------------- 15°C/W
zJunction Temperature ----------------------------------------------------------------------------------------------------- 125°C
zLead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------- 260°C
zStorage Temperature Range -------------------------------------------------------------------------------------------- –65°C to 150°C
zESD Susceptibility (Note 3)
HBM (Human Body Mode) ---------------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ------------------------------------------------------------------------------------------------------ 200V
Recommended Operating Conditions (Note 4)
zInput Voltage, VIN ---------------------------------------------------------------------------------------------------------- 1.4V to 5.5V
zControl Voltage, VCNTL --------------------------------------------------------------------------------------------------- 5V ± 5%
zJunction Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C
RT9199
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DS9199-10 May 2011www.richtek.com
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in the natural convection at TA = 25°C on a high effective thermal conductivity test board (4 Layers,
2S2P) of JEDEC 51-7 thermal measurement standard. The case point of θJC is on the exposed pad for package.
Note 3. Devices are ESD sensitive. Handling precaution recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Standby current is the input current drawn by a regulator when the output voltage is disabled by a shutdown signal on
REFEN pin (VIL < 0.15V). It is measured with VIN = VCNTL = 5V.
Note 6. VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN.
Note 7. Regulation is measured at constant junction temperature by using a 5ms current pulse. Devices are tested for load
regulation in the load range from 0A to 2A peak.
RT9199
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DS9199-10 May 2011 www.richtek.com
Typical Operating Characteristics
Shutdown Threshold vs. Te m perature
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
-50 -25 0 25 50 75 100 125
Temperature (°C)
Shutdown Threshold (V
)
RT9199SP, VCNTL = 5V
Turn On
Turn Off
VIN Current vs. Temperature
0.0
0.5
1.0
1.5
2.0
2.5
3.0
-50 -25 0 25 50 75 100 125
Temperature (°C)
VIN Current (mA)
VIN = 1.8V, VCNTL = 5V
Sink Current Limit vs . Te m pe rature
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-50 -25 0 25 50 75 100 125
Temperature (°C)
Source Current Limit (A)
VIN = 1.8V, VCNTL = 5V
Source Current Lim it vs . Te m perature
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-50-250 255075100125
Temperature (°C)
Source Current Limit (A)
VIN = 1.8V, VCNTL = 5V
VCNTL Pin Current vs. Te m pe rature
0.1
0.2
0.3
0.4
0.5
0.6
-50-25 0 25 50 75100125
Temperature (°C)
Vcntl Pin Current (mA
)
VIN = 1.8V, VCNTL = 5V
Output Voltage vs. Temperature
0.880
0.885
0.890
0.895
0.900
0.905
0.910
0.915
0.920
-50 -25 0 25 50 75 100 125
Temperature (°C)
Output Voltage (V)
VIN = 1.8V, VCNTL = 5V
RT9199
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DS9199-10 May 2011www.richtek.com
1.25VTT @ 1.8A Transient Response
Output Voltage
Transient (mV)
50
0
-50
Output Current
(A)
2
1
0
-1
-2
VIN = 2.5V, VCNTL = 5V, VOUT = 1.25V
Time (25μs/Div)
Swing Frequency : 10kHz
0.9VTT @ 1.8A Transient Response
Output Voltage
Transient (mV)
50
0
-50
Output Current
(A)
2
1
0
-1
-2
VIN = 1.8V, VCNTL = 5V, VOUT = 0.9V
Time (25μs/Div)
Swing Frequency : 10kHz
VIN = 2.5V, VCNTL = 5V
Output Short-Circuit Protection
Output Short Circuit (A)
12
10
8
6
4
2
0
Time (1ms/Div)
Source
VIN = 1.8V, VCNTL = 5V
Output Short-Circuit Protection
Output Short Circuit (A)
12
10
8
6
4
2
0
Time (1ms/Div)
Source
VIN = 1.8V, VCNTL = 5V
Output Short-Circuit Protection
Output Short Circuit (A)
12
10
8
6
4
2
0
Time (1ms/Div)
Sink VIN = 2.5V, VCNTL = 5V
Output Short-Circuit Protection
Output Short Circuit (A)
12
10
8
6
4
2
0
Time (1ms/Div)
Sink
RT9199
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DS9199-10 May 2011 www.richtek.com
General Regulator
The RT9199 could also serves as a general linear regulator.
The RT9199 accepts an external reference voltage at
REFEN pin and provides output voltage regulated to this
reference voltage as shown in Figure 6, where
VOUT = VREFEN x R2/(R1+R2)
As other linear regulator, dropout voltage and thermal issue
should be specially considered. Figure 7 shows the RDS(ON)
over temperature of RT9199. The minimum dropout voltage
could be obtained by the product of RDS(ON) and output
current. For thermal consideration, please refer to the
relative sections.
Application Information
Consideration while designing the resistance of
voltage divider
Refer to the “Typical Application Circuit”. Make sure the
current sinking capability of pull-down NMOS is enough
for the chosen voltage divider to pull-down the voltage at
REFEN pin below 0.15V to shutdown the device.
In addition, the capacitor CSS and voltage divider form the
low-pass filter. There are two reasons doing this design;
one is for output voltage soft-start while another is for noise
immunity.
How to reduce power dissipation on Notebook PC
or the dual channel DDR SDRAM application?
In notebook application, using RichTek's Patent
“Distributed Bus Terminator Topology” with choosing
RichTek's product is encouraged.
Distributed Bus Terminating Topology
R0
R9
R8
R7
R6
R5
R4
R3
R2
R1
R(2N)
R(2N+1)
RT9199
RT9199 VOUT
VOUT
REFEN
BUS(0)
BUS(1)
BUS(2)
BUS(3)
BUS(4)
BUS(5)
BUS(6)
BUS(7)
BUS(8)
BUS(9)
BUS(2N)
BUS(2N+1)
Terminator Resistor
Input Capacitor and Layout Consideration
Place the input bypass capacitor as close as possible to
the RT9199. A low ESR capacitor larger than 470uF is
recommended for the input capacitor. Use short and wide
traces to minimize parasitic resistance and inductance.
Inappropriate layout may result in large parasitic inductance
and cause undesired oscillation between RT9199 and the
preceding power converter.
Thermal Consideration
RT9199 regulators have internal thermal limiting circuitry
designed to protect the device during overload conditions.
For continued operation, do not exceed absolute maximum
operation junction temperature 125°C. The power
dissipation definition in device is :
PD = (VIN - VOUT) x IOUT + VIN x IQ
Figure 6
VCNTL
REFEN
GND
VIN
VOUT
RT9199
VREFEN
R1
R2
Figure 7
RDS(ON) vs. Temperature
0.28
0.3
0.32
0.34
0.36
0.38
0.4
0.42
0.44
0.46
0.48
-50-250 255075100125
Temperature
RDS(ON) (Ω)
VCNTL = 5V, VREFEN = 1V
(°C)
RT9199
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DS9199-10 May 2011www.richtek.com
The maximum power dissipation depends on the thermal
resistance of IC package, PCB layout, the rate of
surroundings airflow and temperature difference between
junction to ambient. The maximum power dissipation can
be calculated by following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
Where TJ(MAX) is the maximum operation junction
temperature 125°C, TA is the ambient temperature and the
θJA is the junction to ambient thermal resistance. The
junction to ambient thermal resistance for SOP-8 package
(Exposed Pad) is 86°C/W, on standard JEDEC 51-7 (4
layers, 2S2P) thermal test board. The maximum power
dissipation at TA = 25°C can be calculated by following
formula :
PD(MAX) = (125°C − 25°C) / 86°C/W = 1.163W
Figure 8 shows the package sectional drawing of SOP-8
(Exposed Pad). Every package has several thermal
dissipation paths. As show in Figure 9, the thermal
resistance equivalent circuit of SOP-8 (Exposed Pad). The
path 2 is the main path due to these materials thermal
conductivity. We define the exposed pad is the case point
of the path 2.
Figure 8. SOP-8 (Exposed Pad) Package Sectional
Drawing
Ambient
Molding Compound
Gold Line Lead Frame
Die Pad
Case (Exposed Pad)
PCB
The thermal resistance θJA of SOP-8 (Exposed Pad) is
determined by the package design and the PCB design.
However, the package design has been decided. If possible,
it’s useful to increase thermal performance by the PCB
design. The thermal resistance can be decreased by
adding copper under the expose pad of SOP-8 package.
Figure 10 show the relation between thermal resistance
θJA and copper area on a standard JEDEC 51-7 (4 layers,
2S2P) thermal test board at TA = 25°C. We have to consider
the copper couldn’t stretch infinitely and avoid the tin
overflow. We use the “Dog-Bone” copper patterns on the
top layer as Figure 11.
0
10
20
30
40
50
60
70
80
90
100
0 1020304050607080
Copper Area (mm2)
Thermal Resistance θ
JA (°C/W)
Figure 10. Relation Between Thermal Resistance θJA and
Copper Area
Figure 11. Dog-Bone Layout
Exposed Pad
W≦2.28mm
Figure 9. Thermal Resistance Equivalent Circuit
Junction
RDIE RDIE-ATTACH RDIE-PAD
RGOLD-LINE RLEAD FRAME
Case
(Exposed Pad)
RPCB
RPCB
Ambient
RMOLDING-COMPOUND
path 1
path 2
path 3
RT9199
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DS9199-10 May 2011 www.richtek.com
As shown in Figure 12, the amount of copper area to which
the SOP-8 (Exposed Pad) is mounted affects thermal
performance. When mounted to the standard SOP-8
(Exposed Pad) pad of 2 oz. copper (Figure 12.a), θJA is
Figure 12. Thermal Resistance vs. Copper Area Layout Thermal Design
(a) Copper Area = 10mm2, θJA = 86°C/W
(b) Copper Area = 30mm2, θJA = 73°C/W
(c) Copper Area = 50mm2, θJA = 68°C/W
(d) Copper Area = 70mm2, θJA = 65°C/W
86°C/W. Adding copper area of pad under the SOP-8
(Exposed Pad) (Figure 12.b) reduces the θJA to 73°C/W.
Even further, increasing the copper area of pad to 70mm2
(Figure 12.d) reduces the θJA to 65°C/W.
RT9199
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DS9199-10 May 2011www.richtek.com
Outline Information
A
B
J
F
H
M
C
D
I
8-Lead SOP Plastic Package
Dimensions In Millimeters Dimen sions In Inches
Symbol Min Max Min Max
A 4.801 5.004 0.189 0.197
B 3.810 3.988 0.150 0.157
C 1.346 1.753 0.053 0.069
D 0.330 0.508 0.013 0.020
F 1.194 1.346 0.047 0.053
H 0.170 0.254 0.007 0.010
I 0.050 0.254 0.002 0.010
J 5.791 6.200 0.228 0.244
M 0.400 1.270 0.016 0.050
RT9199
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DS9199-10 May 2011 www.richtek.com
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design,
specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed
by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
Richtek Technology Corporation
Headquarter
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Richtek Technology Corporation
Taipei Office (Marketing)
5F, No. 95, Minchiuan Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8862)86672399 Fax: (8862)86672377
Email: marketing@richtek.com
A
B
J
F
H
M
C
D
I
Y
X
EXPOSED THERMAL PAD
(Bottom of Package)
8-Lead SOP (Exposed Pad) Plastic Package
Dimensio ns In Millimeters Dimensions In Inche s
Symbol Min Max Min Max
A 4.801 5.004 0.189 0.197
B 3.810 4.000 0.150 0.157
C 1.346 1.753 0.053 0.069
D 0.330 0.510 0.013 0.020
F 1.194 1.346 0.047 0.053
H 0.170 0.254 0.007 0.010
I 0.000 0.152 0.000 0.006
J 5.791 6.200 0.228 0.244
M 0.406 1.270 0.016 0.050
X 2.000 2.300 0.079 0.091
Option 1 Y 2.000 2.300 0.079 0.091
X 2.100 2.500 0.083 0.098
Option 2 Y 3.000 3.500 0.118 0.138
