LP3921 www.ti.com SNVS580A - AUGUST 2008 - REVISED MAY 2013 LP3921 Battery Charger Management and Regulator Unit with Integrated BoomerTM Audio Amplifier Check for Samples: LP3921 FEATURES DESCRIPTION * The LP3921 is a fully integrated charger and multiregulator unit with a fully differential Boomer audio power amplifier designed for CDMA cellular phones. The LP3921 has a high-speed serial interface which allows for the integration and control of a Li-Ion battery charger, 7 low-noise low-dropout (LDO) voltage regulators and a Boomer audio amplifier. 1 23 * * * * * * Charger - DC Adapter or USB Input - Thermally Regulated Charge Current - Under Voltage Lockout - 50 to 950 mA Programmable Charge Current 3.0V to 5.5V Input Voltage Range Thermal Shutdown I2C-Compatible Interface for Controlling Charger, LDO Outputs and Enabling Audio Output LDO's 7 Low-Noise LDO's - 2 x 300 mA - 3 x 150 mA - 2 x 80 mA 2% (typ.) Output Voltage Accuracy on LDO's Audio - Fully Differential Amplification - Ability to Drive Capacitive Loads up to 100 pF - No Output Coupling Capacitors, Snubber Networks or Bootstrap Capacitors Required Space-Efficient 32-pin 5 x 5 mm WQFN Package APPLICATIONS * * * * The Li-Ion charger integrates a power FET, reverse current blocking diode, sense resistor with current monitor output, and requires only a few external components. Charging is thermally regulated to obtain the most efficient charging rate for a given ambient temperature. LDO regulators provide high PSRR and low noise ideally suited for supplying power to both analog and digital loads. The Boomer Audio Amplifier is capable of delivering 1.1 watts of continuous average power to an 8 BTL load with less than 1% distortion (THD+N). Boomer Audio Power Amplifiers were designed specifically to provide high quality output power with a minimal amount of external components. The Boomer Audio Amplifier does not require output coupling capacitors or bootstrap capacitors, and therefore is ideally suited for mobile phone and other low voltage applications where minimal power consumption and part count is the primary requirement. The Boomer Audio Amplifier contains advanced pop & click circuitry which eliminates noises during turn-on and turn-off transitions. CDMA Phone Handsets Low Power Wireless Handsets Handheld Information Appliances Personal Media Players 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Boomer is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2008-2013, Texas Instruments Incorporated LP3921 SNVS580A - AUGUST 2008 - REVISED MAY 2013 www.ti.com System Diagram AC Adapter Li-Ion Charger Ichg Monitor I/O Interface of Baseband Processor + - BB Processor Power Domains Serial Interface Memory 7 x LDO 2 Control RF Audio Peripheral Devices Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 LP3921 www.ti.com SNVS580A - AUGUST 2008 - REVISED MAY 2013 Functional Block Diagram VBATT 10 PF BATT CHG_IN Battery 10 PF VIN1 + 10 PF VIN2 AC Adapter or VBUS supply 4.5V to 6V LDO1 IMON LDO1 LDO2 Linear Charger 1 PF CORE 1.8V @300 mA ACOK_N LDO2 LDO2 1 PF DIGI 3.0V @300 mA LDO2 320 ms debounce 1.5k LDO3 1.5k LDO3 1 PF SDA ANA 3.0V @80 mA LDO2 O/D output SCL TCXO_EN PON_N LDO4 LDO4 PS_HOLD 1 PF RESET_N HF_PWR 320 ms debounce PWR_ON 30 ms debounce RX_EN LDO5 LDO5 1 PF 500k 500k VBATT Serial Interface and Control LP3921 LDO6 Thermal Shutdown 1 PF TX 3.0V @150 mA UVLO LDO7 Voltage Reference 1.0 PF RX 3.0V @150 mA TX_EN LDO6 VDD TCXO 3.0V @80 mA LDO7 1 PF GP 3.0V @150 mA VO+ Shut Down 20k 20k VO+ -IN - Differential Input BOOMER AUDIO + Differential Input RL 8: +IN 20k VO- 20k VSS GNDA GND BYP VO- 1.0 PF Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 3 LP3921 SNVS580A - AUGUST 2008 - REVISED MAY 2013 www.ti.com Connection Diagram Figure 1. Device Pin Diagram 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 32 9 31 10 30 11 29 12 28 13 27 14 26 15 25 16 24 Device Description The LP3921 Charge Management and Regulator Unit is designed to supply charger and voltage output capabilities for mobile systems, e.g. CDMA handsets. The device provides a Li-Ion charging function and 7 regulated outputs. Communication with the device is via an I2C compatible serial interface that allows function control and status read-back. Battery Charge Management provides a programmable CC/CV linear charge capability. Following a normal charge cycle a maintenance mode keeps battery voltage between programmable levels. Power levels are thermally regulated to obtain optimum charge levels over the ambient temperature range. CHARGER FEATURES * * * * * * * * * * * * * * * * 4 Pre-charge, CC, CV and Maintenance modes USB Charge 100 mA/450 mA Integrated FET Integrated Reverse Current Blocking Diode Integrated Sense Resistor Thermal regulation Charge Current Monitor Output Programmable charge current 50 mA - 950 mA with 50 mA steps Default CC mode current 100 mA Pre-charge current fixed 50 mA Termination voltage 4.1V, 4.2V (default), 4.3V, and 4.4V, accuracy better than +/- 0.35% (typ.) Restart level 100 mV, 150 mV (default) and 200 mV below Termination voltage Programmable End of Charge 0.1C (default), 0.15C, 0.2C and 0.25C Enable Control Input Safety timer Input voltage operating range 4.5V - 6.0V Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 LP3921 www.ti.com SNVS580A - AUGUST 2008 - REVISED MAY 2013 REGULATORS Seven low-dropout linear regulators provide programmable voltage outputs with current capabilities of 80 mA, 150 mA and 300 mA as given in the table below. LDO1, LDO2 and LDO3 are powered up by default with LDO1 reaching regulation before LDO2 and LDO3 are started. LDO1, LDO3 and LDO7 can be disabled/enabled via the serial interface. LDO1 and LDO2, if enabled, must be in regulation for the device to power up and remain powered. LDO4, LDO5 and LDO6 have external enable pins and may power up following LDO2 as determined by their respective enable. Under voltage lockout oversees device start up with preset level of 2.85V (typ.). POWER SUPPLY CONFIGURATIONS At PMU start up, LDO1, LDO2 and LDO3 are always started with their default voltages. The start up sequence of the LDO's is given below. Startup Sequence LDO1 -> LDO2 -> LDO3 LDO's with external enable control (LDO4, LDO5, LDO6) start immediately after LDO2 if enabled by logic high at their respective control inputs. LDO7 (and LDO1, LDO3) may be programmed to enable/disable once PS_HOLD has been asserted. DEVICE PROGRAMMABILITY An I2C compatible Serial Interface is used to communicate with the device to program a series of registers and also to read status registers. These internal registers allow control over LDO outputs and their levels. The charger functions may also be programmed to alter termination voltage, end of charge current, charger restart voltage, full rate charge current, and also the charging mode. This device internal logic is powered from LDO2. Table 1. LDO Default Voltages LDO Function mA Default Voltage (V) Startup Default Enable Control 1 CORE 300 1.8 ON SI 2 DIGI 300 3.0 ON - 3 ANA 80 3.0 ON SI 4 TCXO 80 3.0 OFF TCXO_EN 5 RX 150 3.0 OFF RX_EN 6 TX 150 3.0 OFF TX_EN 7 GP 150 3.0 OFF SI Table 2. LDO Output Voltages Selectable via Serial Interface LDO mA 1.5 1.8 1.85 2.5 2.6 2.7 2.75 2.8 2.85 2.9 2.95 3.0 3.05 3.1 3.2 3.3 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 CORE 300 2 DIGI 300 3 ANA 80 4 TCXO 80 5 RX 150 6 TX 150 7 GP 150 + + + + + + + + + + LP3921 Pin Descriptions (1) (1) Type (1) Pin# Name 1 LDO6 A Description LDO6 Output (TX) 2 TX_EN DI Enable control for LDO6 (TX). HIGH = Enable, LOW = Disable 3 LDO5 A A LDO5 Output (RX) Key: A=Analog; D=Digital; I=Input; DI/O=Digital-Input/Output; G=Ground; O=Output; P=Power Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 5 LP3921 SNVS580A - AUGUST 2008 - REVISED MAY 2013 www.ti.com LP3921 Pin Descriptions(1) (continued) Pin# Name Type (1) 4 VIN2 P Battery Input for LDO3 - LDO7 5 LDO7 A LDO7 Output (GP) 6 OUT+ AO Differential output + 7 VDD P 8 OUT- AO Differential output - 9 IN+ AI Differential input + 10 IN- AI Differential input - 11 GND G Analog Ground Pin 12 BYPASS A Amplifier bypass cap 13 LDO4 A LDO4 Output (TCXO) 14 LDO3 A LDO3 Output (ANA) 15 LDO2 A LDO2 Output (DIGI) 16 LDO1 A LDO1 Output (CORE) 17 VIN1 P Battery Input for LDO1 and LDO2 18 GNDA G Analog Ground pin Description DC power input to audio amplifier SDA DI/O 20 SCL DI Serial Interface Clock input. External pull up resistor is needed. (typ. 1.5k) 21 BATT P Main battery connection. Used as a power connection for current delivery to the battery. 22 CHG_IN P DC power input to charger block from wall or car power adapters. 23 PWR_ON DI Power up sequence starts when this pin is set HIGH. Internal 500k. pull-down resistor. IMON A Charge current monitor output. This pin presents an analog voltage representation of the 25 PS_HOLD DI Input for power control from external processor/controller. 26 TCXO_EN DI Enable control for LDO4 (TX). HIGH = Enable, LOW = Disable. 27 HF_PWR DI Power up sequence starts when this pin is set HIGH. Internal 500k. pull-down resistor. 28 VSS G Digital Ground pin 29 PON_N DO Active low signal is PWR_ON inverted. RESET_N DO Reset Output. Pin stays LOW during power up sequence. 60 ms after LDO1 (CORE) is stable this pin is asserted HIGH. 31 ACOK_N DO AC Adapter indicator, LOW when 4.5V- 6.0V present at CHG_IN. 32 RX_EN DI Enable control for LDO5 (RX). HIGH = Enable, LOW = Disable. 19 24 Serial Interface, Data Input/Output Open Drain output, external pull up resistor is needed. (typ. 1.5k) input charging current. VIMON (mV) = (2.47 x ICHG)(mA). 30 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 6 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 LP3921 www.ti.com SNVS580A - AUGUST 2008 - REVISED MAY 2013 Absolute Maximum Ratings (1) (2) -0.3 to +6.5V CHG-IN -0.3 to +6.0V VBATT =VIN1/2, BATT, VDD, HF_PWR -0.3 to VBATT +0.3V, max 6.0V All other Inputs Junction Temperature (TJ-MAX) 150C Storage Temperature -40C to +150C Max Continuous Power Dissipation (PD-MAX) (3) Internally Limited ESD (4) BATT, VIN1, VIN2, VDD, HF_PWR, CHG_IN, PWR_ON 8 kV HBM All other pins 2 kV HBM (1) (2) (3) (4) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is verified. Operating Ratings do not imply verified performance limits. For verified performance limits and associated test conditions, see the Electrical Characteristics tables. If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. Internal Thermal Shutdown circuitry protects the device from permanent damage. The human-body model is 100 pF discharged through 1.5 k. The machine model is a 200 pF capacitor discharged directly into each pin, MIL-STD-883 3015.7. Operating Ratings (1) (2) CHG_IN (3) 4.5 to 6.0V VBATT =VIN1/2, BATT, VDD 3.0 to 5.5V HF_PWR, PWR_ON 0V to 5.5V ACOK_N, SDA, SCL, RX_EN, TX_EN, TCXO_EN, PS_HOLD, RESET_N 0V to (VLDO2 + 0.3V) All other pins 0V to (VBATT + 0.3V) -40C to +125C Junction Temperature (TJ) Ambient Temperature (TA) (4) (1) (2) (3) (4) -40 to 85C Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is verified. Operating Ratings do not imply verified performance limits. For verified performance limits and associated test conditions, see the Electrical Characteristics tables. All voltages are with respect to the potential at the GND pin. Full-charge current is specified for CHG_IN = 4.5 to 6.0V. At higher input voltages, increased power dissipation may cause the thermal regulation to limit the current to a safe level, resulting in longer charging time. Care must be exercised where high power dissipation is likely. The maximum ambient temperature may have to be derated. Like the Absolute Maximum power dissipation, the maximum power dissipation for operation depends on the ambient temperature. In applications where high power dissipation and/or poor thermal dissipation exists, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA_MAX) is dependent on the maximum power dissipation of the device in the application (PD_MAX), and the junction to ambient thermal resistance of the device/package in the application (JA), as given by the following equation:TA_MAX = TJ_MAX-OP - (JA X PDMAX ). Thermal Properties (1) Junction to Ambient Thermal Resistance JA 4L Jedec Board (1) 30 C/W Junction-to-ambient thermal resistance (JA) is taken from thermal modelling result, performed under the conditions and guidelines set forth in the JEDEC standard JESD51-7. The value of (JA) of this product could fall within a wide range, depending on PWB material, layout, and environmental conditions. In applications where high maximum power dissipation exists (high VIN, high IOUT), special care must be paid to thermal dissipation issues in board design. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 7 LP3921 SNVS580A - AUGUST 2008 - REVISED MAY 2013 www.ti.com General Electrical Characteristics Unless otherwise noted, VIN (=VIN1=VIN2=BATT=VDD) = 3.6V, GND = 0V, CVIN1-2=10 F, CLDOX=1 F. Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TA = TJ = -40C to +125C. (1) Symbol IQ(STANDBY) Parameter Standby Supply Current Condition Typ VIN = 3.6V, UVLO on, internal logic circuit on, all other circuits off 2 Limit Min Max Units 5 A 3.0 V POWER MONITOR FUNCTIONS Battery Under-Voltage Lockout VUVLO-R Under Voltage Lockout VIN Rising 2.85 2.7 THERMAL SHUTDOWN Higher Threshold (2) 160 C LOGIC AND CONTROL INPUTS VIL Input Low Level PS_HOLD, SDA, SCL, RX_EN, TCXO_EN, TX_EN (2) 0.25* V VLDO2 PWR_ON, HF_PWR 0.25* (2) V VBATT VIH Input High Level PS_HOLD, SDA, SCL, RX_EN, TCXO_EN, TX_EN 0.75* V VLDO2 (2) PWR_ON, HF_PWR 0.75* (2) V VBATT IIL Logic Input Current RIN Input Resistance All logic inputs except PWR_ON and HF_PWR -5 +5 A 0V VINPUT VBATT PWR_ON, HF_PWR Pull-Down resistance to GND 500 k LOGIC AND CONTROL OUTPUTS VOL Output Low Level VOH Output High Level PON_N, RESET_N, SDA, ACOK_N 0.25* IOUT = 2 mA V VLDO2 PON_N, RESET_N, ACOK_N 0.75* IOUT = -2 mA VLDO2 V (Not applicable to Open Drain Output SDA) (1) (2) All limits are verified. All electrical characteristics having room-temperature limits are tested during production with TJ = 25C. All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Specified by design. LDO1 (CORE) Electrical Characteristics Unless otherwise noted, VIN (=VIN1=VIN2=BATT=VDD) = 3.6V, GND = 0V, CVIN1-2=10 F, CLDOX=1 F. Note VINMIN is the greater of 3.0V or VOUT1+ 0.5V. Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TA = TJ = -40C to +125C. (1) Symbol VOUT1 (1) 8 Parameter Condition Output Voltage Accuracy IOUT1 = 1 mA, VOUT1= 3.0V Output Voltage Default Typ 1.8 Limit Min Max -2 +2 -3 +3 Units % V All limits are verified. All electrical characteristics having room-temperature limits are tested during production with TJ = 25C. All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 LP3921 www.ti.com SNVS580A - AUGUST 2008 - REVISED MAY 2013 LDO1 (CORE) Electrical Characteristics (continued) Unless otherwise noted, VIN (=VIN1=VIN2=BATT=VDD) = 3.6V, GND = 0V, CVIN1-2=10 F, CLDOX=1 F. Note VINMIN is the greater of 3.0V or VOUT1+ 0.5V. Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TA = TJ = -40C to +125C. (1) Symbol IOUT1 Parameter Condition Output Current VINMIN VIN 5.5V Output Current Limit VOUT1 = 0V VDO1 Dropout Voltage IOUT1 = 300 mA VOUT1 Line Regulation VINMIN VIN 5.5V Typ Limit Min Max Units 300 mA 310 mV 600 (2) 220 2 mV IOUT1 = 1 mA Load Regulation en1 1 mA IOUT1 300 mA Output Noise Voltage 10 Hz f 100 kHz, COUT = 1 F PSRR tSTART-UP TTransient (2) (3) (4) 10 mV 45 VRMS 65 dB (3) Power Supply Rejection Ratio F = 10 kHz, COUT = 1 F Start-Up Time from Internal Enable COUT = 1 F, IOUT1 = 300 mA Start-Up Transient Overshoot COUT = 1 F, IOUT1 = 300 mA IOUT1 = 20 mA (3) 60 170 s 60 120 mV (4) (3) Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply in cases it implies operation with an input voltage below the 3.0V minimum appearing under Operating Ratings. For example, this specification does not apply for devices having 1.5V outputs because the specification would imply operation with an input voltage at or about 1.5V. Specified by design. Specified by design. LDO2 (DIGI) Electrical Characteristics Unless otherwise noted, VIN (=VIN1=VIN2=BATT=VDD) = 3.6V, GND = 0V, CVIN1-2=10 F, CLDOX=1 F. Note VINMIN is the greater of 3.0V or VOUT2+ 0.5V. Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TA = TJ = -40C to +125C. (1) Symbol VOUT2 IOUT2 Parameter Condition Output Voltage Accuracy IOUT2 = 1 mA, VOUT2= 3.0V Output Voltage Default Output Current VINMIN VIN 5.5V Typ Limit Min Max -2 +2 -3 +3 Units % 3 Output Current Limit VOUT2 = 0V VDO2 Dropout Voltage IOUT2 = 300 mA VOUT2 Line Regulation VINMIN VIN 5.5V V 300 mA 310 mV 600 (2) 220 2 mV IOUT2 = 1mA Load Regulation en2 1 mA IOUT2 300 mA Output Noise Voltage 10 Hz f 100 kHz, COUT = 1 F PSRR (1) (2) (3) Power Supply Rejection Ratio 10 mV 45 VRMS 65 dB (3) F = 10 kHz, COUT = 1 F IOUT2 = 20 mA (3) All limits are verified. All electrical characteristics having room-temperature limits are tested during production with TJ = 25C. All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply in cases it implies operation with an input voltage below the 3.0V minimum appearing under Operating Ratings. For example, this specification does not apply for devices having 1.5V outputs because the specification would imply operation with an input voltage at or about 1.5V. Specified by design. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 9 LP3921 SNVS580A - AUGUST 2008 - REVISED MAY 2013 www.ti.com LDO2 (DIGI) Electrical Characteristics (continued) Unless otherwise noted, VIN (=VIN1=VIN2=BATT=VDD) = 3.6V, GND = 0V, CVIN1-2=10 F, CLDOX=1 F. Note VINMIN is the greater of 3.0V or VOUT2+ 0.5V. Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TA = TJ = -40C to +125C. (1) Symbol Parameter Condition Typ Limit Min Max Units tSTART-UP Start-Up Time from Shutdown COUT = 1 F, IOUT2 = 300 mA (3) 40 60 s tTransient Start-Up Transient Overshoot COUT = 1 F, IOUT2 = 300 mA (3) 5 30 mV LDO3 (ANA), LDO4 (TCXO) Electrical Characteristics Unless otherwise noted, VIN (=VIN1=VIN2=BATT=VDD) = 3.6V, GND = 0V, CVIN1-2=10 F, CLDOX=1 F. TCXO_EN high. Note VINMIN is the greater of 3.0V or VOUT3/4 + 0.5V. Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TA = TJ = -40C to +125C. (1) Symbol VOUT3, VOUT4 Parameter Condition Output Voltage Accuracy IOUT3/4 = 1 mA, VOUT3/4= 3.0V Output Voltage LDO3 default 3 LDO4 default 3 Output Current VINMIN VIN 5.5V Output Current Limit VOUT3/4 = 0V VDO3, VDO4 Dropout Voltage IOUT3/4 = 80 mA VOUT3 , VOUT4 Line Regulation VINMIN VIN 5.5V IOUT3, IOUT4 Typ Limit Min Max -2 +2 -3 +3 Units % V 80 mA 310 mV 160 (2) 220 2 mV IOUT3/4 = 1 mA Load Regulation 1mA IOUT3/4 80 mA Output Noise Voltage 10 Hz f 100 kHz, en3,en4 COUT = 1 F PSRR 5 mV 45 VRMS 65 dB (3) Power Supply Rejection Ratio F = 10 kHz, COUT = 1 F tSTART-UP Start-Up Time from Enable (3) COUT = 1 F, IOUT3/4 = 80mA 40 60 s tTransient Start-Up Transient Overshoot COUT = 1F, IOUT3/4 = 80 mA 5 30 mV (1) (2) (3) 10 IOUT3/4 = 20 mA (3) (3) All limits are verified. All electrical characteristics having room-temperature limits are tested during production with TJ = 25C. All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply in cases it implies operation with an input voltage below the 3.0V minimum appearing under Operating Ratings. For example, this specification does not apply for devices having 1.5V outputs because the specification would imply operation with an input voltage at or about 1.5V. Specified by design. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 LP3921 www.ti.com SNVS580A - AUGUST 2008 - REVISED MAY 2013 LDO5 (RX), LDO6 (TX), LDO7 (GP) Electrical Characteristics Unless otherwise noted, VIN (=VIN1=VIN2=BATT=VDD) = 3.6V, GND = 0V, CVIN1-2=10 F, CLDOX=1 F. RX_EN, TX_EN high. LDO7 Enabled via Serial Interface. Note VINMIN is the greater of 3.0V or VOUT5/6/7 + 0.5V. Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TA = TJ = -40C to +125C. (1) Symbol VOUT5, VOUT6, VOUT7 Parameter Output Voltage Default Output Voltage IOUT5, IOUT6, IOUT7 Condition IOUT5/6/7 = 1mA, VOUT5/6/7= 3.0V LDO5 3 LDO6 3 LDO7 3 Output Current VINMIN VIN 5.5V Output Current Limit VOUT5/6/7 = 0V IOUT5/6/7 = 150 mA VOUT5, VOUT6, VOUT7 VINMIN VIN 5.5V (2) Max -2 +2 -3 +3 Units % V 200 150 mA 280 mV 2 1mA IOUT5/6/7 150 mA Output Noise Voltage 10 Hz f 100 kHz, COUT = 1 F PSRR Min mV IOUT5/6/7 = 1 mA Load Regulation en5, en6, en7 Limit 300 VDO5, VDO6, VDO7 Dropout Voltage Line Regulation Typ 10 mV 45 VRMS 65 dB (3) Power Supply Rejection Ratio F = 10 kHz, COUT = 1 F tSTART-UP Start-Up Time from Enable COUT = 1 F, IOUT5/6/7 = 150 mA 40 60 s tTransient Start-Up Transient Overshoot COUT = 1 F, IOUT5/6/7 = 150 mA 5 30 mV (1) (2) (3) (4) IOUT5/6/7 = 20 mA (3) (3) (4) All limits are verified. All electrical characteristics having room-temperature limits are tested during production with TJ = 25C. All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply in cases it implies operation with an input voltage below the 3.0V minimum appearing under Operating Ratings. For example, this specification does not apply for devices having 1.5V outputs because the specification would imply operation with an input voltage at or about 1.5V. Specified by design. Internal Thermal Shutdown circuitry protects the device from permanent damage. Charger Electrical Characteristics Unless otherwise noted, VCHG-IN = 5V, VIN (=VIN1=VIN2=BATT=VDD) = 3.6V.CCHG_IN = 10 F. Charger set to default settings unless otherwise noted. Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TA = TJ = -25C to +85C. (1) (2) Symbol VCHG-IN Parameter Input Voltage Range Condition Typ (3) Operating Range VOK_CHG (1) (2) (3) CHG_IN OK trip-point VCHG_IN - VBATT (Rising) 200 VCHG_IN - VBATT (Falling) 50 Limit Min Max 4.5 6.5 4.5 6 Units V mV All limits are verified. All electrical characteristics having room-temperature limits are tested during production with TJ = 25C. All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Junction-to-ambient thermal resistance (JA) is taken from thermal modelling result, performed under the conditions and guidelines set forth in the JEDEC standard JESD51-7. The value of (JA) of this product could fall within a wide range, depending on PWB material, layout, and environmental conditions. In applications where high maximum power dissipation exists (high VIN, high IOUT), special care must be paid to thermal dissipation issues in board design. Specified by design. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 11 LP3921 SNVS580A - AUGUST 2008 - REVISED MAY 2013 www.ti.com Charger Electrical Characteristics (continued) Unless otherwise noted, VCHG-IN = 5V, VIN (=VIN1=VIN2=BATT=VDD) = 3.6V.CCHG_IN = 10 F. Charger set to default settings unless otherwise noted. Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TA = TJ = -25C to +85C. (1)(2) Symbol VTERM ICHG Parameter Condition Battery Charge Termination voltage Default VTERM voltage tolerance TJ = 0C to 85C Typ Limit Min Max 4.2 Units V -1 +1 Fast Charge Current Accuracy ICHG = 450 mA -10 +10 % % Programmable full-rate charge 6.0V VCHG_IN 4.5V current range (default 100 mA) VBATT < (VCHG_IN - VOK_CHG) 50 950 mA 40 60 mA VFULL_RATE < VBATT < VTERM (4) Default 100 Charge current programming step 50 IPREQUAL Pre-qualification current VBATT = 2V ICHG_USB CHG_IN programmable current in USB mode 5.5V VCHG_IN 4.5V 50 Low 100 VBATT < (VCHG_IN - VOK_CHG) VFULL_RATE < VBATT < VTERM mA High 450 Default = 100 mA 100 VFULL_RATE Full-rate qualification threshold VBATT rising, transition from pre-qual to full-rate charging 3 IEOC End of Charge Current, % of full-rate current 0.1C option selected 10 VRESTART Restart threshold voltage VBATT falling, transition from EOC to full-rate charge mode. Default options selected - 4.05V 4.05 IMON IMON Voltage 1 ICHG = 100 mA 0.247 IMON Voltage 2 ICHG = 450 mA 1.112 TREG Regulated junction temperature (5) 115 2.9 3.1 V % 3.97 4.13 0.947 1.277 V V C Detection and Timing (5) TPOK Power OK deglitch time VBATT < (VCC - VOK_CHG) 32 TPQ_FULL Deglitch time Pre-qualification to full-rate charge transition 230 mS TCHG Charge timer Precharge mode 1 Hrs TEOC Deglitch time for end-ofcharge transition Charging Timeout (4) (5) 12 mS 5 230 mS Full-charge current is specified for CHG_IN = 4.5 to 6.0V. At higher input voltages, increased power dissipation may cause the thermal regulation to limit the current to a safe level, resulting in longer charging time. Specified by design. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 LP3921 www.ti.com SNVS580A - AUGUST 2008 - REVISED MAY 2013 Audio Electrical Characteristics Unless otherwise noted, VDD= 3.6V Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TA= TJ = -25C to +85C. (1) Symbol Paramater Conditions Typical Limit Min Max Units PO Output Power THD = 1% (max); f = 1 kHz, RL = 8 0.375 W THD + N Total Harmonic Distortion + Noise PO = 0.25 Wrms; f = 1 kHz 0.02 % Vripple = 200 mVPP PSRR Power Supply Rejection Ratio f = 217 Hz 85 f = 1 kHz 85 dB 73 CMRR Common-Mode Rejection Ratio f = 217 Hz, VCM = 200 mVPP 50 dB VOS Output Offset VacINput = 0V 4 mV (1) All limits are verified. All electrical characteristics having room-temperature limits are tested during production with TJ = 25C. All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Serial Interface Unless otherwise noted, VIN ( = VIN1 = VIN2 = BATT=VDD) = 3.6V, GND = 0V, CVIN1-2=10 F, CLDOX=1 F, and VLDO2 (DIGI) 1.8V. Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TA= TJ = -40C to +125C. (1) (2) Symbol Parameter Condition Typ Limit Min Max fCLK Clock Frequency tBF Bus-Free Time between START and STOP 1.3 s tHOLD Hold Time Repeated START Condition 0.6 s tCLK-LP CLK Low Period 1.3 s tCLK-HP CLK High Period 0.6 s tSU Set-Up Time Repeated START Condition 0.6 s tDATA-HOLD Data Hold Time 50 ns tDATA-SU Data Set-Up Time 100 ns tSU Set-Up Time for STOP Condition 0.6 s tTRANS Maximum Pulse Width of Spikes that Must be Suppressed by the Input Filter of both DATA & CLK Signals (1) (2) 400 Units 50 kHz ns All limits are verified. All electrical characteristics having room-temperature limits are tested during production with TJ = 25C. All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Specified by design. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 13 LP3921 SNVS580A - AUGUST 2008 - REVISED MAY 2013 www.ti.com TECHNICAL DESCRIPTION DEVICE POWER UP AND SHUTDOWN TIMING PWR_ON 30 ms Debounce time PS_HOLD needs to be asserted while PWR_ON is high. PS_HOLD LDO1 87% Reg < 200 Ps LDO2 87% Reg 60 ms RESET 2 I C Control LDO3 LDO7 RX_EN, TX_EN, TCXO_EN LDO4,5,6 Note: Serial I/F commands only take place after PS_HOLD is asserted. Figure 2. Device Power Up Logic Timing: PWR_ON 14 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 LP3921 www.ti.com SNVS580A - AUGUST 2008 - REVISED MAY 2013 If charger is connected (CHG_IN) or HF_PWR is applied, then both events are filtered for 320 ms before enabling LDO1 320 ms CHG_IN PS_HOLD needs to be asserted within 1200 ms after CHG_IN or HF_PWR rising edge has been detected. (HF_PWR level detected for LP3921) HF_PWR 1.2s Debounce time before normal start up sequence, 320 ms. PS_HOLD high < 1.2s from I/P detection PS_HOLD LDO1 87% Reg < 200 Ps LDO2 87% Reg 60 ms RESET 2 I C Control LDO3 LDO7 RX_EN, TX_EN, TCXO_EN LDO4,5,6 Note: Serial I/F commands only take place after PS_HOLD is asserted. Figure 3. Device Power Up Logic Timing: CHG_IN, HF_PWR START UP Device start is initiated by any of the 3 input signals, PWR_ON, HF_PWR and CHG_IN. PWR_ON When PWR_ON goes high the device will remain powered up, a PS_HOLD applied will allow the device to remain powered after the PWR_ON signal has gone low. HF_PWR, CHGIN PS_HOLD needs to be asserted within 1200 ms after a CHG_IN or HF_PWR rising edge has been detected. For applications where a level sensitive input is required the LP3921 is available with a level detect input at HF_PWR. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 15 LP3921 SNVS580A - AUGUST 2008 - REVISED MAY 2013 www.ti.com If charger is connected (CHG_IN) or HF_PWR is applied, then both events are filtered for 320 ms 320 ms before enabling LDO1 CHG_IN PS_HOLD needs to be asserted within 1200 ms after HF_PWR, or CHG_IN rising edge has been detected. 1.2s HF_PWR Either HF_PWR or CHG_IN will enable LDO1 If no enabling signal is high on the rising edge of PS_HOLD, shutdown will occur. PS_HOLD 87% LDO1 200 Ps 87% Reg LDO2 60 ms RESET Figure 4. LP3921 Power On Behavior (Failed PS_Hold) 35 ms PS_HOLD RESET If PS_HOLD is low 35 ms after initially going low, then LDO2-7 are shutdown LDO2 - 7 LDO1 is shutdown 40 Ps after other LDO's are shutdown LDO1 40 Ps Figure 5. LP3921 Normal Shutdown Behavior LP3921 Serial Port Communication Slave Address Code 7h'7E 16 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 LP3921 www.ti.com SNVS580A - AUGUST 2008 - REVISED MAY 2013 Table 3. Control Registers (1) Addr Register (default value) 8h'00 D7 D6 D5 D4 D3 D2 D1 D0 OP_EN (0000 0101) X X X X LDO7_EN LDO3_EN X LDO1_EN 8h'01 LDO1PGM O/P (0000 0001) X X X X V1_OP[3] V1_OP[2] V1_OP[1] V1_OP[0] 8h'02 LDO2PGM O/P (0000 1011) X X X X V2_OP[3] V2_OP[2] V2_OP[1] V2_OP[0] 8h'03 LDO3PGM O/P (0000 1011) X X X X V3_OP[3] V3_OP[2] V3_OP[1] V3_OP[0] 8h'04 LDO4PGM O/P (0000 1011) X X X X V4_OP[3] V4_OP[2] V4_OP[1] V4_OP[0] 8h'05 LDO5PGM O/P (0000 1011) X X X X V5_OP[3] V5_OP[2] V5_OP[1] V5_OP[0] 8h'06 LDO6PGM O/P (0000 1011) X X X X V6_OP[3] V6_OP[2] V6_OP[1] V6_OP[0] 8h'07 LDO7PGM O/P (0000 1011) X X X X V7_OP[3] V7_OP[2] V7_OP[1] V7_OP[0] 8h'0C STATUS (0000 0000) PWR_ON_ TRIB HF_PWR_ TRIG CHG_IN_ TRIG X X X X X 8h'10 CHGCNTL1 (0000 1001) USBMODE _EN CHGMODE _EN Force EOC TOUT_ doubling EN_Tout En_EOC X EN_CHG 8h'11 CHGCNTL2 (0000 0001) X X X Prog_ ICHG[4] Prog_ ICHG[3] Prog_ ICHG[2] Prog_ ICHG[1] Prog_ ICHG[0] 8h'12 CHGCNTL3 (0001 0010) X X VTERM[1] VTERM[0] Prog_ EOC[1] Prog_ EOC[0] Prog_ VRSTRT[1] Prog_ VRSTRT[0] 8h'13 CHGSTATUS1 Batt_Over_ Out CHGIN_ OK_Out EOC Tout_ Fullrate Tout_ Prechg LDO Mode Fullrate PRECHG 8h'14 CHGSTATUS2 X X X X X X Tout_ ConstV Bad_Batt 8h'19 Audio_Amp X X X X X X X amp_en X APU_TSD_ EN PS_HOLD _DELAY 8h'1C (1) MISC Control1 X X X X X X = Not used Bold type = Bits are read-only type Codes other than those shown in the table are disallowed. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 17 LP3921 SNVS580A - AUGUST 2008 - REVISED MAY 2013 www.ti.com The following table summarizes the supported output voltages for the LP3921. Default voltages after startup are highlighted in bold. Table 4. LDO Output Voltage Programming Data Code LDOx PGM O/P LDO1 (V) 8h'00 1.5 LDO2 (V) VLDO3 (V) LDO4 (V) LDO5 (V) LDO6 (V) 1.5 LDO7 (V) 1.5 8h'01 1.8 1.8 1.8 8h'02 1.85 1.85 1.85 8h'03 2.5 2.5 2.5 2.5 8h'04 2.6 2.6 2.6 2.6 8h'05 2.7 2.7 2.7 2.7 2.7 2.7 2.7 8h'06 2.75 2.75 2.75 2.75 2.75 2.75 2.75 8h'07 2.8 2.8 2.8 2.8 2.8 2.8 2.8 8h'08 2.85 2.85 2.85 2.85 2.85 2.85 2.85 8h'09 2.9 2.9 2.9 2.9 2.9 2.9 2.9 8h'0A 2.95 2.95 2.95 2.95 2.95 2.95 2.95 8h'0B 3.0 3.0 3.0 3.0 3.0 3.0 3.0 8h'0C 3.05 3.05 3.05 3.05 3.05 3.05 3.05 8h'0D 3.1 3.1 3.1 3.1 8h'0E 3.2 3.2 3.2 3.2 8h'0F 3.3 3.3 3.3 3.3 The following table summarizes the supported charging current values for the LP3921. Default charge current after startup is 100 mA. Table 5. Charging Current Programming 18 Prog_Ichg[4] Prog_Ichg[3 Prog_Ichg[2] Prog_Ichg[1] Prog_Ichg[0] I_Charge I mA 0 0 0 0 0 50 0 0 0 0 1 100 (Default) 0 0 0 1 0 150 0 0 0 1 1 200 0 0 1 0 0 250 0 0 1 0 1 300 0 0 1 1 0 350 0 0 1 1 1 400 0 1 0 0 0 450 0 1 0 0 1 500 0 1 0 1 0 550 0 1 0 1 1 600 0 1 1 0 0 650 0 1 1 0 1 700 0 1 1 1 0 750 0 1 1 1 1 800 1 0 0 0 0 850 1 0 0 0 1 900 1 0 0 1 0 950 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 LP3921 www.ti.com SNVS580A - AUGUST 2008 - REVISED MAY 2013 Table 6. Charging Termination Voltage Control VTERM[1] VTERM[0] Termination Voltage (V) 0 0 4.1 0 1 4.2 (Default) 1 0 4.3 1 1 4.4 Table 7. End Of Charge Current Control (1) (1) PROG_EOC[1] PROG_EOC[0] End of Charge Current 0 0 0.1 (Default) 0 1 0.15C 1 0 0.2C 1 1 0.25C Note: C is the set charge current. Table 8. Charging Restart Voltage Programming PROG_VRSTRT[1] PROG_VRSTRT[1] Restart Voltage(V) 0 0 VTERM - 50 mV 0 1 VTERM - 100 mV 1 0 VTERM - 150 mV 1 1 VTERM - 200 mV Table 9. USB Charging Selection USB_Mode_En CHG_Mode_En Mode Current 0 0 Fast Charge Default or Selection 1 0 Fast Charge Default or Selection 0 1 USB 100 mA 1 1 USB 450 mA Battery Charge Management A charge management system allowing the safe charge and maintenance of a Li-Ion battery is implemented on the LP3921. This has a CC/CV linear charge capability with programmable battery regulation voltage and end of charge current threshold. The charge current in the constant current mode is programmable and a maintenance mode monitors for battery voltage drop to restart charging at a preset level. A USB charging mode is also available with 2 charge current levels. CHARGER FUNCTION Following the correct detection of an input voltage at the charger pin the charger enters a pre-charge mode. In this mode a constant current of 50 mA is available to charge the battery to 3.0V. At this voltage level the charge management applies the default (100 mA) full rate constant current to raise the battery voltage to the termination voltage level (default 4.2V). The full rate charge current may be programmed to a different level at this stage. When termination voltage (VTERM) is reached, the charger is in constant voltage mode and a constant voltage of 4.2V is maintained. This mode is complete when the end of charge current (default 0.1C) is detected and the charge management enters the maintenance mode. In maintenance mode the battery voltage is monitored for the restart level (4.05V at the default settings) and the charge cycle is re-initiated to re-establish the termination voltage level. For start up the EOC function is disabled. This function should be enabled once start up is complete and a battery has been detected. EOC is enabled via register CHGCNTL1, Table 10. The full rate constant current rate of charge may be programmed to 19 levels from 50 mA to 950 mA. These values are given in Table 5 and Table 13. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 19 LP3921 SNVS580A - AUGUST 2008 - REVISED MAY 2013 www.ti.com The charge mode may be programmed to USB mode when the charger input is applied and the battery voltage is above 3.0V. This provides two programmable current levels of 100 mA and 450 mA for a USB sourced supply input at CHG_IN. Table 9. EOC EOC is disabled by default and should be enabled when the system processor is awake and the system detects that a battery is present. PROGRAMMING INFORMATION Table 10. Register Address 8h'10: CHGCNTL1 BIT NAME 2 En_EOC FUNCTION Enables the End Of Charge current level threshold detection. When set to '0' the EOC is disabled. The End Of Charge current threshold default setting is at 0.1C. This EOC value is set relative to C the set full rate constant current. This threshold can be set to 0.1C, 0.15C, 0.2C or 0.25C by changing the contents of the PROG_EOC[1:0] register bits. Table 11. Register Address 8h'12: CHGCNTL3 BIT NAME 2 Prog_EOC[0] 3 Prog_EOC[1] FUNCTION Set the End Of Charge Current. See Table 7. TERMINATION AND RESTART The termination and restart voltage levels are determined by the data in the VTERM[1:0] and PROG_VSTRT[1:0] bits in the control register. The restart voltage is programmed relative to the selected termination voltage. The Termination voltages available are 4.1V, 4.2V (default), 4.3V, and 4.4V. The Restart voltages are determined relative to the termination voltage level and may be set to 50 mV, 100 mV, 150 mV (default), and 200 mV below the set termination voltage level. Table 12. Register Address 8h'12: CHGCNTL3 20 BIT NAME 4 VTERM[0] 5 VTERM[1] 0 VRSTR[0] 1 VRSTR[1] FUNCTION Set the charging termination voltage. See Table 6. Set the charging restart voltage. See Table 8. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 LP3921 www.ti.com SNVS580A - AUGUST 2008 - REVISED MAY 2013 CHARGER FULL RATE CURRENT Programming Information Table 13. Register Address 8h'11: CHGCNTL2 Data BITs HEX NAME FUNCTION 000[00000] 00 Prog_ICHG 50 mA 000[00001] 01 100 mA 000[00010] 02 150 mA 000[00011] 03 200 mA 000[00100] 04 250 mA 000[00101] 05 300 mA 000[00110] 06 350 mA 000[00111] 07 400 mA 000[01000] 08 450 mA 000[01001] 09 500 mA 000[01010] 0A 550 mA 000[01011] 0B 600 mA 000[01100] 0C 650 mA 000[01101] 0D 700 mA 000[01110] 0E 750 mA 000[01111] 0F 800 mA 000[10000] 10 850 mA 000[10001] 11 900 mA 000[10010] 12 950 mA Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 21 LP3921 SNVS580A - AUGUST 2008 - REVISED MAY 2013 www.ti.com From any mode: VCHG_IN < 4.5V or VCHG_IN > 6.0V or disabled via serial interface. Charger OFF Zero Current 4.5V < VCHG_IN < 6.0V Yes Pre-Charge mode 50mA Constant current VBATT > 3.0V No Yes Full-Rate Charge mode Constant Current (ICHG) VBATT = VTERM No Yes Full-Rate Charge mode Constant Voltage (VTERM) ICHG < EOC No Yes Maintenance mode Zero current VBATT < VRSTRT No Yes Figure 6. Simplified Charger Functional State Diagram (EOC is enabled) The charger operation may be depicted by the following graphical representation of the voltage and current profiles. 22 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 LP3921 www.ti.com SNVS580A - AUGUST 2008 - REVISED MAY 2013 Prequalification to Fast Charge transition 1.0 C Transition to Constant Voltage-mode Maintenance charging starts VTERM Battery Voltage / Charging Current VRSTRT 3.0V Charging current Charging current EOC 50 mA Time Figure 7. Charge Cycle Diagram Further Charger Register Information CHARGER CONTROL REGISTER 1 Table 14. Register Address 8h'10: CHGCNTL1 BIT NAME FUNCTION (if bit = '1') 7 USB_MODE _EN Sets the Current Level in USB mode. 6 CHG_MODE _EN Forces the charger into USB mode when active high. If low, charger is in normal charge mode. 5 FORCE _EOC Forces an EOC event. 4 TOUT_ Doubling Doubles the timeout delays for all timeout signals. 3 EN_Tout Enables the timeout counters. When set to '0' the timeout counters are disabled. 2 EN_EOC Enables the End of Charge current level threshold detection. When set to '0' the functions are disabled. 1 Set_ LDOmode Forces the charger into LDO mode. 0 EN_CHG Charger enable. Table 15. Register Address 8h'13: CHGSTATUS1 BIT NAME 7 BAT_OVER _OUT FUNCTION (if bit = '1') 6 CHGIN_ OK_Out 5 EOC 4 Tout_ Fullrate 3 Tout_ Precharge Set after timeout for precharge mode. 2 LDO_Mode This bit is disabled in LP3921. Contact NSC sales if this option is required as in LP3918-L. 1 Fullrate Is set when battery voltage exceeds 4.7V. Is set when a valid input voltage is detected at CHG_IN pin. Is set when the charging current decreases below the programmed End Of Charge level. Set after timeout on full rate charge. Set when the charger is in CC/CV mode. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 23 LP3921 SNVS580A - AUGUST 2008 - REVISED MAY 2013 www.ti.com Table 15. Register Address 8h'13: CHGSTATUS1 (continued) BIT NAME 0 PRECHG FUNCTION (if bit = '1') Set during precharge. Charger Status Register 2 Read only Table 16. Register Address 8h'13: CHGSTATUS2 BIT NAME 1 Tout_ConstV FUNCTION (if bit = '1') 0 BAD_BATT Set after timeout in CV phase. Set at bad battery state. IMON CHARGE CURRENT MONITOR Charge current is monitored within the charger section and a proportional voltage representation of the charge current is presented at the IMON output pin. The output voltage relationship to the actual charge current is represented in the following graph and by the equation: VIMON(mV) = (2.47 x ICHG)(mA) IMON VOLTAGE (V) 1.729 1.235 0.247 100 500 700 CHARGE CURRENT (mA) Figure 8. IMON Voltage vs. Charge Current Note that this function is not available if there is no input at CHG_IN or if the charger is off due to the input at CHG_IN being less than the compliance voltage. LDO Information OPERATIONAL INFORMATION The LP3921 has 7 LDO's of which 3 are enabled by default, LDO's 1,2 and 3 are powered up during the power up sequence. LDO's 4, 5 and 6 are separately, externally enabled and will follow LDO2 in start up if their respective enable pin is pulled high. LDO2, LDO3 and LDO7 can be enabled/disabled via the serial interface. LDO2 must remain in regulation otherwise the device will power down. While LDO1 is enabled this must also be in regulation for the device to remain powered. If LDO1 is disabled via I2C interface the device will not shut down. INPUT VOLTAGES There are two input voltage pins used to power the 7 LDO's on the LP3921. VIN2is the supply for LDO3, LDO4, LDO5, LDO6 and LDO7. VIN1is the supply for LDO1 and LDO2. 24 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 LP3921 www.ti.com SNVS580A - AUGUST 2008 - REVISED MAY 2013 PROGRAMMING INFORMATION Enable via Serial Interface Table 17. Register Address 8h'00: OP_EN BIT NAME 0 LDO1_EN 2 LDO3_EN 3 LDO7_EN FUNCTION Bit set to '0' - LDO disabled Bit set to '1' - LDO enabled Note that the default setting for this Register is [0000 0101]. This shows that LDO1 and LDO3 are enabled by default whereas LDO7 is not enabled by default on start up. Table 18. LDO Output Programming (1) Register Add (hex) Name Data Range (hex) 01 LDO1PGM O/P 03 - 0F 1.5V to 3.3V (def. 1.8V) 02 LDO2PGM O/P 00 - 0F 2.5V to 3.3V (def 3.0V) 03 LDO3PGM O/P 05 - 0C 2.7V to 3.05V (def 3.0V) 04 LDO4PGM O/P 00 - 0F 1.5V to 3.3V (def 3.0V) 05 LDO5PGM O/P 05 - 0C 2.7V to 3.05V (def 3.0V) 06 LDO6PGM O/P 05 - 0C 2.7V to 3.05V (def 3.0V) 07 LDO7PGM O/P 00 - 0F 1.5V to 3.3V (def 3.0V) (1) Output Voltage See Table 4 for full programmable range of values. EXTERNAL CAPACITORS The Low Drop Out Linear Voltage regulators on the LP3921 require external capacitors to ensure stable outputs. The LDO's on the LP3921 are specifically designed to use small surface mount ceramic capacitors which require minimum board space. These capacitors must be correctly selected for good performance INPUT CAPACITOR Input capacitors are required for correct operation. It is recommended that a 10 F capacitor be connected between each of the voltage input pins and ground (this capacitance value may be increased without limit). This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean analogue ground. A ceramic capacitor is recommended although a good quality tantalum or film capacitor may be used at the input. WARNING Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a low-impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be guaranteed by the manufacturer to have surge current rating sufficient for the application. There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain within its operational range over the entire operating temperature range and conditions. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 25 LP3921 SNVS580A - AUGUST 2008 - REVISED MAY 2013 www.ti.com OUTPUT CAPACITOR Correct selection of the output capacitor is critical to ensure stable operation in the intended application. The output capacitor must meet all the requirements specified in the recommended capacitor table over all conditions in the application. These conditions include DC-bias, frequency and temperature. Unstable operation will result if the capacitance drops below the minimum specified value. The LP3921 is designed specifically to work with very small ceramic output capacitors. The LDO's on the LP3921 are specifically designed to be used with X7R and X5R type capacitors. With these capacitors selection of the capacitor for the application is dependant on the range of operating conditions and temperature range for that application. (See CAPACITOR CHARACTERISTICS). It is also recommended that the output capacitor be placed within 1 cm from the output pin and returned to a clean ground line. CAPACITOR CHARACTERISTICS The LDO's on the LP3921 are designed to work with ceramic capacitors on the input and output to take advantage of the benefits they offer. For capacitance values around 1 F, ceramic capacitors give the circuit designer the best design options in terms of low cost and minimal area. Generally speaking, input and output capacitors require careful understanding of the capacitor specification to ensure stable and correct device operation. Capacitance value can vary with DC bias conditions as well as temperature and frequency of operation. CAP VALUE (% of NOM. 1 PF) Capacitor values will also show some decrease over time due to aging. The capacitor parameters are also dependant on the particular case size with smaller sizes giving poorer performance figures in general. 0603, 10V, X5R 100% 80% 60% 0402, 6.3V, X5R 40% 20% 0 1.0 2.0 3.0 4.0 5.0 DC BIAS (V) Figure 9. DC Bias (V) As an example, Figure 9 shows a typical graph showing a comparison of capacitor case sizes in a Capacitance vs DC Bias plot. As shown in the graph, as a result of DC Bias condition the capacitance value may drop below minimum capacitance value given in the recommended capacitor table (0.7 F in this case). Note that the graph shows the capacitance out of spec for 0402 case size capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers specifications for the nominal value capacitor are consulted for all conditions as some capacitor sizes (e.g., 0402) may not be suitable in the actual application. Ceramic capacitors have the lowest ESR values, thus making them best for eliminating high frequency noise. The ESR of a typical 1 F ceramic capacitor is in the range of 20 m to 40 m, and also meets the ESR requirements for stability. The temperature performance of ceramic capacitors varies by type. Capacitor type X7R is specified with a tolerance of 15% over temperature range -55C to +125C. The X5R has similar tolerance over the reduced temperature range -55C to +85C. Most large value ceramic capacitors (<2.2 F) are manufactured with Z5U or Y5V temperature characteristics, which results in the capacitance dropping by more than 50% as the temperature goes from 25C to 85C. Therefore X7R is recommended over these other capacitor types in applications where the temperature will change significantly above or below 25C. 26 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 LP3921 www.ti.com SNVS580A - AUGUST 2008 - REVISED MAY 2013 NO-LOAD STABILITY The LDO's on the LP3921 will remain stable in regulation with no external load. Table 19. LDO Output Capacitors Recommended Specification Symbol Parameter Capacitor Type Typ Co(LDO1) Capacitance X5R. X74 Co(LDO2) Capacitance Co(LDO3) Capacitance Co(LDO4) Limit Units Min Max 1.0 0.7 2.2 F X5R. X74 1.0 0.7 2.2 F X5R. X74 1.0 0.7 2.2 F Capacitance X5R. X74 1.0 0.7 2.2 F Co(LDO5) Capacitance X5R. X74 1.0 0.7 2.2 F Co(LDO6) Capacitance X5R. X74 1.0 0.7 2.2 F Co(LDO7) Capacitance X5R. X74 1.0 0.7 2.2 F Note: The capacitor tolerance should be 30% or better over the full temperature range. X7R or X5R capacitors should be used. These specifications are given to ensure that the capacitance remains within these values over all conditions within the application. See CAPACITOR CHARACTERISTICS. Thermal Shutdown The LP3921 has internal limiting for high on-chip temperatures caused by high power dissipation etc. This Thermal Shutdown, TSD, function monitors the temperature with respect to a threshold and results in a device power-down. If the threshold of +160C has been exceeded then the device will power down. Recovery from this TSD event can only be initiated after the chip has cooled below +115C. This device recovery is controlled by the APU_TSD_EN bit (bit 1) in control register MISC, 8h'1C. See Table 21. If the APU_TSD_EN is set low then the device will shutdown requiring a new start up event initiated by PWR_ON, HF_PWR, or CHG_IN. If APU_TSD_EN is set high then the device will power up automatically when the shutdown condition clears. In this case the control register settings are preserved for the device restart. The threshold temperature for the device to clear this TSD event is 115C. This threshold applies for any start up thus the device temperature must be below this threshold to allow a start up event to initiate power up. Further Register Information STATUS REGISTER READ ONLY Table 20. Register Address 8h'0C: Status (1) Bit (1) Name Function (if bit = '1') 7 PWR_ON_TRIG 6 HF-PWR-TRIG PMU startup is initiated by PWR_ON. PMU startup is initiated by PWR_TRIG. 5 CHG_IN_TRIG PMU startup is initiated by CHG_IN. Bits <4...0> are not used. MISC CONTROL REGISTER Table 21. Register Address 8h'1C: Misc. (1) Bit (1) Name Function (if bit = '1') 1 APU_TSD_EN 0 PWR_HOLD_DELAY 1b'0: Device will shut down completely if thermal shutdown occurs. Requires a new startup event to restart the PMU. 1b'1: Device will start up automatically after thermal shutdown condition is removed. (Device tries to keep its internal state.) 1b'0: If PWR_HOLD is low for 35 ms, the device will shutdown. (Default) 1b'1: If PWR_HOLD is low for 350 ms, the device will shut down. Bits <7...2> are not used. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 27 LP3921 SNVS580A - AUGUST 2008 - REVISED MAY 2013 www.ti.com Differential Amplifier Explanation Table 22. Register Address 8h'19 Audio_Amp Bit Name 0 Function (if the powerup default is "amplifier disabled") amp_en Bit set to '0' - amplifier disabled Bit set to '1' - amplifier enabled The LP3921 contains a fully differential audio amplifier that features differential input and output stages. Internally this is accomplished by two circuits: a differential amplifier and a common mode feedback amplifier that adjusts the output voltages so that the average value remains VDD/2. When setting the differential gain, the amplifier can be considered to have "halves". Each half uses an input and feedback resistor (Ri1 and RF1) to set its respective closed-loop gain. (See Figure 10.) With Ri1 = Ri2 and RF1 = RF2, the gain is set at -RF / Ri for each half. This results in a differential gain of: AVD = -RF/Ri (1) It is extremely important to match the input resistors to each other, as well as the feedback resistors to each other for best amplifier performance. A differential amplifier works in a manner where the difference between the two input signals is amplified. In most applications, this would require input signals that are 180 out of phase with each other. The LP3921 can be used, however, as a single ended input amplifier while still retaining its fully differential benefits. In fact, completely unrelated signals may be placed on the input pins. The LP3921 simply amplifies the difference between them. A bridged configuration, such as the one used in the LP3921, also creates a second advantage over single ended amplifiers. Since the differential outputs, Vo1 and Vo2, are biased at half-supply, no net DC voltage exists across the load. This assumes that the input resistor pair and the feedback resistor pair are properly matched. BTL configuration eliminates the output coupling capacitor required in single supply, single-ended amplifier configurations. If an output coupling capacitor is not used in a single-ended output configuration, the half-supply bias across the load would result in both increased internal IC power dissipation as well as permanent loudspeaker damage. Further advantages of bridged mode operation specific to fully differential amplifiers like the LP3921 include increased power supply rejection ratio, common-mode noise reduction, and click and pop reduction. Figure 10. Audio Block 28 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 LP3921 www.ti.com SNVS580A - AUGUST 2008 - REVISED MAY 2013 EXPOSED-DAP PACKAGE MOUNTING CONSIDERATIONS The LP3921's exposed-DAP (die attach paddle) package (WQFN) provides a low thermal resistance between the die and the PCB to which the part is mounted and soldered. this allows rapid heat transfer from the die to the surrounding PCB copper traces, ground plane and, finally, surrounding air. Failing to optimize thermal design may compromise the LP3921's high-power performance and activate unwanted, though necessary, thermal shutdown protection. The WQFN package must have its DAP soldered to a copper pad on the PCB> The DAP's PCB copper pad is connected to a large plane of continuous unbroken copper. This plane forms a thermal mass and heat sink and radiation area. Place the heat sink area on either outside plane in the case of a two-sided PCB, or on an inner layer of a board with more than two layers. Connect the DAP copper pad to the inner layer or backside copper heat sink area with a thermal via. The via diameter should be 0.012 in. to 0.013 in. Ensure efficient thermal conductivity by plating-through and solder-filling the vias. Best thermal performance is achieved with the largest practical copper heat sink area. In all circumstances and conditions, the junction temperature must be held below 150C to prevent activating the LP3921's thermal shutdown protection. Further detailed and specific information concerning PCB layout, fabrication, and mounting an WQFN package is available from TI's package Engineering Group under application note AN1187(SNOA401). PCB LAYOUT AND SUPPLY REGULATION CONSIDERATIONS FOR DRIVING 4 LOADS Power dissipated by a load is a function of the voltage swing across the load and the load's impedance. As load impedance decreases, load dissipation becomes increasingly dependent on the interconnect (PCB trace and wire) resistance between the amplifier output pins and the load's connections. Residual trace resistance causes a voltage drop, which results in power dissipated in the trace and not in the load as desired. This problem of decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load dissipation and widest output voltage swing, PCB traces that connect the output pins to a load must be as wide as possible. Poor power supply regulation adversely affects maximum output power. A poorly regulated supply's output voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output signal clipping, and reduced output power. Even with tightly regulated supplies, trace resistance creates the same effects as poor supply regulation. Therefore, making the power supply traces as wide as possible helps maintain full output voltage swing. POWER DISSIPATION Power dissipation might be a major concern when designing a successful amplifier, whether the amplifier is bridged or single-ended. Equation 2 states the maximum power dissipation point for a single-ended amplifier operating at a given supply voltage and driving a specified output load. PDMAX = (VDD)2 / (22RL) Single-Ended (2) However, a direct consequence of the increased power delivered to the load by a bridge amplifier is an increase in internal power dissipation versus a single-ended amplifier operating at the same conditions. PDMAX = 4 * (VDD)2 / (22RL) Bridge Mode (3) Since the LP3921 has bridged outputs, the maximum internal power dissipation is 4 times that of a single-ended amplifier. Even with this substantial increase in power dissipation, the LP3921 does not require additional heat sinking under most operating conditions and output loading. From Equation 3, assuming a 5V power supply and an 8 load, the maximum power dissipation contribution from the audio amplifier is 625 mW. To this must be added the power dissipated from the power management blocks. The maximum power dissipation thus obtained (PTOT) must not be greater than the power dissipation results from Equation 4: PTOT = PPDMU + PDMAX = (TJMAX - TA) / JA (4) Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 29 LP3921 SNVS580A - AUGUST 2008 - REVISED MAY 2013 www.ti.com PDPMU is mainly the sum of power dissipated in the charger and LDO blocks as shown in Equation 5: PDPMU = ICHG (VCHG_IN - VBATT) + (IOUT1 (VBATT - VOUT1) + (IOUT2 (VBATT - VOUT2) + (IOUT3 (VBATT - VOUT3) + ... (approx.) (5) The LP3921's JA in an RTV0032A package is 30C/W. Depending on the ambient temperature, TA, of the system surroundings, Equation 4 can be used to find the maximum internal power dissipation supported by the IC packaging. POWER SUPPLY BYPASSING As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection ratio (PSRR). The capacitor location on both the bypass and power supply pins should be as close to the device as possible. A larger half-supply bypass capacitor improves PSRR because it increases half-supply stability. Typical applications employ a 5V regulator with 10 F and 0.1 F bypass capacitors that increase supply stability. This, however, does not eliminate the need for bypassing the supply nodes of the LP3921. The LP3921 will operate without the bypass capacitor CB, although the PSRR may decrease. A 1 F capacitor is recommended for CB. This value maximizes PSRR performance. Lesser values may be used, but PSRR decreases at frequencies below 1 kHz. The issue of CB selection is thus dependant upon desired PSRR and click and pop performance as explained in PROPER SELECTION OF EXTERNAL COMPONENTS. SHUTDOWN FUNCTION In order to reduce power consumption while not in use, the audio amplifier can be shut down by setting amp_en to 0 in the Audio_Amp register. On power-up, the audio amplifier is in shut down until enabled. (Contact NSC sales for a different option.) (See Table 22.) Thermal shutdown of the PMU will shut down the audio amplifier. (See Thermal Shutdown for recovery options.) Independent temperature sensing within the audio amplifier may also shut down the audio amplifier alone, without affecting PMU control logic. PROPER SELECTION OF EXTERNAL COMPONENTS Proper selection of external components in applications using integrated power amplifiers is critical when optimizing device and system performance. Although the LP3921 is tolerant to a variety of external component combinations, consideration of component values must be made when maximizing overall system quality. The LP3921 is unity-gain stable, giving the designer maximum system flexibility. The LP3921 should be used in low closed-loop gain configurations to minimize THD+N values and maximize signal to noise ratio. Low gain configurations require large input signals to obtain a given output power. Input signals equal to or greater than 1 Vrms are available from sources such as audio codecs. Please refer to AUDIO POWER AMPLIFIER DESIGN for a more complete explanation of proper gain selection. When used in its typical application as a fully differential power amplifier the LP3921 does not require input coupling capacitors for input sources with DC common-mode voltages of less than VDD. Exact allowable input common-mode voltage levels are actually a function of VDD, Ri, and Rf and may be determined by Equation 5: VCMi < (VDD-1.2)*((Rf+(Ri)/(Rf)-VDD*(Ri / 2Rf) (6) -RF / RI = AVD (7) Special care must be taken to match the values of the feedback resistors (RF1 and RF2) to each other as well as matching the input resistors (Ri1 and Ri2) to each other (see Figure 10) more in front. Because of the balanced nature of differential amplifiers, resistor matching differences can result in net DC currents across the load. This DC current can increase power consumption, internal IC power dissipation, reduce PSRR, and possibly damaging the loudspeaker. Table 23 demonstrates this problem by showing the effects of differing values between the feedback resistors while assuming that the input resistors are perfectly matched. The results below apply to the application circuit shown in Figure 10, and assumes that VDD = 5V, RL = 8, and the system has DC coupled inputs tied to ground. 30 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 LP3921 www.ti.com SNVS580A - AUGUST 2008 - REVISED MAY 2013 Table 23. Feedback Resistor Mis-match Tolerance RF1 RF2 V02 - V01 ILOAD 20% 0.8R 1.2R -0.500V 62.5 mA 10% 0.9R 1.1R -0.250V 31.25 mA 5% 0.95R 1.05R -0.125V 15.63 mA 1% 0.99R 1.01R -0.025V 3.125 mA 0% R R 0 0 Similar results would occur if the input resistors were not carefully matched. Adding input coupling capacitors in between the signal source and the input resistors will eliminate this problem, however, to achieve best performance with minimum component count it is highly recommended that both the feedback and input resistors matched to 1% tolerance or better. AUDIO POWER AMPLIFIER DESIGN Design a 1W/8 Audio Amplifier Given: * Power Output: 1 Wrms * Load Impedance: 8 * Input Level: 1 Vrms * Input Impedance: 20 k * Bandwidth: 100 Hz-20 kHz 0.25 dB A designer must first determine the minimum supply rail to obtain the specified output power. To determine the minimum supply rail is to calculate the required VOPEAK using Equation 8 and add the dropout voltages. (8) Using the Output Power vs. Supply Voltage graph for an 8 load, the minimum supply rail just about 5V. Extra supply voltage creates headroom that allows the LP3921 to reproduce peaks in excess of 1W without producing audible distortion. At this time, the designer must make sure that the power supply choice along with the output impedance does not violate the conditions explained in POWER DISSIPATION. Once the power dissipation equations have been addressed, the required differential gain can be determined from Equation 9. (9) Rf / Ri = AVD (10) From Equation 10, the minimum AVD is 2.83. Since the desired input impedance was 20 k, a ratio of 2.83:1 of Rf to Ri results in an allocation of Ri = 20 k for both input resistors and Rf = 60 k for both feedback resistors. The final design step is to address the bandwidth requirement which must be stated as a single -3 dB frequency point. Five times away from a -3 dB point is 0.17 dB down from pass band response which is better than the required 0.25 dB specified. fH = 20 kHz * 5 = 100 kHz (11) The high frequency pole is determined by the product of the desired frequency pole, fH , and the differential gain, AVD. With AVD = 2.83 and fH = 100 kHz, the resulting GBWP = 150 kHz which is much smaller than the LP3921 GBWP of 10 MHz. This figure displays that if a designer has a need to design an amplifier with a higher differential gain, the LP3921 can still be used without running into bandwidth limitations. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 31 LP3921 SNVS580A - AUGUST 2008 - REVISED MAY 2013 www.ti.com I2C Compatible Serial Bus Interface INTERFACE BUS OVERVIEW The I2C compatible synchronous serial interface provides access to the programmable functions and registers on the device. This protocol uses a two-wire interface for bi-directional communications between the IC's connected to the bus. The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL). These lines should be connected to a positive supply, via a pull-up resistor of 1.5 k, and remain HIGH even when the bus is idle. Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on whether it generates or receives the serial clock (SCL). DATA TRANSACTIONS One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock (SCL). Consequently, throughout the clock's high period, the data should remain stable. Any changes on the SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New data should be sent during the low SCL state. This protocol permits a single data line to transfer both command/control information and data using the synchronous serial clock. SDA SCL Data Line Stable: Data Valid Change of Data Allowed Figure 11. Bit Transfer Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following sections provide further details of this process. START AND STOP The Master device on the bus always generates the Start and Stop Conditions (control codes). After a Start Condition is generated, the bus is considered busy and it retains this status until a certain time after a Stop Condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCL) is high indicates a Start Condition. A low-to-high transition of the SDA line while the SCL is high indicates a Stop Condition. SDA SCL S P START CONDITION STOP CONDITION Figure 12. Start and Stop Conditions In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction. This allows another device to be accessed, or a register read cycle. 32 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 LP3921 www.ti.com SNVS580A - AUGUST 2008 - REVISED MAY 2013 ACKNOWLEDGE CYCLE The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte transferred, and the acknowledge signal sent by the receiving device. The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to receive the next byte. Data Output by Transmitter Transmitter Stays Off the Bus During the Acknowledgement Clock Data Output by Receiver Acknowledgement Signal From Receiver SCL 1 2 3-6 7 8 9 S Start Condition Figure 13. Bus Acknowledge Cycle "ACKNOWLEDGE AFTER EVERY BYTE" RULE The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge signal after every byte received. There is one exception to the "acknowledge after every byte" rule. When the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging ("negative acknowledge") the last byte clocked out of the slave. This "negative acknowledge" still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down. ADDRESSING TRANSFER FORMATS Each device on the bus has a unique slave address. The LP3921 operates as a slave device with the address 7h'7E (binary 1111110). Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device should send an acknowledge signal on the SDA line, once it recognizes its address. The slave address is the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends on the bit sent after the slave address -- the eighth bit. When the slave address is sent, each device in the system compares this slave address with its own. If there is a match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver. CONTROL REGISTER WRITE CYCLE * Master device generates start condition. * Master device sends slave address (7 bits) and the data direction bit (R/W = "0"). * Slave device sends acknowledge signal if the slave address is correct. * Master sends control register address (8 bits). * Slave sends acknowledge signal. * Master sends data byte to be written to the addressed register. * Slave sends acknowledge signal. * If master will send further data bytes the control register address will be incremented by one after acknowledge signal. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 33 LP3921 SNVS580A - AUGUST 2008 - REVISED MAY 2013 * www.ti.com Write cycle ends when the master creates stop condition. CONTROL REGISTER READ CYCLE * Master device generates a start condition. * Master device sends slave address (7 bits) and the data direction bit (R/W = "0"). * Slave device sends acknowledge signal if the slave address is correct. * Master sends control register address (8 bits). * Slave sends acknowledge signal. * Master device generates repeated start condition. * Master sends the slave address (7 bits) and the data direction bit (R/W = "1"). * Slave sends acknowledge signal if the slave address is correct. * Slave sends data byte from addressed register. * If the master device sends acknowledge signal, the control register address will be incremented by one. Slave device sends data byte from addressed register. * Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop condition. Table 24. I2C Read/Write Sequences (1) Address Mode Data Read <Start Condition> <Slave Address><r/w = `0'>[Ack] <Register Addr.>[Ack] <Repeated Start Condition> <Slave Address><r/w = `1'>[Ack] [Register Date]<Ack or nAck> ... additional reads from subsequent register address possible <Stop Condition> Data Write <Start Condition> <Slave Address><r/w = `0'>[Ack] <Register Addr.>[Ack] <Register Data>[Ack] ... additional writes to subsequent register address possible <Stop Condition> (1) < > Data from master [ ] Data from slave REGISTER READ AND WRITE DETAIL S Slave Address (7 bits) '0' A R/W From Slave to Master Control Register Add. (8 bits) Register Data (8 bits) A A P Data transferred, byte + Ack A - ACKNOWLEDGE (SDA Low) S - START CONDITION From Master to Slave P - STOP CONDITION Figure 14. Register Write Format 34 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 LP3921 www.ti.com SNVS580A - AUGUST 2008 - REVISED MAY 2013 S Slave Address (7 bits) '0' A Control Register Add. (8 bits) A Sr Slave Address (7 bits) R/W '1' A R/W Register Data (8 bits) A/ P NA Data transferred, byte + Ack/NAck Direction of the transfer will change at this point A - ACKNOWLEDGE (SDA Low) From Slave to Master NA - ACKNOWLEDGE (SDA High) From Master to Slave S - START CONDITION Sr - REPEATED START CONDITION P - STOP CONDITION Figure 15. Register Read Format Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 35 LP3921 SNVS580A - AUGUST 2008 - REVISED MAY 2013 www.ti.com REVISION HISTORY Changes from Original (May 2013) to Revision A * 36 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 35 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LP3921 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LP3921SQ/NOPB NRND WQFN RTV 32 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 L3921SQ LP3921SQE/NOPB ACTIVE WQFN RTV 32 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 L3921SQ LP3921SQX/NOPB NRND WQFN RTV 32 4500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 L3921SQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LP3921SQ/NOPB WQFN RTV 32 LP3921SQE/NOPB WQFN RTV LP3921SQX/NOPB WQFN RTV SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 32 250 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 32 4500 330.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP3921SQ/NOPB WQFN RTV 32 1000 210.0 185.0 35.0 LP3921SQE/NOPB WQFN RTV 32 250 210.0 185.0 35.0 LP3921SQX/NOPB WQFN RTV 32 4500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE RTV0032A WQFN - 0.8 mm max height SCALE 2.500 PLASTIC QUAD FLATPACK - NO LEAD 5.15 4.85 B A PIN 1 INDEX AREA 5.15 4.85 0.8 0.7 C SEATING PLANE 0.05 0.00 0.08 C 2X 3.5 SYMM EXPOSED THERMAL PAD (0.1) TYP 9 16 8 17 SYMM 33 2X 3.5 3.1 0.1 28X 0.5 1 PIN 1 ID 24 32 25 32X 0.5 0.3 32X 0.30 0.18 0.1 0.05 C A B 4224386/B 04/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT RTV0032A WQFN - 0.8 mm max height PLASTIC QUAD FLATPACK - NO LEAD (3.1) SYMM 32 25 SEE SOLDER MASK DETAIL 32X (0.6) 1 24 32X (0.24) 28X (0.5) (3.1) 33 SYMM (4.8) (1.3) 8 17 (R0.05) TYP ( 0.2) TYP VIA 9 16 (1.3) (4.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND METAL UNDER SOLDER MASK METAL EDGE EXPOSED METAL SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK OPENING SOLDER MASK DEFINED SOLDER MASK DETAILS 4224386/B 04/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com EXAMPLE STENCIL DESIGN RTV0032A WQFN - 0.8 mm max height PLASTIC QUAD FLATPACK - NO LEAD (0.775) TYP 32 25 32X (0.6) 32X (0.24) 1 24 28X (0.5) (0.775) TYP 33 (4.8) SYMM (R0.05) TYP 4X (1.35) 8 17 9 16 4X (1.35) SYMM (4.8) SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL SCALE: 20X EXPOSED PAD 33 76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE 4224386/B 04/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. 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