MOS INTEGRATED CIRCUIT
µ
µµ
µ
PD8880
(10680 ×
××
× 10680) PIXELS ×
××
× 3 COLOR CCD LINEAR IMAGE SENSOR
DATA SHEET
Document No. S16032EJ2V0DS00 (2nd edition)
Date Published September 2002 NS CP (K)
Printed in Japan 2002
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
The mark shows major revised points.
DESCRIPTION
The
µ
PD8880 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to
electrical signal and has the function of color separation.
The
µ
PD8880 has 3 rows of (10680+10680) staggered pixels, and each row has a dual-sided readout type of
charge transfer register. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is
suitable for 2400 dpi/A4 color image scanners, color facsimiles and so on.
FEATURES
• Valid photocell : (10680+10680) pixels × 3
• Photocell pitch : 4
µ
m
• Line spacing : 64
µ
m (16 lines) Red line - Green line, Green line - Blue line
8
µ
m (2 lines) Odd line – Even line (for each color)
• Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 107 lx•hour)
• Resolution : 96 dot/mm A4 (210 × 297 mm) size (shorter side)
: 2400 dpi US letter (8.5” × 11”) size (shorter side)
• Drive clock level : CMOS output under 5 V operation
• Data rate : 8 MHz Max.
• Power supply : +12 V
• On-chip circuits : Reset feed-through level clamp circuits
:: Voltage amplifiers
ORDERING INFORMATION
Part Number Package
µ
PD8880CY CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
Data Sheet S16032EJ2V0DS
2
µ
µµ
µ
PD8880
BLOCK DIAGRAM
19
30
16 20 13
5 4
29
3 2 14
TG1
(Blue)
φ
TG2
(Green)
φ
TG3
(Red)
φ
1L
φ
RB
φ
2
φ
2L
φ
1
φ
2
φ
1
φ
GNDVOD
VOUT1
(Blue)
31
VOUT2
(Green)
32
18
17
15
VOUT3
(Red)
CLB
φ
1
GND
D14
D65
D66
D67
S21359
S21360
S1
S2
···· Photocell
(Blue)
D68
CCD analog shift register
CCD analog shift register
Transfer gate
Transfer gate
D64
D14
S21359
S21360
S1
S2
···· Photocell
(Green)
CCD analog shift register
CCD analog shift register
Transfer gate
Transfer gate
D65
D64
D14
S21359
S21360
S1
S2
···· Photocell
(Red)
CCD analog shift register
CCD analog shift register
Transfer gate
Transfer gate
D66
D67
D68
D65
D64
D66
D67
D68
D69
D69
D69
Data Sheet S16032EJ2V0DS 3
µ
µµ
µ
PD8880
PIN CONFIGURATION (Top View)
CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
•
µ
PD8880CY
1
2
3
4
5
6
7
8
9
10
11
NC
NC
VOUT2
VOUT1
IC
2L
φ
TG1
φ
No connection
No connection
NC No connection
NC No connection
Output signal 2 (Green)
Output signal 1 (Blue)
Output drain voltage
Internal connection
Last stage shift register clock 2
Transfer gate clock 2
(for Green)
VOUT3GND
2
φ
TG3
φ
Output signal 3 (Red)Ground
Reset gate clock
Last stage shift register clock 1
ICInternal connection
ICInternal connection
ICInternal connection
ICInternal connection
Shift register clock 1
21360
21360
21360
Red
Green
Blue
1
1
1
Internal connection
Transfer gate clock 1
(for Blue)
Transfer gate clock 3
(for Red)
VOD
IC
1
φ
2
φ
Shift register clock 2
GND
Ground
RB
φ
Shift register clock 1 1
φ
Reset feed-through level
clamp clock CLB
φ
No connection NC
No connection NC
No connection NC
TG2
φ
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
IC Internal connection
IC Internal connection
1L
φ
Shift register clock 2
Cautions 1. Leave pins 6 , 7, 11, 12, 21, 22, 26, 27 (IC) unconnected.
2. Connect the No connection pins (NC) to GND.
Data Sheet S16032EJ2V0DS
4
µ
µµ
µ
PD8880
PHOTOCELL STRUCTURE DIAGRAM
µ
4 m
µ
m2
µ
m2
Channel stopper
Aluminum
shield
PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing)
Blue photocell array
Blue photocell array
Green photocell array
Green photocell array
4
µ
m2 lines
(8
µ
m)
14 lines
(56
µ
m)
2 lines
(8
µ
m)
4
µ
m
4
µ
m
4
µ
m
4
µ
m
4
µ
m
Red photocell array
Red photocell array
14 lines
(56
µ
m)
16 lines
(64
µ
m)
16 lines
(64
µ
m)
2 lines
(8
µ
m)
4
µ
m
4
µ
m
4
µ
m
Data Sheet S16032EJ2V0DS 5
µ
µµ
µ
PD8880
ABSOLUTE MAXIMUM RATINGS (TA = +
++
+25°
°°
°C)
Parameter Symbol Ratings Unit
Output drain voltage VOD −0.3 to +15 V
Shift register clock voltage V
φ
1, V
φ
2, V
φ
1L, V
φ
2L −0.3 to +8V
Reset gate clock voltage V
φ
RB −0.3 to +8V
Reset feed-through level clamp
clock voltage
V
φ
CLB −0.3 to +8V
Transfer gate clock voltage V
φ
TG1 to V
φ
TG3 −0.3 to +8V
Operating ambient temperatureNote TA0 to +60 °C
Storage temperature Tstg −40 to +70 °C
Note Use at the condition without dew condensation.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (TA = +
++
+25°
°°
°C)
Parameter Symbol Min. Typ. Max. Unit
Output drain voltage VOD 11.4 12.0 12.6 V
Shift register clock high level V
φ
1_H, V
φ
2_H, V
φ
1LH, V
φ
2LH 4.8 5.0 5.5 V
Shift register clock low level V
φ
1_L, V
φ
2_L, V
φ
1LL, V
φ
2LL −0.3 0 +0.2 V
Reset gate clock high level V
φ
RBH 4.5 5.0 5.5 V
Reset gate clock low level V
φ
RBL −0.3 0 +0.5 V
Reset feed-through level clamp clock
high level
V
φ
CLBH 4.5 5.0 5.5 V
Reset feed-through level clamp clock
low level
V
φ
CLBL −0.3 0 +0.5 V
Transfer gate clock high level V
φ
TG1H to V
φ
TG3H 4.8 V
φ
1_H
Note V
φ
1_H
Note V
Transfer gate clock low level V
φ
TG1L to V
φ
TG3L −0.3 0 +0.15 V
CCD Transfer speed f
φ
1, f
φ
2−16MHz
Data rate f
φ
RB −28MHz
Note When Transfer gate clock high level (V
φ
TG1H to V
φ
TG3H) is higher than Shift register clock high level (V
φ
1_H),
Image lag can increase.
Data Sheet S16032EJ2V0DS
6
µ
µµ
µ
PD8880
ELECTRICAL CHARACTERISTICS
TA = +25°C, VOD = 12 V, data rate (f
φ
RB) = 2 MHz, storage time = 11.0 ms, input signal clock = 5 Vp-p,
light source : 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm)
Parameter Symbol Test Conditions Min. Typ. Max. Unit
Saturation voltage 1 Vsat1 Note 1 2.5 3.5 −V
Saturation voltage 2 Vsat2 Note 2 1.5 2.5 −V
Photo response non-uniformity PRNU VOUT = 1.0 V −620%
Average dark signal ADS Light shielding −0.4 4.0 mV
Dark signal non-uniformity DSNU Light shielding −2.0 8.0 mV
Power consumption PW−290 450 mW
Output impedance ZO−0.3 1 kΩ
Red RR2.52 3.60 4.68 V/lx•s
Green RG2.31 3.30 4.29 V/lx•s
Response
Blue RB1.26 1.80 2.34 V/lx•s
Image lag IL VOUT = 1.0 V −1.0 7.0 %
Offset level Note 3 VOS 4.5 6.0 7.5 V
Output fall delay time Note 4 tdVOUT = 1.0 V −25 −ns
Total transfer efficiency TTE VOUT = 1.0 V, f
φ
1, f
φ
2 = 6 MHz 92 98 −%
Register imbalance RI VOUT = 1.0 V −1.0 4.0 %
Red −630 −nm
Green −540 −nm
Response peak
Blue −460 −nm
DR1 Vsat1/DSNU, Note 1 −1750 −timesDynamic range
DR2 Vsat1/
σ
CDS, Note 1 −3500 −times
Reset feed-through noise Note 3 RFTN Light shielding −2000 −500 +500 mV
Random noise (CDS)
σ
CDS Light shielding −1.0 −mV
Notes 1. Vsat1: f
φ
1, f
φ
2 ≤ 4 MHz, f
φ
RB ≤ 8 MHz
2. Vsat2: 4 MHz < (f
φ
1, f
φ
2) < 6 MHz, f
φ
RB ≤ 8 MHz (refer to TIMING CHART 3)
3. Refer to TIMING CHART 2.
4. When the fall time of
φ
1L (t1’) is the Typ. value (refer to TIMING CHART 2).
Data Sheet S16032EJ2V0DS 7
µ
µµ
µ
PD8880
INPUT PIN CAPACITANCE (TA = +
++
+25°
°°
°C, VOD = 12 V)
Parameter Symbol Pin name Pin No. Min. Typ. Max. Unit
Shift register clock pin capacitance 1 C
φ
1
φ
14−1100 −pF
13 −1100 −pF
Shift register clock pin capacitance 2 C
φ
2
φ
25−1100 −pF
20 −1100 −pF
Last stage shift register clock pin capacitance 1 C
φ
1L
φ
1L 14 −70 −pF
Last stage shift register clock pin capacitance 2 C
φ
2L
φ
2L 19 −70 −pF
Reset gate clock pin capacitance C
φ
RB
φ
RB 2 −20 −pF
Reset feed-through level clamp clock pin capacitance C
φ
CLB
φ
CLB 3 −20 −pF
Transfer gate clock pin capacitance
φ
TG1 18 −200 −pF
φ
TG2 17 −200 −pF
C
φ
TG
φ
TG3 15 −200 −pF
Remark Pins 4 and 13 (
φ
1), 5 and 20 (
φ
2) are each connected inside of the device.
Data Sheet S16032EJ2V0DS
8
µ
µµ
µ
PD8880
TIMING CHART 1-1 (Bit clamp mode, for each color)
Note Set the
φ
RB and
φ
CLB to high level during this period.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
61
62
63
64
65
66
21425
21426
21427
21428
21429
21430
V
OUT
1 to V
OUT
3
RB
φ
CLB
φ
1L
φ
(4 pixels)(4 pixels)
(21360 pixels)(48 pixels)
1,
φ
2L
φ
2,
φ
TG1 to
φ
TG3
φ
Note Note
Invalid photocellInvalid photocell
Valid photocellOptical black
Data Sheet S16032EJ2V0DS 9
µ
µµ
µ
PD8880
TIMING CHART 1-2 (Line clamp mode, for each color)
Note Set the
φ
RB to high level during this period.
Remark Inverse pulse of the
φ
TG1 to
φ
TG3 can be used as
φ
CLB.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
61
62
63
64
65
66
21425
21426
21427
21428
21429
21430
VOUT1 to VOUT3
RB
φ
CLB
φ
1L
φ
Note
1,
φ
2L
φ
2,
φ
TG1 to
φ
TG3
φ
TG1 to
φ
TG3)(
φ
Note
Invalid photocell
(4 pixels)
Invalid photocell
(4 pixels)
Valid photocell
(21360 pixels)
Optical black
(48 pixels)
Data Sheet S16032EJ2V0DS
10
µ
µµ
µ
PD8880
TIMING CHART 2-1 (Bit clamp mode, for each color)
90%
10%
90%
10%
φ
VOUT
CLB
φ
RB
φ
2L
φ
1L
φ
2
φ
1
90%
10%
90%
10%
90%
10%
RFTN
VOS
t2
t4
t6
t3
t5
td
10%
90%
10%
t10t11t8
t9
t7
t4
t6
t3
t5
td
t10t11t8
t9
t7
t1’t2’
t1
Symbol Min. Typ. Max. Unit
t1, t2 0 30 −ns
t1’, t2’ 0 5 −ns
t3 20 100 −ns
t4 75 200 −ns
t5, t6 0 10 −ns
t7 30 100 −ns
t8 20 100 −ns
t9, t10 0 10 −ns
t11 5 25 −ns
Data Sheet S16032EJ2V0DS 11
µ
µµ
µ
PD8880
TIMING CHART 2-2 (Line clamp mode, for each color)
“H”
φ
VOUT
CLB
φ
RB
φ
2L
φ
1L
φ
2
φ
1
90%
10%
90%
10%
90%
10%
RFTN
VOS
t2’
t1’
t4
t6
t3
t5
td
10%
t4
t6
t3
t5
td
90%
10%
90%
10%
t1 t2
Symbol Min. Typ. Max. Unit
t1, t2 0 30 −ns
t1’, t2’ 0 5 −ns
t3 20 100 −ns
t4 75 200 −ns
t5, t6 0 10 −ns
TIMING CHART 3 (Sift Register Pulse
φ
φφ
φ
1,
φ
φφ
φ
2 = 6 MHz (Max.))
4.8 V or more
0.2 V or less
30 ns or more
30 ns or more
φ
2
φ
1
Data Sheet S16032EJ2V0DS
12
µ
µµ
µ
PD8880
φ
φφ
φ
TG1 to
φ
φφ
φ
TG3,
φ
φφ
φ
1,
φ
φφ
φ
2 TIMING CHART
RB
φ
CLB
(Bit clamp mode)
φ
2
φ
TG1 to
φ
TG3
φ
CLB
(Line clamp mode)
φ
1
φ
10%
90%
90%
90%
90%
90%
10%
t12
t13
t17
t7
t19t9
t20
t10
t23
t21
t22
Note 1
Note 2
t18
t16t15
t14
Symbol Min. Typ. Max. Unit
t7 30 100 −ns
t9, t10 0 10 −ns
t12 5000 10000 50000 ns
t13, t14 0 50 −ns
t15, t16 900 1000 −ns
t17, t18 200 400 −ns
t19 t12 t12 50000 ns
t20, t21 0 50 −ns
t22, t23 30 350 −ns
Notes 1. Set the
φ
RB and
φ
CLB to high level during this period.
2. Set the
φ
RB to high level during this period.
Remark Inverse pulse of the
φ
TG1 to
φ
TG3 can be used as
φ
CLB.
Data Sheet S16032EJ2V0DS 13
µ
µµ
µ
PD8880
φ
φφ
φ
1,
φ
φφ
φ
2 cross points
1
φ
2
φ
1.5 V to 3.5 V 1.5 V to 3.5 V
φ
φφ
φ
1,
φ
φφ
φ
2L cross points
2L
φ
1
φ
2 V or more 0.5 V or more
φ
φφ
φ
2,
φ
φφ
φ
1L cross points
1L
φ
2
φ
2 V or more 0.5 V or more
Remark Adjust cross points (
φ
1,
φ
2), (
φ
1,
φ
2L) and (
φ
2,
φ
1L) with input resistance of each pin.
Data Sheet S16032EJ2V0DS
14
µ
µµ
µ
PD8880
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage : Vsat
Output signal voltage at which the response linearity is lost.
2. Saturation exposure : SE
Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs.
3. Photo response non-uniformity : PRNU
The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light
of uniform illumination. This is calculated by the following formula.
PRNU (%) =
x =
x
j
: Output voltage of valid pixel number j
x
x : maximum of x
j
− x
x
21360
Σ
j = 1
21360
x
j
× 100
∆
∆
x
Register Dark
DC level
VOUT
x
∆
4. Average dark signal : ADS
Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following
formula.
ADS (mV) =
d
j
: Dark signal of valid pixel number j
21360
Σ
j = 1
21360
d
j
Data Sheet S16032EJ2V0DS 15
µ
µµ
µ
PD8880
5. Dark signal non-uniformity : DSNU
Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the
valid pixels at light shielding. This is calculated by the following formula.
d
j
: Dark signal of valid pixel number j
DSNU (mV) : maximum of d
j
− ADS
j = 1 to 21360
ADS
DSNU
Register Dark
DC level
VOUT
6. Output impedance : ZO
Impedance of the output pins viewed from outside.
7. Response : R
Output voltage divided by exposure (lx•s).
Note that the response varies with a light source (spectral characteristic).
8. Image lag : IL
The rate between the last output voltage and the next one after read out the data of a line.
VOUT
TG
Light
VOUT
ON OFF
V1
φ
IL (%) = V1
VOUT
× 100
Data Sheet S16032EJ2V0DS
16
µ
µµ
µ
PD8880
9. Register Imbalance : RI
The rate of the difference between the averages of the output voltage of Odd and Even bits, against the
average output voltage of all the valid pixels.
RI (%) =
2
n
j = 1
j = 1
n
2
(V
2j –1
–
V
2j
)
1
n
n
V
j
×100
∑
∑
n
V
j
: Number of valid pixels
: Output voltage of each pixel
10. Random noise (CDS) :
σ
σσ
σ
CDS
Random noise
σ
CDS is defined as the standard deviation of a valid pixel output signal with 100 times (=100
lines) data sampling at dark (light shielding).
σ
CDS is calculated by the following procedure.
1. One valid photocell in one reading is fixed as measurement point.
2. The output level is measured during the reset feed-through period which is averaged over 100 ns to get
“VDi”.
3. The output level is measured during the Video Output time averaged over 100 ns to get “VOi”.
4. The correlated double sampling output is defined by VCDSi = VDi – VOi
5. Repeat the above procedure (1 to 4) for 100 times (= 100 lines).
6. Calculate the standard deviation
σ
CDS using the following formula equation.
CDS (mV) = , V =
Σ
i = 1
100
(VCDSi – V)2Σ
i = 1
100
VCDSi
100
100
1
σ
Video Output
Reset feed-through
Data Sheet S16032EJ2V0DS 17
µ
µµ
µ
PD8880
STANDARD CHARACTERISTIC CURVES (Reference Value)
DARK OUTPUT TEMPERATURE
CHARACTERISTIC STORAGE TIME OUTPUT VOLTAGE
CHARACTERISTIC (T
A
= +25°C)
Operating Ambient Temperature TA (°C) Storage Time (ms)
8
4
2
1
0.5
0.25
0.1 100 20304050
Relative Output Voltage
Relative Output Voltage
2
1
0.2
0.11510
400 500 600 700 800
100
80
60
40
20
0
B
B
G
R
G
Response Ratio (%)
Wavelength (nm)
TOTAL SPECTRAL RESPONSE CHARACTERISTICS
(without infrared cut filter and heat absorbing filter ) (T
A
= +25°C)
Data Sheet S16032EJ2V0DS
18
µ
µµ
µ
PD8880
APPLICATION CIRCUIT EXAMPLE
PD8880
µ
100 Ω
4.7 Ω
4.7 Ω
B3
+12 V
µ
0.1 F
µ
47 F/25 V
+
B2
+5 V
µ
0.1 F
µ
10 F/16 V
+
B1
200
Ω
47
Ω
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
4.7
Ω
100
Ω
NC
NC
VOUT2
VOUT1
IC
2L
φ
TG1
φ
NC
NC
VOUT3
GND
1
φ
TG3
φ
IC
IC
IC
IC
VOD
IC
1L
φ
2
φ
GND
RB
φ
CLB
φ
TG
φ
2
φ
1
φ
NC
NC
NC
TG2
φ
IC
IC
2
φ
1
Ω
RB
φ
CLB
φ
µ
0.1 F
µ
10 F/16 V
+5 V
+
1
Ω
2
φ
1
φ
1
φ
1L
φ
1
Ω
1
Ω
2L
φ
Cautions 1. Leave pins 6, 7, 11, 12, 21, 22, 26, 27 (IC) unconnected.
2. Connect the No connection pins (NC) to GND.
Remarks 1. The inverters shown in the above application circuit example are the 74HC04 (f
φ
RB < 2 MHz, (f
φ
1, f
φ
2)
< 1 MHz) or 74AC04 (2 MHz ≤ f
φ
RB ≤ 8 MHz, 1 MHz ≤ (f
φ
1, f
φ
2) ≤ 6 MHz).
2. The input clock register of
φ
RB (2 pin) shown in the above application circuit example are the 200 Ω
(74HC04) or 300 Ω (74AC04).
3. Inverters B1 to B3 in the above application circuit example are shown in the figure blow.
47 F/25 V
B1 to B3 EQUIVALENT CIRCUIT
+
µ
12 V
100 Ω
100 Ω
CCD
VOUT
2SC945
2 kΩ
+
Data Sheet S16032EJ2V0DS 19
µ
µµ
µ
PD8880
PACKAGE DRAWING
55.2±0.5
54.8±0.5
12.6±0.5
9.05±0.3
9.25±0.3
4.1±0.5
1st valid pixel
5.9±0.3 1
32 17
16
1
2.0
46.7
1.02±0.15
2.54±0.25 (5.42)
0.46±0.1
4.21±0.5
4.55±0.5 (1.80)
2.58±0.3
0.25±0.05
10.16±0.20
2
3
10.16+0.7
−0.2
Name Dimensions Refractive index
Plastic cap 52.2×6.4×0.7 1.5
1 1st valid pixel The center of the pin1
2 The surface of the CCD chip The top of the cap
3 The bottom of the package The surface of the CCD chip
32C-1CCD-PKG4-1
(Unit : mm)
CCD LINEAR IMAGE SENSOR 32-PIN PLASTIC DIP (10.16 mm (400) )
PD8880CY
µ
Data Sheet S16032EJ2V0DS
20
µ
µµ
µ
PD8880
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below.
If other soldering processes are used, or if the soldering is performed under different conditions, please make sure
to consult with our sales offices.
Type of Through-hole Device
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PD8880CY : CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
Process Conditions
Partial heating method Pin temperature : 300°C or below, Heat time : 3 seconds or less (per pin)
Cautions 1. During assembly care should be taken to prevent solder or flux from contacting the plastic
cap. The optical characteristics could be degraded by such contact.
2. Soldering by the solder flow method may have deleterious effects on prevention of plastic cap
soiling and heat resistance. So the method cannot be guaranteed.
Data Sheet S16032EJ2V0DS 21
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PD8880
NOTES ON HANDLING THE PACKAGES
CLEANING THE PLASTIC CAP
DUST AND DIRT PROTECTING
MOUNTING OF THE PACKAGE
OPERATE AND STORAGE ENVIRONMENTS
Ethyl Alcohol
Methyl Alcohol
Isopropyl Alcohol
N-methyl Pyrrolidone
EtOH
MeOH
IPA
NMP
The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. Don’t either
touch plastic cap surface by hand or have any object come in contact with plastic cap surface. Should dirt
stick to a plastic cap surface, blow it off with an air blower. For dirt stuck through electricity ionized air is
recommended. And if the plastic cap surface is grease stained, clean with our recommended solvents.
Care should be taken when cleaning the surface to prevent scratches.
We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below.
Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is
recommended that a clean surface or cloth be used.
The following are the recommended solvents for cleaning the CCD plastic cap.
Use of solvents other than these could result in optical or physical degradation in the plastic cap.
Please consult your sales office when considering an alternative solvent.
The application of an excessive load to the package may cause the package to warp or break, or cause chips
to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't
have any object come in contact with plastic cap. You should not reform the lead frame. We recommended to
use a IC-inserter when you assemble to PCB.
Also, be care that the any of the following can cause the package to crack or dust to be generated.
1. Applying heat to the external leads for an extended period of time with soldering iron.
2. Applying repetitive bending stress to the external leads.
3. Rapid cooling or heating
Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject
to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid
storage or usage in such conditions.
Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the
devices are transported from a low-temperature environment to a high-temperature environment. Avoid such
rapid temperature changes.
For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E)
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ELECTROSTATIC BREAKDOWN
CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes
detected. Before handling be sure to take the following protective measures.
1. Ground the tools such as soldering iron, radio cutting pliers of or pincer.
2. Install a conductive mat or on the floor or working table to prevent the generation of static electricity.
3. Either handle bare handed or use non-chargeable gloves, clothes or material.
4. Ionized air is recommended for discharge when handling CCD image sensor.
5. For the shipment of mounted substrates, use box treated for prevention of static charges.
6. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on
which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle
straps which are grounded via a series resistance connection of about 1 MΩ.
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RECOMMENDED SOLVENTS
Solvents Symbol
Data Sheet S16032EJ2V0DS
22
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PD8880
[MEMO]
Data Sheet S16032EJ2V0DS 23
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PD8880
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
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PD8880
M8E 00. 4
The information in this document is current as of September, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
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The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
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(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
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NEC (as defined above).
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