LNK603-606/613-616
LinkSwitch-II Family
www.powerint.com July 2009
Energy-Ef cient, Accurate CV/CC Switcher
for Adapters and Chargers
®
Output Power Table
Product385-265 VAC
Adapter1Open Frame2
LNK603/613PG/DG 2.5 W 3.3 W
LNK604/614PG/DG 3.5 W 4.1 W
LNK605/615PG/DG 4.5 W 5.1 W
LNK606/616PG/GG 5.5 W 6.1 W
Table 1. Output Power Table.
Notes:
1. Minimum continuous power in a typical non-ventilated enclosed adapter
measured at +50 °C ambient, device, TJ <100 °C.
2. Maximum practical continuous power in an open frame design with adequate
heatsinking, measured at 50 °C ambient (see Key Applications Considerations
section for more information).
3. Packages: P: DIP-8C, G: SMD-8C, D: SO-8C.
Product Highlights
Dramatically Simplifi es CV/CC Converters
Eliminates Optocoupler and all secondary CV/CC control
circuitry
Eliminates all control loop compensation circuitry
Advanced Performance Features
Compensates for transformer inductance tolerances
Compensates for input line voltage variations
Compensates for cable voltage drop (LNK61X series)
Compensates for external component temperature variations
Very tight IC parameter tolerances using proprietary trimming
technology
Frequency jittering greatly reduces EMI fi lter cost
Even tighter output tolerances achievable with external resistor
selection/trimming
Advanced Protection/Safety Features
Auto-restart protection reduces power delivered by >95% for
output short circuit and control loop faults (open and shorted
components)
Hysteretic thermal shutdown – automatic recovery reduces
power supply returns from the fi eld
Meets HV creepage requirements between Drain and all other
pins both on the PCB and at the package
EcoSmart® – Energy Effi cient
Easily meets all global energy effi ciency regulations
No-load consumption <200 mW at 230 VAC and down to
below 30 mW with optional external bias
On/Off control provides constant effi ciency down to very light
loads – ideal for CEC and ENERGY STAR 2.0 regulations
No current sense resistors – maximizes effi ciency
Green Package
Halogen free and RoHS compliant package
Applications
Chargers for cell/cordless phones, PDAs, MP3/portable audio
devices, adapters, LED drivers, etc.
Description
The LinkSwitch-II dramatically simplifi es low power CV/CC
charger designs by eliminating an optocoupler and secondary
control circuitry. The device introduces a revolutionary control
technique to provide very tight output voltage and current
regulation, compensating for transformer and internal parameter
tolerances along with input voltage variations.
The device incorporates a 700 V power MOSFET, a novel On/Off
control state machine, a high voltage switched current source for
self biasing, frequency jittering, cycle-by-cycle current limit and
hysteretic thermal shutdown circuitry onto a monolithic IC.
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•
•
•
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•
•
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Figure 1. Typical Application/Performance – Not a Simplifi ed Circuit (a) and
Output Characteristic Envelope (b). (see Application Section for
more information).
LinkSwitch-II
Wide Range
HV DC Input
PI-4960-060608
D
S
FB
BP/M
IO
VO±5%
±10%
PI-4906-041008
(a) Typical Application Schematic
(b) Output Characteristic
Rev. E 07/09
2
LNK603-606/613-616
www.powerint.com
Pin Functional Description
Drain (D) Pin:
This pin is the power MOSFET drain connection. It provides
internal operating current for both start-up and steady-state
operation.
Bypass/Multi-Functional Programmable (BP/M) Pin:
This pin has multiple functions:
It is the connection point for an external bypass capacitor for
the internally generated 6 V supply.
It is a mode selection for the cable drop compensation for
LNK61X series.
Feedback (FB) Pin:
During normal operation, switching of the power MOSFET is
controlled by this pin. This pin senses the AC voltage on the bias
winding. This control input regulates both the output voltage in
CV mode and output current in CC mode based on the fl yback
voltage of the bias winding. The internal inductance correction
circuit uses the forward voltage on the bias winding to sense the
bulk capacitor voltage.
Source (S) Pin:
This pin is internally connected to the output MOSFET source for
high voltage power and control circuit common returns.
1.
2.
Figure 2 Functional Block Diagram.
Figure 3. Pin Confi guration.
PI-4908-041508
SOURCE
(S)
LEADING
EDGE
BLANKING
+
-
+
-
+
-
DRAIN
(D)
REGULATOR
6 V
BYPASS
(BP/M)
FEEDBACK
(FB)
SOURCE
(S)
FB
OUT Reset
6 V
5 V
tSAMPLE-OUT
tSAMPLE-INPUT
VILIMIT
ILIM
VILIMIT
VTH
tSAMPLE-OUT
tSAMPLE-INPUT
VILIMIT
6.5 V
Drive
ILIM
DCMAX
DCMAX
FB
Current Limit
Comparator
STATE
MACHINE
CABLE DROP
COMPENSATION
SAMPLE
DELAY
THERMAL
SHUTDOWN
OSCILLATOR
FAULT
Auto-Restart
Open-Loop
INDUCTANCE
CORRECTION
CONSTANT
CURRENT
DQ
PI-3491-012808
3a 3b
DS
BP/M S
S
FB
P Package (DIP-8C)
G Package (SMD-8C) D Package (SO-8C)
8
5
7
1
4
2
S
6
DS
BP/M S
S
FB 8
5
7
1
4
2
S
6
Rev. E 07/09
3
LNK603-606/613-616
www.powerint.com
LinkSwitch-II Functional Description
The LinkSwitch-II combines a high voltage power MOSFET
switch with a power supply controller in one device. Similar to
the LinkSwitch-LP and TinySwitch-III it uses ON/OFF control to
regulate the output voltage. In addition, the switching frequency
is modulated to regulate the output current to provide a
constant current characteristic. The LinkSwitch-II controller
consists of an oscillator, feedback (sense and logic) circuit, 6 V
regulator, over-temperature protection, frequency jittering,
current limit circuit, leading-edge blanking, inductance
correction circuitry, frequency control for constant current
regulation and on/off state machine for CV control.
Inductance Correction Circuitry
If the primary magnetizing inductance is either too high or low
the converter will automatically compensate for this by adjusting
the oscillator frequency. Since this controller is designed to
operate in discontinuous-conduction mode the output power is
directly proportional to the set primary inductance and its
tolerance can be completely compensated with adjustments to
the switching frequency.
Constant Current (CC) Operation
As the output voltage and therefore the fl yback voltage across
the bias winding increases, the feedback pin voltage increases.
The switching frequency is adjusted as the feedback pin voltage
increases to provide a constant output current regulation. The
constant current circuit and the inductance correction circuit
are designed to operate concurrently in the CC region.
Constant Voltage (CV) Operation
As the feedback pin approaches VFBth from the constant current
regulation mode, the power supply transitions into CV
operation. The switching frequency at this point is at its
maximum value, corresponding to the peak power point of the
CCCV characteristic. The controller regulates the feedback pin
voltage to remain at VFBth using an on/off state-machine. The
feedback pin voltage is sampled 2.5 μs after the turn-off of the
high voltage switch. At light loads the current limit is also
reduced to decrease the transformer fl ux density.
Output Cable Compensation
This compensation provides a constant output voltage at the
end of the cable over the entire load range in CV mode. As the
converter load increases from no-load to the peak power point
(transition point between CV and CC) the voltage drop
introduced across the output cable is compensated by
increasing the feedback pin reference voltage. The controller
determines the output load and therefore the correct degree of
compensation based on the output of the state machine. Cable
drop compensation for a 24 AWG (0.3 Ω) cable is selected with
CBP = 1 μF and for a 26 AWG (0.49 Ω) cable with CPB = 10 μF.
Auto-Restart and Open-Loop Protection
In the event of a fault condition such as an output short or an
open loop condition the LinkSwitch-II enters into an appropriate
protection mode as described below.
In the event the feedback pin voltage during the fl yback period
falls below 0.7 V before the feedback pin sampling delay (~2.5 μs)
for a duration in excess of ~450 ms (auto-restart on-time (tAR-ON)
the converter enters into Auto-restart, wherein the power
MOSFET is disabled for 2 seconds (~18% Auto-Restart duty
cycle). The auto-restart alternately enables and disables the
switching of the power MOSFET until the fault condition is
removed.
In addition to the conditions for auto-restart described above, if
the sensed feedback pin current during the Forward period of
the conduction cycle (switch “on” time) falls below 120 μA, the
converter annunciates this as an open-loop condition (top
resistor in potential divider is open or missing) and reduces the
Auto-restart time from 450 msec to approximately 6 clock cycles
(90 μs), whilst keeping the disable period of 2 seconds.
Over-Temperature Protection
The thermal shutdown circuitry senses the die temperature. The
threshold is set at 142 °C typical with a 60 °C hysteresis. When
the die temperature rises above this threshold (142 °C) the
power MOSFET is disabled and remains disabled until the die
temperature falls by 60 °C, at which point the MOSFET is
re-enabled.
Current Limit
The current limit circuit senses the current in the power
MOSFET. When this current exceeds the internal threshold
(ILIMIT), the power MOSFET is turned off for the remainder of that
cycle. The leading edge blanking circuit inhibits the current limit
comparator for a short time (tLEB) after the power MOSFET is
turned on. This leading edge blanking time has been set so that
current spikes caused by capacitance and rectifi er reverse
recovery time will not cause premature termination of the MOSFET
conduction. The LinkSwitch-II also contains a “di/dt” correction
feature to minimize CC variation across the input line range.
6.0 V Regulator
The 6 V regulator charges the bypass capacitor connected to
the BYPASS pin to 6 V by drawing a current from the voltage on
the DRAIN, whenever the MOSFET is off. The BYPASS pin is
the internal supply voltage node. When the MOSFET is on, the
device runs off of the energy stored in the bypass capacitor.
Extremely low power consumption of the internal circuitry
allows the LinkSwitch-II to operate continuously from the
current drawn from the DRAIN pin. A bypass capacitor value of
either 1 μF or 10 μF is suffi cient for both high frequency
decoupling and energy storage.
Rev. E 07/09
4
LNK603-606/613-616
www.powerint.com
Applications Example
Circuit Description
This circuit shown in Figure 4 is confi gured as a primary-side
regulated fl yback power supply utilizing the LNK613DG. With
an average effi ciency of 74% and <40 mW no-load input power
this design easily exceeds the most stringent current energy
effi ciency requirements.
Input Filter
AC input power is rectifi ed by diodes D1 through D4. The
rectifi ed DC is fi ltered by the bulk storage capacitors C1 and
C2. Inductor L1, C1 and C2 form a pi (π) fi lter, which attenuates
conducted differential-mode EMI noise. This confi guration
along with Power Integrations transformer E-shield™ technology
allow this design to meet EMI standard EN55022 class B with
good margin without requiring a Y capacitor, even with the
output connected to safety earth ground. Fusible resistor RF1
provides protection against catastrophic failure. This should be
suitably rated (typically a wire wound type) to withstand the
instantaneous dissipation while the input capacitors charge
when fi rst connected to the AC line.
LNK 613 Primary
The LNK613DG device (U1) incorporates the power switching
device, oscillator, CC/CV control engine, startup, and protection
functions. The integrated 700 V MOSFET provides a large drain
voltage margin in universal input AC applications, increasing
reliability and also reducing the output diode voltage stress by
allowing a greater transformer turns ratio. The device is
completely self-powered from the BYPASS pin and decoupling
capacitor C4. For the LNK61X devices, the bypass capacitor
value also selects the amount of output cable voltage drop
compensation. A 1 μF value selects the standard compensation.
A 10 μF value selects the enhanced compensation. Table 2
shows the amount of compensation for each device and
bypass capacitor value. The LNK60x devices do not provide
cable drop compensation.
The optional bias supply formed by D6 and C5 provides the
operating current for U1 via resistor R4. This reduces the no-
load consumption from ~200 mW to <40 mW and also
increases light load effi ciency.
The rectifi ed and fi ltered input voltage is applied to one side of
the primary winding of T1. The other side of the transformer’s
primary winding is driven by the integrated MOSFET in U1. The
leakage inductance drain voltage spike is limited by an RCD-R
clamp consisting of D5, R2, R3, and C3.
Output Rectifi cation
The secondary of the transformer is rectifi ed by D7, a 1 A, 40 V
Schottky barrier type for higher effi ciency, and fi ltered by C7. If
lower effi ciency is acceptable then this can be replaced with a
1 A PN junction diode for lower cost. In this application C7 was
sized to meet the required output voltage ripple specifi cation
without requiring a post LC fi lter. To meet battery self discharge
requirement the pre-load resistor has been replaced with a
series resistor and Zener network (R8 and VR1). However in
designs where this is not a requirement a standard 1 kΩ
resistor can be used.
Output Regulation
The LNK613 regulates the output using ON/OFF control in the
constant voltage (CV) regulation region of the output character-
Figure 4. Energy Effi cient USB Charger Power Supply (74% Average Effi ciency, <40 mW No-load Input Power).
PI-5111-050808
D
S
FB
BP
R2
470 k7
R3
300 7
R5
13 k7
1%
R7
200 7
R8
200 7
R6
8.87 k7
1%
R4
6.2 k7
RF1
8.2 7
2 W
D5
1N4007
D7
SS14
D6
LL4148
VR1
2MM5230B-7
4.7 V
D1
1N4007
D2
1N4007
D3
1N4007
D4
1N4007
T1
EE16
510
8
1
2
4
NC
3
C7
680 MF
10 V
C6
1 nF
100 V
C1
4.7 MF
400 V
C2
4.7 MF
400 V
C4
1MF
25 V
C5
10 MF
16 V
L1
1.5 mH
C3
820 pF
1 kV
DC
Output
5 V, 555 m
A
U1
LNK613DG
LinkSwitch-II
AC
Input
Rev. E 07/09
5
LNK603-606/613-616
www.powerint.com
istic and frequency control for constant current (CC) regulation.
The feedback resistors (R5 and R6) were selected using
standard 1% resistor values to center both the nominal output
voltage and constant current regulation thresholds.
Key Application Considerations
Output Power Table
The data sheet maximum output power table (Table 1) repre-
sents the maximum practical continuous output power level
that can be obtained under the following assumed conditions:
The minimum DC input voltage is 90 V or higher at 85 VAC
input. The value of the input capacitance should be large
enough to meet these criteria for AC input designs.
Secondary output of 5 V with a Schottky rectifi er diode.
Assumed effi ciency of 70%.
Discontinuous mode operation (KP >1.3).
The part is board mounted with SOURCE pins soldered to a
suffi cient area of copper to keep the SOURCE pin tempera-
ture at or below 90 °C.
Ambient temperature of 50 °C for open frame designs and
an internal enclosure temperature of 60 °C for adapter
designs.
Note: Higher output power are achievable if an output CC
tolerance >±10% is acceptable, allowing the device to be
operated at a higher SOURCE pin temperature.
Output Tolerance
LinkSwitch-II provides an overall output tolerance (including line,
component variation and temperature) of ±5% for the output
voltage in CV operation and ±10% for the output current during
CC operation over a junction temperature range of 0 °C to 100 °C
for the P/G package. For the D package (SO8) additional CC
variance may occur due to stress caused by the manufacturing
fl ow (i.e. solder-wave immersion or IR refl ow). A sample power
supply build is recommended to verify production tolerances for
each design.
Bypass Pin Capacitor Selection
For LinkSwitch-II 60x Family of Devices (without output
cable voltage drop compensation)
A 1 μF BYPASS pin capacitor is recommended. The capacitor
voltage rating should be greater than 7 V. The capacitor’s
dielectric material is not important but tolerance of capacitor
should be ≤ ±50%. The capacitor must be physically located
close to the LinkSwitch-II BYPASS pin.
For LinkSwitch-II 61x Family of Devices (with output cable
voltage drop compensation)
The amount of output cable compensation can be selected with
the value of the Bypass pin capacitor. A value of 1 μF selects
the standard cable compensation. A 10 μF capacitor selects
the enhanced cable compensation. Table 2 shows the amount
of compensation for each LinkSwitch-II device and capacitor
value. The capacitor can be either ceramic or electrolytic but
tolerance and temperature variation should be ≤ ±50%.
1.
2.
3.
4.
5.
6.
The output voltage that is entered into PIXls design spreadsheet
is the voltage at the end of the output cable when the power
supply is delivering maximum power. The output voltage at the
terminals of the supply is the value measured at the end of the
cable multiplied by the output voltage change factor.
LinkSwitch-II Layout Considerations
Circuit Board Layout
LinkSwitch-II is a highly integrated power supply solution that
integrates on a single die, both, the controller and the high
voltage MOSFET. The presence of high switching currents and
voltages together with analog signals makes it especially
important to follow good PCB design practice to ensure stable
and trouble free operation of the power supply. See Figure 5 for
a recommended circuit board layout for LinkSwitch-II.
When designing a printed circuit board for the LinkSwitch-II
based power supply, it is important to follow the following
guidelines:
Single Point Grounding
Use a single point (Kelvin) connection at the negative terminal of
the input fi lter capacitor for the LinkSwitch-II SOURCE pin and
bias winding return. This improves surge capabilities by
returning surge currents from the bias winding directly to the
input fi lter capacitor.
Bypass Capacitor
The BYPASS pin capacitor should be located as close as
possible to the SOURCE and BYPASS pins.
Feedback Resistors
Place the feedback resistors directly at the FEEDBACK pin of
the LinkSwitch-II device. This minimizes noise coupling.
Thermal Considerations
The copper area connected to the source pins provides the
LinkSwitch-II heat sink. A good estimate is that the LinkSwitch-II
will dissipate 10% of the output power. Provide enough copper
area to keep the source pin temperature below 90 °C. Higher
temperatures are allowable only if an output current (CC)
tolerance above ±10% is acceptable. In this case a maximum
source pin temperature below 110 °C is recommended to
provide margin for part to part RDS(ON) variation.
LinkSwitch-II Output Cable Voltage Drop Compensation
Device Bypass Pin
Capacitor Value
Output Voltage
Change Factor
LNK613 1 μF1.035
10 μF1.055
LNK614 1 μF1.045
10 μF1.065
LNK615 1 μF1.050
10 μF1.070
LNK616 1 μF1.060
10 μF1.090
Table 2. Cable Compensation Change Factor vs Device and BYPASS Pin
Capacitor Value.
Rev. E 07/09
6
LNK603-606/613-616
www.powerint.com
Secondary Loop Area
To minimize leakage inductance and EMI the area of the loop
connecting the secondary winding, the output diode and the
output fi lter capacitor should be minimized. In addition,
suffi cient copper area should be provided at the anode and
cathode terminal of the diode for heatsinking. A larger area is
preferred at the quiet cathode terminal. A large anode area can
increase high frequency radiated EMI.
Electrostatic Discharge Spark Gap
An trace is placed along the isolation barrier to form one
electrode of a spark gap. The other electrode on the secondary
is formed by the output return node. The spark gap directs
ESD energy from the secondary back to the AC input. The
trace from the AC input to the spark gap electrode should be
spaced away from other traces to prevent unwanted arcing
occurring and possible circuit damage.
Drain Clamp Optimization
LinkSwitch-II senses the feedback winding on the primary side
to regulate the output. The voltage that appears on the feed-
back winding is a refl ection of the secondary winding voltage
while the internal MOSFET is off. Therefore any leakage
inductance induced ringing can affect output regulation.
Optimizing the drain clamp to minimize the high frequency
ringing will give the best regulation. Figure 6 shows the desired
drain voltage waveform compared to Figure 7 with a large
undershoot due to the leakage inductance induced ring. This
will reduce the output voltage regulation performance. To
Figure 5. PCB Layout Example Showing 5.1 W Design using P Package.
reduce this adjust the value of the resistor in series with the
clamp diode.
Addition of a bias circuit for higher light load effi ciency
and lower no load input power consumption.
The addition of a bias circuit can decrease the no load input
power from ~200 mW down to less than 30 mW at 230 VAC
input. Light load effi ciency also increases which may avoid the
need to use a Schottky barrier vs PN junction output diode
while still meeting average effi ciency requirements.
The power supply schematic shown in Figure 4 has the bias
circuit incorporated. Diode D6, C5 and R4 form the bias circuit.
As the output voltage is less than 8 V, an additional transformer
winding is needed, AC stacked on top of the feedback winding.
This provides a high enough voltage to supply the BYPASS pin
even during low switching frequency operation at no-load.
In Figure 4 the additional bias winding (from pin 2 to pin 1) is
stacked on top of the feedback winding (pin 4 to pin 2). Diode
D6 rectifi es the output and C5 is the fi lter capacitor. A 10 uF
capacitor is recommended to hold up the bias voltage at low
switching frequencies. The capacitor type is not critical but the
voltage rating should be above the maximum value of VBIAS.
The recommended current into the BP pin is equal to IC supply
current (~0.5 mA). The value of R4 is calculated according to
(VBIAS – VBP)/IS2, where VBIAS (10 V typ.) is the voltage across C5,
IS2 (0.5 mA typ.) is the IC supply current and VBP (6.2 V typ.) is
DC
Output
PI-5110-050508
R5
C4
C5
C3
R4
D5
D3
R3
R1
C2
R1
C1
R6
R2
L2
D4
D2
D1
U1
D3
RF1
D7
T1 R8 C6
C7
C8
R9
Output Filter
Capacitors
Input Stage Primary Clamp Output
Diode Snubber
Preload
Resistor
Spark
Gap
Bypass
Capacitor
Feedback
Resistors
Bypass Supply
Components
AC
Input
SSSS
BP D
FB
LinkSwitch-II
Rev. E 07/09
7
LNK603-606/613-616
www.powerint.com
PI-5093-041408
An overshoot
is acceptable
PI-5094-042408
Negative ring may
increase output
ripple and/or
degrade output
regulation
Figure 6. Desired Drain Voltage Waveform with Minimal Leakage
Ringing Undershoot.
Figure 7. Undesirable Drain Voltage Waveform with Large Leakage
Ring Undershoot.
the BP pin voltage. The parameters IS2 and VBP are provided in
the parameter table of the LinkSwitch-II data sheet. Diode D6
can be any low cost diode such as FR102, 1N4148 or
BAV19/20/21.
Quick Design Checklist
As with any power supply design, all LinkSwitch-II designs
should be verifi ed on the bench to make sure that component
specifi cations are not exceeded under worst-case conditions.
The following minimum set of tests is strongly recommended:
Maximum drain voltage – Verify that peak VDS does not exceed
680 V at the highest input voltage and maximum output power.
Maximum drain current – At maximum ambient temperature,
maximum input voltage and maximum output load, verify
drain current waveforms at start-up for any signs of trans-
1.
2.
PI-5116-050808
D
S
FB
BP
R2
470 k7
1 k7
R3
300 7
R5
13 k7
1%
R6
9.31 k7
1%
D5
1N4007
D7
SL13
TI
EE13
510
8
2
4
NC
3
C7
470 MF
10 V
C1
4.7 MF
400 V
C2
4.7 MF
400 V
C4
1MF
50 V
L1
1 mH
C3
820 pF
1 kV
AC
Input
DC
Outpu
t
U1
LNK613DG
LinkSwitch-II
RF1
8.2 7
2 W
D1
1N4007
D2
1N4007
D3
1N4007
D4
1N4007
former saturation and excessive leading edge current spikes.
LinkSwitch-II has a leading edge blanking time of 170 ns to
prevent premature termination of the ON-cycle.
Thermal check – At maximum output power, both minimum
and maximum input voltage and maximum ambient tempera-
ture; verify that temperature specifi cations are not exceeded
for LinkSwitch-II, transformer, output diodes and output
capacitors. Enough thermal margin should be allowed for
part-to-part variation of the RDS(ON) of LinkSwitch-II, as
specifi ed in the data sheet. To assure 10% CC tolerance a
maximum source pin temperature of 90 ºC is recommended.
Design Tools
Up-to-date information on design tools can be found at the
Power Integrations web site: www.powerint.com
3.
Figure 8. LinkSwitch-II Flyback Power Supply Without Bias Supply.
Rev. E 07/09
8
LNK603-606/613-616
www.powerint.com
Parameter Symbol
Conditions
SOURCE = 0 V; TJ = 0 to 100 °C
(Unless Otherwise Specifi ed)
Min Typ Max Units
Control Functions
Output Frequency fOSC
TJ = 25 °C, VFB = VFBth
tON × IFB = 2 mA-μs
LNK603/6 59 66 73 kHz
LNK613/6 58 65 72
Frequency Ratio
(Constant Current) fRATIO(CC)
TJ = 25 °C
Between VFB = 1.0 V and VFB = 1.6 V 1.59 1.635 1.68
Frequency Ratio
(Inductance Correction) fRATIO(IC)
Between tON × IFB = 1.6 mA × μs
and tON × IFB = 2 mA × μs 1.160 1.215 1.265
Frequency Jitter Peak-Peak Jitter Compared to
Average Frequency, TJ = 25 °C ±7 %
Ratio of Output
Frequency at Auto-RST fOSC(AR)
TJ = 25 °C
Relative to fOSC
12 16.5 21 %
Maximum Duty Cycle DCMAX (Note 4,5) 55 %
Feedback Pin Voltage VFBth
TJ = 25 °C
See Figure 19,
CBP = 10 μF
LNK603/604P 1.815 1.840 1.865
V
LNK603/604D 1.855 1.880 1.905
LNK605P, LNK605D 1.835 1.860 1.885
LNK606P, LNK606G 1.775 1.800 1.825
LNK613/614P 1.935 1.960 1.985
LNK613/614/615D 1.975 2.000 2.025
LNK615P 1.975 2.000 2.025
LNK616G, LNK616P 1.935 1.960 1.985
Feedback Pin Voltage
Temperature
Coeffi cient
TCVFB -0.01 %/°C
Feedback Pin Voltage
at Turn-Off Threshold VFB(AR) 0.65 0.72 0.79 V
Cable Compensation
Factor υFB
LNK613
See Figure 19
CBP = 1 μF1.035
CBP = 10 μF1.055
LNK614
See Figure 19
CBP = 1 μF1.045
CBP = 10 μF1.065
Absolute Maximum Ratings(1,4)
DRAIN Voltage .........................................................-0.3 V to 700 V
DRAIN Peak Current: LNK603/613 .................. 320 (480) mA(4)
LNK604/614 .................. 400 (600) mA(4)
LNK605/615 .................. 504 (750) mA(4)
LNK606/616 .................. 654 (980) mA(4)
Peak Negative Pulsed Drain Current ................... ......... -100 mA(2)
Feedback Voltage ................................................. ....... -0.3 V to 9 V
Feedback Current ................................................. ............. 100 mA
BYPASS Pin Voltage ..................................... ............. -0.3 V to 9 V
Storage Temperature ...................................... .... -65 °C to 150 °C
Operating Junction Temperature.........................-40 °C to 150 °C
Lead Temperature(3) .................................................................260 °C
Notes:
1. All voltages referenced to SOURCE, TA = 25 °C.
2. Duration not to exceed 2 msec.
3. 1/16 in. from case for 5 seconds.
4. The higher peak DRAIN current is allowed while the DRAIN
voltage is simultaneously less than 400 V.
5. Maximum ratings specifi ed may be applied, one at a time
without causing permanent damage to the product.
Exposure to Absolute Maximum ratings for extended
periods of time may affect product reliability.
Thermal Impedance
Thermal Impedance: P or G Package:
(θJA) .......................... .........70 °C/W(2); 60 °C/W(3)
(θJC)(1) ............................................... ......... 11 °C/W
D Package:
(θJA .....................................100 °C/W(2); 80 °C/W(3)
(θJC)(1) .......................... ...........................30 °C/W
Notes:
1. Measured on pin 8 (SOURCE) close to plastic interface.
2. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad.
3. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad.
Rev. E 07/09
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Parameter Symbol
Conditions
SOURCE = 0 V; TJ = 0 to 100 °C
(Unless Otherwise Specifi ed)
Min Typ Max Units
Control Functions (cont.)
Cable Compensation
Factor υFB
LNK615
See Figure 19
CBP = 1 μF1.05
CBP = 10 μF1.07
LNK616
See Figure 19
CBP = 1 μF1.06
CBP = 10 μF1.09
Switch “ON-Time” tON
fOSC = 66 kHz
VFB = VFBth
(Note 5)
IFB = -500 μA4
μs
IFB = -1 mA 2
IFB = -1.5 mA 1.33
IFB = -2 mA 1
Minimum Switch
“On”-Time tON(min) (Note 5) 700 ns
Feedback Pin
Sampling Delay tFB See Figure 19 2.35 2.55 2.75 μs
DRAIN Supply
Current
IS1 FB Voltage > VFBth 280 330
μA
IS2
FB Voltage = VFBth -0.1,
Switch ON-Time = tON
(MOSFET Switching at fOSC)
LNK6X3/4 440 520
LNK6X5 480 560
LNK6X6 520 600
BYPASS Pin Charge
Current
ICH1 VBP = 0 V LNK6X3/4 -5.0 -3.4 -1.8
mA
LNK6X5/6 -7.0 -4.8 -2.5
ICH2 VBP = 4 V LNK6X3/4 -4.0 -2.3 -1.0
LNK6X5/6 -5.6 -3.2 -1.4
BYPASS Pin
Voltage VBP 5.65 6.00 6.25 V
BYPASS Pin
Voltage Hysteresis VBPH 0.70 1.00 1.20 V
BYPASS Pin
Shunt Voltage VSHUNT 6.2 6.5 6.8 V
Circuit Protection
Current Limit ILIMIT
LNK6X3
di/dt = 50 mA/μs , TJ = 25 °C186 200 214
mA
LNK6X4
di/dt = 60 mA/μs , TJ = 25 °C233 250 267
LNK6X5
di/dt = 70 mA/μs , TJ = 25 °C293 315 337
LNK6X6
di/dt = 100 mA/μs , TJ = 25 °C382 410 438
Normalized Output
Current IO
TJ = 25 °C
See Figure 21 0.975 1.000 1.025
Leading Edge Blanking
Time tLEB
TJ = 25 °C
(See Note 5) 170 215 ns
Thermal Shutdown
Temperature TSD 135 142 150 °C
Thermal Shutdown
Hysteresis TSDH 60 °C
Rev. E 07/09
10
LNK603-606/613-616
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Parameter Symbol
Conditions
SOURCE = 0 V; TJ = 0 to 100 °C
(Unless Otherwise Specifi ed)
Min Typ Max Units
Output
ON-State
Resistance RDS(ON)
LNK6X3
ID = 50 mA
TJ = 25 °C24 28
Ω
TJ = 100 °C36 42
LNK6X4
ID = 50 mA
TJ = 25 °C24 28
TJ = 100 °C36 42
LNK6X5
ID = 62 mA
TJ = 25 °C16 19
TJ = 100 °C24 28
LNK6X6
ID = 82 mA
TJ = 25 °C9.6 11
TJ = 100 °C14 17
OFF-State
Leakage
IDSS1
VDS = 560 V See Figure 20
TJ = 125 °C See Note 3 50
μA
IDSS2
VDS = 375 V See Figure 20
TJ = 50 °C15
Breakdown
Voltage BVDSS
TJ = 25 °C
See Figure 20 700 V
DRAIN Supply
Voltage 50 V
Auto-Restart
ON-Time tAR-ON
tON × IFB = 2 mA-μs, fOSC = 12 kHz
VFB = 0
See Notes 1, 5
450 ms
Auto-Restart
OFF-Time tAR-OFF 1.2 2 s
Open-Loop FB Pin
Current Threshold IOL See Note 5 -120 μA
Open-Loop
ON-Time See Note 5 90 μs
NOTES:
Auto-restart ON-time is a function of switching frequency programmed by tonx IFB and minimum frequency in
CC mode.
The current limit threshold is compensated to cancel the effect of current limit delay. As a result the output current stays constant
across the input line range.
IDSS1 is the worst case OFF state leakage specifi cation at 80% of BVDSS and maximum operating junction temperature. IDSS2 is a
typical specifi cation under worst case application conditions (rectifi ed 265 VAC) for no-load consumption calculations.
When the duty-cycle exceeds DCMAX the LinkSwitch-II operates in on-time extension mode.
This parameter is derived from characterization.
1.
2.
3.
4.
5.
Rev. E 07/09
11
LNK603-606/613-616
www.powerint.com
1.200
0.600
0.800
1.000
0.200
0.400
0.000
-40 -15 10 35 60 85 110 135
Temperature (°C)
Current Limit
(Normalized to 25 °C)
PI-5085-040508
1.200
0.600
0.800
1.000
0.200
0.400
0.000
-40 -15 10 35 60 85 110 135
Temperature (°C)
Frequency
(Normalized to 25 °C)
PI-5086-041008
1.200
0.600
0.800
1.000
0.200
0.400
0.000
-40 -15 10 35 60 85 110 135
Temperature (°C)
Frequency Ratio
(Normalized to 25 °C)
PI-5087-040508
1.200
0.600
0.800
1.000
0.200
0.400
0.000
-40 -15 10 35 60 85 110 135
Temperature (°C)
Frequency Ratio
(Normalized to 25 °C)
PI-5088-040508
1.200
0.600
0.800
1.000
0.200
0.400
0.000
-40 -15 10 35 60 85 110 135
Temperature (°C)
Feedback Voltage
(Normalized to 25 °C)
PI-5089-040508
1.200
0.600
0.800
1.000
0.200
0.400
0.000
-40 -15 10 35 60 85 110 135
Temperature (°C)
Normalized Output Current
(Normalized to 25 °C)
PI-5090-040508
Figure 9. Current Limit vs, Temperature. Figure 10. Output Frequency vs, Temperature.
Figure 11. Frequency Ratio vs, Temperature (Constant Current). Figure 12. Frequency Ratio vs, Temperature (Inductor Current).
Figure 13. Feedback Voltage vs, Temperature. Figure 14. Normalized Output Current vs, Temperature.
Typical Performance Characteristics
Rev. E 07/09
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Figure 15. Breakdown vs. Temperature.
Typical Performance Characteristics (cont.)
1.1
1.0
0.9
-50 -25 0 25 50 75 100 125 150
Junction Temperature (°C)
B
rea
kd
own
V
o
l
tage
(Normalized to 25 °C)
PI-2213-012301
DRAIN Volta
g
e (V)
Drain
C
urrent (mA)
300
250
200
100
50
150
0
0 2 4 6 8 10
TCASE=25 °C
TCASE=100 °C
PI-5082-040408
LNK6X3 1.0
LNK6X4 1.0
LNK6X5 1.5
LNK6X6 2.5
Scaling Factors:
Drain Voltage (V)
Drain
C
apacitance (pF)
PI-5083-040408
0 100 200 300 400 500 600
1
10
100
1000
LNK6X3 1.0
LNK6X4 1.0
LNK6X5 1.5
LNK6X6 2.5
Scaling Factors:
50
30
40
10
20
0
0 200 400 600
DRAIN Volta
g
e (V)
Power (mW)
PI-5084-040408
LNK6X3 1.0
LNK6X4 1.0
LNK6X5 1.5
LNK6X6 2.5
Scaling Factors:
Figure 16. Output Characteristic.
Figure 17. COSS vs. Drain Voltage. Figure 18. Drain Capacitance Power.
Rev. E 07/09
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Figure 19. Test Set-up for Feedback Pin Measurements.
PI-4961-022708
6.2 V 500 Ω
1) Raise VBP voltage from 0 V to 6.2 V, down to 4.5 V, up to 6.2 V
2) Raise VIN until cycle skipping occurs at VOUT to measure VFBth
3) Reduce VIN until cycle skipping stops at VOUT to measure VFBth-. Cable drop compensaion factor is υFB = VFBth / VFBth-
4) Apply 1.5 V at VIN and measure tFB delay from start of cycle falling edge to the next falling edge
S
DS
S
FB
S
10 μF
BP
+2 V
+
VIN +
VOUT
LinkSwitch-II
Figure 20. Test Set-up for Leakage and Breakdown Tests.
PI-4962-040308
16 V
To measure BVDSS, IDSS1, and IDSS2 follow these steps:
1) Close S1, open S2
2) Power-up VIN source (16 V)
3) Open S1, close S2
4
)
Measure I/V characteristics of Drain
p
in usin
g
the curve tracer
S
DS
S
FB
S
.1 μF
1 μFBP
VIN
LinkSwitch-II
5 μF 50 kΩ
+
Curve
Tracer
S1 S2
4 kΩ
10 kΩ
Rev. E 07/09
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Figure 21. Test Set-up for Output Current Measurements.
PI-4963-022708
50 V
1)The transformer inductance is chosen to set the value of tON × IFB to 2 mA × μS
2) RO is chosen to operate test circuit in the CC region
3) VO is measured
4) Output current is VO / RO
S
DS
S
FB
S
10 μF
BP
LinkSwitch-II
200 Ω
200 V
470 pF
680 μF3.3 V
RO
11.5 kΩ
7.15 kΩ
+
VO
+
Rev. E 07/09
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Notes:
1. Package dimensions conform to JEDEC specification
MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP)
package with .300 inch row spacing.
2. Controlling dimensions are inches. Millimeter sizes are
shown in parentheses.
3. Dimensions shown do not include mold flash or other
protrusions. Mold flash or protrusions shall not exceed
.006 (.15) on any side.
4. Pin locations start with Pin 1, and continue counter-clock-
wise to Pin 8 when viewed from the top. The notch and/or
dimple are aids in locating Pin 1. Pin 3 is omitted.
5. Minimum metal to metal spacing at the package body for
the omitted lead location is .137 inch (3.48 mm).
6. Lead width measured at package body.
7. Lead spacing measured with the leads constrained to be
perpendicular to plane T.
.008 (.20)
.015 (.38)
.300 (7.62) BSC
(NOTE 7)
.300 (7.62)
.390 (9.91)
.367 (9.32)
.387 (9.83)
.240 (6.10)
.260 (6.60)
.125 (3.18)
.145 (3.68)
.057 (1.45)
.068 (1.73)
.120 (3.05)
.140 (3.56)
.015 (.38)
MINIMUM
.048 (1.22)
.053 (1.35)
.100 (2.54) BSC
.014 (.36)
.022 (.56)
-E-
Pin 1
SEATING
PLANE
-D-
-T-
P08C
DIP-8C (P Package)
PI-3933-101507
D S .004 (.10)
⊕
T E D S .010 (.25) M
⊕
(NOTE 6)
.137 (3.48)
MINIMUM
SMD-8C (G Package)
PI-4015-101507
.004 (.10)
.012 (.30)
.036 (0.91)
.044 (1.12)
.004 (.10)
0 -
° 8
°
.367 (9.32)
.387 (9.83)
.048 (1.22) .009 (.23)
.053 (1.35)
.032 (.81)
.037 (.94)
.125 (3.18)
.145 (3.68)
-D-
Notes:
1. Controlling dimensions are
inches. Millimeter sizes are
shown in parentheses.
2. Dimensions shown do not
include mold flash or other
protrusions. Mold flash or
protrusions shall not exceed
.006 (.15) on any side.
3. Pin locations start with Pin 1,
and continue counter-clock-
wise to Pin 8 when viewed
from the top. Pin 3 is omitted.
4. Minimum metal to metal
spacing at the package body
for the omitted lead location
is .137 inch (3.48 mm).
5. Lead width measured at
package body.
6. D and E are referenced
datums on the package
body.
.057 (1.45)
.068 (1.73)
(NOTE 5)
E S
.100 (2.54) (BSC)
.372 (9.45)
.240 (6.10) .388 (9.86)
.260 (6.60) .010 (.25)
-E-
Pin 1
D S .004 (.10)
⊕
⊕
G08C
.420
.046 .060 .060 .046
.080
Pin 1
.086
.186
.286
Solder Pad Dimensions
.137 (3.48)
MINIMUM
Rev. E 07/09
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LNK603-606/613-616
www.powerint.com
Part Ordering Information
• LinkSwitch Product Family
• II Series Number
• Package Identifi er
G Plastic Surface Mount DIP
P Plastic DIP
D Plastic SO-8
• Package Material
G GREEN: Halogen Free and RoHS Compliant
• Tape & Reel and Other Options
Blank Standard Confi gurations
TL Tape & Reel, 1 k pcs minimum for G Package. 2.5 k pcs for D Package. Not available
for P Package.
LNK 615 D G - TL
PI-4526-040207
D07C
SO-8C
3.90 (0.154) BSC
Notes:
1. JEDEC reference: MS-012.
2. Package outline exclusive of mold flash and metal burr.
3. Package outline inclusive of plating thickness.
4. Datums A and B to be determined at datum plane H.
5. Controlling dimensions are in millimeters. Inch dimensions
are shown in parenthesis. Angles in degrees.
0.20 (0.008) C
2X
1 4
5
8
26.00 (0.236) BSC
D
4
A
4.90 (0.193) BSC
2
0.10 (0.004) C
2X
D
0.10 (0.004) C 2X
A-B
1.27 (0.050) BSC
7X 0.31 - 0.51 (0.012 - 0.020)
0.25 (0.010) M C A-B D
0.25 (0.010)
0.10 (0.004)
(0.049 - 0.065)
1.25 - 1.65
1.75 (0.069)
1.35 (0.053)
0.10 (0.004) C
7X
C
H
o
1.27 (0.050)
0.40 (0.016)
GAUGE
PLANE
0 - 8
1.04 (0.041) REF 0.25 (0.010)
BSC
SEATING
PLANE
0.25 (0.010)
0.17 (0.007)
DETAIL A
DETAIL A
C
SEATING PLANE
Pin 1 ID
B
4
+
+ +
4.90 (0.193)
1.27 (0.050) 0.60 (0.024)
2.00 (0.079)
Reference
Solder Pad
Dimensions
+
Rev. E 07/09
17
LNK603-606/613-616
www.powerint.com
For the latest updates, visit our website: www.powerint.com
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power
Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES
NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by
one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A
complete list of Power Integrations patents may be found at www.powerint.com. Power Integrations grants its customers a license under
certain patent rights as set forth at http://www.powerint.com/ip.htm.
Life Support Policy
POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:
A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii)
whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in signifi cant
injury or death to the user.
A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or effectiveness.
The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, PeakSwitch, EcoSmart, Clampless, E-Shield, Filterfuse, StakFET, PI Expert
and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies.
©2008, Power Integrations, Inc.
1.
2.
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Applications Fax
World Wide +1-408-414-9760
Revision Notes Date
C Final data sheet 06/08
D Auto-restart time modifi ed PCN-09131 03/09
E Introduced Max current limit when V DRAIN is below 400 V 07/09
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