ESD9101 ESD Protection Diode Low Capacitance ESD Protection Diodes for High Speed Data Lines The ESD9101 is designed to protect a single high speed data line from ESD. Ultra-low capacitance and low ESD clamping voltage via SCR technology make this device an ideal solution for protecting voltage sensitive high speed data lines. The SOD-923 mico-package allows for easy PCB layout and the ability to be placed in space constrained applications where board area comes at a premium. * Low Capacitance (0.5 pF Max, I/O to GND) * Protection for the Following Standards: * MARKING DIAGRAM SOD-923 CASE 514AB Features * * www.onsemi.com IEC 61000-4-2 (Level 4) & ISO 10605 Low ESD Clamping Voltage SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC-Q101 Qualified and PPAP Capable These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS Compliant XM XX = Specific Device Code M = Date Code G = Pb-Free Package (Note: Microdot may be in either location) PIN CONFIGURATIONS AND SCHEMATICS Cathode Typical Applications * * * * USB 3.0/3.1 HDMI 1.3/1.4/2.0 DisplayPort GPS Antenna Anode MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Pin 1 Rating Symbol Value Unit Operating Junction Temperature Range TJ -55 to +150 C Storage Temperature Range Tstg -55 to +150 C Lead Solder Temperature - Maximum (10 Seconds) TL 260 C ESD 25 25 30 30 20 kV Pins 2 = IEC 61000-4-2 Contact IEC 61000-4-2 Air ISO 10605 150 pF/2 kW ISO 10605 330 pF/2 kW ISO 10605 330 pF/330 W Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. See Application Note AND8308/D for further description of survivability specs. (c) Semiconductor Components Industries, LLC, 2016 November, 2017 - Rev. 1 ORDERING INFORMATION See detailed ordering and shipping information on page 6 of this data sheet. 1 Publication Order Number: ESD9101/D ESD9101 ELECTRICAL CHARACTERISTICS I (TA = 25C unless otherwise noted) Symbol VRWM IPP Parameter Working Peak Voltage IR RDYN Maximum Reverse Leakage Current @ VRWM VBR VBR Breakdown Voltage @ IT V VC VRWMVHOLD Test Current IR IT VHOLD Holding Reverse Voltage IHOLD IHOLD Holding Reverse Current RDYN Dynamic Resistance IT VC RDYN IPP Maximum Peak Pulse Current VC Clamping Voltage @ IPP VC = VHOLD + (IPP * RDYN) -IPP VC = VHOLD + (IPP * RDYN) ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise specified) Parameter Symbol Reverse Working Voltage VRWM Breakdown Voltage VBR Conditions IT = 1 mA, I/O Pin to GND IR Holding Reverse Voltage VHOLD I/O Pin to GND Holding Reverse Current IHOLD I/O Pin to GND 5.3 5.0 V 8.0 V 1.0 mA 2.2 V 97 mA See Figures 1 and 2 V IPP = 8 A IPP = -8 A 5.0 -4.0 V IPP = 16 A IPP = -16 A 7.0 -7.0 I/O Pin to GND GND to I/O Pin 0.30 0.38 VR = 0 V, f = 1 MHz between I/O Pins and GND VR = 0 V, f = 2.5 GHz between I/O Pins and GND VR = 0 V, f = 5.0 GHz between I/O Pins and GND 0.36 0.36 0.36 IEC61000-4-2, 8 KV Contact Clamping Voltage TLP VC CJ Unit 7.0 65 VC Junction Capacitance Max VRWM = 5.0 V, I/O Pin to GND Clamping Voltage RDYN Typ I/O Pin to GND Reverse Leakage Current Dynamic Resistance Min W 0.50 0.45 0.45 pF 90 10 80 0 70 -10 60 -20 VOLTAGE (V) VOLTAGE (V) Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 50 40 30 20 10 -40 -50 -60 -70 0 -10 -20 -30 0 20 40 60 80 100 120 -80 -90 -20 140 TIME (ns) 0 20 40 60 80 100 120 TIME (ns) Figure 1. IEC61000-4-2 +8 kV Contact ESD Clamping Voltage Figure 2. IEC61000-4-2 -8 kV Contact Clamping Voltage www.onsemi.com 2 140 ESD9101 IEC61000-4-2 Waveform IEC 61000-4-2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 3. IEC61000-4-2 Spec Device ESD Gun Under Oscilloscope Test 50 W 50 W Cable Figure 4. Diagram of ESD Clamping Voltage Test Setup The following is taken from Application Note AND8307/D - Characterization of ESD Clamping Performance. systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000-4-2 waveform. Since the IEC61000-4-2 was written as a pass/fail spec for larger www.onsemi.com 3 ESD9101 10 20 -18 18 8 12 6 10 8 4 6 TLP CURRENT (A) TLP CURRENT (A) 14 -14 -12 6 -10 -8 4 -6 2 -4 2 4 8 -16 EQUIVALENT VIEC (kV) EQUIVALENT VIEC (kV) 16 -2 2 0 10 -20 0 0 NOTE: 1 2 3 4 5 6 7 8 9 0 10 0 1 2 3 4 5 6 7 8 VC, VOLTAGE (V) VC, VOLTAGE (V) Figure 5. Positive TLP IV Curve Figure 6. Negative TLP IV Curve 0 10 9 TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns. VIEC is the equivalent voltage stress level calculated at the secondary peak of the IEC 61000-4-2 waveform at t = 30 ns with 2 A/kV. See TLP description below for more information. Transmission Line Pulse (TLP) Measurement L Transmission Line Pulse (TLP) provides current versus voltage (I-V) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 7. TLP I-V curves of ESD protection devices accurately demonstrate the product's ESD capability because the 10s of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 8 where an 8 kV IEC 61000-4-2 current waveform is compared with TLP current pulses at 8 A and 16 A. A TLP I-V curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. For more information on TLP measurements and how to interpret them please refer to AND9007/D. S Attenuator / 50 W Coax Cable 10 MW IM 50 W Coax Cable VM DUT VC Oscilloscope Figure 7. Simplified Schematic of a Typical TLP System Figure 8. Comparison Between 8 kV IEC 61000-4-2 and 8 A and 16 A TLP Waveforms www.onsemi.com 4 ESD9101 I (A) 1.E+00 1.E-01 1.E-02 1.E-03 1.E-04 1.E-05 1.E-06 1.E-07 1.E-08 1.E-09 1.E-10 1.E-11 1.E-12 -2 -1 0 1 2 3 4 5 V (V) 6 7 Figure 9. IV Characteristics www.onsemi.com 5 8 9 10 ESD9101 Latch-Up Considerations therefore latch-up free. In the non-latch up free load line case, the IV characteristic of the snapback protection device intersects the load-line in two points (VOPA, IOPA) and (VOPB, IOPB). Therefore in this case, the potential for latch-up exists if the system settles at (VOPB, IOPB) after a transient. Due to its high holding current, the ESD9101 is suitable for HDMI and 5 V active antenna applications where previous ESD8000 series devices were not. When designing this part into the application, please note the latch-up considerations by performing a loadline analysis corresponding to the data line and ESD9101's SCR characteristics. For a more in-depth explanation of latch-up considerations please refer to Application Note AND9116/D. ON Semiconductor's 9100 series of ESD protection devices utilize a snap-back, SCR type structure. By using this technology, the potential for a latch-up condition was taken into account by performing load line analyses of common high speed serial interfaces. Example load lines for latch-up free applications and applications with the potential for latch-up are shown below with a generic IV characteristic of a snapback, SCR type structured device overlaid on each. In the latch-up free load line case, the IV characteristic of the snapback protection device intersects the load-line in one unique point (VOP, IOP). This is the only stable operating point of the circuit and the system is I I ISSMAX IOPB ISSMAX IOP VOP VDD IOPA V VOPB Latch-up Free Condition V VOPA VDD Potential Latch-up Condition Figure 10. Example Load Lines for Latch-up Free Applications and Applications with the Potential for Latch-up Table 1. SUMMARY OF SCR REQUIREMENTS FOR LATCH-UP FREE APPLICATIONS Application VBR (min) (V) IH (min) (mA) VH (min) (V) HDMI 1.4/1.3a TMDS 3.465 54.78 1.0 USB 2.0 LS/FS 3.301 1.76 1.0 USB 2.0 HS 0.482 N/A 1.0 USB 3.0/3.1 SS 2.800 N/A 1.0 DisplayPort 3.600 25.00 1.0 GPS (Active) 5.200 80.00 1.0 ORDERING INFORMATION Device Package Shipping ESD9101P2T5G SOD-923 (Pb-Free) 8000 / Tape & Reel SZESD9101P2T5G For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 6 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOD-923 CASE 514AB ISSUE D STYLE 1 DATE 03 SEP 2020 STYLE 2 SCALE 8:1 D -X- NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. 5. DIMENSION L WILL NOT EXCEED 0.30mm. -Y- E 1 2X b 0.08 X Y 2 TOP VIEW c HE SIDE VIEW 2X 2X BOTTOM VIEW XM XM STYLE 1 STYLE 2 X M SOLDERING FOOTPRINT* = Specific Device Code = Date Code *This information is generic. Please refer to device data sheet for actual part marking. Pb-Free indicator, "G" or microdot " G", may or may not be present. 1.20 2X INCHES MIN NOM MAX 0.013 0.015 0.016 0.006 0.008 0.010 0.003 0.005 0.007 0.030 0.031 0.033 0.022 0.024 0.026 0.037 0.039 0.041 0.007 REF 0.002 0.004 0.006 GENERIC MARKING DIAGRAM* L L2 2X 0.36 MILLIMETERS MIN NOM MAX 0.34 0.37 0.40 0.15 0.20 0.25 0.07 0.12 0.17 0.75 0.80 0.85 0.55 0.60 0.65 0.95 1.00 1.05 0.19 REF 0.05 0.10 0.15 DIM A b c D E HE L L2 A 0.25 STYLE 1: PIN 1. CATHODE (POLARITY BAND) 2. ANODE PACKAGE OUTLINE STYLE 2: NO POLARITY DIMENSIONS: MILLIMETERS See Application Note AND8455/D for more mounting details *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON23284D Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red. SOD-923, 1.0X0.6X0.37, MAX HEIGHT 0.40 PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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