16 V Rail-to-Rail
Operational Amplifiers
AD8565/AD8566/AD8567
Rev. G
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FEATURES
Single-supply operation: 4.5 V to 16 V
Input capability beyond the rails
Rail-to-rail output swing
Continuous output current: 35 mA
Peak output current: 250 mA
Offset voltage: 10 mV
Slew rate: 6 V/μs
Unity gain stable with large capacitive loads
Supply current: 700 μA per amplifier
Qualified for automotive applications
APPLICATIONS
LCD reference drivers
Portable electronics
Communications equipment
Automotive infotainment systems
GENERAL DESCRIPTION
The AD8565/AD8566/AD8567 are low cost, single-supply, rail-
to-rail input and output operational amplifiers optimized for
LCD monitor applications. They are built on an advanced high
voltage CBCMOS process. The AD8565 contains a single
amplifier, the AD8566 has two amplifiers, and the AD8567 has
four amplifiers.
These LCD op amps have high slew rates, 35 mA continuous
output drive, 250 mA peak output drive, and a high capacitive
load drive capability. They have a wide supply range and offset
voltages below 10 mV. The AD8565/AD8566/AD8567 are ideal
for LCD grayscale reference buffer and VCOM applications.
The AD8565/AD8566/AD8567 are specified over the −40°C to
+85°C temperature range. The AD8565 single is available in a 5-
lead SC70 package. The AD8566 dual is available in an 8-lead
MSOP package. The AD8567 quad is available in a 14-lead
TSSOP package and a 16-lead LFCSP package.
The AD8566WARMZ is the automotive grade version.
PIN CONFIGURATIONS
1
2
3
5
4–IN
+IN
V–OUT
V+
AD8565
TOP VIEW
(Not to Scal e)
01909-001
Figure 1. 5-Lead SC70 Pin Configuration
45
27
36
18
OUT A
–IN A
+IN A
V–
V+
OUT B
–IN B
+IN B
AD8566
TOP VIEW
(No t to Scale)
01909-002
Figure 2. 8-Lead MSOP Pin Configuration
OUT B
+IN B
–IN B
V+
–IN A
+IN A
OUT A
87
510
96
411
312
312
114
OUT C
+IN C
–IN C
V–
–IN D
+IN D
OUT D
AD8567
TOP VIEW
(No t t o S cale)
01909-003
Figure 3. 14-Lead TSSOP Pin Configuration
16
5
13
8
9
12
1
4
1415
2
3
76
11
10
–IN D
+IN D
V–
+IN C
–IN A
+IN A
V+
+IN B
NC
OUT
A
OUT
D
NC
–IN B
OUT B
OUT C
–IN C
AD8567
TOP VIEW
(No t t o S cale)
NOTES
1. THE EXPOSED PAD MUST BE
CONNECTED T O PIN 3, THAT IS, V+.
2
. NC = NO CONNECT .
01909-004
Figure 4. 16-Lead LFCSP Pin Configuration
AD8565/AD8566/AD8567
Rev. G | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Pin Configurations ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 3
Absolute Maximum Ratings ............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution .................................................................................. 4
Typical Performance Characteristics ............................................. 5
Theory of Operation .........................................................................9
Input Overvoltage Protection ......................................................9
Output Phase Reversal ............................................................... 10
Power Dissipation....................................................................... 10
Thermal Pad—AD8567 ............................................................. 10
Total Harmonic Distortion + Noise (THD + N)........................ 11
Short-Circuit Output Conditions............................................. 11
LCD Panel Applications ............................................................ 11
Outline Dimensions ....................................................................... 12
Ordering Guide .......................................................................... 13
REVISION HISTORY
3/10—R e v. F to Re v. G
Changes to Figure 4 .......................................................................... 1
Changes to the Thermal Pad—AD8567 Section ........................ 10
1/10—Re v. E to R e v. F
Changes to Applications and General Description Sections ...... 1
Changes to Figure 4 .......................................................................... 1
Added Exposed Pad Notation to Outline Dimensions ............. 12
Changes to Ordering Guide .......................................................... 13
8/07—Rev. D to Rev. E
Changes to Features Section............................................................ 1
Changes to Phase Margin ................................................................ 3
Changes to Table 2 ............................................................................ 4
Changes to Figure 30 ...................................................................... 10
Updated Outline Dimensions ....................................................... 12
Changes to Ordering Guide .......................................................... 13
2/06—Re v. C to Re v. D
Updated Format .................................................................. Universal
Changes to Figure 6 and Figure 8 .................................................... 5
Added the Thermal Pad—AD8567 Section ................................ 10
Changes to Ordering Guide .......................................................... 13
3/04—Rev. B to Re v. C
Changes to Specifications ................................................................. 2
Changes to TPC 4 .............................................................................. 4
Changes to TPC 10 ............................................................................ 5
Changes to TPC 14 ............................................................................ 6
Changes to TPC 20 ............................................................................ 7
12/03—Re v. A to Re v. B
Updated Ordering Guide ................................................................. 3
Updated Outline Dimensions ....................................................... 11
10/01—Rev. 0 to Rev. A
Edit to 16-Lead CSP and 5-Lead SC70 Pin Configuration .......... 1
Edit to Ordering Guide ..................................................................... 3
7/01—Revision 0: Initial Version
AD8565/AD8566/AD8567
Rev. G | Page 3 of 16
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
4.5 V ≤ VS ≤ 16 V, VCM = VS/2, TA = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS 2 10 mV
Offset Voltage Drift ΔVOS/ΔT −40°C ≤ TA ≤ +85°C 5 µV/°C
Input Bias Current IB 80 600 nA
−40°C ≤ TA ≤ +85°C 800 nA
Input Offset Current IOS 1 80 nA
−40°C ≤ TA ≤ +85°C 130 nA
Input Voltage Range Common-mode input −0.5 VS + 0.5 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to VS, −40°C ≤ TA ≤ +85°C 54 95 dB
Large Signal Voltage Gain AVO RL = 10 kΩ, VO = 0.5 V to (VS − 0.5 V) 3 10 V/mV
Input Impedance ZIN 400 kΩ
Input Capacitance CIN 1 pF
OUTPUT CHARACTERISTICS
Output Voltage High VOH IL = 100 µA VS − 0.005 V
VS = 16 V, IL = 5 mA 15.85 15.95 V
−40°C ≤ TA ≤ +85°C 15.75 V
VS = 4.5 V, IL = 5 mA 4.2 4.38 V
−40°C ≤ TA ≤ +85°C 4.1 V
Output Voltage Low VOL IL = 100 µA 5 mV
VS = 16 V, IL = 5 mA 42 150 mV
−40°C ≤ TA ≤ +85°C 250 mV
VS = 4.5 V, IL = 5 mA 95 300 mV
−40°C ≤ TA ≤ +85°C 400 mV
Continuous Output Current IOUT 35 mA
Peak Output Current IPK VS = 16 V 250 mA
POWER SUPPLY
Supply Voltage VS 4.5 16 V
Power Supply Rejection Ratio PSRR VS = 4 V to 17 V, −40°C ≤ T
A ≤ +85°C 70 90 dB
Supply Current/Amplifier ISY VO = VS/2, no load 700 850 µA
−40°C ≤ TA ≤ +85°C 1 mA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 10 kΩ, CL = 200 pF 4 6 V/µs
Gain Bandwidth Product GBP RL = 10 kΩ, CL = 10 pF 5 MHz
Phase Margin Øm RL = 10 kΩ, CL = 10 pF 65 Degrees
Channel Separation 75 dB
NOISE PERFORMANCE
Voltage Noise Density en f = 1 kHz 26 nV/√Hz
en f = 10 kHz 25 nV/√Hz
Current Noise Density in f = 10 kHz 0.8 pA/√Hz
AD8565/AD8566/AD8567
Rev. G | Page 4 of 16
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage (VS) 18 V
Input Voltage −0.5 V to VS + 0.5 V
Differential Input Voltage VS
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for worst-case conditions, that is, for a device
soldered onto a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θJA θJC Unit
5-Lead SC70 (KS-5) 376 126 °C/W
8-Lead MSOP (RM-8) 210 45 °C/W
14-Lead TSSOP (RU-14) 180 35 °C/W
16-Lead LFCSP (CP-16-4) 381 301 °C/W
1 DAP is soldered down to PCB.
ESD CAUTION
AD8565/AD8566/AD8567
Rev. G | Page 5 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
TEMPERATURE (°C)
0
–0.25
–1.50 –40
INPUT OFFSET VOLTAGE (mV)
–0.50
–0.75
–1.00
–1.25
VCM = VS/2
VS = 16V
25 85
VS = 4.5V
01909-005
Figure 5. Input Offset Voltage vs. Temperature
FRE QUENCY ( Hz )
10
1
0.1
CURRENT NOIS E DE NS IT Y ( pA/√Hz)
10 100 1k 10k
4.5V ≤ VS ≤ 16V
TA = 25° C
01909-006
Figure 6. Current Noise
FREQUENCY (1µ s/DIV )
TIME (50mV/DIV)
V
S
= 16V
R
L
= 10kΩ
C
L
= 100pF
A
V
= +1
T
A
= 25° C
01909-007
Figure 7. Small Signal Transient Response
1000
100
1
10
FRE QUENCY ( Hz )
VOLT AGE NOI SE DENSITY (n V/√Hz)
10 100 1k 10k
4.5V ≤ V
S
≤ 16V
T
A
= 25° C
01909-008
Figure 8. Voltage Noise Density vs. Frequency
SUPPLY VOLT AGE (V)
1.0
0.8
0
SUPP LY CURRENT/ AM P LIFI E R ( mA)
0.6
0.4
0.2
181614121086420
V
O
= V
S
/2
A
V
= +1
T
A
= 25° C
01909-009
Figure 9. Supply Current/Amplifier vs. Supply Voltage
Figure 10. Supply Current/Amplifier vs. Temperature
AD8565/AD8566/AD8567
Rev. G | Page 6 of 16
LOAD CAPACI TANCE ( pF)
100
90
0
OVERSHOOT (%)
80
70
60
50
40
30
20
10
–OS
+OS
10 100 1k
V
S
= 16V
V
IN
= 100mV p - p
R
L
= 10kΩ
A
V
= +1
T
A
= 25° C
01909-011
Figure 11. Small Signal Overshoot vs. Load Capacitance
FREQUENCY (Hz)
OUTPUT SWING (V p-p)
0
2
4
6
8
10
12
14
16
18
10 100 1k 10k 100k 1M 10M
V
S
= 16V
A
V
= +1
R
L
= 10kΩ
DISTORTION < 1%
T
A
= 25° C
01909-012
Figure 12. Closed-Loop Output Swing vs. Frequency
FREQUENCY (Hz)
CLOSED-LOOP GAIN (dB)
10
20
30
40
50
60
0
10 100 1k 10k 100k 1M 10M
4.5V ≤ V
S
≤ 16V
R
L
= 10kΩ
C
L
= 40pF
T
A
= 25° C
A
VCL
= –100
A
VCL
= –10
A
VCL
= +1
01909-013
Figure 13. Closed-Loop Gain vs. Frequency
GAIN (d B)
100
80
60
40
20
FREQUENCY ( Hz )
45
90
135
180
0
225
270
PHASE S HIFT (Degrees)
0
1k 10k 100k 1M 10M 100M
01909-014
V
S
= 16V
R
L
= 10kΩ
C
L
= 40pF
T
A
= 25° C
Figure 14. Open-Loop Gain and Phase Shift vs. Frequency
LOAD CURRENT ( mA)
10
0.1
1
100
1k
OUTPUT VOLTAGE (mV)
0.001 0.01 0.1 110 100
T
A
= 25° C
V
S
= 4.5V V
S
= 16V
01909-015
Figure 15. Output Voltage to Supply Rail vs. Load Current
TEMPERATURE (°C)
150
OUTPUT VOLTAGE (mV)
135
120
105
90
75
60
45
30
15
0
ISINK = 5mA
VS = 4.5V
VS = 16V
–40 25 85
01909-016
Figure 16. Output Voltage Swing to Rail vs. Temperature
AD8565/AD8566/AD8567
Rev. G | Page 7 of 16
150
OUTPUT VOLTAGE (mV)
135
120
105
90
75
60
45
30
15
0
TEMPERATURE (°C)
ISOURCE = 5mA
VS = 4.5V
VS = 16V
–40 25 85
01909-017
Figure 17. Output Voltage Swing to Rail vs. Temperature
FREQUENCY ( Hz )
IM P E DANCE (Ω)
500
450
0
400
350
300
250
200
150
100
50
100 1k 10k 100k 1M 10M
A
V
= +1
T
A
= 25° C
V
S
= 4.5V
V
S
= 16V
01909-018
Figure 18. Closed-Loop Output Impedance vs. Frequency
FREQUENCY (Hz)
CMRR (dB)
20
40
60
80
100
120
0
140
10 100 1k 10k 100k 1M 10M
V
S
= 16V
T
A
= 25° C
01909-019
Figure 19. Common-Mode Rejection Ratio (CMRR) vs. Frequency
POW ER SUPPLY REJECT IO N RATIO (dB)
160
140
–40
120
100
80
60
40
20
0
–20
+PSRR
–PSRR
FREQUENCY (Hz)
100 1k 10k 100k 1M 10M
V
S
= 16V
T
A
= 25° C
01909-020
Figure 20. Power Supply Rejection Ratio vs. Frequency
TIME ( 40µs/DIV)
VOLTAGE (3V/DIV)
VS = 16V
RL = 10kΩ
AV = +1
TA = 25° C
01909-021
Figure 21. No Phase Reversal
INPUT OFFSET VOLTAG E (mV)
1.8k
1.6k
0
800
600
400
200
1.2k
1.0k
1.4k
VS = 16V
TA = 25° C
–10 –8 –6 –4 –2 0 2 4 6 8 10
QUANTITY (Ampl ifiers)
01909-022
Figure 22. Input Offset Voltage Distribution
AD8565/AD8566/AD8567
Rev. G | Page 8 of 16
–5
INP UT OFF S E T CURRENT ( nA)
–1
–2
–3
–4
5
1
0
3
2
4
TEMPERATURE (°C)
V
S
= 4.5V
V
S
= 16V
–40 25 85
01909-023
Figure 23. Input Offset Current vs. Temperature
–350
INP UT BIAS CURRE NT (nA)
–150
–200
–250
–300
0
–50
–100
TEMPERATURE (°C)
VS = 4.5V
VS = 16V
–40 25 85
VCM = VS/2
01909-024
Figure 24. Input Bias Current vs. Temperature
CROSSTALK (dB)
–20
–40
–180
–60
–80
–160
–100
–120
–140
FREQUENCY (Hz)
50 100 1k 10k 60k
16V
4.5V
01909-025
Figure 25. Channel A vs. Channel B Crosstalk
COMMON-MODEVOLTAGE (V)
7
0
BANDWI DTH (M Hz )
6
4
3
2
1
5
0246810 12 14 16
V
S
= 16V
A
V
= +1
R
L
= x
T
A
= 25° C
01909-026
Figure 26. Frequency vs. Common-Mode Voltage (VS = 16 V)
6
5
0
4
3
2
1
0 1 2 3 4 5
COMMON-MODEVOLTAGE (V)
BANDWI DTH (M Hz )
VS = 5V
AV = +1
RL = 10kΩ
TA = 25° C
01909-027
Figure 27. Frequency vs. Common-Mode Voltage (VS = 5 V)
AD8565/AD8566/AD8567
Rev. G | Page 9 of 16
THEORY OF OPERATION
The AD8565/AD8566/AD8567 are designed to drive large
capacitive loads in LCD applications. They have high output
current drive and rail-to-rail input/output operation and are
powered from a single 16 V supply. They are also intended for
other applications where low distortion and high output current
drive are needed.
Figure 28 shows a simplified equivalent circuit for the AD8565/
AD8566/AD8567. The rail-to-rail bipolar input stage is com-
posed of two PNP differential pairs, Q4 to Q5 and Q10 to Q11,
operating in series with diode protection networks, D1 to D2.
Diode network D1 to D2 serves as protection against large
transients for Q4 to Q5 to accommodate rail-to-rail input swing.
D5 to D6 protect Q10 to Q11 against Zenering. In normal oper-
ation, Q10 to Q11 are off, and their input stage is buffered from
the operational amplifier inputs by Q6 to D3 and Q8 to D4.
Operation of the input stage is best understood as a function of
applied common-mode voltage: when the inputs of the AD8565/
AD8566/AD8567 are biased midway between the supplies, the
differential signal path gain is controlled by resistive loads Q4 to
Q5 (via R9, R10). As the input common-mode level is reduced
toward the negative supply (VNEG or GND), the input transistor
current sources, I1 and I2, are forced into saturation, thereby
forcing the Q6 to D3 and Q8 to D4 networks into cutoff.
However, Q4 to Q5 remain active, providing input stage gain.
Inversely, when common-mode input voltage is increased
toward the positive supply, Q4 to Q5 are driven into cutoff, Q3
is driven into saturation, and Q4 becomes active, providing bias
to the Q10 to Q11 differential pair. The point at which the Q10 to
Q11 differential pair becomes active is approximately equal to
(VPOS − 1 V).
R1
R4R3
D2D1
Q4
Q3 BIAS LI NE
V–
D4D3
Q5
Q4
Q10 Q11
C1
C2
D5
D6
Q8
Q6
R10R9
FOLDED
CASCADE
V+
I2I1
VNEG
VPOS
R5 R6
01909-028
Figure 28. AD8565/AD8566/AD8567 Equivalent Input Circuit
The benefit of this type of input stage is low bias current. The
input bias current is the sum of base currents of Q4 to Q5 and
Q6 to Q8 over the range from (VNEG + 1 V) to (VPOS − 1 V).
Outside this range, the input bias current is dominated by the
sum of base currents of Q10 to Q11 for input signals close to
VNEG and of Q6 to Q8 (Q10 to Q11) for signals close to VPOS.
From this type of design, the input bias current of the AD8565/
AD8566/AD8567 not only exhibits different amplitude but also
exhibits different polarities. Figure 29 provides the characteris-
tics of the input bias current vs. the common-mode voltage. It is
important to keep in mind that the source impedances driving
the inputs are balanced for optimum dc and ac performance.
INPUT COMMON-MODE VOLT AGE (V)
0 2
INP UT BIAS CURRE NT (nA)
1000
–1000
800
200
–200
–600
–800
600
400
0
–400
4 6 8 10 12 14 16
V
S
= 16V
T
A
= 25° C
01909-029
Figure 29. AD8565/AD8566/AD8567 Input Bias Current vs.
Common-Mode Voltage
To achieve rail-to-rail output performance, the AD8565/
AD8566/AD8567 design uses a complementary common-
source (or gmRL) output. This con-figuration allows output
voltages to approach the power supply rails, particularly if the
output transistors are allowed to enter the triode region on
extremes of signal swing, which are limited by VGS, the
transistor sizes, and output load current. In addition, this type
of output stage exhibits voltage gain in an open-loop gain
configuration. The amount of gain depends on the total load
resistance at the output of the AD8565/AD8566/AD8567.
INPUT OVERVOLTAGE PROTECTION
As with any semiconductor device, whenever the input exceeds
either supply voltages, attention needs to be paid to the input
overvoltage characteristics. As an overvoltage occurs, the amplifier
could be damaged, depending on the voltage level and the
magnitude of the fault current. When the input voltage exceeds
either supply by more than 0.6 V, internal positive-negative (pn)
junctions allow current to flow from the input to the supplies.
AD8565/AD8566/AD8567
Rev. G | Page 10 of 16
This input current is not inherently damaging to the device as
long as it is limited to 5 mA or less. If a condition exists using
the AD8565/AD8566/AD8567 where the input exceeds the
supply more than 0.6 V, an external series resistor should be
added. The size of the resistor can be calculated by using the
maximum over-voltage divided by 5 mA. This resistance should
be placed in series with either input exposed to an overvoltage.
OUTPUT PHASE REVERSAL
The AD8565/AD8566/AD8567 are immune to phase reversal.
Although device output does not change phase, large currents
due to input overvoltage could damage the device. In applica-
tions where the possibility of an input voltage exceeding the
supply voltage exists, overvoltage protection should be used as
described in the Input Overvoltage Protection section.
POWER DISSIPATION
The maximum allowable internal junction temperature of
150°C limits the maximum power dissipation of AD8565/
AD8566/AD8567 devices. As the ambient temperature
increases, the maximum power dissipated by AD8565/AD8566/
AD8567 devices must decrease linearly to maintain maximum
junction temperature. If this maximum junction temperature is
exceeded momentarily, the device still operates properly once
the junction temperature is reduced below 150°C. If the
maximum junction temperature is exceeded for an extended
period, overheating could lead to permanent damage of the
device.
The maximum safe junction temperature, TJMAX, is 150°C. Using
the following formula, the maximum power that an AD8565/
AD8566/AD8567 device can safely dissipate as a function of
temperature can be obtained:
PDISS = TJMAX − TA/θJA
where:
PDISS is the AD8565/AD8566/AD8567 power dissipation.
TJMAX is the AD8565/AD8566/AD8567 maximum allowable
junction temperature (150°C).
TA is the ambient temperature of the circuit.
θJA is the AD8565/AD8566/AD8567 package thermal resistance,
junction-to-ambient.
The power dissipated by the device can be calculated as
PDISS = (VS − VOUT) × ILOAD
where:
VS is the supply voltage.
VOUT is the output voltage.
ILOAD is the output load current.
Figure 30 shows the maximum power dissipation vs. temper-
ature. To achieve proper operation, use the previous equation to
calculate PDISS for a specific package at any given temperature or
use Figure 30.
AMBIENTTEMPERATURE ( °C)
1.25
0.75
0
–35
MAXIMUM POWER DISSIPATION (W)
0.50
0.25
1.00
–15 525 45 65 85
16-L E AD LFCS P
5-L E AD S C70
8-LEAD MSOP
14-L E AD TSSOP
01909-030
Figure 30. Maximum Power Dissipation vs. Temperature for 5-Lead SC70,
8-Lead MSOP, 14-Lead TSSOP, and 16-Lead LFCSP Packages
THERMAL PAD—AD8567
The AD8567 LFCSP comes with a thermal pad that is attached
to the substrate. This substrate is connected to the most positive
supply, that is, Pin 3 in the LFCSP package and Pin 4 in the
TSSOP package. To be electrically safe, the thermal pad should
be soldered to an area on the board that is electrically isolated
or connected to VDD. Attaching the thermal pad to ground
adversely affects the performance of the part.
Soldering down this thermal pad dramatically improves the
heat dissipation of the package. It is necessary to attach vias that
connect the soldered thermal pad to another layer on the board.
This provides an avenue to dissipate the heat away from the
part. Without vias, the heat is isolated directly under the part.
AD8565/AD8566/AD8567
Rev. G | Page 11 of 16
TOTAL HARMONIC DISTORTION + NOISE (THD + N)
The AD8565/AD8566/AD8567 feature low total harmonic dis-
tortion. Figure 31 shows THD + N vs. frequency. The THD + N
over the entire supply range is below 0.008%. When the device
is powered from a 16 V supply, the THD + N stays below
0.003%. Figure 31 shows the AD8566 in a unity noninverting
configuration.
FRE QUENCY ( Hz )
20
THD+N ( %)
100
10
1
0.01
0.1
1k 10k 30k
VS = ±2. 5V
VS = ±8V
01909-031
Figure 31. THD + N vs. Frequency
SHORT-CIRCUIT OUTPUT CONDITIONS
The AD8565/AD8566/AD8567 do not have internal short-
circuit protection circuitry. As a precautionary measure, it is
recommended not to short the output directly to the positive
power supply or to ground.
It is not recommended to operate the AD8565/AD8566/AD8567
with more than 35 mA of continuous output current. The
output current can be limited by placing a series resistor at the
output of the amplifier whose value can be derived using
mA35
S
X
V
R≥
For a 5 V single-supply operation, RX should have a minimum
value of 143 Ω.
LCD PANEL APPLICATIONS
The AD8565/AD8566/AD8567 amplifier is designed for LCD
panel applications or applications where large capacitive load
drive is required. It can instantaneously source/sink greater than
250 mA of current. At unity gain, it can drive 1 µF without
compensation. This makes the AD8565/AD8566/AD8567 ideal
for LCD VCOM driver applications.
To evaluate the performance of the AD8565/AD8566/AD8567,
a test circuit was developed to simulate the VCOM driver
application for an LCD panel. Figure 32 shows the test circuit.
Series capacitors and resistors connected to the output of the op
amp represent the load of the LCD panel. The 300 Ωa n d 3 k Ω
feedback resistors are used to improve settling time. This test
circuit simulates the worst-case scenario for a VCOM. It drives a
represented load that is connected to a signal switched symmet-
rically around VCOM.
Figure 33 shows a scope photo of the instantaneous output peak
current capability of the AD8565/AD8566/AD8567.
INP UT 0VTO 8V
SQUARE WAVEWITH
15.6µ s P ULSE WIDTH
300Ω
3kΩ
10Ω10Ω10Ω10Ω
10nF 10nF10nF10nF
MEASURE
CURRENT
4V
8V
10ΩTO 20Ω
01909-032
Figure 32. VCOM Test Circuit with Supply Voltage at 16 V
TIME (2µs/DIV)
01909-033
CH 2 = 100mA/DIV
CH 1 = 5V/DIV
10
0%
100
90
Figure 33. Scope Photo of the VCOM Instantaneous Peak Current
AD8565/AD8566/AD8567
Rev. G | Page 12 of 16
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-AA
100709-B
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
Figure 34. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-203-AA
1.00
0.90
0.70
0.46
0.36
0.26
2.20
2.00
1.80
2.40
2.10
1.80
1.35
1.25
1.15
072809-A
0.10 MAX
1.10
0.80
0.40
0.10
0.22
0.08
3
1 2
45
0.65 BSC
COPLANARITY
0.10
SEATING
PLANE
0.30
0.15
Figure 35. 5-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-5)
Dimensions shown in millimeters
COM P LIANT T O JEDEC S TANDARDS M O-153-AB- 1
061908-A
8°
0°
4.50
4.40
4.30
14 8
7
1
6.40
BSC
PI N 1
5.10
5.00
4.90
0.65 BS C
0.15
0.05 0.30
0.19
1.20
MAX
1.05
1.00
0.80 0.20
0.09 0.75
0.60
0.45
COPLANARITY
0.10
SEATING
PLANE
Figure 36. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
AD8565/AD8566/AD8567
Rev. G | Page 13 of 16
COM PLI ANT TO JEDEC STANDARDS MO - 220- V GGC
2.25
2.10 SQ
1.95
16
5
13
8
9
12 1
4
1.95 BSC
PIN 1
INDICATOR TOP
VIEW
4.00
BSC SQ
3.75
BSC SQ
COPLANARITY
0.08
(BOTTOM VIEW)
12° MAX
1.00
0.85
0.80 SEATING
PLANE
0.35
0.30
0.25
0.80 M AX
0.65 TYP 0.05 M A X
0.02 NOM
0.20 RE F
0.65 BSC
0.60 M A X 0.60 MAX
PIN 1
INDICATOR
0.25 MIN
072808-A
0.75
0.60
0.50
FO R P ROPER CONNECT ION OF
THE EXPOSED PAD, REFER TO
THE P IN CONFIGURATION AND
FUNCT I ON DES CRI P TI ONS
SECTIO N OF THI S DATA SHEE T .
Figure 37. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-16-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Abs Max (V)
Temperature
Range Package Description
Package
Option Branding
AD8565AKSZ-REEL7 18 −40°C to +85°C 5-Lead Thin Shrink Small Outline Transistor Package (SC70) KS-5 A0N
AD8566ARM-R2 18 −40°C to +85°C 8-Lead Mini Small Outline Package (MSOP) RM-8 ATA
AD8566ARM-REEL 18 −40°C to +85°C 8-Lead Mini Small Outline Package (MSOP) RM-8 ATA
AD8566ARMZ-R2 18 −40°C to +85°C 8-Lead Mini Small Outline Package (MSOP) RM-8 ATA#
AD8566ARMZ-REEL 18 −40°C to +85°C 8-Lead Mini Small Outline Package (MSOP) RM-8 ATA#
AD8566WARMZ-REEL2 18 −40°C to +85°C 8-Lead Mini Small Outline Package (MSOP) RM-8 LG3
AD8567ARU 18 −40°C to +85°C 14-Lead Thin Shrink Small Outline Package (TSSOP) RU-14
AD8567ARU-REEL 18 −40°C to +85°C 14-Lead Thin Shrink Small Outline Package (TSSOP) RU-14
AD8567ARUZ 18 −40°C to +85°C 14-Lead Thin Shrink Small Outline Package (TSSOP) RU-14
AD8567ARUZ-REEL 18 −40°C to +85°C 14-Lead Thin Shrink Small Outline Package (TSSOP) RU-14
AD8567ACP-R2 18 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-4
AD8567ACP-REEL7 18 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-4
AD8567ACPZ-R2 18 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-4
AD8567ACPZ-REEL 18 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-4
AD8567ACPZ-REEL7 18 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-4
1 Z = RoHS Compliant Part.
2 Qualified for automotive applications.
AD8565/AD8566/AD8567
Rev. G | Page 14 of 16
NOTES
AD8565/AD8566/AD8567
Rev. G | Page 15 of 16
NOTES
AD8565/AD8566/AD8567
Rev. G | Page 16 of 16
NOTES
©2001–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01909-0-3/10(G)