Integrated Device Technology, Inc. CMOS STATIC RAMs 64K (16K x 4-BIT) Separate Data Inputs and Outputs IDT71981S/L 1DT71982S/L FEATURES: + Separate data inputs and outputs IDT71981S/L: outputs track inputs during write mode IDT71982S/L: high impedance outputs during write mode High speed (equal access and cycle time) Military: 20/25/35/45/55/70/85ns (max.) Commercial: 15/20/25/35ns (max.) + Low power consumption + Battery backup operation2V data retention (L version only) High-density 28-pin hermetic and plastic DIP, 28-pin leadless chip carrier, and 28-pin SOJ + Produced with advanced CMOS high-performance technology Inputs and outputs directly TTL-compatible Military product compliant to MIL-STD-883, Class B . DESCRIPTION: The 1DT71981/IDT71982 are 65,536-bit high-speed static RAMs organized as 16K x 4. They are fabricated using IDT's high-performance, high-reliability technologyCMOS. Access times as fast as 15ns are available. These circuits also offer a reduced power standby mode (IsB). When CS1 or CS2 goes high, the circuit will automatically go to, and remain in, this standby mode. in the ultra-low-power standby mode (IsB1), the devices consume less than 2.5mW, typically. This capability provides significant system-level power and cooling savings. The low-power (L) versions aiso offer a battery backup data retention capability where the circuit typically consumes only 30u.W operating off a 2V battery. All inputs and outputs of the IDT71981/IDT71982 are TTL- compatible and operate from a single 5V supply. The 1DT71981/IDT71982 are packaged in either a 28-pin, 300 mil hermetic DIP, 28-pin 300 mil plastic DIP, 28-pin SOJ,or 28-pin leadless chip carrier. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally Suited to military temperature applications demanding the highest level of performance and reliability. FUNCTIONAL BLOCK DIAGRAM Ao DECODER A13 Do Di INPUT DATA CONTROL al al gl g 10771982 ONLY all (D171981 CNLY | The IDT logo 1s a registered trademark of Integrated Device Technology, Inc MILITARY AND COMMERCIAL TEMPERATURE RANGES 6.7 1992 Integrated Device Technology, Inc Vcc GND 65,536-BIT MEMORY ARRAY COLUMN VO Yo v1 Ye Ya 2988 drw OT SEPTEMBER 1992 DSC-1028/3 1IDT71981S/L, IDT71982S/L CMOS STATIC RAM 64K (16K x 4-BIT) Separate Data inputs and Outputs MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS Ao C]1 VY 28 [J Veco At [ye 27 7 Ai3 A2 3 26 | At2 A3 (4 257 Att A4 cys 24 [7 Ato As (16 0263. 23 1] As Ae (17 & 22 [9 D3 Av? [Ja S028-5 241) De As f]9 20 1) Y3 Do [J 10 19 | Y2 Digi fv CS: 12 77) Yo OE (13 16 WE GND (14 15 [] CSe2 2988 drw 02 DIP/SOJ TOP VIEW Ow INDEX = < =< = < | A12 4 An ] Ato | Ag D3 -| D2 4Y3 4 Y2 VY N 2988 drw 03 lsople> Oo tcc TOP VIEW CAPACITANCE (Ta = +25C, f = 1.0MHz) Symbol Parameter'") Conditions | Max.| Unit CIN input Capacitance VIN = OV 7 pF Court Output Capacitance VouT = OV 7 pF NOTE: 2988 thi 04 1. This parameter is determined by device characterization, but is not production tested. PIN DESCRIPTIONS Name Description A0-A13 Address Inputs C81, CS2 Chip Selects WE Write Enable OE Output Enable Do-D3 DATAIN Yo-Y3 DATAouT vec Power GND Ground 2988 tbl OF TRUTH TABLE) Mode S1| CS2| WE | OE | Output Power Standby H x x Xx High Z | Standby Standby x H Xx Xx High Z | Standby Read L L H L Dout Active Write?) L L L L Din Active Write) LJ t|et|H High Z | Active Write) L L L |x High Z | Active Read L L H H High Z | Active NOTES: 2988 tbi 02 1. For 1DT71981 only. 2. For IDT71982 only. 3. H= Vin, L = Vil, X = don't care. ABSOLUTE MAXIMUM RATINGS) Symbol Rating Coml. Mil. Unit VTERM | Terminal Voltage |-0.5 to +7.0] -0.5to+7.0] V with Respect to GND TA Operating Oto+70 | -55to+125] C Temperature TBIAS Temperature 55 to +125] -65to +135] C Under Bias TSTG Storage ~55 to +125] -65to +150] C Temperature Pr Power Dissipation 1.0 1.0 WwW lout DC Output 50 50 mA Current NOTE: 2988 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress fating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions tor extended periods may affect reliability. 6.7IDT71981S/L, IDT71982S/L CMOS STATIC RAM 64K (16K x 4-BIT) Separate Data Inputs and Outputs RECOMMENDED DC OPERATING MILITARY AND COMMERCIAL TEMPERATURE RANGES RECOMMENDED OPERATING CONDITIONS TEMPERATURE AND SUPPLY VOLTAGE Symbol Parameter Min. | Typ. | Max. | Unit Grade Ambient Temperature| GND Veo Vec Supply Voltage 45 | 50) 55] V Military 55C to +125C ov 5V 410% GND Supply Voltage 0 6 oY Commercial OC to +70C ov 5V + 10% ViH Input High Voltage 22 _ 6.0 Vv 2886 tbl 06 VIL Input Low Voltage |-0.5'7] | o8 | v NOTE: 2988 tbi 05 1. Vil (min.) = -3.0V for pulse width less than 20ns, once per cycle. DC ELECTRICAL CHARACTERISTICS Vec = .0V+10% 1DT71981/2S IDT71981/2L Symbol Parameter Test Condition Min. Max. Min. Max. Unit fut} Input Leakage Current Vcc = Max., MIL. _ 10 _ 5 BA Vin = GND to Vcc COM. _ 5 _ 2 [Lo] Output Leakage Current} Vcc = Max., CS1.2 = ViH, MIL. _ 10 _ 5 HA Vout = GND to Vcc COM. _ 5 _ 2 VoL Output Low Voltage loL = 10mA, Vcc = Min. 0.5 _ 0.5 Vv loL = 8A, Vcc = Min. _ 0.4 - 0.4 VOH Output High Voltage IOH = 4mA, Vcc = Min. 24 _ 24 _ Vv 2988 tbl O07 DC ELECTRICAL CHARACTERISTICS") (Voc = 5V + 10%, VLC = 0.2V, VHC = Vcc - 0.2V) 71981/2S15 | 71981/2S20 | 71981/2S25| 71981/2535 | 71981/2S45 |71981/2S55/70|71981/2S85 71981/2L15 | 71981/2L20 | 71981/2L25| 71981/2L35 | 71981/2L45 |71981/2L55/70 | 71981/2L85 Symbol Parameter Power |Com!] Mil. |Com'l| Mil. [ComL.| Mil. |]Coml.| Mil. [Com't.| Mit. | Com't| Mil. [com mil. | Unit Icc1 | Operating Power S |100 | | 100] 105} 100] 105] 100} 105} | 105} | 105 | |105] mA Supply Current CS1,2 = Vil, Outputs Open] L 75 | 1] 70] 80 | 70 | 80] 70} 80] | 80] |} 80 | | 80 Vcc = Max., f = 0!) Icc2 | Dynamic Operating Ss 135 | | 130] 160] 125] 155) 125] 140] | 140] | 140 | |140] mA Current S12 = ViL, Outputs Open} L 125 | | 115] 130] 105) 125) 105) 115] |} 110] | 110 | | 105 Vc = Max., f = fax) IsB Standby Power Supply Ss 60 | |] 55] 70] 50] 60] 45 | 50] | 50) | 50 | | 50] mA Current (TTL Level) S12 2 Vin, Vec = Max., L 45 | | 40 |] 50 | 35 | 50] 30] 40] 7 35] | 35 | | 35 Outputs Open, f = faax'?! \s81 | Full Standby Power S$ 20 | ] 157 25] 15] 20) 15 | 20] | 20}; | 20 | | 20 {mA Supply Current (CMOS Level) S1.2 > VHc, Vcec= Max., VIN > VHC or L 15]/]05/15/05]/15) 05/15] ][15) ]1.5 ] 415 VIN < Vic, f = 0} NOTES: 2988 tbl 06 1. All values are maximum guaranteed values. 2. Atf = fwax address and data inputs are cycling at the maximum frequency of read cycles of 1/tac. f = 0 means no input lines change. 6.7 3IDT71981S/L, IDT71982S/L CMOS STATIC RAM 64K (16K x 4-BIT) Separate Data inputs and Outputs MILITARY AND COMMERCIAL TEMPERATURE RANGES DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (L Version Only) Vic = 0.2V, Vc = Vcc - 0.2V Typ. Max. Vcc @ Voc @ Symbol Parameter Test Condition Min. 2.0v 3.0V 2.0V 3.0V Unit VDR Vcc for Data Retention 2.0 _ _ v IccDR Data Retention Current MIL. _ 10 15 600 900 HA COM. _ 10 15 150 225 tepr) Chip Deselect to Data GS1 or GS2 > Vie 0 _ ns Retention Time Vin 2 VHC or s VLC tr?) Operation Recovery Time trac) _ ns Ay) Input Leakage Current _ _ 2 2 HA NOTES: 2988 tbl 09 1. Ta= +25C. 2. tac = Read Cycle Time. 3. This parameter is guaranteed by device characterization. but is not production tested. LOW Vcc DATA RETENTION WAVEFORM DATA f+ RETENTION * oo MODE Vec 4.5V K. 7 4.5V tcDR VoR22V tR cs Pv i YAY 2988 dew 04 AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise/Fall Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V AC Test Load See Figures 1 and 2 2988 thi 10 5V ov 480Q 4800 DATAouT DATAouT 2550 30pF* 255Q, 5pF* 2988 drw 04 2968 drw 05 Figure 1. AC Test Load Figure 2, AC Test Load (for tcL21, 2, toLz, tcHz1, 2, tonz, tow and twHz) *Includes scope and jig capacitances 6.7 4IDT71981S/L, 1IDT71982S/L CMOS STATIC RAM 64K (16K x 4-BIT) Separate Data Inputs and Outputs MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (Vcc = 5.0V + 10%, All Temperature Ranges) 71981/2818""20 | 719812525. |71981/2538/48?) | 71981/2958) | 71981/28707) | 71981/2S585) 71981/2L15'"720 | 71981/2L25 |71961/2L38/48") | 71981/2L58") | 71981/2L707) | 71981/2L857) Symbol Parameter Min. |Max. [Min.| Max.| Min.| Max. |Min. |Max. | Min.| Max.| Min.|Max. |Unit Read Cycle. tac Read Cycle Time 15/20) 25 | 35/45) | 55 _ 70 _ gs] ns TAA Address Access Time ~- (15/19] ~ | 25) 135/45] | 55 | ] 70 | ] 85 | ns tacs1,2 | Chip Select-1,2 Access Time") |15/20| | 25] |3545] |] 55 | ] 70 | ] 85 | ns tc.z1,2 | Chip Select-1,2 to OutputinLow-z) | 5 | | 5 | ]| 51 ~]5 |] 5 ]] 5] [ns tOE Output Enable to Output Valid ;so | 11 | 20/25; | 35 | 45 | 55 | ns to.z | Output Enable to Output intow-Z) | 5 | 15 | |] 51 {5 |]|5{[] 5] | ns tcnz1,2 | Chip Select1,2 to Output in High-Z' | | 778 | | 10] ] 4 | | 20 | | 25 | ] 30 | ns TOHZ Output Disable to Output in High-2 | | 7/8 | 9 _ 15 | 20 _ 25 | 30 | ns TOH Output Hold from Address Change 5 - 5 _ 5 | 5 _ 5 _ 5 |} | ns tPu Chip Select to Power-Up Time) 0 _ 0 _ 0 |] 0 _ 0 _ Oo} | ns 1PD Chip Deselect to Power-Down Time#)| 115/20] | 25 | |35/4s] | 55 | | 70] | 85 | ns NOTES: 2988 tl 11 1. 0 to +70C temperature range only. 2, 55C to +125C temperature range only. 3. Both chip selects must be active low for the device to be selected. 4. This parameter is guaranteed by device characterization, but is not production tested. 6.7 51DT71981S/L, IDT71982S/L CMOS STATIC RAM 64K (16K x 4-BIT) Separate Data Inputs and Outputs MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF READ CYCLE NO. 1 tRC >| ADDRESS m= 4 toe toiz ) tonz () CS1,2 tacst, 2 toiz1, 29) tcvz1, 2 DATAouT DATA VALID 2988 dew 07 TIMING WAVEFORM OF READ CYCLE NO. 2" 2: 4) } tRC aa] ADDRESS y alt. a! 10H "A tOH >] DATAouT PREVIOUS DATA VALID ) DATA VALID 4 2988 drw 08 TIMING WAVEFORM OF READ CYCLE NO. 3"? 4) lors + a __ tACS1,2 tcHz1, 2{5) bee tCL.Z1, 2(5) __p DATAoutT DATA VALID - be tp (6) 7 le top) ICC me mee em eee eee eee Vec SUPPLY CURRENT jsp NOTES: 1. WE is HIGH for READ cycle. 2. Device is continuously selected, CS: = Vu, CS2 = Vit. 3. Address valid prior to or coincident with CS: and or TS2 transition low. 4. OF = Vi. 5 6. 2988 drw 09 . Transition is measured +200mV from steady state voltage. . This parameter is guaranteed by device characterization but is not production tested. 6.7 6IDT71981S/L, IDT71982S/L CMOS STATIC RAM 64K (16K x 4-BIT) Separate Data Inputs and Outputs MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (vcc = 5.0V + 10%, Ali Tem perature Ranges) 71981/281520 | 71981/2825 | 71981/2835/45| 71981/2855@ | 71981/2870 | 71981/25857) 71981/2L.15(%20 | 71981/2L25 | 71981/2L35/45)| 71981/2L55) | 71981/2L70 | 71981/2L85) Symbol Parameter Min. | Max. | Min. |Max.| Min. | Max. |Min. | Max. | Min.| Max] Min. | Max. [Unit Write Cycle twe Write Cycle Time W4A7) 20 | | 30/40; 50 | 60 | 75 | J|ns tow1,2 Chip Select to End of Write 147) 20 | 25/35) 50 | 60 _ 75 |ns taw Address Valid to End of Write! 14/17] 20 | 25/35) 50 _ 60 _ 75 |ns tas Address Set-up Time 0 _ 0 _ 0 _ 0 _ 0 _ 0 |ns twp Write Puise Width 147) 20 | 25/35) 50 _ 60 _ 78 |ns tWRt2 Write Recovery Time 0 _ 0 _ 0 _ 0 0 _ 0 Ins tWHZ Write Enable to Output _ 5/6 _ 7 | 105] 25 _ 30 | 40 | ns in High 23:5) tOW Data Valid to End of Write 10/10] 13 | 15/20) 25 _ 30 _ 35 |ns {DH Data Hold Time 0 _ 0 _ 0 _ 0 _ 0 _ 0 |ns tow Output Active from 5 _ 5 _ 5 _ 5 _ 5 _ 5 |ns End of Write(?) tly Data Valid to Output |12/15)] | 20 | 30/35 | | 40 | 45] |] 50 | ns ValidS-4) twy Write Enable to Output |12/15)] | 20 |30/35| | 40 | 45) | 50 | ns Valid?-4) NOTES: 2988 tbl 12 1. 0 to +70C temperature range only. 2. -55C to +125C temperature range only. 3. This parameter is guaranteed by device characterization but is not production tested. 4. For 1DT71981S/L only. 5. For IDT71982S/L only. 6.7 7IDT71981S/L, 1OT71982S/L CMOS STATIC RAM 64K (16K x 4-BIT) Separate Data Inputs and Outputs MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING) twc ADDRESS CSi.2 tow tDH ~ DATAIN DATA VALID rXXXKKK DATAouT 2988 drw 10 TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)": ) twe ADDRESS CS1,2 al tow DATAIN DATA VALID TY twy DATAout DATA UNDEFINED DATA VALID DATAour DATA UNDEFINED 2988 drw 11 NOTES: . WE or CS: or CSz must be HIGH during all address transitions. . A write occurs during the overlap (twr) of a LOW WE, a LOW GS: and a low GSz. wr is measured from the earlier of CS1, CS2 or WE going HIGH to the end of the write cycle. If the CS and or Se low transition occurs simultaneously with or atter the WE low transition, outputs remain in a high-impedance state. OE is continuously LOW (GE = Vi). Transition is measured +200mV from steady state. . For IDT71981 only. . For 1DT71982 only. DATAout = DATAIN. OMNAORAN= 6.7 8IDT71981S/L, IDT71982S/L CMOS STATIC RAM 64K (16K x 4-BIT) Separate Data Inputs and Outputs MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF WRITE CYCLE NO. 3 (WE CONTROLLED, OE Low)": ) ADDRESS S12 DATAIN DATAouT! DATA UNDEFINED DATAouT DATA UNDEFINED twe tow twe(?) DATA VALID DATA VALID 2988 drw 12 Commercial (0C to +70C) Military (-55C to +125C) Compliant to MIL-STD-883, Class B 300 mil CERDIP (D28-3) (P28-2) Leadless Chip Carrier (L28-2) 300 mil Small Outline IC, J-Bend (SO28-5) 300 mil Plastic DI Commercial Only Military Only Speed in nanoseconds Military Only Military Only Military Only Standard Power Low Power NOTES: 1. WE or CS: or CS2 must be HIGH during all address transitions. 2. A write occurs during the overlap (twe) of a LOW WE, a low CS: and a LOW CSa. 3. twa is measured from the earlier of CS1, CS2 or WE going HIGH to the end of the write cycle. 4. if the CS: and or CS: low transition occurs simultaneously with or after the WE low transition, outputs remain in a high-impedance state. 5. OE is continuously LOW (OE = Vit). 6. Transition is measured +200mV from steady state. 7. For 1DT71981 only. 8. For IDT71982 only. 9. DATAouT = DATAIN. ORDERING INFORMATION IDT XXXX x XX XX x Device Power Speed Package Process/ Type Temperature Range Blank B D P L Y 15 20 25 35 45 55 70 85 Js PL | 71981 64K (16K x 4-Bit} 171982 64K (16K x 4-Bit) High Impedance Outputs 2988 drw 13 6.7