________________General Description
The MAX847 is a complete power-supply and monitor-
ing system for two-way pagers or other low-power digi-
tal communications devices. It requires few external
components. Included on-chip are:
• A 1-cell input, 80mA output, synchronous-rectified
boost DC-DC regulator with a digitally controlled
+1.8V to +4.9V output
• Three low-noise linear-regulator outputs
• Three DAC-controlled comparators for software-
driven 3-channel A/D conversion
• SPI™-compatible serial interface
• Reset and low-battery (LBO) warning outputs
• Charger for NiCd, NiMH, lithium battery, or storage
capacitor for RF PA power or system backup
• Two 1.8Ω(typical) serial-controlled open-drain
MOSFET switches
An evaluation kit for the MAX847 (MAX847EVKIT) is
available to aid in design and prototyping.
Pin Configuration appears at end of data sheet.
____________________________Features
♦80mA Output from 1 Cell at 90% Efficiency
♦13µA Idle Mode™ (coast) Current
♦Selectable Low-Noise PWM or Low-Current
Operation
♦PWM Operating Frequency Synchronized to
Seven Times an External Clock Source
♦Operates at 270kHz with No External Clock
♦Automatic Backup-Battery Switchover
________________________Applications
Two-Way Pagers
GPS Receivers
1-Cell Powered Hand-Held Equipment
MAX847
1-Cell, Step-Up
Two-Way Pager System IC
________________________________________________________________
Maxim Integrated Products
1
MAX847
INPUT
SINGLE AA
ALKALINE BATTERY
0.8V TO 1.8V BATT
LX1
OUT
PGND
REG2IN
OFS
REG1
OUTPUT 2
2.85V ANALOG
LOW-BATTERY
IN/OUT
RESET
IN/OUT
SERIAL
I/O
1.8Ω
DRIVERS
A/D INPUT
OPTIONAL
OUTPUT 1
3V LOGIC
OUTPUT 3
1V RECEIVER
TO RF PA
NiCd BATTERY STACK
OR
STORAGE CAPACITOR
REG2
REG3
NICD
AGNDREFFILT
LBI
LBO
RSIN
RSO
CS
SCL
SDI
SDO
DR1
DR2
DR2IN
DRGND
CH0
SYNC
RUN COAST RUN
____________________________________________________Typical Operating Circuit
PART
MAX847EEI -40°C to +85°C
TEMP. RANGE PIN-PACKAGE
28 QSOP
19-1349; Rev 1a; 10/98
Ordering Information
Idle Mode is a trademark of Maxim Integrated Products. SPI is a trademark of Motorola, Inc.
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
EVALUATION KIT MANUAL
FOLLOWS DATA SHEET
MAX847
1-Cell, Step-Up
Two-Way Pager System IC
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(OUT = 3.0V, BATT = 1.2V, NICD = 3.6V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
BATT, OUT, NICD, LBO, RSO to AGND...................-0.3V to +6V
REG1, OFS, REG2, REF, R2IN to AGND...-0.3V to (OUT + 0.3V)
SCL, SDO, SDI, CS , SYNC, FILT, DR2IN,
CH0, LBI, RSIN, RUN to AGND...................-0.3V to (REG1 + 0.3V)
REG3 .......................................................-0.3V to (REG2 + 0.3V)
DR1, DR2 to DRGND ...............................-0.3V to (BATT + 0.3V)
PGND, DRGND to AGND......................................-0.3V to +0.3V
LX1 to PGND .............................................-0.3V to (OUT + 0.3V)
Continuous Power Dissipation (TA= +70°C)
28-Pin QSOP (derate 8mW/°C above +70°C) .............640mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +165°C
Lead Temperature (soldering, 10sec).............................+300°C
TA= +25°C
Run or Coast Mode
Incremental supply current when on
REG2, REG3 and CH DAC off, VOUT = 2.8V
REG2, REG3 and CH DAC on
Coast mode
Incremental supply current when on
CONDITIONS
V0.9 1.1
BATT Minimum Start-Up Voltage
(Note 3)
V
0.8 OUT x
0.8
BATT Typical Operating Range
(Note 2)
µA30CH DAC Supply Current (Note 4)
µA13 25Coast Mode Supply Current (Note 4) µA875 1350Run Mode Supply Current (Note 4) µA0.5 2BATT Supply Current (Note 5)
µA20REG3 Supply Current (Note 4)
UNITSMIN TYP MAXPARAMETER
IREF = 0 to 20µA, OUT = 1.8V to 4.9V V-1.5% 1.28 1.5%Reference Voltage
IDR = 120mA Ω
1.8 2.8
DR1, DR2 On-Resistance
VDR = 5V nA1 250DR1, DR2 Leakage Current
TA= +25°C
TA= -40°C to +85°C
ISDO = 100µA mV200SDO Output Low
ISDO = -100µA, from REG1 V
VREG1
- 0.2
SDO Output High
Includes CS, SDI, SCL, DR2IN, SYNC, and RUN V0.4Logic Input Level Low
Includes CS, SDI, SCL, DR2IN, SYNC, and RUN V
VREG1
- 0.4
Logic Input Level High
3.6
50% duty cycle MHz5SCL Maximum Clock Rate ns100SDI Setup Time, tDS ns50SDI Hold Time, tDH
Logic Input = 0 to 3.3V; includes CS, SDI, SCL,
DR2IN, SYNC, and RUN µA-1 1Logic Input Current
Charger and Backup Modes off, NICD = 3.6V µA1.2 3
NICD Input Current, Standby
(Note 6)
Incremental supply current when on µA
Backup mode, NICD = 3.6V, OUT = 3V
50REG2 Supply Current (Note 4)
µA20 40
NICD Input Supply Current, Backup
(Note 7) Charger and Backup Modes off,
BATT = 0V and OUT = 0V µA1.2 3
NICD Input Current, Power Fail
(Note 8)
GENERAL PERFORMANCE
SERIAL-INTERFACE TIMING SPECIFICATIONS (Note 9)
MAX847
1-Cell, Step-Up
Two-Way Pager System IC
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(OUT = 3.0V, BATT = 1.2V, NICD = 3.6V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
%-3.5 3.5
OUT Error, Coast Mode
(Note 11)
IOUT = 1mA to 80mA, Run Mode mV25OUT Load Regulation
Coast Mode, OUT = 1.8V to 4.9V
Circuit of Figure 2, OUT = 3.0V, BATT = 1.1V
Circuit of Figure 2, OUT = 3.0V, BATT = 1.0V
CONDITIONS
BATT = 0.8V to 1.5V mV25OUT Line Regulation
LX1 Ω
0.45 0.9
LX1 On-Resistance
ns100
CS Pulse Width High, tCSW
ns70SCL to SDO Output Valid, tDO
ns50
SCL Pulse Width High or Low,
tCH, tCL
mA80 115
Output Current, Run Mode
(Note 10)
mA15 40
Output Current, Coast Mode
(Note 10)
UNITSMIN TYP MAXPARAMETER
NMOS
PMOS 0.65 1.3
TA= +25°C, FILT connected to REF kHz210 270 325Frequency, Free-Run fSYNC = 38.4kHz kHz268.8Frequency, Locked fSYNC = 38.4kHz, FILT network = 1nF (22nF + 10kΩ)kHz±15Jitter (Note 14) fSYNC = 38.4kHz, FILT network = 1nF (22nF + 10kΩ)ms1 25Capture Time (Note 14)
0.2V < (OUT - NICD) < 2V, 15mA_CHG = 1 mA7 25Current High 0.2V < (OUT - NICD) < 2V, 1mA_CHG = 1 mA0.45 1.5Current Low OUT = 2.8V, IOUT = 20mA, NICD = 3.3V %-3.5 3.5OUT Error, Backup Regulator
Backup Mode, NICD = 3.3V Ω
510
Backup-Regulator
On-Resistance (Note 15)
ns70
CS to SDO Disable, tTR
%-3.5 3.5
OUT Error, Run Mode
(Note 12) Run Mode, OUT = 1.8V to 4.9V
mV30 100 170
OUT DAC Step Size
(Note 13) Coast or Run Mode,
OUT = 1.8V to 4.9V
ns50 ns50
CS to SCL Hold Time, tCSH
CS to SCL Setup Time, tCSS
ns70
CS to SDO Output Valid, tDV
OUT = 3.0V %76 83Maximum LX1 Duty Cycle IOUT = 80mA, COUT = 47µF with ESR < 0.25ΩmVp-p70OUT Voltage Ripple During the inductor charge cycle mA480 600 720LX1 Switch Current Limit
DC-DC CONVERTER
PHASE-LOCKED LOOP (PLL)
NICD CHARGER
MAX847
1-Cell, Step-Up
Two-Way Pager System IC
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(OUT = 3.0V, BATT = 1.2V, NICD = 3.6V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
IREG2 = 0 to 24mA, OUT = 3.0V, ROFS = 15kΩmV120 155 190REG2 Voltage Drop
OUT = 3.0V, IREG1 = 65mA
f = 268.8kHz, CREG1 = 10µF ceramic
CONDITIONS
f = 268.8kHz, CREG1 = 10µF, ceramic,
ROFS = 15kΩ, COFS = 0.1µF, IREG2 = 15mA dB30 40
REG2 Supply Rejection
(Note 15)
f = 268.8kHz, CREG1 = 1µF ceramic dB40 50REG3 Supply Rejection (Note 15)
nA-50 -3 50LBI/RSIN Input Current IOUT = 1mA mV30 400LBO/RSO Output Low Output = 5.5V nA1 250LBO/RSO Output Leakage
Ω
1.5 3.1REG1 PMOS On-Resistance dB15 25REG1 Supply Rejection (Note 15)
UNITSMIN TYP MAXPARAMETER
10mV overdrive µs15 50
LBO/RSO Response Time
(Note 15)
V0.2 1.27CH0 Threshold Range (Note 15) Measures NICD V1.2 5.08CH1 Threshold Range (Note 15) Measures BATT V0.2 1.27CH2 Threshold Range (Note 15)
mV10
CH0 Threshold Resolution
(Note 15)
Measures NICD mV40
CH1 Threshold Resolution
(Note 15)
Measures BATT mV10
CH2 Threshold Resolution
(Note 15)
mV7.5 16 30
LBI/RSIN Input Hysteresis
(Note 15)
IREG2 = 0.1mA to 24mA mV9REG2 Load Regulation
REG3 Output Voltage IREG3 = 0 to 2mA 0.96 1.0 1.04 V
Falling input V0.58 0.60 0.63LBI/RSIN Input Threshold
At thresholds of 200mV, 800mV, and 1270mV %
-2.0 2.0
-15mV +15mV
CH0 Error
At thresholds of 1200mV, 3200mV, and 5080mV %
-3.0 3.0
-60mV +60mV
CH1 Error
3.2 3.3 3.4
IOUT = 1mA, OUT = 4.9V V
3.15 3.45
REG1 Clamp Voltage TA= +25°C
TA= -40°C to +85°C
At thresholds of 200mV, 800mV, and 1270mV %
-2.0 2.0
-15mV +15mV
CH2 Error
mV1 2 4CH0 Input Hysteresis (Note 15)
LINEAR REGULATORS
DATA-ACQUISITION AND VOLTAGE MONITORS
mV4 8 16CH1 Input Hysteresis (Note 15)
MAX847
1-Cell, Step-Up
Two-Way Pager System IC
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(OUT = 3.0V, BATT = 1.2V, NICD = 3.6V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
CONDITIONS mV1 2 4CH2 Input Hysteresis (Note 15) UNITS
MIN TYP MAXPARAMETER
CH0 = 0.2V to 1.27V nA-100 100CH0 Input Current
10mV overdrive µs0.6 1.0
CH Comparator Response Time
(Note 15)
Note 1: Specifications to -40°C are guaranteed by design, not production tested.
Note 2: This is not a tested parameter, since the IC is powered from OUT, not BATT. The only limitation in the BATT range is the
inability to generate more than 5 times, or less than 1.15 times the BATT voltage at OUT. This is due to PWM controller
duty-cycle limitations in Run Mode.
Note 3: Minimum start-up voltage is tested by determining when the LX pins can draw at least 50mA for 1µs (min) at a 50kHz (min)
repetition rate. This guarantees that the IC will deliver at least 200µA at the OUT pin.
Note 4: This supply current is drawn from the OUT pin. Current drain from the battery depends on voltages at BATT and OUT and
on the DC-to-DC converter’s efficiency.
Note 5: Current into BATT pin in addition to the supply current at OUT. This current is roughly constant from Coast to Run Mode.
Note 6: Current into NICD pin when NICD isn’t being charged and isn’t regulating OUT.
Note 7: Current into NICD pin when NICD is regulating OUT. Doesn’t include current drawn from OUT by the rest of the circuit.
Measured by setting the OUT regulation point to 2.8V and holding OUT at 3.0V.
Note 8: Current into NICD pin when BATT and OUT are both at 0V. This test guarantees that NICD won’t draw significant current
when the main battery is removed and backup is not activated.
Note 9: Serial-interface timing specifications are not tested and are provided for design guidance only. Serial-interface functionali-
ty is tested by clocking data in at 5MHz with a 50% duty-cycle clock and checking for proper operation. With OUT set
below 2.5V, the serial-interface clock frequency should be reduced to 1MHz to ensure proper operation.
Note 10: This specification is not directly tested but is guaranteed by correlation to LX on-resistance and current-limit tests.
Note 11: Measured by using the internal feedback network and Coast-Mode error comparator to regulate OUT. Doesn’t include
ripple voltage due to inductor currents.
Note 12: Measured by using the internal feedback network and Run-Mode error comparator to regulate OUT. Doesn’t include ripple
voltage due to inductor currents.
Note 13: Uses the OUT measurement techniques described for the OUT Error, Coast Mode, and OUT Error Run Mode specifications.
Note 14: PLL acquisition characteristics depend on the impedance at the FILT pin. The specification is not tested and is provided
for design guidance only.
Note 15: The limits in this specification are not guaranteed and are provided for design guidance only.
__________________________________________Typical Operating Characteristics
(Circuit of Figure 2, TA= +25°C, unless otherwise noted.)
100
40 1 1000
EFFICIENCY vs. LOAD CURRENT
(RUN MODE, VOUT = 3.0V)
60
50
80
90
70
MAX847TOC01
LOAD CURRENT (mA)
EFFICIENCY (%)
10 100
VIN = 2.0V
VIN = 0.8V
VIN = 1.0V
VIN = 1.2V
VIN = 1.5V
EFFICIENCY vs. LOAD CURRENT
(COAST MODE, VOUT = 3.0V)
MAX847TOC02
LOAD CURRENT (mA)
EFFICIENCY (%)
100 1000
40
50
60
80
70
90
100
0.1 1 10
VIN = 2.0V
VIN = 0.8V VIN = 1.0V
VIN = 1.2V
VIN = 1.5V
EFFICIENCY vs. LOAD CURRENT
(COAST MODE, VOUT = 2.4V)
MAX847TOC03
LOAD CURRENT (mA)
EFFICIENCY (%)
100 1000
40
50
60
80
70
90
100
0.1 1 10
VIN = 2.0V
VIN = 0.8V
VIN = 1.0V VIN = 1.2V
VIN = 1.5V
MAX847
1-Cell, Step-Up
Two-Way Pager System IC
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(Circuit of Figure 2, TA= +25°C, unless otherwise noted.)
0
20
60
40
80
100
0.5 1 1.5 2
NO-LOAD BATTERY CURRENT
vs. BATTERY VOLTAGE
MAX847-toc04
BATTERY VOLTAGE (V)
BATTERY CURRENT (mA)
VOUT = 3.0V
COAST MODE
0
100
50
200
150
250
300
0 10.5 1.5 2 2.5
MAXIMUM LOAD CURRENT vs.
BATTERY VOLTAGE
MAX847-TOC05
BATTERY VOLTAGE (V)
MAXIMUM LOAD CURRENT (mA)
RUN MODE
COAST MODE
(VOUT = 3.0V)
1 10 100
START-UP INPUT VOLTAGE
vs. LOAD CURRENT
MAX847-TOC06
LOAD CURRENT (mA)
INPUT VOLTAGE (V)
0
0.6
0.4
0.2
0.8
1.0
1.2
1.4
1.6
1.8
2.0
VOUT = 3.0V
COAST MODE
0
5
15
10
20
25
0 21 3 4 5 6
NICD CHARGING CURRENT vs.
NICD VOLTAGE
MAX847-TOC7
OUTPUT VOLTAGE (V)
NICD CHARGING CURRENT (mA)
15mA MODE
VOUT = 4.9V
20
-80 100 200 300 400 500 600
LX NOISE SPECTRUM
(RUN MODE, SYNC OPERATION)
-60
MAX847-09
FREQUENCY (kHz)
NOISE (dBV)
-40
-20
0
0
2
1
3
0 21 3 4 5
DR1 OR DR2 ON-RESISTANCE vs. VOUT
MAX847-toc08
VOUT VOLTAGE (V)
RON (Ω)
100
00.1 1 10 100 1000 10,000
REG2 NOISE SPECTRUM
(RUN MODE)
20
MAX847TOC-10
FREQUENCY (kHz)
NOISE (dBµV)
40
60
80
MAX847
1-Cell, Step-Up
Two-Way Pager System IC
_______________________________________________________________________________________ 7
______________________________________________________________Pin Description
CH0 is compared to a 7-bit DAC that adjusts from 0.2V to 1.27V. The comparison result is sent to the
CH0 OUT register.
CH09
Reset Input. Triggers RSO and resets IC when input is below 0.6V. Comparator with hysteresis (18mV).RSIN 10 Low-Battery Input. Triggers LBO and internal serial bit.LBI11 An external RC network sets the PLL loop response (at SYNC) to adjust frequency lock time versus jit-
ter: 1nF II (22nF + 10kΩ). Connect to REF when SYNC is not used.
FILT12
Sync Input for PWM Switch Rate. A 38.4kHz input results in a 268.8kHz PWM rate (7 times the sync
frequency).
SYNC13
Serial Clock for SPI InterfaceSCL5 Open-Drain Output for LBI ComparatorLBO 6 Reset Output. Open drain goes low when RSIN drops below 0.6V. All serial registers are reset (or set)
to POR state as well.
RSO7
1.28V Reference. Bypass with a 1µF capacitor.REF8
Power Ground. Source of LX1 NFET.PGND4 Serial Data Output for SPI InterfaceSDO3
PIN
Serial Data Input for SPI InterfaceSDI2
Connect LX1 to the inductor. LX1 is internally connected to an NFET that switches to PGND and a PFET
that switches to OUT.
LX11
FUNCTIONNAME
Resistor sets offset between OUT (or REG1 or any other point) and REG2. ROFS = 15kΩresults in
150mV.
OFS14
Analog GroundAGND15 Ground for DR1 and DR2 FET SourcesDRGND16 Open-Drain FET Switch. Activated via the serial-interface bit.DR117 Logic Input. ANDed with the DR2ON bit to control the DR2 switch.DR2IN18 Open-Drain FET. On via AND of the DR2ON bit and the DR2IN pin.DR219 1V, 2mA Regulator Output. On via the serial interface. Low noise.REG320 24mA REG2 Output. Linearly regulated to the voltage at the OFS pin (voltage difference =
10µA ·ROFS). REG2 isolates noise.
REG221
REG2 Input. Connect to OUT, REG1, or another voltage source.R2IN22
15mA or 1mA Settable Charge Current from OUT to 3-Cell NICD Stack. When the NICD_REG_ON bit is
set (Table 2), NICD becomes an input to the linear regulator at OUT, and the DC-DC converter is off.
NICD23
PFET output connected to OUT. Output is clamped such that it cannot rise above 3.3V, regardless of
the voltage set at OUT.
REG124
DC-DC Converter Output and Feedback Point. Digitally controlled from 1.8V to 4.9V in 100mV steps
(Table 6).
OUT25
Positive Connection to Battery. The IC is powered from OUT. BATT26
Chip Select for SPI Serial Interface
CS
27
Run/Coast. Permits toggling between Run and Coast Modes via logic signal. Run is selected when
either RUN or the internal RUN/COAST bit is high. Coast is selected when both are low.
RUN28
MAX847
1-Cell, Step-Up
Two-Way Pager System IC
8 _______________________________________________________________________________________
LBO
LBI
CH0
0.6V
CH0
RUN/
COAST
OV0–OV4
SERIAL
I/O
CH1
CH2CP2
CP1
CP0
S1
7DAC0–DAC7
RESET
CONTROL
V FEEDBACK
CHARGE
NICD
OR
BACKUP
REGULATOR
PWM
(PFM IN
COAST)
CHG/REG
+
–
CPLB
N
6
11
25 27
SDOSDISCL
3 26
9
REF
0.6V
1µF
10µA3.3V
1.0V
REG3
1µF
8
RSIN 10
17 18 19 16 15
20
21
14
DR1 DR2IN DR2 DRGND
N
1.8Ω1.8Ω
REG2 ON
REG3 ON
N N
P
P
N
P
7
+
–
+
–
+
–
FROM
NICD
FROM
BATTERY
7-BIT
CH
DAC
5
5
REG2
REG1
R2IN COFS
0.1µF
OFS
NICD
ROFS
15k
10µF
10µF
OUT
SYNC
FILT
PGND
LX1
BATT
1-CELL
BATTERY IN L1
22µH
22µF
47µF
+
–
AOUT
+
–
CPRS
CS
28
RUN
1.28V
REFERENCE
1.0V
+
–
AR3
BACKUP
REGULATOR
CLAMP ON WHEN
OV4 = 1
3.3V
CLAMP
1mA/
15mA
CHARGE
P
+
–
AR2
+
–
AR1
AGND
22
23
24
25
13 1nF 22nF
10k
12
4
1
x7
PLL
LBO
RSO
MAX847
Figure 1. Functional Diagram
______________ Detailed Description
The MAX847 contains several functional blocks that
simplify the integration of power-supply and monitoring
functions within a 1-cell powered system. They are
described in the following subsections.
Voltage Regulators
Regulator outputs include the following:
• OUT: Main switch-mode boost output
•REG1: 1.5Ωswitch and output voltage clamp. Switches
REG1 to OUT and clamps REG1 at 3.3V when OUT
is set to 3.4V or more.
•REG2: Linear-regulated, 24mA low-noise output that
regulates so that VOUT - VREG2 is a set difference
voltage (10µA •ROFS). Output peak-to-peak ripple is
typically 2mV with a 10µF bypass capacitor at REG2.
REG2 clamps output at 3.3V.
•REG3: Low-noise, 1V linear regulator that supplies
2mA.
Main DC-DC Boost Converter (OUT)
OUT is the main DC-DC converter’s output. It supplies
current from the internal synchronous-rectified boost reg-
ulator and needs no external FETs or voltage-setting
resistors. The output voltage (VOUT) is adjusted from
1.8V to 4.9V in 100mV steps (Tables 2 and 6) by internal
DAC control using a serial-data command. OUT can
supply up to 80mA, less the current supplied to the other
regulators (REG1, REG2, and REG3).
OUT can also be put into a low-current, pulse-skipping
Coast Mode (13µA typical quiescent current) by reset-
ting the RUN/COAST serial input bit and holding the
RUN pin at 0V. OUT supplies up to 40mA in Coast
Mode. Typically, when changing from Run to Coast
Mode, a lower OUT voltage is also set (Table 5) to fur-
ther reduce system operating current. The extent of this
reduction depends on the minimum operating voltage
of the system components when they are in standby or
sleep states.
MAX847
1-Cell, Step-Up
Two-Way Pager System IC
_______________________________________________________________________________________ 9
MAX847
AA ALKALINE
BATT
26 1
11
6
9
27
5
2
3
25
4
24
22
14
21
20
10
7
23
15
3.0V LOGIC
R6
2.85V ANALOG
TO RF PA
3-CELL
NiCd
ROFS
15k
1V
RCVR
OUT
PGND
REG1
R2IN
OFS
REG2
L1
22µH
MBRO52OL
C1
47µF
C6
0.1µF
CERAMIC
C2
10µF
C3
10µF
C4
1µF
TO µC RESET
R3
1.3M
R6
R4
470k
C7
COFS
0.1µF
C10
1nF C9
22nF
R7
10kΩC8
0.1µF
C5
22µF
SERIAL
I/O
A/D IN
17
19
18
16
1312
8
28
1.8Ω
DRIVERS
38.4kHz
REG3
RSIN
RSO
NICD
AGNDRUN
LBI
R1
330k
R2
470k
R5
REG1
LBO
CH0
CS
SCL
SDI
SDO
DR1
DR2
DR2IN
DRGND
SYNC
FILT
REF
RUN COAST
LX1
Figure 2. Standard Application Circuit
MAX847
OUT can be set as low as 1.8V; however, some run
mode functions are limited when VOUT is below 2.5V:
• The allowed serial-interface clock rate is reduced.
• Internal LX FET and DR1 and DR2 on-resistance
increases.
Logic Supply (REG1)
REG1 is not a regulator in the conventional sense, but
rather a 1.5ΩPFET that acts as either a switch or a volt-
age clamp, depending on the programmed OUT volt-
age. When OUT is set to 3.3V or less, REG1 operates
as a switch. When OUT is set to 3.4V or more, the
REG1 output clamps at 3.3V. This arrangement limits
VREG1 to an acceptable voltage for logic when OUT is
programmed to a higher voltage (typically >4V) for
charging (see
Charger Circuit
and
Backup Linear
Regulator
sections).
Low-Noise Analog Supply (REG2)
REG2 is a linear, 24mA low-dropout regulating circuit
whose input is R2IN. The REG2 output (VREG2) is set by
ROFS. ROFS does not set an absolute voltage, but rather
an offset level from R2IN (Figure 2). VREG2 is set by:
VREG2 = VR2IN - 10µA ·ROFS
Typically R2IN and ROFS are tied to OUT, in which
case: VOUT - VREG2 = 10µA ·ROFS
ROFS adjusts VOUT - VREG2 to allow REG2 noise rejec-
tion to be traded for voltage drop and consequent effi-
ciency loss. A 15kΩ(typical) ROFS value sets a 150mV
voltage difference. R2IN typically is supplied from OUT
or REG1 but can be connected elsewhere as long as the
voltage applied to R2IN does not exceed VOUT. For low-
est output noise on REG2, connect R2IN to REG1.
Note that the REG2 output also clamps at 3.3V.
Low-Noise, 1V Analog Supply (REG3)
REG3 is a 1V, low-noise linear regulator that supplies up
to 2mA. REG3’s input is internally connected to REG2.
PWM Frequency Synchronization
The MAX847 DC-DC converter operates with or without
a clock at the SYNC input. If a SYNC clock is used, a
PLL filter network must be connected at FILT (see R7,
C9, and C10 in Figure 2). The DC-DC converter (in
Run Mode) operates at 7fSYNC. The MAX847 is
designed for a 38.4kHz SYNC clock and hence a
268.8kHz switching frequency. If a SYNC clock is not
used then FILT must be tied to REF and R7, C9, and
C10 should be omitted. Note that if a SYNC clock is not
used, and FILT is
not
connected to REF, the MAX847
will not enter Run Mode.
With no SYNC clock, and FILT tied to REF, the DC-DC
converter nominally operates at 270kHz when in Run
Mode. The Run Mode switching frequency has no rela-
tion to the serial-data clock rate.
On initial power-up, the MAX847 is designed to start in
Coast Mode, with Run Mode normally commanded by
system via the serial interface, or the RUN pin, after the
system has started. Under some circumstances, the
MAX847 may power up in Run Mode. These circum-
stances are:
1) If a SYNC clock is not used (REF tied to FILT).
2) If the SYNC clock is used and is provided at initial
power-up when REG1 is 1.5V or higher.
3) If the SYNC clock is used, the connection shown in
Figure 3 is added, and the SYNC clock is present
when RSO is cleared (logic high).
These choices are outlined in Table 1.
Voltage Detectors (LBO and Reset)
The MAX847 contains two voltage-detector inputs: LBI
and RSIN. The LBI and RSIN comparator outputs are
open-drain pins (LBO and RSO) for a real-time hard-
ware output. LBO is also readable via the serial inter-
face. Both LBI and RSIN trigger at a 0.6V input
threshold and have about 18mV hysteresis. RSO also
triggers the MAX847 internal power-on reset (POR).
7-Bit ADC (CH0 Input and CH1, CH2)
Three analog channels are compared to a 7-bit, serially
programmed digital-to-analog converter (CH DAC). The
CH DAC voltage can be varied in 10mV steps from
200mV to VREF - 1LSB (or 1.27V) (Table 2). CH0 is an
external input, while CH1 and CH2 are signals internally
generated from the NICD and BATT pins. NICD is inter-
nally divided by four before being compared to CH
DAC, while BATT directly connects to CH2.
1-Cell, Step-Up
Two-Way Pager System IC
10 ______________________________________________________________________________________
MAX847
2N2907
Q1
OUT
FILT
RSO
25
12
7
C1
R8
1M R6
1M
Figure 3. Add PNP to allow start-up in Run Mode before the
SYNC input clock is active.
The comparison threshold voltages for each channel
are described in the following equations:
VTH(CH0: pin 9) = D ·10mV
VTH (CH1: NICD) = D ·40mV
VTH(CH2: BATT) = D ·10mV
where D is the decimal equivalent of the binary code
DAC0–DAC6 (Table 2). DAC0 is the LSB. A DAC code
of 1111111 equates to D = 127. When all zeros are pro-
grammed, the CH DAC and CH_ comparators turn off.
CH0, CH1, and CH2 comparison results reside in the
three MSB locations of the output serial data (Table 5).
The CH_ OUT data is delayed by one read cycle. In
other words, each CH_ OUT bit is the result of the com-
parison made against the CH DAC voltage pro-
grammed during the previous serial-write operation.
An analog-to-digital (A/D) conversion can be performed
on a channel by using the system software to step
through a successive-approximation routine or, if the
input is partially known, by setting the CH DAC to a
voltage near the estimated point and checking succes-
sive CH_ OUT bits.
A faster A/D shortcut can be used for battery measure-
ments when the goal is a “go, no go” determination. For
this type of test, the CH DAC can simply be set to the
desired limit, and CH_ OUT supplies the result on the
next serial-write operation. One instance in which this
shortcut saves time is during a battery-impedance
check. The unloaded battery voltage can first be mea-
sured, if time allows, using one of the techniques
described in the previous paragraph. Then the magni-
tude of the loaded voltage drop can be quickly checked
with a single comparison to see if it is within the desired
limit.
The A/D circuitry can be invoked in both Run and Coast
Mode.
Open-Drain Drivers
Two open-drain drivers (DR1 and DR2) are activated
via the serial interface. DR1 and DR2 are grounded
1.8Ω(typical) NFETs that can sink up to 120mA. The
maximum sink current is limited by on-resistance and
package dissipation to about 240mA total sink current
for both switches. Note that DR1 and DR2 are designed
to sink current only from the main battery (BATT) and
cannot be pulled above BATT.
DR2 is controlled by an external input (DR2IN) as well
as a serial input bit. DR2IN is ANDed with the DR2ON
serial-control bit, allowing DR2 to drive an audio beep-
er. The audio-frequency clock is applied to DR2IN, and
ON/OFF gating is applied to DR2ON. Both DR2IN (pin
18) and DR2ON (serial bit) must be high for DR2 to
switch on. DR1 is controlled only by DR1ON (serial bit).
Run and Coast Modes
The MAX847’s default mode is Coast. Run Mode is
selected by either serial command (Table 2) or by
pulling the RUN pin high. The RUN serial bit and the
RUN pin are logically ORed. Both must be low to imple-
ment Coast Mode. In Coast Mode, the DC-DC convert-
er pulses only as needed to satisfy the load, holding
MAX847 operating current to typically 13µA. In Run
Mode the DC-DC converter employs fixed-frequency
MAX847
1-Cell, Step-Up
Two-Way Pager System IC
______________________________________________________________________________________ 11
Table 1. Run and Coast Mode Start-Up Requirements
SYNC OPERATION CIRCUIT CONNECTION START-UP MODE CAPABILITY
No SYNC clock is used. 1) Connect REF to FILT
2) Remove R7, C9, and C10
Can start in either Coast or Run Mode
by tying RUN pin appropriately. In Run
Mode the DC-DC converter operates at
270kHz.
On initial power-up, system can supply
SYNC clock to MAX847 when REG1 is
greater than 1.5V. Use standard Figure 2 circuit
Can start in either Coast or Run Mode
by tying RUN pin appropriately. In Run
Mode the DC-DC converter operates at
7fSYNC once the SYNC clock is applied.
On initial power-up, system can supply
SYNC clock to MAX847 before, or
concurrent with, RSO going high. Add Q1 as shown in Figure 3
Can start in either Coast or Run Mode
by tying RUN pin appropriately. In Run
Mode the DC-DC converter operates at
7fSYNC once the SYNC clock is applied.
On start-up, system does not supply
SYNC clock to MAX847 until after RSO
goes high. Use standard Figure 2 circuit
Must start in Coast Mode.
Run Mode may
then be started by the system after start-up.
MAX847
pulse width modulation (PWM), as well as synchroniza-
tion, to minimize noise.
Some MAX847 functions are confined to Run Mode
while others remain active in both Run and Coast.
These are outlined as follows.
Various circuit functions can be disabled as follows:
Functions that
always remain on are:
• Serial I/O
• Reference (REF)
• OUT
• REG1
• LBI, RSIN (and LBO, RSO)
Functions that can be
programmed on or off
are (Table 1):
•DR1 and DR2
• REG2 and REG3
• NICD charger (Note: This may overload OUT if
turned on in Coast Mode when other loads are
present)
•NICD backup regulator
• CH0, CH1, CH2 and CH DAC
Functions that
always turn off in Coast Mode
are:
• SYNC and PLL circuits
• DC-DC PWM control circuits
Power-On Reset
The MAX847 has an internal POR circuit (VOUT < 1.6V)
to ensure an orderly power-up when a battery is first
applied. This feature is separate from the RSO com-
parator; however, if RSO goes low during operation, all
serial registers are set to the same predetermined
states as on power-up. The POR states for each regis-
ter are listed in Table 3.
Note that the MAX847 always comes out of reset in
Coast Mode; consequently, it cannot supply full power
until Run Mode is selected by either the RUN pin or ser-
ial command. System software cannot exercise full load
current until Run Mode is enabled.
Charger Circuit
A charger current source from OUT to NICD is activat-
ed via a serial bit (Table 2). The current source can
charge a small 3-cell NICD or NIMH battery (typically
coin cell) or a 1-cell lithium battery. The charge current
can be set to either 15mA or 1mA. When both 15mA
and 1mA are set, the charger runs at 15mA. OUT sets
the maximum charge (or float) voltage. When charging
is implemented, VOUT must also be set high enough to
allow sufficient headroom for the charger current
source. The VOUT - VNICD difference should normally
be between 0.2V and 0.5V. Charger current vs. output
voltage is graphed in the
Typical Operating
Characteristics
. Note also that charging current
reduces the OUT current available for other loads.
1-Cell, Step-Up
Two-Way Pager System IC
12 ______________________________________________________________________________________
R2 (MSB) R0 D3 D1
0 0 DR1_ON REG2_ON
0 1 LBO_Sets_
BACKUP 15mA_CHG
0 0 OV3 OV1
0 1 X X
Table 2. Serial-Bit Assignments
R1
0
0
1
1
D4
DR2_ON
X
OV4
X
D2 D0
RUN/
COAST
1mA_CHG
OV0
X
REG3_ON
BACKUP
OV2
X
1 DAC5 DAC3 DAC1DAC6 DAC4 DAC0DAC2
Table 3. Serial-Bit Power-On-Reset (POR) States
R2 R0 D3 D1
0 0 POR = 0 POR = 0
0 1 POR = 0 POR = 0
0 0 POR = 1 POR = 0
0 1 X X
R1
0
0
1
1
D4
POR = 0
X
POR = 0
X
D2 D0
POR = 0
POR = 0
POR = 0
X
POR = 0
POR = 0
POR = 1
X
1 POR = 0 POR = 0 POR = 0POR = 0 POR = 0 POR = 0POR = 0
Backup Linear Regulator
The BACKUP serial input bit turns on the backup regu-
lator, which sources current from NICD to OUT. This
regulator backs up OUT by using the rechargeable bat-
tery (at NICD) when the main battery (at BATT) is
depleted or removed. The backup regulator pass
device’s resistance is typically 5Ω, so it can typically
supply 20mA with only 100mV of dropout.
All DC-DC converter and charging circuitry is disabled
when the backup regulator is turned on, but all other
functions remain active. Activate BACKUP manually by
serial command, or set it to trigger automatically when
LBO goes low.
Automatic Backup
Setting the LBO_Sets_BACKUP serial bit (Table 2) pro-
grams the IC so that when LBO goes low, the backup
regulator automatically turns on without instructions
from the microprocessor (µP). When the LBO_
Sets_BACKUP bit is 0, the backup regulator is turned
on only by setting the BACKUP bit. The BACKUP bit
also overrides the LBO_Sets_BACKUP bit. Figure 4
shows the logic for this function.
If the main battery is depleted, and the NICD battery is
drained during backup, RSO goes low while the back-
up regulator is supplying OUT (if RSI is used to monitor
OUT or REG1). When RSO falls, the serial registers
reset to their POR states (with the DC-DC converter on
in Coast Mode and the backup regulator off, Tables 2,
3, and 4). This prevents the IC from getting hung up
with the DC-DC converter off when a new main battery
is inserted. This sequence is required because if the
MAX847 did not default to “DC-DC converter on” when
coming out of reset, the µP (still reset by RSO) would
not be able to provide the device with serial instructions
to turn on.
Serial Interface
The MAX847 has an SPI-compatible serial interface.
The serial-interface lines are Chip Select (CS), Serial
Clock (SCL), Serial Data In (SDI), and Serial Data Out
(SDO). Serial input data is arranged in 8-bit bytes. Most
bytes contain a 3-bit address pointer (R2, R1, R0)
along with 5 bits of input data (D4–D0). For common
operations such as selecting Run or Coast Mode, acti-
vating REG2 or REG3, or turning on DR1 or DR2, only
the 000 (R2, R1, R0) address register needs to be writ-
ten. The serial input data format for all MAX847 opera-
tions is outlined in Tables 2, 3, and 4.
MAX847
1-Cell, Step-Up
Two-Way Pager System IC
______________________________________________________________________________________ 13
15mA_CHG
1mA_CHG
TO
CHARGER
CONTROL
TO
BACKUP
REGULATOR
BACKUP
LBO_SETS_BACKUP
LBO
Figure 4. Logic for Charger Control and BACKUP, and for
LBO_Sets_BACKUP Serial Input Bits
INPUT BIT
LBO_Sets_BACKUP 1 = Allow LBO to turn on backup regulator and disable DC-DC converter (POR state is no con-
nection between LBO and BACKUP).
OV0–OV4
RUN/COAST
Sets OUT Output Voltage (POR state is VOUT = 3.0V).
DAC0–DAC6 Sets 7-bit CH DAC voltage for A/D conversion (POR state is all zeros with DAC and compara-
tors off).
REG2_ON, REG3_ON
DR1, DR2
1mA_CHG, 15mA_CHG
FUNCTION
1 = Run Mode, 0 = Coast Mode (POR state is Coast Mode).
1 = Turn on selected regulator (POR state is off).
1 = Turn on selected switch (POR state is off).
1 = Turn on selected charge current to NICD. If both are set, the charge current is 15mA (POR
state is off).
BACKUP 1 = Turn on backup linear regulator from NICD to OUT and disable DC-DC converter (POR
state is BACKUP off). Setting this bit overrides 1mA_CHG, 15mA_CHG, and LBO_Sets_BACK-
UP (Figure 1).
Table 4. Input-Bit Function Description
MAX847
Serial data is clocked in and out MSB first. Input data is
latched on the CLK rising edge, and output data is
shifted out on the CLK falling edge. When CS goes low,
DO immediately contains the MSB output bit (D7). D6 is
not clocked out until the falling clock edge that follows
the first rising clock edge after a Chip Select. See the
timing diagrams in Figures 5 and 6.
SPI writes and reads concurrently, so it may be neces-
sary to perform dummy writes in order to read output
data. Four output data bits (D7–D4, Table 5) are sent
from SDO each time a serial operation occurs.
When R2 = 0, R0 and R1 are address pointers.
However, when R2 = 1, the 7 remaining bits (R1, R0
and D4–D0) become DAC programming bits. This vio-
1-Cell, Step-Up
Two-Way Pager System IC
14 ______________________________________________________________________________________
CS
SCL
SDO D7 D6
R1R2 D4R0 D2D3 D0D1
D5 D4 0 0 0 0
SDI
Figure 6. CS, SCL, SDO, and SDI Serial Timing
• • •
• • •
• • •
• • •
CS
SCLK
DIN
DOUT
tCSH tCSS tCL
tDS tDH
tDV
tCH
tDO tTR
tCSH
Figure 5. Detailed Serial-Interface Timing
lation of programming etiquette (R1 and R0 are some-
times address bits and other times data bits) allows the
CH DAC to be loaded with only one write operation.
Writing all zeros to the CH DAC turns it, the CH0, CH1,
and CH2 comparators, and the NICD and BATT voltage-
sensing resistors off to minimize current consumption.
This reduces current drain from OUT by about 30µA.
Applications Information
Component Selection
The MAX847 requires minimal design calculation and is
optimized for the component values shown in Figure 2.
However, some flexibility in component selection is still
allowed, as described in the following text. A list of suit-
able components is provided in Table 7.
Inductor L1 is nominally 22µH, but values from 10µH to
47µH should be satisfactory. The inductor current rat-
ing should be 500mA or more if full output current
(80mA) is needed. If less output current is required, the
inductor current rating can be reduced proportionally
but should never be less than 250mA.
Inductor resistance should be minimized for best effi-
ciency, but since the MAX847 N-channel switch resis-
tance is typically 0.45Ω, efficiency does not improve
significantly for coil resistances below 0.2Ω.
Filter capacitors C1–C4 should be low-ESR types (tan-
talum or ceramic) for lowest ripple and best noise
rejection. A high-frequency 0.1µF ceramic cap should
be used in parallel to reduce transient noise at OUT.
The values shown in Figure 2 are optimized for each
output’s rated current. Lower required output current
allows smaller capacitance values.
Resistors at the LBI and RSIN inputs set the voltage at
which the LBO and RSO outputs trigger. The voltage
threshold for both LBI and RSI is 0.6V. The resistors
required to set a desired trip voltage, VTRIP (Figure 2),
are calculated by:
R1 = R2[(VTRIP(LBO) / 0.6) - 1]
R3 = R4[(VTRIP(RSO) / 0.6) - 1]
MAX847
1-Cell, Step-Up
Two-Way Pager System IC
______________________________________________________________________________________ 15
D7 (MSB) D5 D3–D0
CH2_OUT CH0_OUT X
D6
CH1_OUT
D4
LBO
FUNCTION
CH_ OUT and LBO output bits. A 1 indicates
that the selected channel (CH_) voltage is
greater than the CH DAC voltage or that LBI is
less than 0.6V.
Table 5. Serial Output Data
SERIAL-DATA BIT
OV4 OV2 OV0
0 0 0
0 0 1
OV3
0
0
OV1
0
0
VOUT
(V)
1.8
1.9
0 0 00 1 2.0
0 0 10 1 2.1
0 1 00 0 2.2
0 1 10 0 2.3
0 1 00 1 2.4
0 0 01 0 2.6
0 0 11 0 2.7
0 0 01 1 2.8
0 0 11 1 2.9
0 1 01 0 3.0
0 1 11 0 3.1
0 1 01 1 3.2
0 1 11 1 3.3
1 0 00 0 3.4
1 0 10 0 3.5
1 0 00 1 3.6
1 0 10 1 3.7
1 1 00 0 3.8
1 1 10 0 3.9
1 1 00 1 4.0
1 1 10 1 4.1
1 0 01 0 4.2
1 0 11 0 4.3
1 0 01 1 4.4
1 0 11 1 4.5
1 1 01 0 4.6
1 1 11 0 4.7
1 1 01 1 4.8
1 1 11 1 4.9
0 1 10 1 2.5
Table 6. VOUT Output Voltage
MAX847
1-Cell, Step-Up
Two-Way Pager System IC
16 ______________________________________________________________________________________
To minimize battery drain, use large values for R2 and
R4 (>100kΩ) in the above equations; 470kΩis a good
starting value.
See the
Low-Noise Analog Supply (REG2)
section for
information on selecting ROFS.
Since LBO and RSO are open-drain outputs, pull-up
resistors (R5, R6) are usually required. Normally these
will be pulled up to REG1. 100kΩis recommended as a
compromise between response time and current drain,
although other values can be used. Since LBI and RSO
are high (open circuit) during normal operation, current
normally does not flow in R5 and R6 until a low-battery
or reset event occurs.
Logic Levels
Note that since the MAX847’s internal logic is powered
from REG1, the input logic levels at the digital inputs:
DR2IN, RUN, SYNC, CS, SCL, and SDI, as well as the
logic output levels of SDO, are governed by the voltage
of REG1. Logic high inputs at these pins should not
exceed VREG1. Digital inputs should either be driven
from external logic (or a µP) powered from REG1, or by
open-drain logic devices that are pulled up to REG1.
Board Layout and Noise Reduction
The MAX847 makes every effort in its internal design to
minimize noise and EMI. Nevertheless, prudent layout
practices are still suggested for best performance.
Recommendations include:
1) Keep trace lengths at L1 and LX1, as well as at
PGND, as short and as wide as possible. Since LX1
swing between VBAT and VOUT at a high rate, mini-
mizing LX1 trace length serves to reduce the PC
board area that can act as an antenna.
2) The filter capacitors at OUT, REG1, REG2, and
REG3 should be placed as close as possible to
their respective pins (no more than 0.5mm away).
3) A shielded inductor at L1 will minimize radiation
noise, but may not be essential. Toroids will also
exhibit EMI performance similar to that of shielded
coils.
4) The LX1, OUT, and PGND pins are located at the
uppermost part of the IC to facilitate PC layout.
Keep power components in this area to minimize
coupling to other parts of the circuit. Other pins in
this area are digital and are not affected by close
proximity to switching nodes.
5) Use a separate short wide ground trace for PGND
and the ground side of the BATT and OUT filter
capacitors. Tie this trace to the ground plane.
Table 7. External Components
SUPPLIER PART NO. COMMENTS
CD54-220
LQH4N220K 0.94Ω, 2.6mm high,
low current, low cost
Murata LQH3C221 0.71Ω, 2mm high, low
current, low cost
0.18Ω, 4.5mm high
Sprague 595D series
CD43-220
Tantalum
TDK NLC565050-220K 0.43Ω, 5mm high
Coilcraft DT1608C-223 0.16Ω, 3.18mm high,
shielded
AVX TPS series Tantalum
Marcon THCR series Ceramic
Sprague 595D series Tantalum
Polystor A-10300 1.5F
0.378Ω, 3.2mm high
Sumida CDRH62B-220 0.34Ω, 3mm high,
shielded
INDUCTORS (22µH)
CAPACITORS
STORAGE CAPACITOR (optional at NICD pin)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RUN
CS
BATT
OUT
REG1
NICD
AGND
R2IN
REG2
REG3
DR2
DR2IN
DR1
DRGND
OFS
SYNC
FILT
LBI
RSIN
CH0
REF
RSO
LBO
SCL
PGND
SDO
SDI
LX1
QSOP
TOP VIEW
MAX847
Pin Configuration
MAX847
1-Cell, Step-Up
Two-Way Pager System IC
______________________________________________________________________________________ 17
QSOP.EPS
Package Information
MAX847
1-Cell, Step-Up
Two-Way Pager System IC
18 ______________________________________________________________________________________
NOTES
