ATMEGA169-16AI SL710 - Atmel

2514P–AVR–07/06

Features

•High Performance, Low Power AVR® 8-Bit Microcontroller

•Advanced RISC Architecture

– 130 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

– On-Chip 2-cycle Multiplier

•Non-volatile Program and Data Memories

– 16K bytes of In-System Self-Programmable Flash

Endurance: 10,000 Wr ite/Erase Cycles

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– 512 bytes EEPROM

Endurance: 100,000 Write/Erase Cycles

– 1K byte Internal SRAM

– Programming Lock for Software Security

•JTAG (IEEE std. 1149.1 compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

•Peripheral Features

– 4 x 25 Segment LCD D ri ve r

– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode

– Real Time Counter with Separate Oscillator

– Four PWM Channels

– 8-channel, 10-bit ADC

– Programmable Serial USART

– Master/Slave SPI Serial Interface

– Universal Serial Interface with Start Condition Detector

– Programmable Watchdog Timer with Separ ate On-chip Oscillator

– On-chip Analog Comparator

– Interrupt and Wake-up on Pin Change

•Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated Oscillator

– External and Internal Interru pt Sou rces

– Five Sleep Modes: Idle, ADC Noise Reduction, Powe r-save, Power-down , and

Standby

•I/O and Packages

– 53 Programmable I/O Lines

– 64-lead TQFP and 64-pad QFN/MLF

•Speed Grade:

– ATmega16 9V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 8 MHz @ 2.7 - 5.5V

– ATmega16 9: 0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V

•Tem perature range:

– -40°C to 85°C Industrial

•Ultra-Low Power Consumption

– Active Mode:

1 MHz, 1.8V: 350µA

32 kHz, 1.8V: 20µA (including Oscillator)

32 kHz, 1.8V: 40µA (including Oscillator and LCD)

– Power-down Mode:

0.1µA at 1.8V

8-bit

Microcontroller

with 16K Bytes

In-System

Programmable

Flash

ATmega169V

ATmega169

Notice:

Not recommended in new

designs.

ATmega169/V

2514P–AVR–07/06

Pin Configurations Figure 1. Pinout ATmega169

Note: The large center pad underneath the QFN/MLF packages is made of metal and internally

connected to GND. It should be soldered o r glued to the board to ensure good mechani-

cal stability. If the center pad is left unconnected, the package might loosen from the

board.

Disclaimer Typical values contained in this datasheet are based on simulations and characteriza-

tion of other AVR microcontrollers manufactured on the same process technology. Min

and Max values will be available after the device is characterized.

PC0 (SEG12)

VCC

GND

PF0 (ADC0)

PF7 (ADC7/TDI)

PF1 (ADC1)

PF2 (ADC2)

PF3 (ADC3)

PF4 (ADC4/TCK)

PF5 (ADC5/TMS)

PF6 (ADC6/TDO)

AREF

GND

AVCC

(RXD/PCINT0) PE0

(TXD/PCINT1) PE1

LCDCAP

(XCK/AIN0/PCINT2) PE2

(AIN1/PCINT3) PE3

(USCK/SCL/PCINT4) PE4

(DI/SDA/PCINT5) PE5

(DO/PCINT6) PE6

(CLKO/PCINT7) PE7

(SS/PCINT8) PB0

(SCK/PCINT9) PB1

(MOSI/PCINT10) PB2

(MISO/PCINT11) PB3

(OC0A/PCINT12) PB4

(OC2A/PCINT15) PB7

(T1/SEG24) PG3

(OC1B/PCINT14) PB6

(T0/SEG23) PG4

(OC1A/PCINT13) PB5

PC1 (SEG11)

PG0 (SEG14)

(SEG15) PD7

PC2 (SEG10)

PC3 (SEG9)

PC4 (SEG8)

PC5 (SEG7)

PC6 (SEG6)

PC7 (SEG5)

PA7 (SEG3)

PG2 (SEG4)

PA6 (SEG2)

PA5 (SEG1)

PA4 (SEG0)

PA3 (COM3)

PA0 (COM0)

PA1 (COM1)

PA2 (COM2)

PG1 (SEG13)

(SEG16) PD6

(SEG17) PD5

(SEG18) PD4

(SEG19) PD3

(SEG20) PD2

(INT0/SEG21) PD1

(ICP1/SEG22) PD0

(TOSC1) XTAL1

(TOSC2) XTAL2

RESET

GND

VCC

ATmega169

INDEX CORNER

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Overview

The ATmega169 is a low-power CMOS 8-bit micr ocontrolle r based on the AVR enhanced RISC architectu re. By executing

powerful instructions in a single clock cycle, the ATmega169 achieves throughputs approaching 1 MIPS per MHz allowing

the system designer to optimize power consumption versus processing speed.

Block Diagram

Figure 2. Block Diagram

PROGRAM

COUNTER

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

STACK

POINTER

PROGRAM

FLASH

MCU CONTROL

SRAM

GENERAL

PURPOSE

REGISTERS

INSTRUCTION

TIMER/

COUNTERS

INSTRUCTION

DECODER

DATA DIR.

REG. PORTB

DATA DIR.

REG. PORTE

DATA DIR.

REG. PORTA

DATA DIR.

REG. PORTD

DATA REGISTER

PORTB

DATA REGISTER

PORTE

DATA REGISTER

PORTA

DATA REGISTER

PORTD

TIMING AND

CONTROL

OSCILLATOR

INTERRUPT

UNIT

EEPROM

SPI

USART

STATUS

ALU

PORTB DRIVERS

PORTE DRIVERS

PORTA DRIVERS

PORTF DRIVERS

PORTD DRIVERS

PORTC DRIVERS

PB0 - PB7PE0 - PE7

PA0 - PA7PF0 - PF7

VCC

GND

AREF

XTAL1

XTAL2

CONTROL

LINES

ANALOG

COMPARATOR

PC0 - PC7

8-BIT DATA BUS

RESET

AVCC CALIB. OSC

DATA DIR.

REG. PORTC

DATA REGISTER

PORTC

ON-CHIP DEBUG

JTAG TAP

PROGRAMMING

LOGIC

BOUNDARY-

SCAN

DATA DIR.

REG. PORTF

DATA REGISTER

PORTF

ADC

PD0 - PD7

DATA DIR.

REG. PORTG

DATA REG.

PORTG

PORTG DRIVERS

PG0 - PG4

UNIVERSAL

SERIAL INTERFACE

AVR CPU

LCD

CONTROLLER/

DRIVER

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The AVR core combines a rich instruction set with 32 general purpose working registers.

All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing

two independent registers to be accessed in one single instruction executed in one clock

cycle. The resulting ar chitectu re is more code efficient wh ile achieving th roughputs up to

ten times faster than conventional CISC microcontrollers.

The ATmega169 provides t he following featur es: 16K bytes of In-System Pro grammable

Flash with Read-While-Write capabilities, 512 bytes EEPROM, 1K byte SRAM,

54 general purpose I/O lines, 32 general purpose working registers, a JTAG interface

for Boundary-scan, On-chip Debugging support and programming, a complete On-chip

LCD controller with internal step-up voltage, three flexible Timer/Counters with compare

modes, internal and e xter na l i nterr up ts, a ser ial pr ogram mab le USART, Univer sa l Seria l

Interface with Start Condition Detector, an 8-channel, 10-bit ADC, a programmable

Watchdog Timer with internal Oscillator, an SPI serial port, and five software s electable

power saving modes. The Idle mode stops the CPU while allowing the SRAM,

Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-

down mode saves the re gister contents but freezes the Oscillator, disabling all oth er

chip functions until the next interrupt or hardware reset. In Power-save mode, the asyn-

chronous timer and the LCD controller continues to run, allowing the user to maintain a

timer base and opera te the LCD display while the rest of the device is sleeping. The

ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous

timer, LCD controller and ADC, to minimize switching noise during ADC conver sions. In

Standby mode, the crystal/resonator Oscillator is running whil e the rest of the device is

sleeping. This allows very fast start-up combined with low-po wer consumption.

The device is manufactured u sing At mel’s hig h de nsity no n- vo latile m emo ry te chno logy.

The On-chip ISP Flash allows th e program memory to be reprogrammed In-System

through an SPI serial interface, by a conventional non-volatile memory programmer, or

by an On-chip Boot program running on the AVR core. The Boot program can use any

interface to download the application program in the Application Flash memory. Soft-

ware in the Boot Flash section will continue to run while the Application Flash section is

updated, providing true R ead-While-Write operation. By combining an 8-b it RISC CPU

with In-System Self- Pro gr amm able Fl ash on a monolit hic chip, th e Atmel ATmeg a16 9 is

a powerful microcontroller that pr ovides a highly flexible and cost effective solution to

many embedded control applications.

The ATmega169 AVR is sup port ed with a fu ll suite of pr ogra m a nd system d evelo pment

tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Cir-

cuit Emulators, and Evaluation kits.

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Pin Descriptions

VCC Digital supply voltage.

GND Ground.

Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port A outp ut buf f ers have symmetr ical drive chara cter istics with both high sink

and source capability. As inputs, Port A pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port A also ser ves the funct ions of var ious special features of the ATmega169 as listed

on page 62.

Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port B outp ut buf f ers have symmetr ical drive chara cter istics with both high sink

and source capability. As inputs, Port B pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port B has better driving capabilities than the other ports.

Port B also ser ves the funct ions of var ious special features of the ATmega169 as listed

on page 63.

Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port C outp ut buff er s have symmet rica l dr ive cha racte ristics wit h bot h hi gh sink

and source capability. As inputs, Port C pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port C also serves the f un ctio ns of spe cial fe at ur es of t he ATme ga1 69 as listed o n p age

66.

Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port D outp ut buff er s have symmet rica l dr ive cha racte ristics wit h bot h hi gh sink

and source capability. As inputs, Port D pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATmega169 as listed

on page 68.

Port E (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port E outp ut buf f ers have symmetr ical drive chara cter istics with both high sink

and source capability. As inputs, Port E pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port E also ser ves the funct ions of var ious special features of the ATmega169 as listed

on page 70.

Port F (PF7..PF0) Port F serves as the analog inputs to the A/D Converter.

Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used.

Port pins can provide internal pull-up resistors (selected for each bit). The Port F output

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buffers have symmetrical drive characteristics with both high sink and source capability.

As inputs, Port F pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port F pins are tri-stated when a reset condition becomes

active, even if the clock is not ru nning. If the JT AG interfa ce is enabled, th e pull-up resi s-

tors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset

occurs.

Port F also serves the functions of the JTAG interface.

Port G (PG4..PG0) Port G is a 5-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port G o utput b uffers have symmetrical d rive charac teristics with both hig h sink

and source capability. As inputs, Port G pins that ar e externally pulled low will source

current if the pu ll-up resistors are a ctivated. The Port G pin s are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port G also serves the functions of various special features of the ATmega169 as listed

on page 70.

RESET Reset input. A low level on this pin for longer than the minimum pulse length will gener-

ate a reset, even if the clock is not running. The minimum pulse length is given in Table

16 on page 38. Shorter pulses are not guaranteed to generate a reset.

XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

XTAL2 Output from the inverting Oscillator amplifier.

AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally

connected to VCC, even if the ADC is not used. If the ADC is used, it should be con -

nected to VCC through a low-pass filter.

AREF This is the analog reference pin for the A/D Converter.

LCDCAP An external capacitor (typical > 470 nF) must be connected to the LCDCAP pin as

shown in Figure 98. This capacitor acts as a reservoir for LCD power (VLCD). A large

capacitance reduces ripple on VLCD but increases the time until VLCD reaches its target

value.

About Code

Examples This documentation con tains simple code examples t hat briefly show how to use various

parts of the device. Be awar e that not all C co mpiler vendors inclu de bit definit ions in the

header files and interrupt handling in C is compiler depende nt. Please confirm with the

C compiler documentation for more details.

These code examples assume that the part specific header file is included before com-

pilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC",

"CBI", and "SBI" instructions must be replaced with instructions that allow access to

extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and

"CBR".

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AVR CPU Core

Introduction This section discusses the AVR core architecture in general. The main function of the

CPU core is to ensure correct program execution. The CPU must therefore be able to

access memories, perform calculat ions, control peripherals, and handle interrupts.

Architectural Overview Figure 3. Block Diagram of the AVR Arc hit ect ure

In order to maximize per for man ce and parallelism, the AVR uses a Harvard archit ecture

– with separate memories and buses for program and data. Instructions in the program

memory are executed with a single level pipelining. While one instruction is be ing exe-

cuted, the next instruction is pre-fetched from the program memory. This concept

enables instructions to be executed in every clock cycle. The program memory is In-

System Reprog ra m m ab le Fla sh me mo r y.

The fast-access Register File contains 32 x 8-bit general purpose working registers with

a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU)

operation. In a typical ALU operation, two operands are output from the Register File,

Flash

Program

Memory

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registrers

ALU

Status

and Control

I/O Lines

EEPROM

Data Bus 8-bit

Data

SRAM

Direct Addressing

Indirect Addressing

Interrupt

Unit

SPI

Unit

Watchdog

Timer

Analog

Comparator

I/O Module 2

I/O Module1

I/O Module n

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the operation is executed, and the result is stored back in the Register File – in one

clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for

Data Space addressing – enabling efficient address calculations. One of the these

address pointers can also be used as an ad dress pointer for look up tables in Flash pro-

gram memory. These added function registers are the 16-bit X-, Y-, and Z-re gister,

described later in this section.

The ALU supports arithmetic and logic operations between registers or between a con-

stant and a register. Single register operations can also be executed in the ALU. After

an arithmetic operation, the Status Register is updated to reflect information about the

result of the ope ratio n.

Program flow is provided by conditional and unconditional jump and call instructions,

able to directly address the whole address space. Most AVR instructions have a single

16-bit word format. Every program memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot Program section and

the Application Program section. Both sections have dedicated Lock bits for write and

read/write pro tec tio n. The SPM inst ru ction th at wr ite s into th e Applica tion Flash me mor y

section must reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is

stored on the Stack. The Stack is effectively allocated in the general data SRAM, and

consequently the Stack size is only limited by the total SRAM size and the usage of the

SRAM. All user programs must initialize the SP in the Reset routine (before subroutines

or interrupts are executed) . The Stack Pointer (SP) is read/write accessible in the I/O

space. The data SRAM can easily be accessed through the five different addressing

modes supported in the AVR architecture.

The memory spaces in the AVR architectur e are all linear and regular memory maps.

A flexible interrupt modu le has its control registers in the I/O space with an additional

Global Interrupt Enable bit in the Status Register . All interrupts have a sepa rate Interrupt

Vector in the Interrupt Vector table. The interrupts have priority in accordance with their

Interrupt Vector position. The lower the Interr upt Vector address, the higher the priority.

The I/O memory space contains 64 ad dresses for CPU peripheral functions as Control

Registers, SPI, and o ther I/O fu nctions. Th e I /O Memory can be accesse d directly, or as

the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition,

the ATmega16 9 has Extended I/O spac e from 0x60 - 0xFF in SRAM where only the

ST/STS/STD and LD/LDS/LDD instructions can be used.

ALU – Arithmetic Logic

Unit The high-perfo rmance AVR ALU operates in di rect connection with all th e 32 general

purpose workin g registers. Within a single clock cycle, arithme tic operations between

general purpose registe rs or between a register and an immediate are executed. The

ALU operations are divided int o thre e main cate gor ies – ar ithmet ic, logical, and bi t-f unc-

tions. Some implementations of the architecture also provide a powerful multiplier

supporting both signed/unsigned multiplication and fractional format. See the “Instruc-

tion Set” section for a det ailed description.

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Status Register The Status Register contains information about the result of the most recently executed

arithmetic instruction. This information can be used for altering program flow in order to

perform conditional opera tions. Note that the Status Register is updated after all ALU

operations, as specified in the Instruction Set Reference. This will in many cases

remove the need for using the de dicated compare instructions, resulting in faster an d

more compact code.

The Status Register is not automatically stored when entering an interrupt routine and

restored when returning from an interrupt. This must be handled by software.

The AVR Status Register – SREG – is defined as:

• Bit 7 – I: Globa l Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individ-

ual interrupt enable control is then performed in separate control registers. If the Global

Interrupt Enable Register is cleared, none of th e interrupts are enabled independent of

the individual interrupt ena ble settings. The I- bit is cleared by hardware aft er an interrupt

has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-

bit can also be set an d cleared by the application with the SEI and CLI instru ctions, as

described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instruction s BLD (Bit LoaD) an d BST (Bit STore) u se the T-bit a s source or

destination for the operated bit. A bit from a registe r in the Register File can be copied

into T by the BST instru ction, and a bit in T can be copied into a bit in a register in the

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic oper ations. Half Ca rry Is

useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N ⊕ V

The S-bit is always an exclusive or between th e Negative Flag N and the Two’s Comple-

ment Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V sup ports two’s complement arithmetics. See

the “Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See

the “Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the

“Instruction Set Description” for detailed information.

Bit 76543210

ITHSVNZCSREG

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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• Bit 0 – C: Ca rry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruc-

tion Set Description” for detailed information.

General Purpose

achieve the required performance and flexibility, the following input/output schemes are

supported by the Register File:

• One 8-bit output op erand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands an d on e 16 -b it result input

• One 16-bit output operand and one 16-bit result input

Figure 4 shows the structure of the 32 general purpose working registers in the CPU.

Figure 4. AVR CPU General Purpose Work ing Registers

Most of the in structions op erating on the Registe r File have d irect access to all re gisters,

and most of them are single cycle instructions.

As shown in Figure 4, each register is also assigned a data memory address, mapping

them directly int o the fir st 3 2 loca t ions o f the user Dat a Space. Althou gh not b eing phys-

ically implemented as SRAM locations, this memory organization provides great

flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to

index any register in the file.

7 0 Addr.

R0 0x00

R1 0x01

R2 0x02

…

R13 0x0D

General R14 0x0E

Purpose R15 0x0F

Working R16 0x10

Registers R17 0x11

…

R26 0x1A X-register Low Byte

R27 0x1B X-register High Byte

R28 0x1C Y-register Low Byte

R29 0x1D Y-register High Byte

R30 0x1E Z-regist er Low Byte

R31 0x1F Z-re gi ster High Byte

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The X-register, Y-register, and

Z-register The registers R26..R31 have some added functions to their general purpose usage.

These registers are 16-bit address pointers for indirect addressing of the data space.

The three indirect address registers X, Y, and Z are de fined as described in Figure 5.

Figure 5. The X-, Y-, and Z-regi sters

In the different addressing modes these address registers have functions as fixed dis-

placement, automatic increment, and automatic decrement (see the instruction set

reference for details).

Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for

storing return addresses after interrupts and subroutine calls. The Stack Pointer Regis-

ter always points to the to p of the Sta ck. Note that the Stack is imple mente d as growin g

from higher memory locations to lower memory locations. This implies that a Stack

PUSH command decreases the Stack Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Inter-

rupt Stacks are loc ated. This Stack space in th e data SRAM must be defined b y the

program before any subroutine calls are executed or interrupts are enabled. The Stack

Pointer must be set to p oint above 0xFF. The Stack Pointer is d ecremented by one

when data is pushed ont o the Stac k with the PUSH inst ruct ion, and it is decrement ed by

two when the return address is pushed onto the Stack with subroutine call or interrupt.

The Stack Pointer is incremented by one when data is popped from the Stack with the

POP instruction, and it is incremented by two when data is popped from the Stack with

return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implem ented as two 8- bit re gisters in the I/O space. The n um-

ber of bits actually used is implemen tatio n depen den t . Note th at the data space in some

implementations of the AVR architecture is so small that only SPL is needed. In this

case, the SPH Register will not be present.

15 XH XL 0

X-register 707 0

R27 (0x1B) R26 (0x1A)

15 YH YL 0

Y-register 707 0

R29 (0x1D) R28 (0x1C)

15 ZH ZL 0

Z-register 70 7 0

R31 (0x1F) R30 (0x1E)

Bit 151413121110 9 8

– – – – – SP10 SP9 SP8 SPH

SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

00000000

ATmega169/V

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Instruction Execution

Timing This section describes the g enera l access timing con cepts for instr uction execut ion. The

AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock

source for the chip. No internal clock division is used.

Figure 6 shows the pa rallel instru ction fetches an d instructio n executions enabled b y the

Harvard archit ecture an d the f ast-access Register File co ncept. Th is is the basic pipelin-

ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results for

functions per cost, functions per clocks, and functions per power-unit.

Figure 6. The Parallel Instruction Fetches and Instruction Executions

Figure 7 shows the internal timing concept for the Register File. In a single clock cycle

an ALU operation using two register operands is executed, and the result is stored back

to the destination register.

Figure 7. Single Cycle ALU Operation

Reset and Interrupt

Handling The AVR provides several differ en t in terr up t sou rces. These in te rrupt s and the sepa ra te

Reset Vector ea ch have a separate program vector in the program memor y space. All

interrupts are assigned individual enable bits which must be written logic one together

with the Global Interrupt En able bit in the Status Re gister in order to enable the interrupt.

Depending on the Program Counter value, interrupts may be automatically disabled

when Boot Lock bits BLB02 or BLB12 ar e program med. Th is feature imp roves so ftware

security. See the section “Memory Programming” on page 266 for details.

The lowest addresses in the program memory sp ace are by default defined as th e Reset

and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 46.

The list also determines the priority levels of the different interrupts. The lower the

address the higher is the priority level. RESET has the highest priority, and next is INT0

– the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of

the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR).

Refer to “Interrupts” on page 46 for more information. The Reset Vector can also be

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

T1 T2 T3 T4

CPU

Total Execution Time

egister Operands Fetch

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

clkCPU

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moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see

“Boot Loader Support – Read-While-Write Self-Programming” on page 252.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts

are disabled. The user software can write logic one to the I-bit to enable nested inter-

rupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is

automatically set when a Return from Interrupt instruct ion – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that

sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the

actual Interrupt Vector in order to execute the interrupt handling routine, and hardware

clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a

logic one to th e flag bit posit ion(s) to be clear ed. If an inte rrupt condition occurs while the

corresponding interru pt enable bit is cleared, the Interrupt F lag will be set and remem-

bered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or

more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the cor-

responding Interrupt Flag(s) will be set and remembered until the Global Interrupt

Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present.

These interrupts do not necessarily have Inte rrupt Flags. If the interrupt condition disap-

pears before the interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and exe-

cute one more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt rou-

tine, nor restored when returning from an interrupt routine. This must be handled by

software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately

disabled. No interrupt will be executed after the CLI instr uction, even if it occurs simulta-

neously with the CLI instruction. The following example shows how this can be used to

avoid interrupts during the time d EEPROM write sequence.

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMWE ; start EEPROM write

sbi EECR, EEWE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

__disable_interrupt();

EECR |= (1<<EEMWE); /* start EEPROM write */

EECR |= (1<<EEWE);

SREG = cSREG; /* restore SREG value (I-bit) */

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When using the SEI instruction to enable interrupts, the instruction following SEI will be

executed before any pending interrupts, as shown in this example.

Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles

minimum. After four clock cycles the program vector address for the actual interrupt

handling routine is executed . During th is four clock cycle period, th e Progra m Counter is

pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this

jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle

instruction, this instruction is completed befo re the interrupt is served. If an interrup t

occurs when the MCU is in sleep mode, the interrupt execution response time is

increased by four clock cycles. This incr ease comes in addition to the start-up time from

the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four

clock cycles, the Progra m Cou nter (two b ytes) is poppe d b ack fr om th e Stack, th e Stack

Pointer is incremented by two, and the I-bit in SREG is set.

Assembly Code Example

sei ; set Global Interrupt Enable

sleep ; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

__enable_interrupt(); /* set Global Interrupt Enable */

__sleep(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

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AVR ATmega169

Memories This section describes the different memories in the ATmega169. The AVR architecture

has two main memory spaces, the Data Memory and the Program Memory space. In

addition, the ATmega169 features an EEPROM Memory for data storage. All three

memory spaces are linear and regular.

In-System

Reprogrammable Flash

Program Memory

The ATmega169 contains 16K bytes On-chip In-System Reprogrammable Flash mem-

ory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is

organized as 8K x 16. For software security, the Flash Program memory space is

divided into two sections, Boot Program section and Application Program section.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The

ATmega169 Program Cou nter (PC) is 13 bits wide, thus addressing the 8K program

memory locations. The operation of Boot Program section and associated Boot Lock

bits for software protection are described in detail in “Boot Loader Support – Read-

While-Write Self-Prog ramming” on page 252. “Memory Prog ramming ” on page 26 6 con-

tains a detailed des cription on Flash data serial down loading using the SPI pins or the

JTAG interface.

Constant tables can be allocated within the entire program memory address space (see

the LPM – Load Program Memory instruction description).

Timing diagrams for instruction fetch and execution are presented in “In struction Execu-

tion Timing” on page 12.

Figure 8. Program Memory Map

0x0000

0x1FFF

Program Memory

Application Flash Section

Boot Flash Section

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SRAM Data Memory Figure 9 shows how the ATmega169 SRAM Memory is or ganized.

The ATmega169 is a complex microcontroller with more peripheral units than can be

supported within the 64 locations reserved in the Opcode for the IN and OUT instruc-

tions. For the Extended I /O space from 0x60 - 0xFF in SRAM, only the ST/ST S/STD and

LD/LDS/LDD instructions can be used.

The lower 1, 280 d at a memo ry loca tio ns a ddress bo th the Regist er File , th e I/ O memo ry,

Extended I/O memory, and the internal data SRAM. The first 32 locations address the

Extended I/O memory, and the next 1024 locations address the internal data SRAM.

The five differen t addressing modes f or the data memor y cover: Direct, Indir ect with Dis-

placement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In

the Register File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base

address given by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-

increment, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Regis-

ters, and the 1,024 bytes of internal data SRAM in the ATmeg a169 are all accessible

through all th ese add ressing mode s. T he Regist er File is d escribed in “Gene ra l Pur pose

Figure 9. Data Memory Map

32 Registers

64 I/O Registers

Internal SRAM

(1024 x 8)

0x0000 - 0x001F

0x0020 - 0x005F

0x04FF

0x0060 - 0x00FF

Data Memory

160 Ext I/O Reg.

0x0100

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Data Memory Access Times This section describes the general access timing concepts for internal memory access.

The internal dat a SRAM access is perfor med in two clk CPU cycles as described in Figure

10.

Figure 10. On-chip Data SRAM Access Cycles

EEPROM Data Memor y The ATmega169 contains 512 bytes of data EEPROM memory. It is organized as a sep-

arate data space, in which single bytes can be read and written. The EEPRO M has an

endurance of at least 100,000 write/erase cycles. The access between the EEPROM

and the CPU is described in the following, specifying the EEPROM Address Registers,

the EEPROM Data Register, and the EEPROM Control Register.

For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM,

see page 281, page 285, and page 269 respectively.

EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 1. A self-timing function, how-

ever, lets the user software detect when the next byte can be written. If the user code

contains instructions that write the EEPROM, some precautions must be taken. In

heavily filtered power supp lies, VCC is likely to rise or fall slowly on power-up/down. This

causes the device for some period of time to run at a voltage lower than specified as

minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page

21. for details on how to avoid proble ms in these situations.

In order to prevent unin tentional EEPROM writes, a spe cific write proced ure must be fol-

lowed. Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next

instruction is executed. When the EEPROM is written, the CPU is halted for two clock

cycles before th e ne xt ins tru ct ion is execu te d .

clk

Data

ddress Address valid

T1 T2 T3

Compute Address

Read Write

CPU

Memory Access Instruction Next Instruction

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The EEPROM Address

• Bits 15..9 – Res: Reserved Bits

These bits are reserved bits in the ATmega169 and will always read as zero.

• Bits 8..0 – EEAR8..0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address

in the 512 bytes EEPROM space. The EEPROM data bytes are addressed linearly

between 0 and 511. The initial va lue o f EEAR is un define d. A pr ope r va lue must b e writ-

ten before the EEPROM may be accessed.

The EEPROM Data Register –

EEDR

• Bits 7..0 – EEDR7..0: EEPROM Data

For the EEPROM write operation, the EEDR R egister contains the data to be written to

the EEPROM in the address given by the EEAR Register. For the EEPROM read oper-

ation, the EEDR contains the data read out from the EEPROM at the address given by

EEAR.

The EEPROM Control Register

– EECR

• Bits 7..4 – Res: Reserved Bits

These bits are reserved bits in the ATmega169 and will always read as zero.

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set.

Writing EERIE to zero disab les t he in te rr upt. Th e EEPROM Rea dy inte rr up t gen er ates a

constant interrupt when EEWE is cleared.

• Bit 2 – EEMWE: EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be

written. When EEMWE is set, setting EEWE within four clock cycles will write data to the

EEPROM at the selected address. If EEMWE is zero, setting EEWE will have no effect.

When EEMWE has been written to on e by software, hard ware clears the bit to zero after

four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.

Bit 151413121110 9 8

–––––––EEAR8EEARH

EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

76543210

Read/WriteRRRRRRRR/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value0000000X

XXXXXXXX

Bit 76543210

MSB LSB EEDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

––––EERIEEEMWEEEWEEEREEECR

Read/Write R R R R R/W R/W R/W R/W

Initial Value000000X0

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• Bit 1 – EEWE: EEPROM Write Enable

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When

address and data are correctly set up, the EEWE bit must be written to one to write the

value into the EEPROM. The EEMWE bit must be written to one before a logical one is

written to EEWE, otherwise no EEPROM write takes place. The following procedure

should be followed when writing the EEPROM (the order of steps 3 and 4 is not

essential):

1. Wait until EEWE becomes zero.

2. Wait until SPMEN in SPMCSR becomes zero.

3. Write new EEPROM address to EEAR (optional).

4. Write new EEPROM data to EEDR (optional).

5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.

6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.

The EEPROM can not be programm ed during a CPU write to the Flash memory. The

software must check that the F lash programming is completed befor e initiating a new

EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing

the CPU to program the Flas h. If the Flash is never being updat ed by the CPU, step 2

can be omitted. See “Boot Loader Support – Read-While-Write Self-Programming” on

page 252 for details about Boot programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the

EEPROM Master Write Enable will time-out. If an interrupt routine accessing the

EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be

modified, causing the interrupted EEPROM access to fail. It is recommended to have

the Global Interrupt Flag cleared during all the steps to avoid these problems.

When the write access time has elap sed, the EEWE bit is cleared by hardware. The

user software can poll this bit and wait for a zero before writing the next byte. When

EEWE has been set, the CPU is halted for two cycles before the next instruction is

executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the

correct address is set up in the EEAR Register, the EERE bit must be written to a logic

one to trigger the EEPROM read. The EEPROM read access takes one instruction, and

the requested data is available immediately. When the EEPROM is read, the CPU is

halted for four cycle s bef or e th e ne xt ins tru ct ion is executed.

The user should poll the EEWE bit bef ore star ting the read ope ration. I f a write operation

is in progress, it is neither possible to read the EEPROM, nor to change the EEAR

The calibrated Oscillator is used to time the EEPROM accesses. Table 1 lists the typical

programming time for EEPROM access from the CPU.

Table 1. EEPROM Programming Time

Symbol Number of Calibrated RC Oscillator Cycles Typ Programming Time

EEPROM write

(from CPU) 67 584 8.5 ms

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The following code examples show one assembly and one C function for writing to the

EEPROM. The examples assume that inter rupts are controlled (e.g. by disabling inter-

rupts globally) so that no interrupts will occur during execution of these functions. The

examples also assume that no Flash Boot Loader is present in the software. If such

code is present, the EEPROM write function must also wait for any ongoing SPM com-

mand to finish.

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_write

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Write data (r16) to Data Register

out EEDR,r16

; Write logical one to EEMWE

sbi EECR,EEMWE

; Start eeprom write by setting EEWE

sbi EECR,EEWE

ret

C Code Example

void EEPROM_write(unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEWE))

;

/* Set up address and Data Registers */

EEAR = uiAddress;

EEDR = ucData;

/* Write logical one to EEMWE */

EECR |= (1<<EEMWE);

/* Start eeprom write by setting EEWE */

EECR |= (1<<EEWE);

}

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The next code examples sh ow assemb ly and C functions for read ing t he EEPROM . The

examples assume that interrupts are controlled so that no interrupts will occur during

execution of these functi ons.

EEPROM Write During Power-

down Sleep Mode When entering Power-down sleep mode while an EEPROM write operation is active, the

EEPROM write operation will continue, and will complete before the Write Access time

has passed. Ho wever, when the write opera tion is completed, the clock co ntinues run-

ning, and as a consequence, the device does not enter Power-down entirely. It is

therefore recommended to verify that the EEPROM write operation is completed before

entering Power-down.

Preventing EEPROM

Corruption During periods of low VCC, the EEPROM data can be corrupted because the supply volt-

age is too low for the CPU and the EEPROM to operate properly. These issues are the

same as for board level systems using EEPROM, and the same design solutions should

be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too

low. First, a regular write sequen ce to the EEPROM requires a minimum voltage to

operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the

supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design

recommendation:

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_read

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from Data Register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEWE))

;

/* Set up address register */

EEAR = uiAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from Data Register */

return EEDR;

}

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Keep the AVR RESET active (low) during periods of insufficient power supply voltage.

This can be done by enabling the internal Brown-out Detector (BOD). If the detection

level of the internal BOD does not match the needed detection level, an external low

VCC reset Protection circuit can be used. If a reset occurs while a write operation is in

progress, the write operation will be completed provided that the power supply voltage is

sufficient.

I/O Memory The I/O space definition of the ATmega169 is shown in “Register Summary” on page

339.

All ATmega169 I/Os and peripherals are placed in the I/O space. All I/O locations may

be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data

between the 32 general purpose working registers and the I/O sp ace. I/O Registers

within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI

instructions. In these registers, the value of single bits can be checked by using the

SBIS and SBIC instructions. Refer to the instruction set section for more details. When

using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be

used. When add ressing I/O Re gister s as dat a spac e using LD and ST instructions, 0x20

must be added to these addresses. Th e ATmega169 is a complex microcontroller with

more peripheral units than can be supported within the 64 location reserved in Opcode

for the IN an d OUT inst ruction s. F or the Ext ended I/O sp ace fro m 0x60 - 0xFF in SRAM,

only the ST/STS/STD and LD/LDS/LDD instructions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike

most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and

can therefore be used on registers containing such Status Flags. The CBI and SBI

instructions work with regist ers 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

General Purpose I/ O Regist er s The ATmega169 contains three General Purpose I/O Registers. These registers can be

used for storing any information, and they are particularly useful for storing global vari-

ables and Status Flags. General Purpose I/O Registers within the address range 0x00 -

0x1F are directly bit-accessible u sing the SBI, CBI, SBIS, and SBIC instruction s.

General Purpose I/O Register

2 – GPIOR2

General Purpose I/O Register

1 – GPIOR1

General Purpose I/O Register

0 – GPIOR0

Bit 76543210

MSB LSB GPIOR2

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

MSB LSB GPIOR1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

MSB LSB GPIOR0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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System Clock and

Clock Options

Clock Systems and their

Distribution Figure 11 presents the principal clock systems in the AVR and their distribution. All of

the clocks need not be active at a give n time. In order to reduce power con sumption, the

clocks to modules not being used can be halted by using different sleep modes, as

described in “Power Management and Sleep Modes” on page 32. The clock systems

are detailed below.

Figure 11. Clock Distribution

CPU Clock – clkCPU The CPU clock is routed to parts of the system concerned with operation of the AVR

core. Examples of such modules are th e General Purpose Register File, t he Status Reg-

ister and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the

core from performing general operations and calculations.

I/O Clock – clkI/O The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and

USART. The I/O clock is also used by the External Interrupt module, but note that some

external interrupts are detected by asynchronous logic, allo wing such interrupts to be

detected even if the I/ O clock is halted. Also note that start conditio n detection in the USI

module is carried out asynchronously when clkI/O is halted, enab ling USI start condition

detection in all sleep modes.

Flash Clock – clkFLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually

active simultaneously with the CPU clock.

Asynchronous Timer Clock –

clkASY

The Asynchronous Time r clock allows the Asynchronous Timer/Counter and the LCD

controller to be clocked directly from an external clock or an external 32 kHz clock crys-

tal. The dedicated clock domain allows using this Timer/Counter as a real-time counter

even when the device is in sleep mode. It also allows the LCD controller output to con-

tinue while the rest of the device is in sleep mode.

General I/O

Modules

Asynchronous

Timer/Counter CPU Core RAM

clk

I/O

clk

ASY

AVR Clock

Control Unit clk

CPU

Flash and

EEPROM

clk

FLASH

Source clock

Watchdog Timer

Watchdog

Oscillator

Reset Logic

Clock

Multiplexer

Watchdog clock

Calibrated RC

Oscillator

Timer/Counter

Oscillator Crystal

Oscillator Low-frequency

Crystal Oscillator

External Clock

LCD Controller

System Clock

Prescaler

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ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and

I/O clocks in order to reduce noise generated by digital circuitry. This gives more accu-

rate ADC conversion results.

Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as

shown below. The clock from the selected source is input to the AVR clock generator,

and routed to the appropriate modules.

Note: 1. F or all fuses “1” means unprogrammed while “0” means programmed.

The various choices for each clocking o ption is given in the following sections. When the

CPU wakes up from Power-down or Power-save, the selected clock source is used to

time the start-up, ensuring stable Oscillator operation before instruction execution starts.

When the CPU starts from reset, the re is an additional delay allowing the powe r to reach

a stable level before commencing normal opera tion. The Watchdog Oscillator is use d

for timing this real-time part of the start-up time. The number of WDT Oscillator cycles

used for each time-out is shown in Table 3. The frequency of the Watchdog Oscillator is

voltage dependent as shown in “ATmega169 Typical Characteristics” on page 305.

Default Clock Source The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed.

The default clock source setting is the Internal RC Oscillator with longest start-up time

and an initial system clo ck prescaling of 8 . This default set ting ensures t hat all users can

make their desired clock source setting using an In-System or Parallel programmer.

Table 2. Device Clocking Options Select(1)

Device Cloc king Option CKSEL3..0

External Crystal/Ceramic Resonator 1111 - 1000

External Low-frequency Crystal 0111 - 0110

Calibrated Internal RC Oscillator 0010

Exter nal Clock 0000

Reserved 0011, 0001, 0101, 0100

Table 3. Number of Watchdog Oscillator Cycles

Typ Ti me-out (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles

4.1 ms 4.3 ms 4K (4,096)

65 ms 69 ms 64K (65,536)

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Crystal Oscillator XTAL1 and XTAL2 are input and output , respectively, of an inver ting amplifier which can

be configured for use as an On-chip Oscillator, as shown in Figure 12. Either a quartz

crystal or a ceramic resonator may be used.

C1 and C2 should always be equal for both crystals and resonators. The optimal value

of the capacitors depends on the crystal or resonator in use, the amount of stray capac-

itance, and the electromagnetic noise of the environmen t. Some initial guidelin es for

choosing capacitors for use with crystals are given in Table 4. For ceram ic resonators,

the capacitor values given by the manufacturer should be used.

Figure 12. Crystal Oscillator Connections

The Oscillator can operate in three different modes, each optimized for a specific fre-

quency range. T he operating mode is selected by the fuses CKSEL3..1 as shown in

Table 4.

Notes: 1. This option should not be used with crystals, only with ceramic resonators.

The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown

in Table 5.

Table 4. Crystal Oscillator Operating Modes

CKSEL3..1 Frequency Range (MHz) Recommended Range for Capacitors C1

and C2 for Use with Crystals (pF)

100(1) 0.4 - 0.9 –

101 0.9 - 3.0 12 - 22

110 3.0 - 8.0 12 - 22

111 8.0 - 12 - 22

XTAL

GND

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Notes: 1. These options should only be used when not operating close to the maximum fre-

quency of the device, and only if frequency stability at start-up is not important for the

application. These options are not suitable for crystals.

2. These options are intended for use with ceramic resonators and will ensure fre-

quency stability at star t-up. They can also be used with cr ystals when not operating

close to the maximum frequency of the device, and if frequency stability at start-up is

not important for the application.

Low-frequency Crystal

Oscillator To use a 32.768 kHz wa tch crystal as the cloc k so ur ce for th e d evice, t he low-f re quency

crystal Oscillator must be selected by setting the CKSEL Fuses to “0110” or “0111”. The

crystal should be connected as shown in Figure 12. When this Oscillator is selected,

start-up times are determined by the SUT Fuses as shown in Table 6 and CKSEL1..0 as

shown in Table 7.

Table 5. Start-up Times for the Crystal Oscillator Clock Selection

CKSEL0 SUT1..0

Start-up Time from

Power-down and

Power-save

Additional Delay

from Reset

(VCC = 5.0V) Recommended Usage

0 00 258 CK(1) 14CK + 4.1 ms Ceramic resonator, fast

rising power

0 01 258 CK(1) 14CK + 65 ms Ceramic resonator,

slowly rising power

010 1K CK

(2) 14CK Ceramic resonator,

BOD enabled

011 1K CK

(2) 14CK + 4.1 ms Ceramic resonator, fast

rising power

100 1K CK

(2) 14CK + 65 ms Ceramic resonator,

slowly rising power

101 16K CK 14CK Crystal Oscillator , BOD

enabled

110 16K CK 14CK + 4.1 ms Crystal Oscillator, fast

rising power

111 16K CK 14CK + 65 ms Crystal Oscillator,

slowly rising power

Table 6. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection

SUT1..0 Additional Delay from Reset (VCC = 5.0V) Recommended Usage

00 14CK Fast rising power or BOD enabled

01 14CK + 4.1 ms Slowly rising power

10 14CK + 65 ms Stable frequency at star t-up

11 Reserved

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Note: 1. This option should only be used if frequency stability at start-up is not impor tant for

the application

Calibrated Internal RC

Oscillator The calibrated internal RC Oscillator provides a fix ed 8.0 MHz clock. The frequency is

nominal value at 3V and 25°C. If 8 MHz frequency exceeds the specification of the

device (depends on VCC), the CKDIV8 Fuse must be programmed in order to divide the

internal frequency by 8 during start-up. The device is shipped with the CKDIV8 Fuse

programmed. See “System Clock Prescaler” on page 29. for more details. This clock

may be selected as the system clock by programming the CKSEL Fuses as shown in

Table 8. If selected, it will operate with no external components. During reset, hardware

loads the calibration byte into the OSCCAL Register and thereby automatically cali-

brates the RC Oscillator. At 3V and 25°C, this calibratio n gives a frequency within ± 10 %

of the nominal frequency. Using calibration methods as described in application notes

available at www.atmel .com/avr it is possible to achieve ± 2% accuracy at any given VCC

and Temperature. When this Oscillator is used as the chip clock, the Watchdog Oscilla-

tor will still be used for the Watchdog Timer and for the Reset Time-out. For more

information on the pre-programmed calibration value, see the section “Calibration Byte”

on page 269.

Note: 1. The device is shipped with this option selected.

When this Oscillator is selected, start-up times are determined by the SUT Fuses as

shown in Table 9. Selecting internal RC Oscillator allows the XTAL1/TOSC1 and

XTAL2/TOSC2 pins to be used as timer oscillator pins.

Note: 1. The device is shipped with this option selected.

Table 7. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection

CKSEL3..0 Start-up Time from

Power-down and Power-sa ve Recommended Usage

0110(1) 1K CK

0111 32K CK Stable frequency at start-up

Table 8. Internal Calibrated RC Oscillator Operating Modes(1)

CKSEL3..0 N ominal Frequency

0010 8.0 MHz

Table 9. Start-up times for the internal calibrated RC Oscillator clock selection

SUT1..0 Start-up Time from Power-

dow n and Power-sav e Ad ditional Delay fr om

Reset (VCC = 5.0V) Recommended Usage

00 6 CK 14CK BOD enabled

01 6 CK 14CK + 4.1 ms Fast rising power

10(1) 6 CK 14CK + 65 ms Slowly rising power

11 Reserved

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Oscillator Calibration Register

– OSCCAL

• Bits 6..0 – CAL6..0: Oscillator Calibration Value

Writing the calibration byte to this address will trim the internal Oscillator to remove pro-

cess variations from the Oscillator frequ ency. This is done automatically during Chip

Reset. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-

zero values to this register will increase the frequency of the internal Oscillator. Writing

0x7F to the register gives the highest available frequency. The calibrated Oscillator is

used to time EEPROM and Flash access. If EEPROM or Flash is written, do not cali-

brate to more than 10% abo ve the nominal frequency. Otherwise, the EEPROM or Flash

write may fail. Note that the Oscillator is intended for calibration to 8.0 MHz. Tuning to

other values is not guaranteed, as indicated in Table 10.

External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in

Figure 13. To run the device on an extern al clock, the CKSEL Fuses must be pro-

grammed to “0000”.

Figure 13. External Clock Drive Configuration

When this clock source is selected, start-up times are determined by the SUT Fuses as

shown in Table 12.

Bit 76543210

– CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL

Read/Write R R/W R/W R/W R/W R/W R/W R/W

Initial Value Device Specific Calibration Value

Table 10. Internal RC Oscillator Frequency Range.

OSCCAL Value Min Frequency in Percentage of

Nominal Frequency Max Frequency in Percentage of

Nominal Frequency

0x00 50% 100%

0x3F 75% 150%

0x7F 100% 200%

Table 11. Crystal Oscillator Clock Frequency

CKSEL3..0 Frequency Range

0000 0 - 16 MHz

EXTERNAL

CLOCK

SIGNAL

XTAL2

XTAL1

GND

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When applying an external clock, it is required to avoid sudden change s in the applied

clock frequency to en sure stable operation of the MCU. A variation in frequency of mo re

than 2% from one clock cycle to the next can lead to unpredictable behavior. It is

required to ensure that the MCU is kept in Reset during such changes in the clock

frequency.

Note that the System Clock Prescaler can be used to implement run-time changes of

the internal clock frequency while still ensuring stable operation. Refer to “System Clock

Prescaler” on page 29 for details.

Clock Output Buffer When the CKOUT Fuse is programmed, the system Clock will be output on CLKO. This

mode is suitable when chip clock is used to drive other circuits on th e syst em. Th e clock

will be output also during reset and the normal operation of I/O pin will be overridden

when the fuse is programmed. Any clock source, inclu ding internal RC Oscillator, can be

selected when CLKO serves as clock output. If the System Clock Prescaler is used, it is

the divided system clock that is output when the CKOUT Fuse is programmed.

Timer/Counter Oscillator ATmega169 share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with XTAL1

and XTAL2. This means that the Timer/Counter Oscillator can only be used when the

calibrated internal RC Oscillator is selected as system clock source. The Oscillator is

optimized for use with a 32.768 kHz watch crystal. See Figure 12 on page 25 for crystal

connection.

Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Reg-

ister is written to log ic one. See “Asynchron ous oper ation of the Timer /Counter” o n page

138 for further description on selecting external clock as input instead of a 32 kHz

crystal.

System Cloc k Prescaler The ATmega169 system clock can be divided by setting the “Clock Prescale Register –

CLKPR” on page 30 . This feature ca n be used to dec rease the system clock frequency

and power consumption when the requirement for processing power is low. This can be

used with all clock source options, and it will affect the clock frequency of the CPU and

all synchronous peripherals. clkI/O, clkADC, clkCPU, and clk FLASH are divide d by a f actor as

shown in Table 13.

When switching between prescaler settings, the System Clock Prescaler ensures that

no glitches occur in the clock system and that no intermediate frequency is higher than

neither the clock frequency correspondin g to the previous setting, nor the clock fre-

quency corresponding to the new setting.

The ripple counter that implements the prescaler runs at the frequency of the undivided

clock, which may be faster than the CPU’s clock frequency. Hence, it is not possible to

determine the state of the prescaler – even if it were readable, and the exact time it

takes to switch from one clock division to another cannot be exactly predicted. From the

Table 12. Start-up Times for the External Clock Selection

SUT1..0 Start-up Time from Power-

down and Po wer-save Additional Delay fr om

Reset (VCC = 5.0V) Recommended Usage

00 6 CK 14CK BOD ena bled

01 6 CK 14CK + 4.1 ms Fast rising power

10 6 CK 14CK + 65 ms Slowly rising power

11 Reserved

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time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the

new clock frequency is active. In this interval, 2 active clock edges are produced. Here,

T1 is the previous clock period, and T2 is th e period corresponding to the new prescaler

setting.

To avoid unintentional changes of clock frequency, a special write procedure must be

followed to change the CLKPS bits:

1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other

bitsin CLKPR to zero.

2. Within four cycles, write the desired value to CLKPS while writing a zero to

CLKPCE.

Interrupts must be d isa bled whe n chang i ng pr esca ler sett i ng to ma ke sur e th e wri te pr o-

cedure is not interrupted.

Clock Prescale Register –

CLKPR

• Bit 7 – CLKPCE: Clock Prescal er Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The

CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to

zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits

are written. Rewritin g the CLKPCE bit within th is time-out period does neith er extend the

time-out period , no r clea r the CL KPCE bit.

• Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 - 0

These bits define the division factor between the selected clock source and the internal

system clock. These bits can be written run-time to vary the clock frequency to suit the

application requirements. As the divider divides the master clock input to the MCU, the

speed of all synchronous peripher als is reduced when a division f actor is used. The divi-

sion factors are given i n Table 13.

The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unpro-

grammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits

are reset to “001 1”, giving a d ivision fa ctor of 8 a t start up. This featu re should be u sed if

the selected clock source has a higher frequency than the maximum frequency of the

device at the present operating conditions. Note that any value can be written to the

CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must

ensure that a sufficient division factor is ch osen if the se lected clock source has a high er

frequency than the maximum frequency of the device at the present operating condi-

tions. The device is shipped with the CKDIV8 Fuse programmed.

Bit 76543210

CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR

Read/Write R/W R R R R/W R/W R/W R/W

Initial Value 0 0 0 0 See Bit Description

ATmega169/V

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Table 13. Clock Prescaler Select

CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor

0000 1

0001 2

0010 4

0011 8

0100 16

0101 32

0110 64

0111 128

1000 256

1001 Reserved

1010 Reserved

1011 Reserved

1100 Reserved

1101 Reserved

1110 Reserved

1111 Reserved

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Power Management

and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby

saving power. The AVR provid es various sleep modes allowing the user to tailor the

power consum p tio n to the ap p licat ion ’s re qu ire m en ts.

To enter any of the five slee p modes, the SE bit in SMCR must be written to lo gic one

and a SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR

save, or Standby) will be activated by the SLEEP instruction. See Table 14 for a sum-

mary. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes

up. The MCU is then halt ed for four cycles in addition to the start-u p time, exec utes th e

interrupt routine, and resumes execution from the instruction following SLEEP. The con-

tents of the Register File and SRAM are unaltered when the device wakes up from

sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the

Reset Vector.

Figure 11 on page 23 presents the different clock systems in the ATmega169, and their

distribution. The figure is helpful in selecting an appropriate sleep mode.

Sleep Mode Control Register –

SMCR The Sleep Mode Control Regi ster contains control bits for power management.

• Bits 3, 2, 1 – SM2..0: Sleep Mode Select Bits 2, 1, and 0

These bits select between the five available sleep modes as shown in Table 14.

Note: 1. Standby mode is only recommended for use with external crystals or resonators.

• Bit 1 – SE: Sleep Enable

The SE bit must be wr itten to logic o ne to make the MCU e nter the sleep mo de when the

SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is

the programmer’s purpose, it is recommended to write the Sleep Enable (SE) bit to one

just before the execution of the SLEEP instruction and to clear it immediately after wak-

ing up.

Bit 76543210

–––– SM2 SM1 SM0 SE SMCR

Read/Write R R R R R/W R/W R/W R/W

Initial Value00000000

Table 14. Sleep Mode Select

SM2 SM1 SM0 Sleep Mode

000Idle

0 0 1 ADC Noise Reduction

010Power-down

011Power-save

100Reserved

101Reserved

110Standby

(1)

111Reserved

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Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter

Idle mode, stopping the CPU but allowing LCD controller, the SPI, USART, Analog

Comparator, ADC, USI, Timer/Counters, Watchdog, and the interrupt system to con-

tinue operating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the

other clocks to run.

Idle mode ena bles the MCU to wake up from external triggere d interrupts as well as

internal ones like the Timer Overflow and USART Transmit Complete interrupts. If

wake-up from the Analog Co mparator interrupt is not require d, the Analog Comparator

can be powered down by setting the ACD bi t in the Analog Comparat or Control and Sta-

tus Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is

enabled, a conversion starts automatically when this mode is entered.

ADC Noise Reduction

Mode When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter

ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external in ter-

rupts, the USI start condition detection, Timer/Counter2, LCD Controller, and the

Watchdog to continue operating (if enabled). This sleep mode basically halts clkI/O,

clkCPU, and clkFLASH, while allowing the other clocks to run.

This improves the noise environment for the ADC, enabling higher resolution measure-

ments. If the ADC is enabled, a conversion starts automatically when this mode is

entered. Apart form the ADC Conversion Complete interrupt, only an External Reset, a

Watchdog Reset, a Brown-out Reset, an LCD controller interrupt, USI start condition

interrupt, a Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, an external

level interrupt on INT0 or a pin change interrupt can wake up the MCU from ADC Noise

Reduction mode.

Power-down Mode When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter

Power-down mode. In this mode, the external Oscillator is stopped, while the external

interrupts, the USI start condition detection, and the Watchdog continue operating (if

enabled). On ly an Extern al Rese t, a Watchdog Reset , a Bro wn-out Re set, USI st art con-

dition interrupt, an external level interrupt on INT0, or a pin change interrupt can wake

up the MCU. This sleep mode basically halts all generated clocks, allowing operation of

asynchronous modules only.

Note that if a level triggered interr upt is used for wake-up from Power-down mode, the

changed level must be h eld for some t ime t o wake up t he MCU. Ref er t o “ External Inter-

rupts” on page 51 for details.

When waking up from Power-down mode, there is a delay from the wake-up condition

occurs until the wake -up become s effe ct ive. T his allo ws th e clock t o rest ar t and b ecome

stable after having been stopped. The wake-up period is defined by the same CKSEL

Fuses that define the Reset Time-out period, as described in “Clock Sources” on page

24.

Power-save Mode When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter

Power-save mode. This mode is identical to Power-down, with one exception:

If Timer/Counter2 and/or the LCD con troller are enabled, they will keep running during

sleep. The device can wake up from either Timer Overflow or Output Compare event

from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in

TIMSK2, and the Global Interrupt Enable bit in SREG is set. It can also wake up from an

LCD controller interrupt.

If neither Timer/Counter2 nor the LCD controller is running, Power-down mod e is rec-

ommended instead of Power-save mode.

ATmega169/V

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The LCD controller and Timer/Coun ter2 can be clocked both synchronously and asyn -

chronously in Power-save mode. The clock source for the two modules can be selected

independent of each other. If neither the LCD controller nor the Timer/Counter2 is using

the asynchronous clock, the Timer/C ounter Oscillator is stopped during sleep. If neither

the LCD controller nor the Timer /Counter2 is using the synchronous clock, the clock

source is stopped during sleep. Note that even if the synchronous clock is running in

Power-save, this clock is only available for the LCD controller and Timer/Counter2.

Standb y Mode When the SM2..0 bit s are 11 0 and a n exter nal cryst al/reson ator clo ck o ption is sel ecte d,

the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to

Power-down with the exception that the Oscillator is kept running. From Standby mode,

the device wakes up in six clock cycles.

Notes: 1. Only recommended with external crystal or resonator selected as clock source.

2. If either LCD controller or Timer/Counter2 is running in asynchronous mode.

3. For INT0, only level interrupt.

Power Reduction

peripherals to reduce power con sumption. The current state of the per ipheral is frozen

and the I/O re giste rs can no t b e r ead o r wri tt en. Re so urce s used by th e per i phera l when

stopping the clock will remain occup ied, hence the peripheral shou ld in most cases be

disabled before stopping the clock. Waking up a module, which is done by clearing the

bit in PRR, puts the module in the same state as before shutdown.

Module shutdown can be used in Idle mode and Active mode to significantly reduce the

overall power consumption. See “Su pply Current of I/O mod ules” on page 310 for exam-

ples. In all other sleep modes, the clock is already stopped.

Power Reduction Register -

PRR

• Bit 7..5 - Res: Reserved bits

These bits are reserved in ATmega169 and will always read as zero.

Table 15. Active Clock Domains and Wake-up Sources in the Different Sleep Modes.

Active Clock Domains Oscillators Wake-up Sources

Sleep Mod e clkCPU clkFLASH clkIO clkADC clkASY

Main Clock

Source

Enabled

Timer

Osc

Enabled

INT0

and Pin

Chang

eUSI Start

Condition LCD

Controller Timer2

SPM/

EEPROM

Ready ADC Other

I/O

Idle X X X X X(2) XX XXXXX

ADC Noise

Reduction X X X X(2) X(3) XX

(2) X(2) XX

Power-down X(3) X

Power-save X X X(3) XXX

Standby(1) XX

(3) X

Bit 765432 1 0

– – – PRLCD PRTIM1 PRSPI PRUSART0 PRADC PRR

Read/Write R R R R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

ATmega169/V

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• Bit 4 - PRLCD: Power Reduction LCD

Writing logic one to this bit shuts down the LCD controller. The LCD controller must be

disabled and the display discharg ed before shut down. See "Disabling the LCD" on

page 217 for details on how to disable the LCD controller.

• Bit 3 - PRTIM1: Power Reduction Timer/Counter1

Writing a logic one to this bit shuts down the Timer/Counter1 module. When the

Timer/Counter1 is enabled, operation will continue like before the shutdown.

• Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface

Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the

clock to the module. When waking up the SPI again, the SPI should be re initialized to

ensure proper operation.

• Bit 1 - PRUSART0: Power Reduction USART0

Writing a logic one to this bit shuts down the USART by stopping the clock to the mod-

ule. When waking up the USART again, the USART should be re initialized to ensure

proper operation.

• Bit 0 - PRADC: Power Reduction ADC

Writing a logic one to this bit shuts down the ADC. The ADC must be disabled be fore

shut down. The analog comparator cannot use the ADC input MUX when the ADC is

shut down.

Note: The Analog Comparator is disabled using the ACD-bit in the “Analog Comparator Control

and Status Register – ACSR” on page 190.

Minimizing Po wer

Consumption There are several issues to consider when trying to minimize the power consumption in

an AVR controlled system. In general, sleep modes should be used as much as possi-

ble, and the sleep mode should be selected so that as few as possible of the device’s

functions are operating. All functions not needed should be disabled. In particular, the

following modules may need special consideration when trying to achieve the lowest

possible power consumption.

Analog to Digital Converter If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should

be disabled before entering any sleep mode. When the ADC is turned off and on again,

the next conversion will b e an extended conversion. Refer to “Analog to Digital Con-

verter” on page 193 for details on ADC operation.

Analog Comparator When entering Idle mode, the Analog Comparator should be disabled if not used. When

entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In

other sleep modes, the Analog Comparator is automatically disabled. However, if the

Analog Compara tor is set up to use the In tern al Voltag e Refe renc e as inpu t, the Ana log

Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Ref-

erence will be enabled, independent of sleep mode. Refer to “Analog Comparator” on

page 190 for details on how to conf igure the Analog Comparator.

ATmega169/V

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Brown-out Detector If the Brown- ou t De te ct or is n ot ne ed ed by the app lication, this m odu le should be tur ned

off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in

all sleep modes, and hence, always consume power. In the deeper sleep modes, this

will contribute significantly to the total current consumption. R efer to “Brown-out Detec-

tion” on page 40 for details on how to configure the Brown-out Detector.

Internal Voltage Reference The Internal Voltage Reference will be enab led when needed by the Brown-out Detec-

tion, the Analog Comparator or the ADC. If these modules are disabled as described in

the sections above, the internal voltage reference will be disabled and it will not be con-

suming power. When turned on again, the user must allow the reference to start up

before the output is used. If the reference is kept on in sleep mode, the output can be

used immediately. Refer to “Internal Voltage Reference” on page 42 for details on the

start-up time.

Watchdog Timer If the Wat chdo g Timer is not ne eded in th e app lica tion, th e mod ule should be t ur ned off.

If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence,

always consume power. In the deeper sleep modes, this will contribute significantly to

the total current consumption. Refer to “Watchdog Timer” on page 43 for details on how

to configure the Watchdog Timer.

Port Pins When entering a sleep mode, all port pins should be configured to use minimum power.

The most important is then to ensure that no pins drive resistive loads. In sleep modes

where both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buff-

ers of the device will be disabled. This ensures that no power is consumed by the input

logic when not needed. In some cases, the input logic is needed for detecting wake-up

conditions, and it will then be enabled. Refer to the section “Digital Input Enable and

Sleep Modes” on page 59 for details on which pins are enabled. If the input buffer is

enabled and the input signa l is left float ing or ha ve an analog signal le vel close to V CC/2,

the input buffer will use excessive power.

For analog input pins, the digital input buffer should be disabled at all times. An analog

signal level close to VCC/2 on an input pin can cause significant current even in active

mode. Digital input buffers can be disabled by writing to the Digital Input Disable Regis-

ters (DIDR1 and DIDR0). Refer to “Digital Input Disable Register 1 – DIDR1” on page

192 and “Digital Input Disable Register 0 – DIDR0” on page 209 for details.

JTAG Interface and

On-chip Debug System If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power

down or Power save sleep mode, the main clock source remains enabled. In these

sleep modes, this will contribute significantly to the total current consumption. There are

three alternative ways to avoid this:

• Disable OCDEN Fuse.

• Disable JTAGEN Fuse.

• Write one to the JTD bit in MCUCSR.

The TDO pin is left floating when the JTAG interface is enabled while the JTAG TAP

controller is not shifting data. If the hardware connected to the TDO pin does not pull up

the logic level, power consumption will increase. Note that the TDI pin for the next

device in the scan chain contains a pull-up that avoids this problem. Writing the JTD bit

in the MCUCSR register to one or leaving the JTAG fuse unprogrammed disables the

JTAG interface.

ATmega169/V

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System Control and

Reset

Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts exe-

cution from the Reset Vector. The instruction placed at th e Reset Vector must be a JMP

– Absolute Jump – instruction to the reset handling routine. If the program never

enables an interrupt source, the Interrupt Vectors are not used, and regular program

code can be place d at thes e loca tions. This is als o the case if the Re set Vect or is in the

Application section while the Interrupt Vectors are in the Boot section or vice versa. The

circuit diagram in F igure 14 shows t he reset logic. Table 16 defines the electr ical param-

eters of the reset c ircu itr y.

The I/O ports of the AVR are immediately reset to their initial state when a reset source

goes active. This does not require any clock source to be running.

After all reset source s have gone inactive, a dela y counter is invoked, stretching the

internal reset. This allows the power to reach a stable level before normal operation

starts. The time-out period of the delay counter is defined by the user through the SUT

and CKSEL Fuses. The diffe rent selec tions for t he dela y pe riod ar e pr esen ted in “Clo ck

Sources” on page 24.

Reset Sources The ATmega169 has five sources of reset:

• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on

Reset threshold (VPOT).

• External Reset. The MCU is reset when a low level is present on the RESET pin f or

longer than the minimum pulse length.

• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and

the Watchdog is enabled.

• Brown-out Reset. The MCU is reset when th e supply v oltage VCC is below th e

Brown-out Reset threshold (VBOT) and the Brown-out Detector is enabled.

• JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset

1149.1 (JTAG) Boundary-scan” on page 232 for details.

ATmega169/V

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Figure 14. Reset Logic

Notes: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT

(falling)

Table 16. Reset Characteristics

Symbol Parameter Condition Min Typ Max Units

VPOT

Power-on Reset Threshold

Voltage (rising) TA = -40°C

to 85°C 0.7 1.0 1.4 V

Power-on Reset Threshold

Voltage (falling)(1) TA = -40°C

to 85°C 0.6 0.9 1.3 V

VRST RESET Pin Threshold Voltage VCC = 3V 0.2 VCC 0.9 VCC V

tRST Minimum pulse width on

RESET Pin VCC = 3V 2.5 µs

MCU Status

Brown-out

Reset Circuit

BODLEVEL [2..0]

Delay Counters

CKSEL[3:0]

TIMEOUT

WDRF

BORF

EXTRF

PORF

DATA B U S

Clock

Generator

SPIKE

FILTER

Pull-up Resistor

JTRF

JTAG Reset

Watchdog

Oscillator

SUT[1:0]

Power-on Reset

Circuit

ATmega169/V

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Power-on Res et A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec-

tion level is defined in Table 16. The POR is activated whenever VCC is below the

detection level. The POR circuit can be used to trigger the start-up Reset, as well as to

detect a failure in supply voltage.

A Power-on Rese t (PO R) circu it ensur es t hat the device is reset fr om Powe r- on . Reach-

ing the Power-on Reset threshold voltage invokes the delay counter, which determines

how long the device is kept in RESET after VCC rise. The RESET signal is activated

again, without any delay, when VCC decreases below the detection level.

Figure 15. MCU Start-up, RESET Tied to VCC

Figure 16. MCU Start-up, RESET Extended Externally

RESET

TIME-OUT

NTERNAL

RESET

TOUT

POT

RST

RESET

TIME-OUT

NTERNAL

RESET

TOUT

POT

RST

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External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer

than the minimum pulse width (see Table 16) will gen erate a reset, even if the clock is

not running. Shorter pulses are not guaranteed to generate a reset. When the applied

signal reaches the Reset Threshold Voltage – VRST – on its positive edge, the delay

counter starts the MCU after the Time-out period – tTOUT – has expired.

Figure 17. External Reset During Operation

Brown-out Detection ATmega169 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC

level during operation by comparing it to a fixed trigger level. The trigger level for the

BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to

ensure spike free Brown-out Detection. The hysteresis on the detection level should be

interprete d as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.

Note: 1. VBOT may be below nominal minimum operating voltage for some devices. For

devices where this is the case, the device is tested down to VCC = VBOT during the

production test. This guarantees that a Brown-Out Reset will occur before VCC drops

to a voltage where correct operation of the microcontroller is no longer guaranteed.

The test is performed using BODLEVEL = 110 for ATmega169V.

Table 17. BODLEVEL Fuse Coding(1)

BODLEVEL 2..0 Fuses Min VBOT Typ VBOT Max VBOT Units

111 BOD Disabled

110 1.7 1.8 2.0

V101 2.5 2.7 2.9

100 4.1 4.3 4.5

011

Reserved

010

001

000

Table 18. Brown-out Characteristics

Symbol Parameter Min Typ Max Units

VHYST Brown-out Detector Hysteresis 50 mV

tBOD Min Pulse Width on Brown-out Reset 2 µs

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When the BOD is enabled, and VCC decreases to a value below the trigger level (VBOT-

in Figure 18), the Brown- out Rese t is immediat ely activated . When VCC increases above

the trigger level (VBOT+ in Figure 18), the delay counter starts the MCU after the Time-

out period tTOUT has expired.

The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level

for longer than tBOD given in Table 16.

Figure 18. Brown-out Reset During Operation

Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle dura-

tion. On the falli ng edge of this pulse, the dela y timer star ts counting the Time-out per iod

tTOUT. Refer to page 43 fo r details on operation of the Watchdog Timer.

Figure 19. Watchdog Reset Durin g Operation

MCU Status Register –

MCUSR The MCU Status Register provides information on which reset source caused an MCU

reset.

• Bit 4 – JTRF: JTAG Reset Flag

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register

selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or

by writing a logic zero to the flag.

VCC

RESET

TIME-OUT

NTERNAL

RESET

VBOT- VBOT+

tTOUT

Bit 76543210

––– JTRF WDRF BORF EXTRF PORF MCUSR

Read/Write R R R R/W R/W R/W R/W R/W

Initial Value 0 0 0 See Bit Description

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• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by

writing a logic zer o to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by

writing a logic zer o to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by

writing a logic zer o to the flag.

• Bit 0 – PORF: Po wer-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to

the flag.

To make use of the Reset Flags to identify a reset condition, the user should read and

then Reset the MCUSR as early as possible in the program. If the register is cleared

before another reset occurs, the source of the reset can be found by examining the

Reset Flags.

Internal Voltage

Reference ATmega169 features an internal bandgap reference. This reference is used for Brown-

out Detection, and it can be used as an input to the Analog Comparator or the ADC.

Voltage Reference Enable

Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used.

The start-up time is give n in Table 19. To save power, the reference is not a lways turned

on. The refere nce is on during the following situations:

1. When the BOD is enabled (by prog ramming the BODLEVEL [2..0] Fuse).

2. When the bandgap reference is connected to t he Analog Compar at or ( b y settin g

the ACBG bit in ACSR).

3. When the ADC is enabled.

Thus, when the BOD is not enabled, after se ttin g the ACBG bi t or enabling the ADC, the

user must always allow t he reference t o start up befor e the output fr om the Analog Com-

parator or ADC is used. To reduce power consum ption in Power-down mode, the user

can avoid the three conditions above to en sure that the reference is turned off before

entering Power-down mode.

Table 19. Internal Voltage Reference Characteristics

Symbol Parameter Condition Min Typ Max Units

VBG Bandgap reference voltage VCC = 2.7V,

TA= 25°C 1.0 1.1 1.2 V

tBG Bandgap reference start-up time VCC = 2.7V,

TA= 25°C 40 70 µs

IBG Bandgap reference current

consumption VCC = 2.7V,

TA= 25°C 15 µA

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Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at

1 MHz. This is the typical value at VCC = 5V. See characterizatio n dat a for ty pical values

at other VCC levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset

interval can be adjus ted as shown in Table 21 on page 44. Th e WDR – Watchdog Reset

– instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is

disabled and when a Chip Reset occurs. Eight different clock cycle periods can be

selected to determine the reset period. If the reset period expires without another

Watchdog Reset, the ATmega169 resets and executes from the Reset Vector. For tim-

ing details on the Watchdog Reset, refer to Table 21 on page 44.

To prevent unintentional d isabling of the Watchdog or unintentional change of time-out

period, two differ ent safety levels are se lected by the fuse WDTON as shown in Table

20. Refer to “Timed Sequences for Changing the Configuration of the Watchdog Timer”

on page 45 for details.

Figure 20. Watchdog Timer

Watchdog Timer Control

• Bits 7..5 – Res: Reserved Bits

These bits are reserved bits in the ATmega169 and will always read as zero.

• Bit 4 – WDCE: Watchdog Change Enable

This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog

will not be disabled. Once written to one, hardware will clear this bit after four clock

cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. This

bit must also be set when changing the prescaler bits. See “Timed Sequences for

Changing the Configuration of the Watchdog Timer” on page 45.

Table 20. WDT Configuration as a Function of the Fuse Settings of WDTON

WDTON Safety

Level WDT Initial

State How to Disable the

WDT How to Change

Time-out

Unprogrammed 1 Disabled Timed sequence Timed sequence

Programmed 2 Enabled Always enabled Timed sequence

WATCHDOG

OSCILLATOR

Bit 76543210

– – – WDCE WDE WDP2 WDP1 WDP0 WDTCR

Read/Write R R R R/W R/W R/W R/W R/W

Initial Value00000000

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• Bit 3 – WDE: Watchdog Enable

When the WDE is written to logic one, the Watchdog Timer is e nabled, and if the WDE is

written to logic zero, t he Watch dog Ti mer fun ctio n is disab led. WDE can only be clear ed

if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the follow-

ing procedur e m ust be fo llowe d :

1. In the same operation, write a logic one to WDCE and WDE. A logic one mu st be

written to WDE even though it is set to one before the disable operation starts.

2. Within the next four clock cycles, write a logic 0 to WDE. This disables the

Watchdog.

In safety level 2, it is not possible to disable the Watchdog Timer, even with the algo-

rithm described ab ove. See “Timed Sequences for Chang ing the Configuration of the

Watchdog Timer” on page 45.

• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0

The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer presca ling when the

Watchdog Timer is e nabled. The differen t prescaling values and their corresponding

Timeout Periods are shown in Table 21.

Note: Also see Figure 191 on page 332.

Table 21. Watchdog Timer Prescale Select

WDP2 WDP1 WDP0 Number of WDT

Oscillator Cycles Typical Time-out

at VCC = 3.0V Typical Time-out

at VCC = 5.0V

0 0 0 16K cycles 15.4 ms 14.7 ms

0 0 1 32K cycles 30.8 ms 29.3 ms

0 1 0 64K cycles 61.6 ms 58.7 ms

0 1 1 128K cycles 0.12 s 0.12 s

1 0 0 256K cycles 0.25 s 0.23 s

1 0 1 512K cycles 0.49 s 0.47 s

1 1 0 1,024K cycles 1.0 s 0.9 s

1 1 1 2,048K cycles 2.0 s 1.9 s

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The following code example shows one assembly and one C function for turning off the

WDT. The example assumes that interrupts are controlled (e.g. by disabling interrupts

globally) so that no interrupts will occur during execution of these functions.

Note: 1. See “About Code Examp les” on page 6.

Timed Sequences for Changing the Configuration of the Watchdog Timer

The sequence for changing configuratio n differs slightly between the two safety levels.

Separate procedu res are described for each level.

Safety Level 1 In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the

WDE bit to 1 without an y restriction. A timed sequen ce is needed when changing th e

Watchdog Time-out period or disabling an enabled Watchdog Timer. To disable an

enabled Watchdog Tim er , and/ or chan ging th e Wat chdo g Tim e-o ut, th e followin g pr oce-

dure must be followed:

1. In the same operation, write a logic one to WDCE and WDE. A logic one mu st be

written to WDE regardless of the previous value of the WDE bit.

2. Within the next f our cloc k cycles, in t he same operation, write the WDE and WDP

bits as desired, but with the WDCE bit cleared.

Safety Level 2 In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read

as one. A timed sequence is needed when changing the Watchdog Time-out period. To

change the Watchdog Time-out, the following procedure must be followed:

1. In the same operation, write a logical one to WDCE and WDE. Even though the

WDE always is set, the WDE must be written to one to start the timed sequence.

2. Within the next four clock cycles, in the sa me operation, write the WDP bits as

desired, but with the WDCE bit cleared. The value written to the WDE bit is

irrelevant.

Assembly Code Example(1)

WDT_off:

; Reset WDT

wdr

; Write logical one to WDCE and WDE

in r16, WDTCR

ori r16, (1<<WDCE)|(1<<WDE)

out WDTCR, r16

; Turn off WDT

ldi r16, (0<<WDE)

out WDTCR, r16

ret

C Code Example(1)

void WDT_off(void)

{

/* Reset WDT */

__watchdog_reset();

/* Write logical one to WDCE and WDE */

WDTCR |= (1<<WDCE) | (1<<WDE);

/* Turn off WDT */

WDTCR = 0x00;

}

ATmega169/V

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Interrupts This section describes the specifics of the interrupt handling as performed in

ATmega169. Fo r a general explanat ion of the AVR interrupt ha ndling, refer to “Reset

and Interrup t Handling” on page 12.

Interrupt Vectors in

ATmega169

Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader

address at reset, see “Boot Loader Support – Read-While-Write Self-Programming”

on page 252.

2. When the IVSEL bit in MCUCR is set, Interr upt Vectors will be moved to the start of

the Boot Flash Section. The address of each Interrupt Vector will then be the address

in this table added to the start address of the Boot Flash Section.

Table 22. Reset and Interrupt Vectors

Vector

No. Program

Address(2) Source Interrupt Definition

1 0x0000(1) RESET External Pin, Power-on Reset, Brown-out Reset,

Watchdog Reset, and JTAG AVR Reset

2 0x0002 INT0 External Interrupt Request 0

3 0x0004 PCINT0 Pin Change Interrupt Request 0

4 0x0006 PCINT1 Pin Change Interrupt Request 1

5 0x0008 TIMER2 COMP Timer/Counter2 Compare Match

6 0x000A TIMER2 OVF Timer/Counter2 Overflow

7 0x000C TIMER1 CAPT Timer/Counter1 Capture Event

8 0x000E TIMER1 COMPA Timer/Counter1 Compare Match A

9 0x0010 T IMER1 COMPB Timer/Counter1 Compare Match B

10 0x0012 TIMER1 OVF Timer/Counter1 Overflow

11 0x0014 TIMER0 COMP Timer/Counter0 Compare Match

12 0x0016 TIMER0 OVF Timer/Counter0 Overflow

13 0x0018 SPI, STC SPI Serial Transfer Complete

14 0x001A USART, RX USART, Rx Complete

15 0x001C USART, UDRE USART Data Register Empty

16 0x001E USART, TX USART, Tx Complete

17 0x0020 USI START USI Start Condition

18 0x0022 USI OVERFLOW USI Overflow

19 0x0024 ANALOG COMP Analog Comparator

20 0x0026 ADC ADC Conversion Complete

21 0x0028 EE READY EEPROM Ready

22 0x002A SPM READY Store Program Memory Ready

23 0x002C LCD LCD Start of Frame

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Table 23 shows reset and Interrupt Vectors placement for the various combinations of

BOOTRST and IVSEL settings. If the program never enables an interrupt source, the

Interrupt Vectors are not used, and regular program code can be placed at these loca-

tions. This is also the case if the Reset Vector is in the Application section while the

Interrupt Vectors are in the Boot section or vice versa.

Note: 1. The Boot Reset Address is shown in Table 113 on page 264. For the BOOTRST

Fuse “1” means unprogrammed while “0” means programmed.

The most typical and general program setup for the Reset and Interrupt Vector

Addresses in ATmega169 is:

Address Labels Code Comments

0x0000 jmp RESET ; Reset Handler

0x0002 jmp EXT_INT0 ; IRQ0 Handler

0x0004 jmp PCINT0 ; PCINT0 Handler

0x0006 jmp PCINT1 ; PCINT0 Handler

0x0008 jmp TIM2_COMP ; Timer2 Compare Handler

0x000A jmp TIM2_OVF ; Timer2 Overflow Handler

0x000C jmp TIM1_CAPT ; Timer1 Capture Handler

0x000E jmp TIM1_COMPA ; Timer1 CompareA Handler

0x0010 jmp TIM1_COMPB ; Timer1 CompareB Handler

0x0012 jmp TIM1_OVF ; Timer1 Overflow Handler

0x0014 jmp TIM0_COMP ; Timer0 Compare Handler

0x0016 jmp TIM0_OVF ; Timer0 Overflow Handler

0x0018 jmp SPI_STC ; SPI Transfer Complete Handler

0x001A jmp USART_RXC ; USART RX Complete Handler

0x001C jmp USART_DRE ; USART,UDR Empty Handler

0x001E jmp USART_TXC ; USART TX Complete Handler

0x0020 jmp USI_STRT ; USI Start Condition Handler

0x0022 jmp USI_OVFL ; USI Overflow Handler

0x0024 jmp ANA_COMP ; Analog Comparator Handler

0x0026 jmp ADC ; ADC Conversion Complete Handler

0x0028 jmp EE_RDY ; EEPROM Ready Handler

0x002A jmp SPM_RDY ; SPM Ready Handler

0x002C jmp LCD_SOF ; LCD Start of Frame Handler

;

0x002E RESET: ldi r16, high(RAMEND); Main program start

0x002F out SPH,r16 Set Stack Pointer to top of RAM

0x0030 ldi r16, low(RAMEND)

0x0031 out SPL,r16

0x0032 sei ; Enable interrupts

0x0033 <instr> xxx

... ... ... ...

Table 23. Reset and Interrupt Vectors Placement(1)

BOOTRST IVSEL Reset Address Interrupt Vectors Start Address

1 0 0x0000 0x0002

1 1 0x0000 Boot Reset Address + 0x0002

0 0 Boot Reset Address 0x0002

0 1 Boot Reset Address Boot Reset Address + 0x0002

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When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and

the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most

typical and general program setup for the Reset and Interrupt Vector Addresses is:

Address Labels Code Comments

0x0000 RESET: ldi r16,high(RAMEND) ; Main program start

0x0001 out SPH,r16 ; Set Stack Pointer to top of RAM

0x0002 ldi r16,low(RAMEND)

0x0003 out SPL,r16

0x0004 sei ; Enable interrupts

0x0005 <instr> xxx

;

.org 0x1C02

0x1C02 jmp EXT_INT0 ; IRQ0 Handler

0x1C04 jmp PCINT0 ; PCINT0 Handler

... ... ... ;

0x1C2C jmp SPM_RDY ; Store Program Memory Ready Handler

When the BOOTRST Fuse is programm ed and the Boot section size se t to 2K bytes, the

most typical and general progr am setup for t he Reset and Inte rrupt Vector Addresses is:

Address Labels Code Comments

.org 0x0002

0x0002 jmp EXT_INT0 ; IRQ0 Handler

0x0004 jmp PCINT0 ; PCINT0 Handler

... ... ... ;

0x002C jmp SPM_RDY ; Store Program Memory Ready Handler

;

.org 0x1C00

0x1C00 RESET: ldi r16,high(RAMEND) ; Main program start

0x1C01 out SPH,r16 ; Set Stack Pointer to top of RAM

0x1C02 ldi r16,low(RAMEND)

0x1C03 out SPL,r16

0x1C04 sei ; Enable interrupts

0x1C05 <instr> xxx

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When the BOOTRST Fuse is programm ed, the Boot section size set to 2K bytes and t he

IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typ-

ical and general progr am setup for the Reset and Interr upt Vector Addresses is:

Address Labels Code Comments

;

.org 0x1C00

0x1C00 jmp RESET ; Reset handler

0x1C02 jmp EXT_INT0 ; IRQ0 Handler

0x1C04 jmp PCINT0 ; PCINT0 Handler

... ... ... ;

0x1C2C jmp SPM_RDY ; Store Program Memory Ready Handler

;

0x1C2E RESET: ldi r16,high(RAMEND) ; Main program start

0x1C2F out SPH,r16 ; Set Stack Pointer to top of RAM

0x1C30 ldi r16,low(RAMEND)

0x1C31 out SPL,r16

0x1C32 sei ; Enable interrupts

0x1C33 <instr> xxx

Moving Interrupts Between

Application and Boot Space The General Interrupt Control Register controls the placement of the Interrupt Vector

table.

MCU Control Register –

MCUCR

• Bit 1 – IVSEL: Interrupt Vector Select

When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the

Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the begin-

ning of the Boot Loader section of the Flash. The actual address of the start of the Boot

Flash Section is determined by the BOOTSZ Fuses. Refer to the section “Boot Loader

Support – Read-While-Write Self-Programming” on page 252 for details. To avoid unin-

tentional changes of Interrupt Vector tables, a special write procedure must be followed

to change the IVSEL bit:

1. Write the Interrupt Vector Change Enable ( IVCE) bit to one.

2. Within four cycles, write the desired value to IVSEL while writing a zero to

IVCE.

Interrupts will automatically be disabled while this sequence is executed. Interrupts are

disabled in the cycle IVCE is set, and they remain disabled until after the instruction fol-

lowing the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four

cycles. The I-bit in the Status Register is unaffected by the automatic disabling.

Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is pro-

grammed, interrupts are disabled while executing from the Application section. If

Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is pro-

gramed, interrupts are disabled while executing from the Boot Loader section. Refer to

the section “Boot Loader Support – Read-While-Write Self-Programming” on page 252

for details on Boot Lock bits.

Bit 76543210

JTD – – PUD –– IVSEL IVCE MCUCR

Read/Write R/W R R R/W R R R/W R/W

Initial Value 0 0 0 0 0 0 0 0

ATmega169/V

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• Bit 0 – IVCE: Interrupt Vector Change Enable

The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is

cleared by hardware four cycles after it is written or when IVSEL is written. Setting the

IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code

Example below.

Assembly Code Example

Move_interrupts:

; Enable change of Interrupt Vectors

ldi r16, (1<<IVCE)

out MCUCR, r16

; Move interrupts to Boot Flash section

ldi r16, (1<<IVSEL)

out MCUCR, r16

ret

C Code Example

void Move_interrupts(void)

{

/* Enable change of Interrupt Vectors */

MCUCR = (1<<IVCE);

/* Move interrupts to Boot Flash section */

MCUCR = (1<<IVSEL);

}

ATmega169/V

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External Interrupts The External Interrupts are triggered by the INT0 pin or any of the PCINT15..0 pins.

Observe that, if enabled , the interrupts will trigger even if the INT0 or PCINT15..0 pins

are configured as outputs. This feature provides a way of generating a software inter-

rupt. The pin change interrupt PCI1 will trigger if any enabled PCINT15..8 pin toggles.

Pin change interrupts PCI0 will trigger if any enabled PCINT7..0 pin toggles. The

PCMSK1 and PCMSK0 Registers control which pins contribute to the pin change inter-

rupts. Pin change interrupts on PCINT15..0 are detected asynchronously. This implies

that these interrupts can be used for waking the part also from sleep modes other than

Idle mode.

The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is set

up as indicated in the specification for the External Interrupt Control Register A –

EICRA. When the INT0 interrupt is enabled and is configured as level triggered, the

interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising

edge interrupts on INT0 requires the presence of an I/O clock, described in “Clock Sys-

tems and their Distribution” on page 23. Low level interrupt on INT0 is detected

asynchronously. This implies that this interrupt can be used for waking the part also

from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes

except Idle mode.

Note that if a level triggered interrupt is used for wake-up from Power-down, the

required level must be held long enough for the MCU to complete the wake-up to trigger

the level interrupt. If the level disappears before the end of the Start-up Time, the MCU

will still wake up, but no interrupt will be generated. The start-up time is defined by the

SUT and CKSEL Fuses as described in “System Clock and Clock Options” on page 23.

Pin Change Interrupt

Timing An example of timing of a pin change interrupt is shown in Figure 21.

Figure 21. Pin Change Interrupt

clk

PCINT(n)

pin_lat

pin_sync

pcint_in_(n)

pcint_syn

cint_setflag

PCIF

PCINT(0) pin_sync pcint_syn

pin_lat

D Q

pcint_setflag PC

clk clk

PCINT(0) in PCMSK(x)

pcint_in_(0) 0

ATmega169/V

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External Interrupt Control

control.

• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the

corresponding int errupt mask are set. Th e level and edges on the external INT0 pin that

activate the interrupt are defined in Table 24. The value on the INT0 pin is sampled

before detecting edges. If edge or toggle interrupt is selected, pulses that last longer

than one clock period will generate an interrupt. Shorter pulses are not guaranteed to

generate an interrupt. If low level interrupt is selected, the low level must be held until

the completion of the currently executing instruction to generate an interrupt.

Bit 76543210

– – – – – – ISC01 ISC00 EICRA

Read/WriteRRRRRRR/WR/W

Initial Value00000000

Table 24. Interrupt 0 Sense Control

ISC01 ISC00 Description

0 0 The low level of INT0 generates an interrupt request.

0 1 Any logical change on INT0 generates an interrup t request.

1 0 The falling edge of INT0 generates an interr upt request.

1 1 The rising edge of INT0 generates an interrupt request.

ATmega169/V

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External Interru p t Mas k

• Bit 7 – PCIE1: Pin Change Interrupt Enable 1

When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

pin change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will

cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is exe-

cuted from the PCI1 Interrupt Vector. PCINT15..8 pins are enabled individually by the

PCMSK1 Register.

• Bit 6 – PCIE0: Pin Change Interrupt Enable 0

When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

pin change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause

an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed

from the PCI0 Inte rru p t Vec tor. PCINT7..0 pins are enabled individually by the PCMSK0

• Bit 0 – INT0: External Interrupt Request 0 Enab le

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

the external pin interrupt is enable d. The Interrupt Sen se Control0 bits 1/0 ( ISC01 and

ISC00) in the Exter nal Interru pt Contro l Register A (EICR A) define wh ether th e extern al

interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity

on the pin will cause an interrupt request even if INT0 is configured as an output. The

corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Inter-

rupt Vector.

External Interru p t Fl ag

• Bit 7 – PCIF1: Pin Change Interrupt Flag 1

When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1

becomes set (one). If the I-bit in SREG and the PCIE1 bit in EIMSK are set (one), the

MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-

rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to

it.

• Bit 6 – PCIF0: Pin Change Interrupt Flag 0

When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0

becomes set (one). If the I-bit in SREG and the PCIE0 bit in EIMSK are set (one), the

MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-

rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to

it.

Bit 76543210

PCIE1 PCIE0 – – – – –INT0EIMSK

Read/Write R/W R/W R R R R R R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

PCIF1 PCIF0 – – – – – INTF0 EIFR

Read/Write R/W R/W R R R R R R/W

Initial Value 0 0 0 0 0 0 0 0

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• Bit 0 – INTF0: External Interrupt Flag 0

When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0

becomes set (one). If the I-bit in SREG and the INT0 bit in EIMS K are set (one), the

MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-

rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to

it. This flag is always cleared when INT0 is configured as a level interrupt.

Pin Change Mask Regist er 1 –

PCMSK1

• Bit 7..0 – PCINT15..8: Pin Change Enable Mask 15..8

Each PCINT15..8-bit selects whether pin change inte rrupt is enabled on the correspon d-

ing I/O pin. If PC INT15..8 is set an d the PCIE1 bit in EIMSK is set, pin ch ange interr upt

is enabled on the corresponding I/O pin. If PCINT15..8 is cleared, pin change interrupt

on the corresponding I/O pin is disabled.

Pin Change Mask Regist er 0 –

PCMSK0

• Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0

Each PCINT7..0 bit selects whether pin change interrupt is enabled on the correspond-

ing I/O pin. If PCINT7..0 is set and th e PCIE0 bit in EI MSK is se t, pi n chan ge int er rupt is

enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on

the corresponding I/O pin is disabled.

Bit 76543210

PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 PCMSK1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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I/O-Ports

Introduction All AVR ports have true Re ad-Modify-Write functionality when used as general digital

I/O ports. T h is m e an s that the dir ec tio n o f one port p in can be chang ed w i th ou t u n int en -

tionally changing the direction of an y other pin with the SBI and CBI instructions. The

same applies when changing drive value (if configured as output) or enabling/disabling

of pull-up resistors (if configured as input). Each output buffer has symmetrical drive

characteristics with both high sink and source capability. The pin driver is strong enough

to drive LED displays directly. All port pins have individually selectable pull-up resistors

with a supply-voltage invariant resistance. All I/O pins have protection diodes to both

VCC and Ground as indicated in Figure 22. Refer to “Electrical Characteristics” on page

298 for a complete list of parameters.

Figure 22. I/O Pin Equivalent Schematic

All registers and bit references in this section are written in general form. A lower case

“x” represents the numbering letter for the port, and a lower case “n” represents the bit

number. However, when using the register or bit defines in a program, the precise form

must be used. For example, PORTB3 for bit no. 3 in Por t B, here documented gener ally

as PORTxn. The physical I/O Registers and bit locations are listed in “Register Descrip-

tion for I/O-Ports” on page 76.

Three I/O memory address locations are allocated for each port, one each for the Data

Port Input Pins I/O location is read only, while the Data Register and the Data Direction

result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up

Disable – PUD bit in MCUCR disables the pull-up function for all pins in all ports when

set.

Using the I/O port as General Digital I/O is described in “ Ports as Ge neral Dig ita l I/ O” on

page 56. Most port pins are multiplexed with alternate functions for the peripheral fea-

tures on the device. How each alte rn ate fu nct ion int er fer es with th e port pin is de scr ibed

in “Alternate Port Functions” on page 60. Refer to the individual module sections for a

full description of the alternate functions.

Cpin

Logic

Rpu

See Figure

"General Digital I/O" for

Details

Pxn

ATmega169/V

2514P–AVR–07/06

Note that enabling t he a lt ernat e f unc tio n of som e o f the po rt pin s doe s not af fect th e u se

of the other pin s in the port as general digital I/O.

Ports as General Digital

I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 23 shows a

functional descript ion of one I/O-port pin, here generically called Pxn.

Figure 23. General Digital I/O(1)

Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins wi thin the same por t.

clkI/O, SLEEP, and PUD are common to all ports.

Configuring the Pin Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in

“Register Description for I/O-Ports” on page 76, the DDxn bits are accessed at the

DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at

the PINx I/O address.

The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written

logic one, Pxn is configure d as an outp ut pin. If DDxn is written logic zero, Pxn is config-

ured as an input pin.

If PORTxn is written logic one when the pin is configured as an input pin, the pull-up

resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic

zero or the pin has to be configured as an output pin. The port pins are tri-stated when

reset condition becomes active, even if no clocks are running.

If PORTxn is written logic one when the pi n is configure d as an output pin, the por t pin is

driven high (one). If PORTxn is written logic zero when the pin is configured as an out-

put pin, the port pin is driven low (zero).

clk

RPx

RRx

RDx

WDx

PUD

SYNCHRONIZER

WDx: WRITE DDRx

WRx: WRITE PORTx

RRx: READ PORTx REGISTER

RPx: READ PORTx PIN

PUD: PULLUP DISABLE

clk

I/O

: I/O CLOCK

RDx: READ DDRx

RESET

CLR

PORTxn

CLR

DDxn

PINxn

DATA B US

SLEEP

SLEEP: SLEEP CONTROL

Pxn

I/O

WPx

WRx

WPx: WRITE PINx REGISTER

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Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of

DDRxn. Note that th e SBI inst ru ction ca n be use d to togg le one sing le bit in a po rt .

Switching Between Input and

Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn,

PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDx n, PORTxn} =

0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up

enabled state is fully acceptable, as a high -impedant environment will not notice the dif-

ference between a strong high driver and a pull-up. If this is not the case, the PUD bit in

the MCUCR Register can be set to disable all pull-ups in all ports.

Switching between input with pull-up and output low generates the same problem. The

user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state

({DDxn, PORTxn} = 0b11) as an int ermediate step.

Table 25 summarizes the control signals for the pin value.

Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read through

the PINxn Register bit. As shown in Figure 23, the PINxn Register bit and the preceding

latch constitute a synchronizer. This is needed to avoid metastability if the physical pin

changes value near the edge of the internal clock, but it also introduces a delay. Figure

24 shows a timing diagram of the synchronization when reading an externally applied

pin value. The maximum and minimum pro pagation dela ys are den oted tpd,max and tpd,min

respectively.

Figure 24. Synchronization when Reading an Externally Applied Pin value

Table 25. Port Pin Configurations

DDxn PORTxn PUD

(in MCUCR) I/O Pull-up Comment

0 0 X Input No Tri-state (Hi-Z)

0 1 0 Input Yes Pxn will source current if ext. pulled

low.

0 1 1 Input No Tri-state (Hi-Z)

1 0 X Output No Output Low (Sink)

1 1 X Output No Output High (Source)

XXX in r17, PINx

0x00 0xFF

INSTRUCTIONS

SYNC LATCH

PINxn

r17

XXX

SYSTEM CLK

pd, max

pd, min

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Consider the clock period starting shortly after the first falling edge of the system clock.

The latch is closed when the clock is low, and goes transparent when the clock is high,

as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is

latched when the syst em clock goes low. I t is clocked into the PINxn Reg ister at the suc-

ceeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a

single signal transition on the pin will be delayed between ½ and 1½ system clock

period depending upon the time of assertion.

When reading back a sof tware a ssigned pi n value, a nop instr uction must be inser ted as

indicated in Figure 25. The out instruction sets the “SYNC LATCH” signal at the positive

edge of the clock. In this case, the delay tpd through the synchronizer is 1 system clock

period.

Figure 25. Synchronization when Reading a Software Assigned Pin Value

out PORTx, r16 nop in r17, PINx

0xFF

0x00 0xFF

SYSTEM CLK

r16

INSTRUCTIONS

SYNC LATCH

PINxn

r17

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The following code e xample shows h ow to set port B pins 0 an d 1 high, 2 and 3 low, and

define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The

resulting pin values are read back again, but as previously discussed, a nop instruction

is included to be able to rea d back the value recently assigned to some of the pins.

Note: 1. For the assembly program, two temporary registers are used to minimize the time

from pull-ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set,

defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers.

Digital Input Enab le and Sleep

Modes As shown in Figure 23, the digital input signal can be clamped to ground at the input of

the Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep

Controller in Power-down mode, Power-save mode, and Standby mode to avoid high

power con sum p tio n if s om e in pu t sig na ls are left floa tin g, o r ha ve a n an a log signal level

close to VCC/2.

SLEEP is overridden for port pins enabled as external interrupt pins. If the external inter-

rupt request is not enabled, SLEEP is active also for these pins. SLEEP is also

overridden by various other alternate functions as described in “Alternate Port Func-

tions” on page 60.

If a logic high level (“one”) is present on an asynchronous external interrupt pin config-

ured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the

external interrupt is not enabled, the corresponding External Interrupt Flag will be set

when resuming from the above mentioned Sleep mode, as the clamping in these sleep

mode produces the requested logic change.

Assembly Code Example(1)

...

; Define pull-ups and set outputs high

; Define directions for port pins

ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)

ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)

out PORTB,r16

out DDRB,r17

; Insert nop for synchronization

nop

; Read port pins

in r16,PINB

...

C Code Example

unsigned char i;

...

/* Define pull-ups and set outputs high */

/* Define directions for port pins */

PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);

DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);

/* Insert nop for synchronization*/

__no_operation();

/* Read port pins */

i = PINB;

...

ATmega169/V

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Unconnected Pins If some pins are unused, it is recommend ed to ensure that these pins have a defined

level. Even though most of the digital inputs are disabled in the deep sleep modes as

described above, floating inputs should be avoided to reduce current consumption in all

other modes where the digital inputs are enable d (Reset, Active mode and Idle mode).

The simplest met hod to ensu re a define d level of an unused p in, is to enabl e the inter nal

pull-up. In this case, the pull-up will be disabled during reset. If low power consumption

during reset is important, it is recomme nded to use an external pull-up or pull-dow n.

Connecting unused pins directly to VCC or GND is not recommended, since this may

cause excessive currents if the pin is accidentally configured as an output.

Alternate Port Functions Mos t port pins have alte rnate functions in addition to being gen eral digital I/Os. Fig ure

26 shows how the port pin control signals from the simplified Figure 23 can be overrid-

den by altern ate function s. The ove rriding sig nals may not be present in all port pins, b ut

the figure serves as a generic description applicable to all port pins in the AVR micro-

controller family.

Figure 26. Alternate Port Functions(1)

Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins wi thin the same por t.

clkI/O, SLEEP, and PUD are common to all ports. All other signals are unique for each

pin.

clk

RPx

RRx

WRx

RDx

WDx

PUD

SYNCHRONIZER

WDx: WRITE DDRx

WRx: WRITE PORTx

RRx: READ PORTx REGISTER

RPx: READ PORTx PIN

PUD: PULLUP DISABLE

clk

I/O

: I/O CLOCK

RDx: READ DDRx

SET

CLR

DIxn

AIOxn

DIEOExn

PVOVxn

PVOExn

DDOVxn

DDOExn

PUOExn

PUOVxn

PUOExn: Pxn PULL-UP OVERRIDE ENABLE

PUOVxn: Pxn PULL-UP OVERRIDE VALUE

DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE

DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE

PVOExn: Pxn PORT VALUE OVERRIDE ENABLE

PVOVxn: Pxn PORT VALUE OVERRIDE VALUE

DIxn: DIGITAL INPUT PIN n ON PORTx

AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx

RESET

CLR

PINxn

PORTxn

DDxn

DATA BU S

DIEOVxn

SLEEP

DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE

DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE

SLEEP: SLEEP CONTROL

Pxn

I/O

PTOExn

WPx

PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE

WPx: WRITE PINx

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Table 26 summarizes the function of the overriding signals. The pin and port indexes

from Figure 26 are not shown in the succeeding tables. The overriding signals are gen-

erated intern ally in the modules having the alternate function.

The following subs ections shortly describe the alterna te functions for each port, an d

relate the overriding signals to the alternate function. Refer to the alternate function

description for further details.

Table 26. Generic Desc rip tio n of Ov er rid ing Sign als for Alte rn at e Fu n ctio ns

Signal Name Full Name Description

PUOE Pull-up Override

Enable If this signal is set, the pull-up enable is controlled by the

PUOV signal. If this signal is cleared, the pull-up is

enabled when {DDxn, PORTxn, PUD} = 0b010.

PUOV Pul l-up Override

Value If PUOE is set, the pull-up is enabled/disabled when

PUOV is set/cleared, regardless of the setting of the

DDxn, PORTxn, and PUD Register bits.

DDOE Data Direction

Override Enable If this signal is set, the Output Driver Enable is controlled

by the DDOV signal. If this signal is cleared, the Output

driver is enabled by the DDxn Register bit.

DDOV Data Direction

Override Value If DDOE is set, the Output Driver is enabled/ disabled

when DDOV is set/cleared, regardless of the setting of

the DDxn Register bit.

PVOE Port Value

Override Enable If this signal is set and the Output Driver is enabled, the

port value is controlled by the PVOV signal. If PVOE is

cleared, and the Output Driver is enabled, the port Value

is controlled by the PORTxn Register bit.

PVOV Port Value

Override Value If PVOE is set, the port value is set to PVOV, regardless

of the setting of the PORTxn Register bit.

PTOE Port Toggle

Override Enable If PTOE is set, the PORTxn Register bit is inverted.

DIEOE Digital Input

Enable Override

Enable

If this bit is set, the Digital Input Enable is controlled by

the DIEO V signal. If this signal is cleared, the Digital Input

Enable is determined b y MCU state (Normal mode, sleep

mode).

DIEOV Digital Input

Enable Override

Value

If DIEOE is set, the Digital Input is enabled/disabled when

DIEOV is set/cleared, regardless of the MCU state

(Nor mal mode, sleep mode).

DI Digital Input This is the Digital Input to alternate functions. In the

figure, the signal is connected to the output of the schmitt

trigger but before the synchronizer. Unless the Digital

Input is used as a clock source, the module with the

alternate function will use its own synchronizer.

AIO Analog

Input/Output This is the Analog Input/output to/from alternate

functions. The signal is connected directly to the pad, and

can be used bi-directionally.

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MCU Control Register –

MCUCR

• Bit 4 – PUD: Pull-up Disable

When this bit is written to one, the pull-ups in the I/O po rts are disabled even if the DDxn

and PORTxn Registers ar e configured to enable the pull-u ps ({DDxn, PORTxn} = 0b 01).

See “Configuring the Pin” on page 56 for more details about this feature.

Alternate Functions of Port A The Port A has an alternate function as COM0:3 and SEG0:3 for the LCD Controller.

Table 28 and Table 29 relates the alternate functions of Port A to the overriding signals

shown in Figure 26 on page 60.

Bit 7 6 5 4 3 2 1 0

JTD ––PUD– – IVSEL IVCE MCUCR

Read/Write R/W R R R/W R R R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Table 27. Port A Pins Alternate Functions

Port Pin Alternate Function

PA7 SEG3 (LCD Front Plane 3)

PA6 SEG2 (LCD Front Plane 2)

PA5 SEG1 (LCD Front Plane 1)

PA4 SEG0 (LCD Front Plane 0)

PA3 COM3 (LCD Back Plane 3)

PA2 COM2 (LCD Back Plane 2)

PA1 COM1 (LCD Back Plane 1)

PA0 COM0 (LCD Back Plane 0)

Table 28. Overriding Signals for Alt ernate Functions in PA7..PA4

Signal Name PA7/SEG3 PA6/SEG2 PA5/SEG1 PA4/SEG0

PUOE LCDEN LCDEN LCDEN LCDEN

PUOV0000

DDOE LCDEN LCDEN LCDEN LCDEN

DDOV 0 0 0 0

PVOE0000

PVOV0000

PTOE––––

DIEOE LCDEN LCDEN LCDEN LCDEN

DIEOV 0 0 0 0

DI ––––

AIO SEG3 SEG2 SEG1 SEG0

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Alternate Functions of Port B The Port B pins with alternate functio ns are shown in Table 30.

The alternate pin configuration is as follows:

• OC2A/PCINT15, Bit 7

OC2, Output Compare Match A output: The PB7 pin can serve as an external output for

the Timer/Counter2 Output Compare A. The pin has to be configured as an output

(DDB7 set (one) ) to serv e this func tion. The O C2A pin is also the o utput pin for the PWM

mode timer function.

PCINT15, Pin Change Interrupt source 15: The PB7 pin can serve as an external inter-

rupt source.

Table 29. Overriding Signals for Alt ernate Functions in PA3..PA0

Signal Name PA3/COM3 PA2/COM2 PA1/COM1 PA0/COM0

PUOE LCDEN •

(LCDMUX>2) LCDEN •

(LCDMUX>1) LCDEN •

(LCDMUX>0) LCDEN

PUOV0000

DDOE L CDEN •

(LCDMUX>2) LCDEN •

(LCDMUX>1) LCDEN •

(LCDMUX>0) LCDEN

DDOV0000

PVOE0000

PVOV0000

PTOE––––

DIEOE LCDEN •

(LCDMUX>2) LCDEN •

(LCDMUX>1) LCDEN •

(LCDMUX>0) LCDEN

DIEOV0000

DI––––

AIO COM3 COM2 COM1 COM0

Table 30. Port B Pins Alternate Functions

Port Pin Alternate Functions

PB7 OC2A/PCINT15 (Output Compare and PWM Output A for Timer/Counter2 or Pin

Change Interrupt15).

PB6 OC1B/PCINT14 (Output Compare and PWM Output B for Timer/Counter1 or Pin

Change Interrupt14).

PB5 OC1A/PCINT13 (Output Compare and PWM Output A for Timer/Counter1 or Pin

Change Interrupt13).

PB4 OC0A/PCINT12 (Output Compare and PWM Output A for Timer/Counter0 or Pin

Change Interrupt12).

PB3 MISO/PCINT11 (SPI Bus Master Input/Slav e Output or Pin Change Interrupt11).

PB2 MOSI/PCINT10 (SPI Bus Master Output /Slave Input or Pin Change Interrupt10).

PB1 SCK/PCINT9 (SPI Bus Serial Clo ck or Pin Change Interrup t9).

PB0 SS/PCINT8 (SPI Slave Select input or Pin Change Interrupt8).

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• OC1B/PCINT14, Bit 6

OC1B, Output Compare Match B output: The PB6 pin can serve as an external output

for the Timer/Counter1 Output Compare B. The pin has to be configured as an output

(DDB6 set (one) ) to serv e this func tion. The O C1B pin is also the o utput pin for the PWM

mode timer function.

PCINT14, Pin Change Interrupt Source 14: The PB6 pin can serve as an external inter-

rupt source.

• OC1A/PCINT13, Bit 5

OC1A, Output Compare Match A output: The PB5 pin can serve as an external output

for the Timer/Counter1 Output Compare A. The pin has to be configured as an output

(DDB5 set (one) ) to serv e this func tion. The O C1A pin is also the o utput pin for the PWM

mode timer function.

PCINT13, Pin Change Interrupt Source 13: The PB5 pin can serve as an external inter-

rupt source.

• OC0A/PCINT12, Bit 4

OC0A, Output Compare Match A output: The PB4 pin can serve as an external output

for the Timer/Counter0 Output Compare A. The pin has to be configured as an output

(DDB4 set (one) ) to serv e this func tion. The O C0A pin is also the o utput pin for the PWM

mode timer function.

PCINT12, Pin Change Interrupt Source 12: The PB4 pin can serve as an external inter-

rupt source.

• MISO/PCINT11 – Port B, Bit 3

MISO: Master Data input, Slave Data output pin for SPI. When the SPI is enabled as a

Master, this pin is configured as an input regardless of the setting of DDB3. When the

SPI is enabled as a Slave, the data direction of this pin is controlled by DDB3. When the

pin is forced to be an input, the pull-up can still be controlled by the PORTB3 bit.

PCINT11, Pin Change Interrupt Source 11: The PB3 pin can serve as an external inter-

rupt source.

• MOSI/PCINT10 – Port B, Bit 2

MOSI: SPI Master Data output, Slave Data input for SPI. When the SPI is enabled as a

Slave, this pin is configured a s an input r egardless of th e setting of DDB2. When th e SPI

is enabled as a Master, t he data direction of this pin is controlled by DDB2. When the pin

is forced to be an input, the pull-up can still be controlled by the PORTB2 bit.

PCINT10, Pin Change Interrupt Source 10: The PB2 pin can serve as an external inter-

rupt source.

• SCK/PCINT9 – Por t B, Bit 1

SCK: Master Clock output, Slave Clock input pin for SPI. When the SPI is enabled as a

Slave, this pin is configured a s an input r egardless of th e setting of DDB1. When th e SPI

is enabled as a Master, t he data direction of this pin is controlled by DDB1. When the pin

is forced to be an input, the pull-up can still be controlled by the PORTB1 bit.

PCINT9, Pin Change Inter rupt Source 9: The PB1 pin can serve as an external int errupt

source.

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•SS/PCINT8 – Port B, Bit 0

SS: Slave Port Select input. When the SPI is enabled as a Slave, this pin is configured

as an input regardle ss of the setting of DDB0. As a Slave, the SPI is acti vate d whe n this

pin is driven low. When the SPI is enabled as a Master, the data direction of this pin is

controlled by DDB0. When the pin is forced to be an input, the pull-up can still be con-

trolled by the PORTB0 bit

PCINT8, Pin Change Inter rupt Source 8: The PB0 pin can serve as an external int errupt

source.

Table 31 and Table 32 rela te the alternate functions of Port B to the overrid ing signals

shown in Figure 26 on page 60. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute

the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE

INPUT.

Table 31. Overriding Signals for Alt ernate Functions in PB7..PB4

Signal

Name PB7/OC2A/

PCINT15 PB6/OC1B/

PCINT14 PB5/OC1A/

PCINT13 PB4/OC0A/

PCINT12

PUOE0000

PUOV0000

DDOE 0 0 0 0

DDOV 0 0 0 0

PVOE OC2A ENABLE OC1B ENABLE OC1A ENABLE OC0A ENABLE

PVOV OC2A OC1B OC1A OC0A

PTOE––––

DIEOE PCINT15 •

PCIE1 PCINT14 • PCIE1 PCINT13 • PCIE1 PCINT12 •

PCIE1

DIEOV1111

DI PCINT15 INPUT PCINT14 INPUT PCINT13 INPUT P CINT12 INPUT

AIO––––

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Alternate Functions of Port C The Port C has an alternate function as the SEG5:12 for the LCD Controller

Table 32. Overriding Signals for Alt ernate Functions in PB3..PB0

Signal

Name PB3/MISO/

PCINT11 PB2/MOSI/

PCINT10 PB1/SCK/

PCINT9 PB0/SS/

PCINT8

PUOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR

PUOV PORTB3 • PUD PORTB2 • PUD PORTB1 • PUD POR T B0 • PUD

DDOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR

DDOV 0 0 0 0

PVOE SPE • MSTR SPE • MSTR SPE • MSTR 0

PVOV SPI SLAVE

OUTPUT SPI MSTR

OUTPUT SCK OUTPUT 0

PTOE – – – –

DIEOE PCINT11 • PCIE1 PCINT10 • PCIE1 PCINT9 • PCIE1 PCINT8 •

PCIE1

DIEOV 1 1 1 1

DI PCINT11 INPUT

SPI MSTR INPUT PCINT10 INPUT

SPI SLAVE INPUT PCINT9 INPUT

SCK INPUT PCINT8 INPUT

SPI SS

AIO – – – –

Table 33. Port C Pins Alternate Fun ctions

Port Pin Alternate Function

PC7 SEG5 (LCD Front Plane 5)

PC6 SEG6 (LCD Front Plane 6)

PC5 SEG7 (LCD Front Plane 7)

PC4 SEG8 (LCD Front Plane 8)

PC3 SEG9 (LCD Front Plane 9)

PC2 SEG10 (LCD Front Plane 10)

PC1 SEG11 (LCD Front Plane 11)

PC0 SEG12 (LCD Front Plane 12)

ATmega169/V

2514P–AVR–07/06

Table 34 and Table 35 relate the alternate functions of Port C to the overriding signals

shown in Figure 26 on page 60.

Table 34. Overriding Signals for Alternate Functions in PC7..PC4

Signal

Name PC7/SEG5 PC6/SEG6 PC5/SEG7 PC4/SEG8

PUOE LCDEN LCDEN LCDEN LCDEN

PUOV0000

DDOE LCDEN LCDEN LCDEN LCDEN

DDOV0000

PVOE0000

PVOV0000

PTOE––––

DIEOE LCDEN LCDEN LCDEN LCDEN

DIEOV0000

DI––––

AIO SEG5 SEG6 SEG7 SEG8

Table 35. Overriding Signals for Alternate Functions in PC3..PC0

Signal

Name PC3/SEG9 PC2/SEG10 PC1/SEG11 PC0/SEG12

PUOE LCDEN LCDEN LCDEN LCDEN

PUOV 0 0 0 0

DDOE LCDEN LCDEN LCDEN LCDEN

DDOV 0 0 0 0

PVOE 0 0 0 0

PVOV 0 0 0 0

PTOE – – – –

DIEOE LCDEN LCDEN LCDEN LCDEN

DIEOV 0 0 0 0

DI – – – –

AIO SEG9 SEG10 SEG11 SEG12

ATmega169/V

2514P–AVR–07/06

Alternate Functions of Port D The Port D pins with alter nate functions are shown in Table 36.

The alternate pin configuration is as follows:

• SEG15 - SEG20 – Port D, Bit 7:2

SEG15-SEG20, LCD front plan e 15-20.

• INT0/SEG2 1 – Port D, Bit 1

INT0, External Interrupt Source 0. The PD1 pin can serve as an external interrupt

source to the MCU.

SEG21, LCD front plan e 21 .

• ICP1/SEG22 – Port D, Bit 0

ICP1 – Input Capture pin1: The PD0 pin can act as an Input Capture pin for

Timer/Counter1.

SEG22, LCD front plan e 22

Table 36. Port D Pins Alternate Fun ctions

Port Pin Alternate Function

PD7 SEG1 5 (LCD front plane 15)

PD6 SEG1 6 (LCD front plane 16)

PD5 SEG1 7 (LCD front plane 17)

PD4 SEG1 8 (LCD front plane 18)

PD3 SEG1 9 (LCD front plane 19)

PD2 SEG2 0 (LCD front plane 20)

PD1 INT0/SEG21 (External Interrupt0 Input or LCD front plane 21)

PD0 ICP1/SEG22 (Timer/Counter1 Input Capture pin or LCD front plan e 22)

ATmega169/V

2514P–AVR–07/06

Table 37 and Table 38 relates the alternate functions of Port D to the overriding signals

shown in Figure 26 on page 60.

Table 37. Overriding Signals for Alt ernate Functions PD7..PD4

Signal

Name PD7/SEG15 PD6/SEG16 PD5/SEG17 PD4/SEG18

PUOE LCDEN •

(LCDPM>1) LCDEN •

(LCDPM>2) LCDEN •

(LCDPM>2)

PUOV0000

DDOE LCDEN •

(LCDPM>1) LCDEN •

(LCDPM>2) LCDEN •

(LCDPM>2)

DDOV0000

PVOE0000

PVOV0000

PTOE––––

DIEOE LCDEN •

(LCDPM>1) LCDEN •

(LCDPM>2) LCDEN •

(LCDPM>2)

DIEOV0000

DI––––

AIO SEG15 SEG16 SEG17 SEG18

Table 38. Overriding Signals for Alternate Functions in PD3..PD0

Signal

Name PD3/SEG19 PD2/SEG20 PD1/INT0/SEG21 PD0/ICP1/SEG22

PUOE LCDEN •

(LCDPM>3) LCDEN •

(LCDPM>4) LCDEN •

(LCDPM>4)

PUOV 0 0 0 0

DDOE LCDEN •

(LCDPM>3) LCDEN •

(LCDPM>4) LCDEN •

(LCDPM>4)

DDOV 0 0 0 0

PVOE 0 0 0 0

PVOV 0 0 0 0

PTOE – – – –

DIEOE LCDEN •

(LCDPM>3) LCDEN •

(LCDPM>3) LCDEN + (INT0

ENABLE) LCDEN •

(LCDPM>4)

DIEOV 0 0 LCDEN • (INT0

ENABLE) 0

DI – – INT0 INPUT ICP1 INPUT

AIO – –

ATmega169/V

2514P–AVR–07/06

Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 39.

• PCINT7 – Port E, Bit 7

PCINT7, Pin Change Inter rupt Source 7: The PE7 pin can serve as an external int errupt

source.

CLKO, Divided System Clock: The divided system clock can be output on the PE7 pin.

The divided system clock will be output if the CKOUT Fuse is programmed, regardless

of the PORTE7 and DDE7 settings. It will also be output during reset.

• DO/PCINT6 – Port E, Bit 6

DO, Universal Seria l Inte rf ac e Dat a ou tp ut .

PCINT6, Pin Change Inter rupt Source 6: The PE6 pin can serve as an external int errupt

source.

• DI/SDA/PCINT5 – Port E, Bit 5

DI, Universal Serial Interface Data input.

SDA, Two-wire Serial Interface Data:

PCINT5, Pin Change Inter rupt Source 5: The PE5 pin can serve as an external int errupt

source.

• USCK/SCL/PCINT4 – Port E, Bit 4

USCK, Universal Serial Interface Clock.

SCL, Two-wire Ser ial Int er fac e Clock.

PCINT4, Pin Change Inter rupt Source 4: The PE4 pin can serve as an external int errupt

source.

• AIN1/PCINT3 – Port E, Bit 3

AIN1 – Analog Comparator Negative input. This pin is directly connected to the negative

input of the Analo g Com p ar ator.

PCINT3, Pin Change Inter rupt Source 3: The PE3 pin can serve as an external int errupt

source.

Table 39. Port E Pins Alternate Functions

Port Pin Alternate Function

PE7 PCINT7 (Pin Change Interrupt7)

CLKO (Divided System Clock)

PE6 DO/PCINT6 (USI Data Output or Pin Change Interrupt6)

PE5 DI/SDA/PCINT5 (USI Data Input or TWI Serial DAta or Pin Change Interrupt5)

PE4 USCK/SCL/PCINT4 (USART External Clock Input/Output or TWI Serial Clock or

Pin Change Interrupt4)

PE3 AIN1/PCINT3 (Analog Comparator Negative Input or Pin Change Interrupt3)

PE2 XCK/AIN0/ PCINT2 (USART External Clock or Analog Comparator Positive Input

or Pin Change Interrupt2)

PE1 TXD/PCINT1 (USART Transmit Pin or Pin Change Interrupt1)

PE0 RXD/PCINT0 (USART Receive Pin or Pin Change In te rrupt0)

ATmega169/V

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• XCK/AIN0/PCINT2 – Port E, Bit 2

XCK, USART External Clock. The Data Direc tion Register (DDE2) controls whether the

clock is output (DDE2 set) or input (DDE2 cleared). Th e XCK pin is active only when the

USART operates in synchronous mode.

AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive

input of the Analo g Com p ar ator.

PCINT2, Pin Change Inter rupt Source 2: The PE2 pin can serve as an external int errupt

source.

• TXD/PCINT1 – P ort E, Bit 1

TXD0, UART0 Transmit pin.

PCINT1, Pin Change Inter rupt Source 1: The PE1 pin can serve as an external int errupt

source.

• RXD/PCINT0 – Por t E, Bit 0

RXD, USART Receive pin. Receive Data (Data input pin for the USART). When the

USART Receiver is enabled this pin is configured as an input regardless of the value of

DDE0. When the USART forces this pin to be an input, a logical one in PORTE0 will turn

on the internal pull-up.

PCINT0, Pin Change Inter rupt Source 0: The PE0 pin can serve as an external int errupt

source.

Table 40 and Table 41 relates the alternate functions of Port E to the overriding signals

shown in Figure 26 on page 60.

Note: 1. CKOUT is one if the CKOUT Fuse is programmed

Table 40. Overriding Signals for Alternate Functions PE7..PE4

Signal

Name PE7/PCINT7 PE6/DO/

PCINT6 PE5/DI/SDA/

PCINT5 PE4/USCK/SCL/

PCINT4

PUOE 0 0 USI_TWO-WIRE 0

PUOV 0 0 0 0

DDOE CKOUT(1) 0 USI_TWO-WIRE USI_TWO-WIRE

DDOV 1 0 (SDA + PORTE5) •

DDE5 (USI_SCL_HOLD +

PORTE4) + DDE4

PVOE CKOUT(1) USI_THREE-

WIRE USI_TWO-WIRE •

DDE5 USI_TWO-WIRE •

DDE4

PVOV clkI/O DO 0 0

PTOE – – – USITC

DIEOE PCINT7 •

PCIE0 PCINT6 •

PCIE0 (PCINT5 • PCIE0)

+ USISIE (PCINT4 • PCIE0) +

USISIE

DIEOV 1 1 1 1

DI PCINT7

INPUT PCINT6

INPUT DI/SDA INPUT

PCINT5 INPUT USCKL/SCL IN PUT

PCINT4 INPUT

AIO – – – –

ATmega169/V

2514P–AVR–07/06

Note: 1. AIN0D and AIN1D is described in “Digital Input Disable Register 1 – DIDR1” on page

192.

Alternate Functions of Port F The Port F has an alternate function as analog input for the ADC as shown in Table 42.

If some Port F pins are configured as outputs, it is essential that these do not switch

when a conversion is in progress. This might corrupt the result of the conversion. If the

JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS) and

PF4(TCK) will be activated even if a reset occurs.

• TDI, ADC7 – Port F, Bit 7

ADC7, Analog to Digital Converter, Channel 7.

TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or

Data Register (scan chains). When the JTAG interface is enabled, this pin can not be

used as an I/O pin.

Table 41. Overriding Signals for Alt ernate Functions in PE3..PE0

Signal

Name PE3/AIN1/

PCINT3 PE2/XCK/AIN0/

PCINT2 PE1/TXD/

PCINT1 PE0/RXD/PCINT0

PUOE 0 0 TXEN RXEN

PUOV 0 0 0 PORTE0 • PUD

DDOE 0 0 TXEN RXEN

DDOV 0 0 1 0

PVOE 0 XCK OUTPUT

ENABLE TXEN 0

PVOV 0 XCK TXD 0

PTOE – – – –

DIEOE (PCINT3 •

PCIE0) +

AIN1D(1)

(PCINT2 • PCIE0) +

AIN0D(1) PCINT1 •

PCIE0 PCINT0 • PCIE0

DIEOV PCINT3 • PCIE0 PCINT2 • PCIE0 1 1

DI PCINT3 INPUT XCK/PCINT2 INPUT PCINT1 INPUT RXD/PCINT0

INPUT

AIO AIN1 INPUT A IN0 INPUT – –

Table 42. Port F Pins Alternate Functions

Port Pin Alternate Function

PF7 ADC7/TDI (ADC input channel 7 or JTAG Test Data Input)

PF6 ADC6/TDO (ADC input channel 6 or JTAG Test Data Output)

PF5 ADC5/TMS (ADC input channel 5 or JTAG Test mode Select)

PF4 ADC4/TCK (ADC input channel 4 or JTAG Test ClocK)

PF3 ADC3 (ADC input channel 3)

PF2 ADC2 (ADC input channel 2)

PF1 ADC1 (ADC input channel 1)

PF0 ADC0 (ADC input channel 0)

ATmega169/V

2514P–AVR–07/06

• TDO, ADC6 – Port F, Bit 6

ADC6, Analog to Digital Converter, Channel 6.

TDO, JTAG Test Data Ou t: Serial output d ata from Instr uction Register or Data Regis-

ter. When the JTAG interface is enabled, this pin can not be used as an I/O pin. In TAP

states that shift out data, the TDO pin drives actively. In other states the pin is pulled

high.

• TMS, ADC5 – Port F, Bit 5

ADC5, Analog to Digital Converter, Channel 5.

TMS, JTAG Test mode Se lect: This pin is u sed for navigating th rough th e TAP-controller

state machine. When the JTAG interface is enabled, this pin can not be used as an I/O

pin.

• TCK, ADC4 – Port F, Bit 4

ADC4, Analog to Digital Converter, Channel 4.

TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG inter-

face is enabled, this pin can not be used as an I/O pin.

• ADC3 - ADC0 – Port F, Bit 3:0

Analog to Digital Converter, Channel 3-0.

Table 43. Overriding Signals for Alternate Functions in PF7..PF4

Signal

Name PF7/ADC7/TDI PF6/ADC6/TDO PF5/ADC5/TMS PF4/ADC4/TCK

PUOE JTAGEN JTAGEN JTAGEN JTAGEN

PUOV 1 1 1 1

DDOE JTAGEN JTAGEN JTAGEN JTAGEN

DDOV 0 SHIFT_IR +

SHIFT_DR 00

PVOE 0 JTAGEN 0 0

PVOV 0 TDO 0 0

PTOE – – – –

DIEOE JTAGEN JTAGEN JTAGEN JTAGEN

DIEOV 0 0 0 0

DI – – – –

AIO TDI

ADC7 INPUT ADC6 INPUT TMS

ADC5 INPUT TCK

ADC4 INPUT

ATmega169/V

2514P–AVR–07/06

Alternate Functions of Port G The alternate pin configuration is as follows:

The alternate pin configuration is as follows:

• T0/SEG23 – Port G, Bit 4

T0, Timer/Counter0 Counter Source.

SEG23, LCD front plan e 23

• T1/SEG24 – Port G, Bit 3

T1, Timer/Counter1 Counter Source.

SEG24, LCD front plan e 24

• SEG4 – Port G, Bit 2

SEG4, LCD front plane 4

• SEG13 – Port G, Bit 1

SEG13, Segment dr ive r 13

• SEG14 – Port G, Bit 0

SEG14, LCD front plan e 14

Table 44. Overriding Signals for Alternate Functions in PF3..PF0

Signal

Name PF3/ADC3 PF2/ADC2 PF1/ADC1 PF0/ADC0

PUOE0000

PUOV0000

DDOE0000

DDOV0000

PVOE0000

PVOV0000

PTOE––––

DIEOE0000

DIEOV0000

DI––––

AIO ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT

Table 45. Port G Pins Alternate Functions

Port Pin Alternate Function

PG4 T0/SEG23 (Timer/Counter0 Clock Input or LCD Front Plane 23)

PG3 T1/SEG24 (Timer/Counter1 Clock Input or LCD Front Plane 24)

PG2 SEG4 (LCD Front Plane 4)

PG1 SEG13 (LCD Front Plane 13)

PG0 SEG14 (LCD Front Plane 14)

ATmega169/V

2514P–AVR–07/06

Table 45 and Table 46 relates the alternate functions of Port G to the overriding signals

shown in Figure 26 on page 60.

Table 46. Overriding Signals for Alternate Functions in PG4

Signal

Name PG4/T0/SEG23

PUOE LCDEN • (LCDPM>5)

PUOV 0

DDOE LCDEN • (LCDPM>5)

DDOV 1

PVOE 0

PVOV 0

PTOE – – – –

DIEOE LCDEN • (LCDPM>5)

DIEOV 0

DI T0 INPUT

AIO SEG23

Table 47. Overriding Signals for Alternate Functions in PG3:0

Signal

Name PG3/T1/SEG24 PG2/SEG4 PG1/SEG13 PG0/SEG14

PUOE LCDEN •

(LCDPM>6) LCDEN L CDEN •

(LCDPM>0) LCDEN • (LCD P M> 0)

PUOV 0 0 0 0

DDOE LCDEN •

(LCDPM>6) LCDEN L CDEN •

(LCDPM>0) LCDEN • (LCD P M> 0)

DDOV 0 0 0 0

PVOE 0 0 0 0

PVOV 0 0 0 0

PTOE – – – –

DIEOE LCDEN •

(LCDPM>6) LCDEN L CDEN •

(LCDPM>0) LCDEN • (LCD P M> 0)

DIEOV 0 0 0 0

DI T1 INPUT – – –

AIO SEG24 SEG4 SEG13 SEG14

ATmega169/V

2514P–AVR–07/06

I/O-Ports

Port A Data Register – PORTA

P ort A Data Direct ion Register

– DDRA

Port A Input Pins Address –

PINA

Port B Data Register – PORTB

P ort B Data Direct ion Register

– DDRB

Port B Input Pins Address –

PINB

Port C Data Register – PORTC

P ort C Data Direct ion Register

– DDRC

Bit 76543210

PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 PORTA

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 PINA

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

Bit 76543210

PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTB

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

Bit 76543210

PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 PORTC

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 DDRC

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

ATmega169/V

2514P–AVR–07/06

Port C Input Pins Address –

PINC

Port D Data Register – PORTD

P ort D Data Direct ion Register

– DDRD

Port D Input Pins Address –

PIND

Port E Data Register – PORTE

P ort E Data Direction Register

– DDRE

Port E Input Pins Address –

PINE

Port F Data Register – PORTF

Port F Data Direction Register

– DDRF

Bit 76543210

PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 PINC

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

Bit 76543210

PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 PORTD

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 PIND

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

Bit 76543210

PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 PORTE

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 DDRE

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 PINE

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

Bit 76543210

PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTF0 PORTF

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 DDRF

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

ATmega169/V

2514P–AVR–07/06

Port F Input Pins Address –

PINF

Port G Data Register – PORTG

P ort G Data Direction Register

– DDRG

Port G Input Pins Address –

PING

Bit 76543210

PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 PINF

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

Bit 76543210

–––

PORTG4 PORTG3 PORTG2 PORTG1 PORTG0 PORTG

Read/Write R R R R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

– – – DDG4 DDG3 DDG2 DDG1 DDG0 DDRG

Read/Write R R R R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

– – – PING4 PING3 PING2 PING1 PING0 PING

Read/Write R R R R/W R/W R/W R/W R/W

Initial Value 0 0 0 N/A N/A N/A N/A N/A

ATmega169/V

2514P–AVR–07/06

8-bit Timer/Counter0

with PWM Timer/Counter0 is a general purpose, single compare unit, 8-bit Timer/Counter module.

The main featur es ar e:

•Single Compare Unit Counter

•Clear Timer on Compare Match (A uto Reload)

•Glitch-free, Phase Correct Pulse Width Modulator (PWM)

•Frequency Generator

•External Event Counter

•10-bit Clock Prescaler

•Overflow and Compare Match Interrupt Sources (TOV0 and OCF0A)

Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 27. For the

actual placement of I/O pins, refer to “Pinout ATmega169” on pag e 2. CPU accessible

I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O

page 89.

Figure 27. 8-bit Timer/Counter Block Diagram

Registers The Timer/Counter (T CNT0) and Outpu t Compare Register (OCR0A) are 8-bit re gisters.

Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer

Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer

Interrupt Mask Reg ister (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.

The Timer/Counter ca n be clocked internally, via the p rescaler, or by an external clock

source on the T0 pin. The Clock Select logic block controls which cloc k source and edge

the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is

inactive when no clock source is selected. The output from the Clock Select logic is

referred to as the timer clock (clkT0).

The double buffered Output Compare Register (OCR0A) is compared with the

Timer/Counter value at all times. Th e result of the compare can be used by the Wave-

form Generat or to gener ate a PWM or vari able frequency ou tput on t he Output Co mpare

pin (OC0A). See “Output Compare Unit” on page 81. for details. The compare match

Timer/Counter

DATA BU S

TCNTn

Waveform

Generation OCn

= 0

Control Logic

0xFF

BOTTOM

count

clear

direction

TOVn

(Int.Req.)

OCRn

TCCRn

Clock Select

Edge

Detector

( From Prescaler )

clkTn

TOP

OCn

(Int.Req.)

ATmega169/V

2514P–AVR–07/06

event will also set the Compare Flag (OCF0A) which can be used to generate an Output

Compare interrupt request.

Definitions Many register and bit ref ere nces in this se ct ion ar e wr itt en in g ene ral fo rm . A lo wer case

“n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the

Output Compar e unit number, in this case unit A. However , when using the register or

bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing

Timer/Counter 0 counter value and so on.

The definitions in Table 48 are also used extensively throughout the document.

Timer/Counter Clock

Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock

source is selected by the Clock Select logic which is controlled by the Clock Select

(CS02:0) bits located in the Timer/Counter Control Register (TCCR0A). For details on

clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on

page 93.

Counter Unit The main part of t he 8-bit T imer/Co unter is the p rogramma ble bi-dire ctional cou nter unit.

Figure 28 shows a block diagram of the count er and its surroundings.

Figure 28. Counter Unit Block Diagr am

Signal description (internal signals):

count Increment or decrement TCNT0 by 1.

direction Select between increment and decrement.

clear Clear TCNT0 (set all bits to zero).

clkTnTimer/Counter clo ck, re fe rr ed to as clk T0 in the following.

top Signalize that TCNT0 has reached maximum value.

bottom Signalize that TCNT0 has reached minimum value (zero).

Table 48. Definitions

BOTTOM The counter reaches the BOTTOM when it becomes 0x00.

MAX The counter reaches its MAXimum wh en it becomes 0xFF (decimal 255).

TOP The cou nter reaches the TOP when it becomes equal to the highest

value in the count sequence. The TOP value can be assigned to be the

fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The

assignment is depen dent on the mode of opera tion.

DATA BUS

TCNTn Control Logic

count

TOVn

(Int.Req.)

Clock Select

top

Edge

Detector

( From Prescaler )

clkTn

bottom

direction

clear

ATmega169/V

2514P–AVR–07/06

Depending of the mode of operation used, the counter is cleared, incremented, or dec-

remented at each timer clock (clkT0). clkT0 can be generated from an external or internal

clock source, selected by the Clock Select bits (CS02:0). When no clock source is

selected (CS02:0 = 0) t he timer is st opped. However, the TCNT0 value ca n be accessed

by the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has

priority over) all counter clear or count operations.

The counting sequence is determined by the setting of the WGM01 and WGM00 bits

located in the Timer/Counter Co ntrol Register (TCCR0A). There ar e close connections

between how the counter behaves (counts) and how waveforms are generated on the

Output Compare output OC0A. For more details about advanced counting sequences

and waveform gener ation, see “Modes of Operation” on page 84.

The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation

selected by the WGM01:0 bits. TOV0 can be used for generating a CPU int errupt.

Output Compare Unit The 8-bit comparator continuously compares TCNT0 with the Output Compare Register

(OCR0A). Whenever TCNT0 equals OCR0A, the comparator signals a match. A match

will set the Output Compare Flag (OCF0A) at the next timer clock cycle. If enabled

(OCIE0A = 1 and Global Interrupt Flag in SREG is set), the Output Compare Flag gen-

erates an Output Co mpare int errupt . The OCF0 A Flag is automat ically cleare d when the

interrupt is executed. Alternatively, the OCF0A Flag can be clea red by s oftware by writ -

ing a logical one to its I/O bit location. The Waveform Generator uses the match signal

to generate an output according to operating mode set by the WGM01:0 bits and Com-

pare Output mode (COM0A1:0) bits. The max and bottom signals are used by the

Waveform Generator for handling the special cases of the extreme values in some

modes of operation (See “Modes of Operation” on page 84.).

Figure 29 shows a block diagram of the Out put Compare unit.

Figure 29. Output Compare Unit, Block Diagram

OCFnx (Int.Req.)

= (8-bit Comparator )

OCRnx

OCnx

DATA BUS

TCNTn

WGMn1:0

Waveform Generator

top

FOCn

COMnx1:0

bottom

ATmega169/V

2514P–AVR–07/06

The OCR0A Register is double buffered when using any of the Pulse Width Modulation

(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation,

the double bu ffering is disabled. The double buffering synchronizes the upd ate of the

OCR0 Compare Register to either to p or bottom of t he counting se quence. The synchro-

nization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby

making the output glitch-free.

The OCR0A Register access may seem complex, but this is not case. When th e d ou b le

buffering is enabled, the CPU has access to the OCR0A Buffer Register, and if double

buffering is disabled the CPU will access the OCR0A directly.

Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be

forced by writin g a one to the Force Output Compare (FOC0A ) bit. Forcing compare

match will not set the OCF0A Flag or reload/clear the timer, but the OC0A pin will be

updated as if a real compare match had occurred (the COM0A1 :0 bits settings define

whether the OC0A pin is set, cleared or toggled).

Compare Match Bloc king by

TCNT0 Write All CPU write operations to the TCNT0 Register will block any compare match that

occur in the next timer clock cycle, even when the timer is stopped. This feature allows

OCR0A to be initialized to the same value as TCNT0 without triggering an interrupt

when the Timer/Counter clock is enabled.

Using the Output Compare

Unit Since writing TCNT0 in any mode of operation will block all compare matches for one

timer clock cycle, there are risks involved when changing TCNT0 when using the Output

Compare unit, ind ependently of wheth er the Timer/ Counter is run ning or not. If the value

written to TCNT0 equals the OCR0A value, the compare match will be missed, resulting

in incorrect wavefor m generation . Similarly, do not write t he TCNT0 value eq ual to BOT-

TOM when the counter is downcounting.

The setup of the OC0A should be performed before setting the Data Direction Register

for the port pin to output. The easiest way of setting the OC0A value is to use the Force

Output Com pare (FOC0A) stro be bits in Normal m ode. The OC0A Regist er keeps its

value even when changing between Waveform Generation mod es.

Be aware that the COM0A1:0 bits are not double buffered together with the compare

value. Changing the COM0A1:0 bits will take effect immediately.

ATmega169/V

2514P–AVR–07/06

Compare Match Output

Unit The Compare Out put mode ( COM0A1: 0) bits ha ve two f unctions. The Wavefor m Gener-

ator uses the COM0A1:0 bits for defining the Output Compare (OC0A) state at the next

compare match. Also, t he COM0A1:0 bits con trol the OC0A pin output source. Figure 30

shows a simplifie d schemat ic of the log ic affecte d by the COM 0A1:0 bit setting. The I/O

Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the

general I/O port control registers (DDR and PORT) that are affected by the COM0A1:0

bits are shown. Wh en re ferring to the OC0A sta te, the re feren ce is for the in tern al OC0A

Figure 30. Compare Match Output Unit, Schematic

The general I/O port functio n is overridden by the Output Compare (OC0A) from the

Waveform Generator if either of the COM0A1:0 bits are set. However, the OC0A pin

direction (input or output) is still controlled by the Data Direction Register (DDR) for the

port pin. T he Data D irectio n Regis ter bit f or the OC0A pin (DDR_O C0A) m ust be se t as

output before t he OC0A value is visible on the pin. The port override function is indepen-

dent of the Waveform Generation mode.

The design of the Output Compare pin logic allows initialization of the OC0A state

before the output is enabled. Note that some COM0A1:0 bit settings are reserved for

certain modes of operation. See “8-bit Timer/Counter Register Description” on page 89.

Compare Output Mode and

Waveform Generat ion The Waveform Generator uses the COM0A1:0 bits differently in Normal, CTC, and

PWM modes. For all modes, setting the COM0A1:0 = 0 tells the Waveform Generator

that no action on t he OC0A Regi ste r is to b e perf or med on th e n ext compa re m atch . For

compare output actions in the non-PWM m odes refer to Table 50 on page 90. For fast

PWM mode, refer to Table 51 on page 90, and for phase correct PWM refer to Table 52

on page 91.

A change of the COM0A1:0 bits state will have effect at the first compare match after the

bits are written. For non-PWM mod es, the action can be forc ed to have immediate effect

by using the FOC0A strobe bits.

PORT

DDR

OCn

OCnx

Waveform

Generator

COMnx1

COMnx0

DATA BU S

FOCn

clkI/O

ATmega169/V

2514P–AVR–07/06

Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Co mpare

pins, is defined by the combination of the Waveform Generation mode (WGM01:0) and

Compare Output mode (COM0A1:0) bits. The Compare Output mode bits do not affect

the counting sequence, while the Waveform Generation mode bits do. The COM0A1:0

bits control whether the PWM output genera ted should be inverted or not (inverte d or

non-inverted PWM). For non-PWM modes the COM0A1 :0 bits control whether the out-

put should be set, cleare d, or toggled at a compare match (See “Com pare Match Ou tput

Unit” on page 83.).

For detailed timing information refer to Figure 34, Figure 35, Figure 36 and Figure 37 in

“Timer/Counter Timing Diagrams” on page 88.

Normal Mode The simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the

counting direction is a lways up (incrementing) , and no counte r clear is performe d. The

counter simply overrun s whe n it passes it s maximum 8-bit va lue (T OP = 0xFF) and t hen

restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag

(TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The

TOV0 Flag in this case beha ves like a ninth bit, except that it is only set, not cleared.

However, combined with the timer overflow interrupt that automatically clears the TOV0

Flag, the timer resolution can be increase d by software. There are no special cases to

consider in the Normal mode, a new counter value can be written anytime.

The Output Compare unit can be used to generate interrupts at some given time. Using

the Output Compare to generate waveforms in Normal mode is not recommended,

since this will occupy too much of the CPU time.

Clear Timer on Compare

Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM01:0 = 2), the OCR0A Register is used

to manipulate the counter resolution. In CTC mode the counter is cleared to zero when

the counter value (TCNT0) matches the OCR0A. The OCR0A defines the top value for

the counter, hence also its resolution. This mode allows greater control of the compare

match output frequency. It also simplifies the operation of counting external even ts.

The timing diagram for the CTC mode is shown in Figure 31. The counter value

(TCNT0) increases until a compare match occurs between TCNT0 and OCR0A, and

then counter (TCNT0) is cleared.

Figure 31. CTC Mode, Timing Diagram

An interrupt can be generated each time the counter value reaches the TOP value by

using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be

used for updatin g the TOP value. However, changing TOP to a value close to BOTTOM

when the counter is running with none or a low prescaler value must be done with care

since the CTC mode d oes not h ave th e double buffer ing feat ure. If the new value wr itten

CNTn

(

Toggle)

OCnx Interrupt Flag Set

1 4

eriod

2 3

(COMnx1:0 = 1)

ATmega169/V

2514P–AVR–07/06

to OCR0A is lower than the current value of TCNT0, the counter will miss the compare

match. The counter will then have to count to its maximum value (0xFF) and wrap

around star ting at 0x 00 bef or e th e com p ar e mat ch can occur.

For generating a waveform output in CTC mode, the OC0A output can be set to toggle

its logical level on each compa re match by setting th e Compare Output mode bits to tog-

gle mode (COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the

data direction for the pin is set to output. The waveform generated will have a maximum

frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero (0 x00). The wavefor m frequ ency

is defined by the following equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

As for the Normal mode of oper at ion, t he TOV0 F lag is set in the sam e t imer cloc k cycle

that the counter counts from MAX to 0x00.

Fast PWM Mode Th e fast Pu lse Width Mo dulat ion or fast PWM mod e (WGM01:0 = 3) prov ides a high fre-

quency PWM waveform generation option. The fast PWM differs from the other PWM

option by its single-slope operation. The counter coun ts from BOTTO M to MAX then

restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare

(OC0A) is clear ed on the comp are match between TCNT0 an d OCR0A, and se t at BOT-

TOM. In inverting Compare Output mode, the output is set on compare match and

cleared at BOTTOM. Due to the single- slope operation, the operating frequ ency of the

fast PWM mode can be twice as high as the phase correct PWM mode that use dual-

slope operation. This high frequency makes the fast PWM mode well suited for power

regulation, rectification, and DAC applications. High frequency allows physically small

sized external components (coils, capacitors), and therefor e reduces total system cost.

In fast PWM mode, th e co un ter is increme nt ed unt il the count er value mat c hes the MAX

value. The counter is then cleared at the following timer clock cycle. The timing diagram

for the fast PWM mode is shown in Figure 32. The TCNT0 value is in t he timi ng diag ram

shown as a histogram for illustrating the single-slope operation. The diagram includes

non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0

slopes represent compare matches between OCR0A and TCNT0.

Figure 32. Fast PWM Mode, Timing Diagram

fOCnx fclk_I/O

2N1OCRnx+()⋅⋅

----------------------------------------------

----

TCNTn

OCRnx Update and

TOVn Interrupt Flag Set

Period 2 3

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCRnx Interrupt Flag Se

4 5 6 7

ATmega169/V

2514P–AVR–07/06

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If

the interrupt is enabled, the interrupt handler routine can be used for updating the com-

pare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the

OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM and an

inverted PWM output can b e generated by set ting the COM0A1:0 to thr ee (See Table 51

on page 90). The actual OC0A value will only be visible on the port pin if the data direc-

tion for the port pin is set as output. The PWM waveform is generated by setting (or

clearing) the OC0A Register at the compare match between OCR0A and TCNT0, and

clearing (or setting) the O C0A Register at the timer clock cycle the counter is cleared

(changes from MAX to BOTTOM).

The PWM frequency for th e output can be calculated by the following equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR0A Register represents special cases when generating

a PWM waveform output in th e fast PWM m ode. If the O CR0 A is set eq ual to BOTTO M,

the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR 0A

equal to MAX will result in a constantly high or low output (depending on the polarity of

the output set by the COM0A1:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved

by setting OC0A to toggle its logical level on each compare match (COM 0A1:0 = 1). The

waveform generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A is

set to zero. This feature is similar to the OC0A toggle in CTC mode, except the double

buffer feature of the Output Compare unit is enabled in the fast PWM mode.

Phase Correct PWM Mode The phase correct PWM mode (WGM01:0 = 1) provides a high resolut ion phase correct

PWM waveform generation option. The phase correct PWM mode is based on a dual-

slope operation. The counter counts repeatedly from BOTTOM to MAX and then from

MAX to BOTTOM. In no n-inverting Compar e Output mode , the Output Compare (OC0A)

is cleared on the compare match between TCNT0 and OCR0A while upcounting, and

set on the compa re match while d owncounting . In inverting Outp ut Compare m ode, the

operation is inverted. The dual-slop e operation ha s lower maxim um operat ion frequency

than single slope operation. However, due to the symmetric feature of the dual-slope

PWM modes, these modes are preferred for motor control applications.

The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase

correct PWM mo de the counter is incr emented until the counte r value matches MAX.

When the counter reaches MAX, it changes the count direction. The TCNT0 value will

be equal to MAX for one timer clock cycle. The timing diagram for the phase correct

PWM mode is shown on Figure 33. The TCNT0 value is in the timing diagram shown as

a histogram for illustrating the dual-slope operation. The diagram includes non-inverted

and inverted PWM outputs. The sm all horizont al line marks on the TCNT0 slope s r epre-

sent compare matches between OCR0A and TCNT0.

fOCnxPWM fclk_I/O

N256⋅

------------------=

ATmega169/V

2514P–AVR–07/06

Figure 33. Phase Correct PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOT-

TOM. The Interrupt Flag can be use d to generate an interrupt each time the counter

reaches the BOTTOM value.

In phase corr ect PWM mode, the compare uni t allows generation of PWM waveforms on

the OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM . An

inverted PWM output can b e generated by set ting the COM0A1:0 to thr ee (See Table 52

on page 91). The actual OC0A value will only be visible on the port pin if the data direc-

tion for the port pin is set a s output. The PWM waveform is gen erated by clearing (or

setting) the OC0A Register at the compare match between OCR0A and TCNT0 when

the counter increments, and setting (or clearing) the OC0A Register at compare match

between OCR0A and TCNT0 when the counter decrements. The PWM frequency for

the output when using phase correct PWM can be calculated by the following equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR0A Register represent special cases when generating a

PWM waveform output in the phase correct PWM mode. If the OCR0A is set equal to

BOTTOM, the output will be continuously low and if set equal to MAX the output will be

continuously high for non-inverted PWM mode. For inverted PWM the output will have

the opposite logic values.

At the very start of period 2 in Figure 33 OCn has a transition from high to low even

though there is no Compar e Match. The poi nt of th is transit ion is to gu arantee symmetr y

around BOTTOM. There are two cases that give a transition without Compare Match.

• OCR0A changes its value from MAX, like in Figure 33. When the OCR0A value is

MAX the OCn pin value is the same as the result of a d own-counting Compare

Match. To ensure symmetry around BOTTOM the OCn value at MAX must

correspond to t he result of an up-counting Compare Match.

TOVn Interrupt Flag Set

OCnx Interrupt Flag Set

1 2 3

TCNTn

Period

OCn

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCRnx Update

fOCnxPCPWM fclk_I/O

N510⋅

------------------=

ATmega169/V

2514P–AVR–07/06

• The timer starts counting from a value higher than the one in OCR0A, and for that

reason misses the Compare Match and hence the OCn change that would have

happened on the way up.

Timer/Counter Timing

Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore

shown as a clock enable signal in the following figures. The figures include information

on when Interrupt Flags are set. Figure 34 contains timing data for basic Timer/Counter

operation. The fig ure shows the count sequence close to th e MAX value in all modes

other than phase correct PWM mode.

Figure 34. Timer/Counter Timing Diagram, no Prescaling

Figure 35 shows the same timing data, but with the prescaler enabled.

Figure 35. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)

Figure 36 shows the set ting of OCF0A in all modes except CTC mode.

Figure 36. Timer/Counter Timing Diagram, Setting of OCF0A, with Prescaler (fclk_I/O/8)

clk

(clkI/O/1)

TOVn

clk

I/O

TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1

TOVn

TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1

clk

I/O

clk

(clkI/O/8)

OCFnx

OCRnx

TCNTn

OCRnx Value

OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2

clk

I/O

clk

(clkI/O/8)

ATmega169/V

2514P–AVR–07/06

Figure 37 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode .

Figure 37. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with

Prescaler (fclk_I/O/8)

8-bit Timer/Counter

Timer/Counter Control

• Bit 7 – FOC0A: Force Output Compare A

The FOC0A bit is only active when the WGM00 bit specifies a non-PWM mode. How-

ever, for ensuring compatibility with future devices, this bit must be set to zero when

TCCR0A is written when operating in PWM mode. When writing a logical one to the

FOC0A bit, an immediate compare match is forced on the Waveform Generation unit.

The OC0A output is changed according to its COM0A1:0 bits setting. Note that the

FOC0A bit is implemented as a strobe. Therefore it is the value present in the

COM0A1:0 bits that determines the effect of the forced compare.

A FOC0A strobe will not generate a ny interrupt, nor will it clear the timer in CTC mode

using OCR0A as TOP.

The FOC0A bit is always read as zero.

• Bit 6, 3 – WGM01:0: Waveform Generation Mode

These bits control the coun ting sequence of the counter, the source for the maximum

(TOP) counter value , and what type of waveform generation to be use d. Modes of oper-

ation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare

match (CTC) mode, a nd two t ypes of Pulse Width Modulatio n (PWM) modes. See Table

49 and “Modes of Oper ation” on page 84.

OCFnx

OCRnx

TCNTn

(CTC)

TOP

TOP - 1 TOP BOTTOM BOTTOM + 1

clk

I/O

clk

(clkI/O/8)

Bit 7 6 5 4 3 2 1 0

FOC0A WGM00 COM0A1 COM0A0 WGM01 CS02 CS01 CS00 TCCR0A

Read/Write W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

ATmega169/V

2514P–AVR–07/06

Note: 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 def-

initions. However, the functionality and location of these bits are compatible with

previous versions of the timer.

• Bit 5:4 – COM0A1 :0: Compare Match Output Mode

These bits control the Output Compare pin (OC0A) behavior. If one or both of the

COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the

I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit cor-

responding to the OC0A pin must be set in order to enable the output driver.

When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the

WGM01:0 bit setting. Table 50 shows the COM0A1:0 bit functionality when the

WGM01:0 bits are set to a normal or CTC mode (non-PWM).

Table 51 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast

PWM mode.

Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case,

the compare match is ignored, but the set or clear is done at BOTTOM. See “Fast

PWM Mode” on page 85 for more details.

Table 49. Waveform Generation Mode Bit Description(1)

Mode WGM01

(CTC0) WGM00

(PWM0) Timer/Counter

Mode of Operation TOP Update of

OCR0A at TOV0 Flag

Set on

0 0 0 Normal 0xFF Immediate MAX

1 0 1 PWM, Phase Correct 0xFF T OP BO TTOM

2 1 0 CTC OCR0A Immediate MAX

3 1 1 Fast PWM 0xFF BOTTOM MAX

Table 50. Compare Output Mode, non-PWM Mode

COM0A1 COM0A0 Description

0 0 Normal port operation, OC0A disconnected.

0 1 Toggle OC0A on compare match

1 0 Clear OC0A on compare match

1 1 Set OC0A on compare match

Table 51. Compare Output Mode, Fast PWM Mode(1)

COM0A1 COM0A0 Description

0 0 Normal port operation, OC0A disconnected.

01Reserved

1 0 Clear OC0A on compare match, set OC0A at BOTTOM

(non-inverting mode)

1 1 Set OC0A on compare match, clear OC0A at BOTTOM

(inverting mode)

ATmega169/V

2514P–AVR–07/06

Table 52 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to

phase correct PWM mode.

Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case,

the compare match is ignored, but the set or clear is done at TOP. See “Phase Cor-

rect PWM Mode” on page 86 for more details.

• Bit 2:0 – CS02:0: Clock Se lect

The three Cloc k Select bits select the clock source to be used by the Timer/Counter.

If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will

clock the counter even if the pin is configured as an output. This feature allows software

control of the co unting.

Timer/Counter Register –

TCNT0

The Timer/Counter Register gives direct access, both for read and write operations, to

the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes)

the compare match on the following timer clock. Modifying the counter (TCNT0) while

the counter is running, introduces a risk of missing a compare match between TCNT0

and the OCR0A Register.

Table 52. Compare Output Mod e, Phase Correct PWM Mode(1)

COM0A1 COM0A0 Description

0 0 Normal port operation, OC0A disconnected.

01Reserved

1 0 Clear OC0A on compare match when up-counting. Set OC0A on

compare match when downcounting.

1 1 Set OC0A on compare match when up-counting. Clear OC0A on

compare match when downcounting.

Table 53. Clock Select Bit Description

CS02 CS01 CS00 Description

0 0 0 No clock source (Timer/Counter stopped)

001clk

I/O/(No prescaling)

010clk

I/O/8 (From prescaler)

011clk

I/O/64 (From prescaler)

100clk

I/O/256 (From prescaler)

101clk

I/O/1024 (From prescaler)

1 1 0 External clock source on T0 pin. Clock on falling edge.

1 1 1 External clock source on T0 pin. Clock on rising edge.

Bit 76543210

TCNT0[7:0] TCNT0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

ATmega169/V

2514P–AVR–07/06

Output Compare Re gister A –

OCR0A

The Output Compare Register A contains an 8-bit value that is continuously compared

with the counter value (TCNT0). A match can be used to generate an Output Compare

interrupt, or to generate a waveform output on the OC0A pin.

Timer/Counter 0 Interrupt

Mask Register – TIMSK0

• Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable

When the OCIE0A bit is written to one, and the I-bit in the Status Register is set (one),

the Timer/C ounter 0 Comp are Matc h A interr upt is en abled. Th e corres pondin g interr upt

is executed if a compare match in Timer/Counter0 occurs, i.e., when the OCF0A bit is

set in the Timer/Counter 0 Interrupt Flag Register – TIFR0.

• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 b it is writ te n to o ne, and t he I-bit in the St atus Re giste r is se t ( one), t he

Timer/Counter0 Over flow interr upt is enabled . The correspond ing interrupt is executed if

an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the

Timer/Coun te r 0 In te rr up t Fla g Re gist er – TIFR0 .

Timer/Counter 0 Interrupt Flag

• Bit 1 – OCF0A: Output Compare Flag 0 A

The OCF0A bit is set (one) when a compare match occurs between th e Timer/Counter0

and the data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware

when executing the corresponding interru pt handling vecto r. Alternatively, OCF0A is

cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A

(Timer/Counter0 Compare match Interrupt Enable), and OCF0A are set (one), the

Timer/Counter0 Compare match Interrupt is executed.

• Bit 0 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared

by hardware when executing the corresponding interrupt handling vector. Alternatively,

TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0

(Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the

Timer/Counter0 Overflow interrupt is executed. In phase correct PWM mode, this bit is

set when Timer/Counter 0 changes counting direction at 0x00.

Bit 76543210

OCR0A[7:0] OCR0A

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

––––––OCIE0ATOIE0TIMSK0

Read/WriteRRRRRRR/WR/W

Initial Value00000000

Bit 76543210

––––––OCF0ATOV0 TIFR0

Read/WriteRRRRRRR/WR/W

Initial Value00000000

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Timer/Counter0 and

Timer/Counter1

Prescalers

Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the

Timer/Counters can have differe nt prescaler settings. The description below ap plies to

both Timer/Counter1 and Timer/Counter0.

Internal Clock Source The Timer/Counter can be clocked directly by th e syst em clock (by set t ing t he CSn 2:0 =

1). This provides the fastest operation, w ith a maximum Timer/Counter clock frequency

equal to system clock frequency (fCLK_I/O). Alternatively, one of four taps from the pres-

caler can be used as a clock source. The presca led clock has a frequency of either

fCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or fCLK_I/O/1024.

Prescaler Reset The prescaler is free running, i.e., operates independently of the Clock Select logic of

the Timer/Counter, and it is shared by Timer/Counter1 and Timer/Counter0. Since the

prescaler is not affected by the Timer/Counter’s clock se lect, the state of the prescaler

will have implications for situations where a prescaled clock is used. One ex ample of

prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 >

CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the

first count occurs can be from 1 to N+1 system clock cycles, where N equals the pres-

caler divisor (8, 64, 256, or 1024).

It is possible to use the prescaler reset for synchronizing the Timer/Counter to program

execution. However, care must be taken if the other Timer/Counter that shares the

same prescaler also uses prescaling. A prescaler reset will affect the prescaler period

for all Timer/Counters it is connected to.

External Clock Source An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock

(clkT1/clkT0). The T1/T0 pin is sample d once every system clock cycle by the pin syn-

chronization logic. The synchronized (sampled) signal is then passed through the edge

detector. Figure 38 shows a functional equivalent block diagram of the T1/T0 synchroni-

zation and edge detector logic. The registers are clocked at the positive edge of the

internal system clock (clkI/O). The latch is transparent in the high period of the internal

system clock.

The edge det ector gener ates one clkT1/clkT0 pulse for each positive ( CSn2:0 = 7) or neg-

ative (CSn2:0 = 6) edge it detects.

Figure 38. T1/T0 Pin Sampling

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system

clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated.

Enabling and disabling of the clock input must be done when T1/T0 has been stable for

at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock

pulse is generated.

Each half period of the external clock applied must be longer than one system clock

cycle to ensure correct sampling. The external clock must be guaranteed to have less

than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since

Tn_sync

(To Clock

Select Logic)

Edge DetectorSynchronization

DQDQ

clkI/O

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the edge detector uses sampling, the maximum frequency of an external clock it can

detect is half the samplin g fr eq uency (Nyqu i st sa mpli ng t heo rem). However , due t o va ri-

ation of the system clock frequency and duty cy cle caused by Oscillator source (cry stal,

resonator, and capacit ors) tolerances, it is recomm ended that maximum freq uency of an

external clock source is less than fclk_I/O/2.5.

An external clock source can not be presca le d.

Figure 39. Prescaler for Timer/Counter0 and Timer/Counter 1(1)

Note: 1. The synchronization logic on the input pins (T1/T0) is shown in Figure 38.

General Timer/Counter

Control Register – GTCCR

• Bit 7 – TSM: Timer/Counter Synchronization Mode

Writing the TSM b it to one activates the Time r/Counter Synchronization mod e. In this

mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the

corresponding prescaler reset signals asserted. This e nsures that the corresponding

Timer/Counters are halted and can be configured to the same value without the risk of

one of them advancing during configuration. When the TSM bit is written to zero, the

PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting

simultaneously.

• Bit 0 – PSR10: Prescaler Rese t Timer/Counter1 and Timer/Counter0

When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This

bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that

Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this pres-

caler will affect both timers.

PSR10

Clear

clkT1 clkT0

clkI/O

Synchronization

Bit 7 6 5 4 3 2 1 0

TSM – – – – – PSR2 PSR10 GTCCR

Read/Write R/W R R R R R R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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16-bit

Timer/Counter1 The 16-bit Timer/Counter unit allows accurate program execution timing (event man-

agement), wave generation, and signal timing measurement. The main features are:

•True 16-bit Design (i.e., Allows 16-bit PWM)

•Two independent Output Compare Units

•Double Buffered Output Compare Registers

•One Input Capture Unit

•Input Capture Noise Canceler

•Clear Timer on Compare Match (A uto Reload)

•Glitch-free, Phase Correct Pulse Width Modulator (PWM)

•Variable PWM Period

•Frequency Generator

•External Event Counter

•Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)

Overview Most register and bit references in this section are written in general form. A lower case

“n” replaces the Timer/Counter number, and a lower case “x” replaces the Output Com-

pare unit number. However, when using the register or bit defines in a program, the

precise form must be used, i.e., TCNT1 for accessing Timer/Cou nter1 counter value

and so on.

A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 40. For the

actual placement of I/O pins, refer to “Pinout ATmega169” on pag e 2. CPU accessible

I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O

on page 117.

The PRTIM1 bit in “Power Reduction Register - PRR” on page 34 must be written to

zero to enable Timer/Counter1 module

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Figure 40. 16-bit Timer/Counter Block Diagram(1)

Note: 1. Refer to Figure 1 on page 2, Table 29 on page 63, and Table 35 on page 67 for

Timer/Counter1 pin placement and descrip tion.

Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture

accessing the 16-bit registers. These procedures are described in the section “Access-

ing 16-bit Registers” on pa ge 98. The Timer/Counter Control Registers (TCCR1A/B) are

8-bit registers and have no CPU access restrictio ns. Interrupt requests (abbre viated to

Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR1).

All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK1).

TIFR1 and TIMSK1 are not shown in the figure.

The Timer/Counter ca n be clocked internally, via the p rescaler, or by an external clock

source on the T1 pin. The Clock Select logic block controls which cloc k source and edge

the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is

inactive when no clock source is selected. The output from the Clock Select logic is

referred to as the timer clock (clkT1).

The double buffered Output Compare Registers (OCR1A/B) are compared with the

Timer/Counter va lue at all time. The result of the compare can be used by the Waveform

Generator to generate a PWM or variable frequency output on the Output Compare pin

(OC1A/B). See “Output Compare Units” on page 104. The compare match event will

Clock Select

Timer/Counter

DATA BU S

OCRnA

OCRnB

ICRn

TCNTn

Waveform

Generation

Waveform

Generation

OCnA

OCnB

Noise

Canceler

ICPn

Fixed

TOP

Values

Edge

Detector

Control Logic

= 0

TOP BOTTOM

Count

Clear

Direction

TOVn

(Int.Req.)

OCnA

(Int.Req.)

OCnB

(Int.Req.)

ICFn (Int.Req.)

TCCRnA TCCRnB

( From Analog

Comparator Ouput )

Edge

Detector

( From Prescaler )

clkTn

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also set the Compare Match Flag (OCF1A/B) which can be used to generate an Output

Compare interrupt request.

The Input Capture Register can capture the Timer/Coun ter value at a given external

(edge triggered) event on either the Input Capture pin (ICP1) or on the Analog Compar-

ator pins (See “Analog Comparator” on page 190.) The Input Capture unit includes a

digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes.

The TOP value, or maximum Timer/Counter value, can in some modes of operation be

defined by either the OCR1A Register, the ICR1 Register, or by a set of fixed values.

When using OCR1A as TOP value in a PWM mode, the OCR1A Register can not be

used for generating a PWM output. However, the TOP value will in this case be double

buffered allowing the TOP value to be changed in run time. If a fixed TOP value is

required, the ICR1 Register can be used as an alternative, freeing th e OCR1A to be

used as PWM output.

Definitions The following definitions are used extensively throughout the section:

Compatibility The 16-bit Timer/Coun ter has been u pdate d and improved fro m previous versions of the

16-bit AVR Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier

version regarding:

• All 16-bit Timer/Counter related I/O Register a ddress locations, including Timer

Interrupt Registers.

• Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt

Registers.

• Interrupt Vectors.

The following control bits have changed name, but have same functionality and register

location:

• PWM10 is changed to WGM10.

• PWM11 is changed to WGM11.

• CTC1 is changed to WGM12.

The following bits are added to the 16-bit Timer/Counter Control Registers:

• FOC1A and FOC1B are added to TCCR1C.

• WGM13 is added to TCCR1B.

The 16-bit Timer/Counter has improvements that will affect the compatibility in some

special cases.

Table 54. Definitions

BOTTOM The counter reaches the BOTTOM when it becomes 0x0000.

MAX The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535).

TOP

The counter reaches the TOP when it becomes equal to the highest value in the

count sequence. The TOP value can be assigned to be one of the fixed values:

0x00FF, 0x01FF, or 0x03 FF, or to the value stored in the OCR1A or ICR1 Regis-

ter. The assignment is dependent of the mode of operation.

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Accessing 16-bit

Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR

CPU via the 8-b it data bus. The 16-bit register must be byte accessed using two read or

write operations. Each 1 6-bit time r has a sin gle 8-bit register for tem porary stor ing of the

high byte of the 16- bit a ccess. The same t empor ary r egist er is share d bet ween all 16- bit

registers within ea ch 16-bit t imer. Acce ssing the low byt e triggers the 16-bit rea d or write

operation. When the low byte of a 16-bit register is written by the CPU, the high byte

stored in the temporary register, and the low byte written are both copied into the 16-bit

CPU, the high byte of the 16 -bit register is copied into the temporary register in the

same clock cycle as the low byte is read.

Not all 16-bit accesses uses the temporary register for the high byte. Reading the

OCR1A/B 16-bit registe rs does not involve using the temporary register.

To do a 16-bit writ e, th e high byt e mu st be wr it te n befo re th e low byt e. For a 16 -b it rea d,

the low byte must be read before the high byte.

The following code examples show how to access the 16-bit Timer Registers assuming

that no interru pts updates the temporary register. The same principle can be used

directly for accessing the OCR1A/B and ICR1 Registers. Note that when using “C”, the

compiler handles the 16-bit access.

Note: 1. See “About Code Examp les” on page 6.

The assembly code example returns the TCNT1 value in the r17:r16 register pair.

It is important to notice that accessing 16-bit registers are atomic operations. If an inter-

rupt occurs between the two instructions accessing the 16-bit register, and the interrupt

code updates the temporary register by accessing the same or any other of the 16-bit

Timer Registers, then the result of the access outside the interrupt will be corrupted.

Therefore, when both the main code and the interrupt code update the temporary regis-

ter, the main code must disable the interrupts during the 16-bit access.

Assembly Code Examples(1)

...

; Set TCNT1 to 0x01FF

ldi r17,0x01

ldi r16,0xFF

out TCNT1H,r17

out TCNT1L,r16

; Read TCNT1 into r17:r16

in r16,TCNT1L

in r17,TCNT1H

...

C Code Examples(1)

unsigned int i;

...

/* Set TCNT1 to 0x01FF */

TCNT1 = 0x1FF;

/* Read TCNT1 into i */

i = TCNT1;

...

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The following code examples show how to do an atomic read of the TCNT1 Register

contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the

same principle .

Note: 1. See “About Code Examp les” on page 6.

The assembly code example returns the TCNT1 value in the r17:r16 register pair.

Assembly Code Example(1)

TIM16_ReadTCNT1:

; Save global interrupt flag

in r18,SREG

; Disable interrupts

cli

; Read TCNT1 into r17:r16

in r16,TCNT1L

in r17,TCNT1H

; Restore global interrupt flag

out SREG,r18

ret

C Code Example(1)

unsigned int TIM16_ReadTCNT1( void )

{

unsigned char sreg;

unsigned int i;

/* Save global interrupt flag */

sreg = SREG;

/* Disable interrupts */

__disable_interrupt();

/* Read TCNT1 into i */

i = TCNT1;

/* Restore global interrupt flag */

SREG = sreg;

return i;

}

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The following code examples show how to do an atomic write of the TCNT1 Register

contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the

same principle .

Note: 1. See “About Code Examp les” on page 6.

The assembly code example requires that the r17:r16 register pair contains the va lue to

be written to TCNT1.

Reusing the Temporary High

Byte Register If writing to more than one 16-bit reg ister where t he high byte is the same for all regi sters

written, then the high byte only needs to be written o nce. However, note that the same

rule of atomic operation described previously also applies in this case.

Assembly Code Example(1)

TIM16_WriteTCNT1:

; Save global interrupt flag

in r18,SREG

; Disable interrupts

cli

; Set TCNT1 to r17:r16

out TCNT1H,r17

out TCNT1L,r16

; Restore global interrupt flag

out SREG,r18

ret

C Code Example(1)

void TIM16_WriteTCNT1( unsigned int i )

{

unsigned char sreg;

unsigned int i;

/* Save global interrupt flag */

sreg = SREG;

/* Disable interrupts */

__disable_interrupt();

/* Set TCNT1 to i */

TCNT1 = i;

/* Restore global interrupt flag */

SREG = sreg;

}

101

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Timer/Counter Clock

Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock

source is selected by the Clock Select logic which is controlled by the Clock Select

(CS12:0) bits located in the Timer/Counter control Register B (TCCR1B). For details on

clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on

page 93.

Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional

counter unit. Figure 41 shows a block diagram of the counter and its surroundings.

Figure 41. Counter Unit Block Diagr am

Signal description (internal signals):

Count Increment or decrement TCNT1 by 1.

Direction Select between increment and decrement.

Clear Clear TCNT1 (set all bits to zero).

clkT1Timer/Counter clock.

TOP Signalize that TCNT1 has reached maximum value.

BOTTOM Signalize that TCNT1 ha s reached minimum value (zero).

The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High

(TCNT1H) containing the uppe r eight bits of the counter, and Counter Low (TCNT1L)

containing the lower eight bits. The TCNT1H Register can only be indirectly accessed

by the CPU. When the CPU does an access to the TCNT1H I/O location, the CPU

accesses the high byte temporary register (TEMP). The temporary register is updated

with the TCNT1H value when the TCNT1L is read, and TCNT1H is updated with the

temporary register value when TCNT1L is written. This allows the CPU to read or write

the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is impor-

tant to notice that there are special cases of writing to the TCNT1 Register when the

counter is counting that will give unpredictable results. The special cases are described

in the sections where they are of importance.

Depending on the mode of operation used, the counter is cleared, incremented, or dec-

remented at each timer clock (clkT1). The clkT1 can be generated from an external or

internal clock source, selected by the Clock Sele ct bits (CS12:0). When no clock source

is selected (CS12:0 = 0) the timer is stopped. However, the TCNT1 value can be

accessed by the CPU, independent of whether clk T1 is present or not. A CPU write ove r-

rides (has priority over) all counter clear or count operations.

The counting sequence is determined by the setting of the Waveform Generation mode

bits (WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and

TCCR1B). There are close connections between how the cou nter behaves (counts) and

TEMP (8-bit)

DATA BUS (8-bit)

TCNTn (16-bit Counter)

TCNTnH (8-bit) TCNTnL (8-bit) Control Logic

Count

Clear

Direction

TOVn

(Int.Req.)

Clock Select

TOP BOTTOM

Edge

Detector

( From Prescaler )

clkTn

102

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how waveforms are generated on the Output Compare outputs OC1x. For more details

about advanced counting seque nces and waveform generation, se e “Modes of Opera-

tion” on page 107.

The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation

selected by the WGM13:0 bits. TOV1 can be used for generating a CPU int errupt.

Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events

and give them a time-stamp indicat ing time of occurr ence. The ext ernal signal in dicat ing

an event, or multiple events, can be applied via the ICP1 p in or alternatively, via the

analog-comparator unit. The time-stamps can then be used to calculate frequen cy, duty-

cycle, and other features of the signal applied. Alternatively the time-stamps can be

used for creating a log of the events.

The Input Capture unit is illustrated by the block diagram shown in Figure 42. The ele-

ments of the block diagram that are not directly a part of the Input Capture unit are gray

shaded. The small “n ” in register and bit names indicates t he Timer/Counter number.

Figure 42. Input Capture Unit Block Diagram

When a change of the logic level (an event) occurs on the Input Capture pin (ICP1),

alternatively on the Analog Comparator output (ACO), and this chan ge confirms to the

setting of the edge detector, a capture will be triggered. When a capture is triggered, the

16-bit value of the counter (TCNT1) is written to the Input Capture Register (ICR1). The

Input Capture Flag (ICF1) is set at the same system clock as the TCNT1 value is copied

into ICR1 Register. If enabled (ICIE1 = 1), the Input Capture Flag generat es an Input

Capture interrup t. The ICF1 Flag is autom atically cleared when th e interrupt is executed.

Alternatively the ICF1 Flag can be cleared by software by writing a logical one to its I/O

bit location.

Reading the 16-bit value in the In put Capture Register (I CR1) is done by first readin g the

low byte (ICR1L) and then the high byte (ICR1H). When the low byte is read the high

byte is copied into the high byte temporary register (TEMP). When the CPU reads the

ICR1H I/O location it will access the TE MP Regis ter.

ICFn (Int.Req.)

Analog

Comparator

WRITE ICRn (16-bit Register)

ICRnH (8-bit)

Noise

Canceler

ICPn

Edge

Detector

TEMP (8-bit)

DATA BUS (8-bit)

ICRnL (8-bit)

TCNTn (16-bit Counter)

TCNTnH (8-bit) TCNTnL (8-bit)

ACIC* ICNC ICES

ACO*

103

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The ICR1 Register can only be written when using a Waveform Generation mode that

utilizes the ICR1 Register for defining the counter’s TOP value. In these cases the

Waveform Generation mode (WGM13:0) bits must be set before the TOP value can be

written to the I CR1 Register . When wr itin g the ICR1 Reg iste r the hig h byt e must b e wri t-

ten to the ICR1H I/O location before the low byte is written to ICR1L.

For more information on how to access the 16-bit registers refer to “Accessing 16-bit

Registers” on page 98.

Input Capture Trigger Source The main trigger source for the Input Capture unit is the Input Capture pin (ICP1).

Timer/Counter1 can alternatively use the Analog Comparator output as trigger source

for the Input Capture unit. The Analog Comparator is selected as trigger source by set-

ting the Analog Comparator Input Capture (ACIC) bit in the Analo g Comp arator C ontrol

and Status Register (ACSR). Be aw are that changing trigger source can trigger a cap-

ture. The Input Capture Flag must th erefore be cleared after the change.

Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs are

sampled using the same technique as for the T1 pin (Figure 38 on page 93). The edge

detector is also identical. However, when the noise canceler is enabled, addition al logic

is inserted before the edge detector, which increases the delay by four system clock

cycles. Note that the input of the noise canceler and edge detector is always enabled

unless the Timer/Counter is set in a Waveform Ge neration mode that uses ICR1 to

define TOP.

An Input Capture can be triggered by software by controlling the port of the ICP1 pin.

Noise Canceler The noise canceler improves noise immunity by using a simple dig ital filtering scheme.

The noise canceler input is monitored over four samples, and all four must be equal for

changing the output that in turn is used by the edge detector.

The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit

in Timer/Counter Control Register B (TCCR1B). When enabled t he noise cancel er in tro-

duces additional f our syst em clock cycle s of de lay from a chang e applie d t o the input , to

the update of the I CR1 Register . The no ise canceler uses the system clock and is ther e-

fore not affected by the prescaler.

Using the Input Capture Unit The main challenge when using the Input Capture unit is to assign enough pr ocessor

capacity for handling the incomin g even ts. The tim e betwee n two events is crit ical. If the

processor has not read the captured value in the ICR1 Register before the next event

occurs, the ICR1 will be overwritten with a new value. In this case the result of the cap-

ture will be incorrect.

When using the I nput Captur e interrup t, the ICR1 Re gister shou ld be read as ear ly in the

interrupt handler routine as possible. Even though the Input Capture interrupt has rela-

tively high priority, the maximum interrupt response time is dependent on the maximum

number of clock cycles it takes t o handle any of the other interrupt requests.

Using the Input Capture unit in any mode of operation when the TOP value (resolution)

is actively changed during operation, is not recommended.

Measurement of an external signa l’s duty cycle requires that the trigger edge is changed

after each capture. Changing the edge sensing must be done as early as possible after

the ICR1 Register has been read. After a change of the edge, the Inpu t Capture Flag

(ICF1) must be cleared by software (writing a logical one to the I/O bit location). For

measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt

handler is used).

104

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Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Co mpare Re gis-

ter (OCR1x). If TCNT equals OCR1x the compara tor signals a match. A match will set

the Output Com pare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x =

1), the Output Compare Flag generates an Output Compare interrupt. The OCF1x Flag

is automatically cleared when the interrupt is executed. Alternatively the OCF1x Flag

can be cleared by software by writing a logical one to its I/O bit location. The Waveform

Generator uses th e matc h signa l to gene ra te an ou tp ut acco rdin g to ope ra tin g mode set

by the Waveform Generation mode (WGM13:0) bits and Compare Output mode

(COM1x1:0) bits. The TOP and BOTTOM signals are used by the Waveform Generator

for handling the special cases of the extreme values in some modes of operation (See

“Modes of Operation” on page 107.)

A special feature of Output Compare unit A allows it to define the Timer/Counter TOP

value (i.e., counter resolution). In addition to the counter resolution, the TOP value

defines the period time for waveforms generate d by the Waveform Generator.

Figure 43 shows a b lock diagram of the Outp ut Compar e un it. The smal l “ n” in t he regi s-

ter and bit names indicates the device number (n = 1 fo r Timer/Counter 1), and the “x”

indicates Output Compare unit (A/B). The elements of the block diagram that are not

directly a part of the Output Compare unit are gray shaded.

Figure 43. Output Compare Unit, Block Diagram

The OCR1x Register is double buffered when using any of the twelve Pulse Width Mod-

ulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of

operation, the double buffering is disabled. The double buffering synchronizes the

update of the OCR1x Compare Register to either TOP or BOTTOM of the counting

sequence. The synchronizati on p revents the occurren ce of odd-le ngth, n on-symmet rical

PWM pulses, thereby making the out put glitch-free.

The OCR1x Register access may seem complex, bu t this is not case . When the d ouble

buffering is enabled, the CPU has access to the OCR1x Buffer Register, and if double

buffering is disabled the CPU will access the OCR1x directly. The content of the OCR1x

OCFnx (Int.Req.)

= (16-bit Comparator )

OCRnx Buffer (16-bit Register)

OCRnxH Buf. (8-bit)

OCnx

TEMP (8-bit)

DATA BUS (8-bit)

OCRnxL Buf. (8-bit)

TCNTn (16-bit Counter)

TCNTnH (8-bit) TCNTnL (8-bit)

COMnx1:0WGMn3:0

OCRnx (16-bit Register)

OCRnxH (8-bit) OCRnxL (8-bit)

Waveform Generator

TOP

BOTTOM

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(Buffer or Compare) Register is only changed by a write operation (the Timer/Counter

does not update t his register automa tically as the TCNT1 a nd ICR1 Regist er). Therefo re

OCR1x is not read via the high byte temporary register (TEMP). However, it is a good

practice to read the low byt e first as when accessing other 16- bit registers. Writing the

OCR1x Registers must be done via the TEMP Register since the compare of all 16 bits

is done continuously. The high byte (OCR1xH) has to be written first. When the high

byte I/O location is written by the CPU, the TEMP Register will be updated by the value

written. Then whe n the lo w byte (OCR1xL) is written to the lower eight bits, the high byte

will be copied into the upper 8-bits of either the OCR1x buffer or OCR1x Compare Reg-

ister in the same system clock cycle.

For more infor mation of how to access the 16-bit registers refer to “Accessing 16-bit

Registers” on page 98.

Force Output Compare In non-PWM Waveform Generation modes, the match output of the comparator can be

forced by writing a one to the Force Output Compare (FOC1x) bit. Forcing compare

match will not set the OCF1x Flag or reload/clear the timer, but the OC1x pin will be

updated as if a real compare match had occurred (the COMx1:0 bits settings define

whether the OC1x pin is set, cleared or toggled).

Compare Match Bloc king by

TCNT1 Write All CPU writes to the TCNT1 Register will block any compare match that occurs in the

next timer clock cycle, e ven whe n the timer is st opped . T his feat ure a llows OCR1x to be

initialized to the same value as TCNT1 without triggering an interrupt when the

Timer/Counter clock is enabled.

Using the Output Compare

Unit Since writing TCNT1 in any mode of operation will block all compare matches for one

timer clock cycle, there are risks involved when changing TCNT1 when using any of the

Output Compare units, independent of whether the Timer/Counter is running or not. If

the value written to TCNT1 equals the OCR1x value, the compare match will be missed,

resulting in incorrect waveform generation. Do not write the TCNT1 equal to TOP in

PWM modes with variable TOP values. The compare match for the TOP will be ignored

and the counter will continue to 0xFFFF. Similarly, do not write the TCNT1 value equal

to BOTTOM when the counter is downcounting.

The setup of the OC1x should be performed before setting the Data Direction Register

for the port pin to output. The easiest way of setting the OC1x value is to use the Force

Output Compare (FOC1x) strob e bits in Normal mode. The OC1x Reg ister keeps its

value even when changing between Waveform Generation mod es.

Be aware that the COM1x1:0 bits are not double buffered together with the compare

value. Changing the COM1x1:0 bits will take effect immediately.

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Compare Match Output

Unit The Compare Output mode (COM1x1:0) bits have two functions. The Waveform G ene r-

ator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next

compare match. Secondly the COM1x1:0 bits control the OC1x pin output source. Fig-

ure 44 shows a sim plified schematic of the log ic affected by the COM 1x1:0 bit setting.

The I/O Regist ers, I/ O bits, and I /O pins in the f igure are shown in bold. Only th e par ts of

the general I/O Port Control Registers (DDR and PORT) that are affected by the

COM1x1:0 bits are shown. When referring to the OC1x state, the reference is for the

internal OC1x Register, not the OC1x pin. If a system reset occur, the OC1x Register is

reset to “0”.

Figure 44. Compare Match Output Unit, Schematic

The general I/O port function is overridden by the Output Compare (OC1x) from the

Waveform Generator if either of the COM1x1:0 bits are set. However, the OC1x pin

direction (input or output) is still controlled by the Data Direction Register (DDR) for the

port pin. The Data Direction Register bit for the OC1x pin (DDR_OC1x) must be set as

output before t he OC1x value is visible on the pin . The port override functi on is generally

independent of the Waveform Generation mode, but there are some exceptions. Re fer

to Table 55, Table 56 and Table 57 for details.

The design of the Output Co mpare pin log ic allows initia lization of the OC1x state before

the output is enabled. Note that some COM1x1:0 bit settings are reserved for certain

modes of operation. See “16-bit Timer/Counter Register Description” on page 117.

The COM1x1:0 bits have no effect on the Input Capture unit.

PORT

DDR

OCnx

Waveform

Generator

COMnx1

COMnx0

DATA BUS

FOCnx

clk

I/O

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Compare Output Mode and

Waveform Generat ion The Waveform Ge ner ator u se s t he COM1 x1 :0 b i ts d iff e ren tl y in nor mal, CTC, and PWM

modes. For all modes, setting the COM1x1:0 = 0 tells the Waveform Generator that no

action on the OC1x Register is to be performed on the next compare match. For com-

pare output actions in the non-PWM modes refer to Table 55 on page 117. For fast

PWM mode refe r to Table 56 on page 11 7, and for phase corr ect and phase and fre -

quency correct PWM refer to Table 57 on page 118.

A change of the COM1x1:0 bits state will have effect at the first compare match after the

bits are written. For non-PWM mod es, the action can be forc ed to have immediate effect

by using the FOC1x strobe bits.

Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Co mpare

pins, is de fined by th e combina tion of the Waveform Generation mode (WGM13:0) and

Compare Output mo de (COM1x1:0) bits. The Compare Output mode bits do not affect

the counting sequence, while the Waveform Generation mode bits do. The COM1x1:0

bits control whether the PWM output genera ted should be inverted or not (inverte d or

non-inverted PWM ). For non-PWM modes the COM1 x1:0 bits control whether th e out-

put should be set, cleared or toggle at a compare match (See “Compare Match Output

Unit” on page 106.)

For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 115.

Normal Mode The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the

counting direction is a lways up (incrementing) , and no counte r clear is performe d. The

counter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and

then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counte r Over-

flow Flag (TOV1) will be set in the same timer clock cycle as the TCNT1 becomes zero.

The TOV1 Flag in this case be haves like a 17th bit, excep t that it is only se t, not clea red.

However, combined with the timer overflow interrupt that automatically clears the TOV1

Flag, the timer resolution can be increase d by software. There are no special cases to

consider in the Normal mode, a new counter value can be written anytime.

The Input Capture unit is easy to use in Normal mode. However, observe that the maxi-

mum interval bet ween the extern al events must not exceed t he resolution of the count er.

If the interval between events are too long, the timer overflow interrupt or the prescaler

must be used to extend the resolution for the capture unit.

The Output Co mpare units ca n be used to genera te interru pts at some given time. Using

the Output Compare to generate waveforms in Normal mode is not recommended,

since this will occupy too much of the CPU time.

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Clear Timer on Compare

Match (CTC) Mode In Cle ar Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1

cleared to zero when the counter value (TCNT1) matches either the OCR1A (WGM13:0

= 4) or the ICR1 (WGM13:0 = 12). The OCR1A or ICR1 define the top value for the

counter, hence also its resolution. Th is mode allows greater control of the compare

match output frequency. It also simplifies the operation of counting external even ts.

The timing diagram for the CTC mode is shown in Figure 45. The counter value

(TCNT1) increases until a compare match occurs with either OCR1A or ICR1, and then

counter (TCNT1) is cleared.

Figure 45. CTC Mode, Timing Diagram

An interrupt can be generated at each time the counter value reaches the TOP value by

either using the OCF 1A or ICF1 Flag according to the register used to define the TOP

value. If the interrupt is enabled, the interrupt handler routine can be used for updating

the TOP value. However, changing the TO P to a value close to BOTTOM when the

counter is running with none or a low prescaler value must be done with care since the

CTC mode does not have the double buffering feature. If the new value written to

OCR1A or ICR1 is lower than the current value of TCNT1, the counter will miss the com-

pare match. The counter will then have to count to its maximum value (0xFFFF) and

wrap around starting at 0x0000 before the compare match can occur. In many cases

this feature is not desirable. An alternative will then be to use the fast PWM mode using

OCR1A for defining TOP (WGM13:0 = 15) since the OCR1A then will be double

buffered.

For generating a waveform output in CTC mode, the OC1A output can be set to toggle

its logical level on each compa re match by setting th e Compare Output mode bits to tog-

gle mode (COM1A1:0 = 1). The OC1A value will not be visible on the port pin unless the

data direction for the pin is set to output (DDR_OC1A = 1). The waveform generated will

have a maximum freq uency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). The

waveform frequency is defined by the following equation:

The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).

As for the Normal mode of oper at ion, t he TOV1 F lag is set in the sam e t imer cloc k cycle

that the counter counts from MAX to 0x0000.

TCNTn

OCnA

(Toggle)

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

1 4

Period 2 3

(COMnA1:0 = 1)

OCnA fclk_I/O

2N1OCRnA+()⋅⋅

-----------------------------------------------

----

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Fast PWM Mode The fast Pulse Width Modulation o r f a st PWM m ode (WG M13:0 = 5, 6, 7 , 14, o r 1 5) pr o-

vides a high frequen cy PWM waveform generation option . The fast PWM differs from

the other PWM options by its single-slo pe oper at ion. Th e co unte r coun ts from BOTTOM

to TOP then restar ts from BOTT OM. In non- inverting Compar e Outpu t mode, the Output

Compare (OC1x) is cleared on the compa re match between TCNT1 and OCR1x, and

set atBOTTOM. In inverting Comp ar e Outpu t mode output is set on comp ar e mat ch and

cleared at BOTTOM. Due to the single- slope operation, the operating frequ ency of the

fast PWM mode can be twice as high as the phase correct and phase and frequency

correct PWM modes that use dual-slope operation. This high frequency makes the fast

PWM mode well suited for power regulatio n, rectification, and DAC applications. High

frequency allows physically small size d external components (coils, capacitors), he nce

reduces total system cost.

The PWM resolution for fast PW M can be fixed to 8-, 9-, or 10-bit, or defined by eithe r

ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to

0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM

resolution in bits can be calculated by using the following equation:

In fast PWM mode the counter is incremented until the counter value matches either

one of the fixe d values 0x0 0FF, 0x0 1FF, or 0x03F F (WGM13: 0 = 5, 6, or 7) , the va lue in

ICR1 (WGM13:0 = 14), or the value in OCR1A (WGM13:0 = 15). The co unter is then

cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is

shown in Figure 46. The figure shows fast PWM mode when OCR1A or ICR1 is used to

define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illus-

trating the single-slop e operation. The diagram includes non- inverted and inverted PWM

outputs. The small horizontal line marks on the TCNT1 slopes represent compare

matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a com-

pare match occurs.

Figure 46. Fast PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In

addition the OC1A or ICF1 Flag is set at the same timer clock cycle as TOV1 is set

when either OCR1A or ICR1 is used for defining the TOP value. If one of the interrupts

are enabled, the interrupt handler routine can be used for updating the TOP and com-

pare values.

RFPWM TOP 1+()log 2()log

-------------------------------

----

TCNTn

OCRnx / TOP Update

and TOVn Interrupt Flag

Set and OCnA Interrupt

Flag Set or ICFn

Interrupt Flag Set

(Interrupt on TOP)

1 7

Period 2 3 4 5 6 8

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

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When changing the TOP value the program must ensure that the new TOP value is

higher or equal to the value of all of the Compare Registers. If the TOP value is lower

than any of the Compare Registers, a compare match will never occur betwe en the

TCNT1 and the OCR1x. Note that when usin g fixed TOP values the unused bits are

masked to zero when an y of th e OCR1x Registers are writ te n.

The procedure for u pdating ICR1 differs from upd ating OCR1A when used for defining

the TOP value. The ICR1 Register is not double buffered. This means that if ICR1 is

changed to a low value when the counter is running with none or a low prescaler value,

there is a risk that the new ICR1 value written is lower than the current value of TCNT1.

The result will then be that the counter will miss the compare match at the TOP value.

The counter will then have to count to the MAX value (0xFFFF) and wrap around start-

ing at 0x0000 before the compare match can occur. The OCR1A Register however, is

double buffered. This feature allows the OCR1A I/O location to be written anytime.

When the OCR1A I/O location is written the value written will be put into the OCR1A

Buffer Register. The OCR1A Compare Register will then be updated with the value in

the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The update is

done at the same timer clock cycle as the TCNT1 is cleared and the TOV1 Flag is set.

Using the ICR1 Register for defining TOP works well when using fixed TOP values. By

using ICR1, the OCR1A Register is free to be used for generating a PWM output on

OC1A. However, if the base PWM frequency is actively changed (by changing the TOP

value), using the OCR1A as TOP is clearly a better choice due to its double buffer

feature.

In fast PWM mode, the compare units allow generation of PWM waveforms on the

OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an

inverted PWM output can be generat ed by setting the COM1x1:0 t o three (see Table on

page 117). The actual OC1x value will only be visible on the port pin if the data direction

for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by set-

ting (or clear ing) the OC1x Register at the compare match between OCR1x and TCNT1,

and clearing (or setting) the OC1x Register at the timer clock cycle the counter is

cleared (change s from TOP to BOTTOM).

The PWM frequency for th e output can be calculated by the following equation:

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCR1x Register represents special cases when generating

a PWM waveform ou tput in the fast PWM mode. If the OCR1x is set equal to BOTTOM

(0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle. Setting the

OCR1x equal to TOP will result in a constant high or low output (depending on the polar-

ity of the output set by the COM1x1:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved

by setting OC1A to toggle its logical level on each compare match (COM1A1:0 = 1).

This applies only if OCR1A is used to def ine the TOP value (WGM13:0 = 15). The wave-

form generated will have a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set to

zero (0x0000). This feature is similar to the OC1A toggle in CTC mode, except the dou-

ble buffer feature of the Output Compare unit is enabled in the fast PWM mode.

OCnxPWM fclk_I/O

N1TOP+()⋅

-------------------------------

----

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Phase Correct PWM Mode The ph ase correct Pulse Width Modula tion o r phase correct PWM mode (WGM13: 0 = 1,

2, 3, 10, or 11) provides a high resolution phase correct PWM waveform generation

option. The phase correct PWM mode is, like the phase and frequency correct PWM

mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM

(0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output

mode, the Output Compare (OC1x) is cleared on the compare match between TCNT1

and OCR1x while upcounting, and set on the compare match while downcounting. In

inverting Outp ut Compare m ode, the operatio n is inverte d. The dua l-slope operat ion has

lower maximum operation frequency than single slope operation. However, due to the

symmetric feature of the dual-slope PWM modes, these modes are preferred for motor

control applications.

The PWM resolution f or the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or

defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or

OCR1A set to 0x0003), and the maxim um resolution is 16-bit (ICR1 or OCR1A set to

MAX). The PWM resolution in bits can be calculated by using the following equation:

In phase correct PWM m ode t he coun t er is incre men ted unt il th e cou nter value ma t ches

either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the

value in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter

has then reached the TOP and changes the count direction. The TCNT1 value will be

equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM

mode is shown on Figu re 47 . The fi gure sho ws phase corr ect PWM m ode when OCR1A

or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a

histogram for illustrating the dual-slope operation. The diagram includes non-inverted

and inverted PWM outputs. The sm all horizont al line marks on the TCNT1 slope s r epre-

sent compare matches between OCR1x and TCNT1. The OC1x Interr upt Flag will be

set when a compare match occur s.

Figure 47. Phase Correct PWM Mode, Timing Diagram

RPCPWM TOP 1+()log 2()log

-------------------------------

----

OCRnx/TOP Update and

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

1 2 3 4

TOVn Interrupt Flag Set

(Interrupt on Bottom)

TCNTn

Period

OCnx

(COMnx1:0 =

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The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOT-

TOM. When either OCR1A or ICR1 is used for definin g the TOP value, the OC1A or

ICF1 Flag is set accordingly at the same timer clock cycle as the OCR1x Registers are

updated with the double buffer value (at TOP). The Interrupt Flags can be used to gen-

erate an interrupt each time the counter reaches the TOP or BOTTOM value.

When changing the TOP value the program must ensure that the new TOP value is

higher or equal to the value of all of the Compare Registers. If the TOP value is lower

than any of the Compare Registers, a compare match will never occur betwe en the

TCNT1 and the OCR1x. Note that when using fixed TOP values, the unused bits are

masked to zero when any of t he OCR1x Reg isters are writ ten. As the t hird period sho wn

in Figure 47 illustrates, changing the TOP actively while the Timer/Counter is running in

the phase correct mode can result in an unsymmetrical output. The reason for this can

be found in the time of update of the OCR1x Register. Since the OCR1x update occurs

at TOP, the PWM period starts and ends at TOP. This implies that the length of the fall-

ing slope is determined by the pr evious TOP valu e, while th e length of the rising slope is

determined by the new TOP valu e. When these two values differ the two slopes of the

period will differ in length. The difference in length gives the unsymmetrical result on the

output.

It is recommended to use the phase and frequency correct mode instead of the phase

correct mode when changing the TOP value while the Timer/Counter is running. When

using a static TOP value there are practically no differences between the two modes of

operation.

In phase correct PWM mode, the compare uni ts allow generation of PWM waveforms on

the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and

an inverted PWM outp ut can be gener ated by setting the COM 1x1:0 to t hree ( See Table

57 on page 118). The actual OC1x value will only be visible on the port pin if the data

direction for the port pin is set as output (DDR_OC1x). The PWM waveform is gener-

ated by setting (or clearing) the OC1x Register at the compare match between OCR1x

and TCNT1 when the coun ter increme nts, and clear ing (or sett ing) the O C1x Register at

compare match between OCR1x and TCNT1 when the counter decrements. The PWM

frequency for the output when using phase correct PWM can be calculated by the fol-

lowing equation:

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCR1x Register represent special cases when generating a

PWM waveform output in the pha se correct PWM mode. If the OCR1x is set equal to

BOTTOM the output will be continuously low and if set equal to TOP the output will be

continuously high for non-inverted PWM mode. For inverted PWM the output will have

the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 11)

and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle.

fOCnxPCPWM fclk_I/O

2NTOP⋅⋅

----------------------------=

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Phase and Frequency Correct

PWM Mode The phase and frequency correct Pulse Width Modulation, or phase and frequency cor-

rect PWM mode (WGM13:0 = 8 or 9) provides a high resolution phase and frequency

correct PWM waveform generation option. The phase and frequency correct PWM

mode is, like the phase correct PWM mode, based on a dual-slope operation. The

counter counts repe atedly from BOTTO M (0x0 000) to TOP an d th en fr om TOP to BOT-

TOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared

on the compare match between TCNT1 and OCR1x while upcounting, and set on the

compare match while downcounting. In inverting Compare Output mode, the operation

is inverted. The dual-slope operation gives a lower maximum operation frequency com-

pared to the single-slope operation. However, due to the symmetric feature of the dual-

slope PWM modes, these modes are preferred for motor control applications.

The main difference between the phase correct, and the phase and frequency correct

PWM mode is the time the OCR1x Register is upda ted by the OCR1x Buffer Register,

(see Figure 47 and Figure 48).

The PWM resolution for the phase and frequency correct PWM mode can be defined by

either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to

0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM

resolution in bits can be calculated using the following equation:

In phase and frequency correct PWM mode the counter is incremented until the counter

value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A

(WGM13:0 = 9). The counter has then reached the TOP and changes the count direc-

tion. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing

diagram for t he ph ase co rr ect and f re que ncy correct PWM mode is shown on Figure 48.

The figure shows phase and frequen cy correct PWM mode when OCR1A or ICR1 is

used to define TO P. The TCNT1 value is in th e timing d iagram shown as a histogra m for

illustrating the dual-slope operation. The diagram includes n on-inverted and inverted

PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare

matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a com-

pare match occurs.

Figure 48. Phase and Frequency Correct PWM Mode, Timing Diagram

RPFCPWM TOP 1+()log 2()log

-------------------------------

----

OCRnx/TOP Updateand

TOVn Interrupt Flag Set

(Interrupt on Bottom)

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Se

(Interrupt on TOP)

1 2 3 4

TCNTn

Period

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

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The Timer/Counter Overflow Flag (TOV1) is set at the same tim er clock cycle as the

OCR1x Registers are updated with the double buffer value (at BOTTOM). When either

OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag set when

TCNT1 has reached TOP. The I nterrupt Flags can th en be used to genera te an interru pt

each time the counter reaches the TOP or BOTTOM value.

When changing the TOP value the program must ensure that the new TOP value is

higher or equal to the value of all of the Compare Registers. If the TOP value is lower

than any of the Compare Registers, a compare match will never occur betwe en the

TCNT1 and the OCR1x.

As Figure 48 shows the output generated is, in co ntrast to the phase correc t mode, sym-

metrical in all periods. Since the OCR1x Registers are updated at BOTTOM, the length

of the rising and the falling slopes will always be equal. This gives symmetrical output

pulses and is therefore frequency correct.

Using the ICR1 Register for defining TOP works well when using fixed TOP values. By

using ICR1, the OCR1A Register is free to be used for generating a PWM output on

OC1A. However, if the base PWM frequency is actively changed by changing the TOP

value, using the OCR1A as TOP is clearly a better choice due to its double buffer

feature.

In phase and frequency correct PWM mode, the compare units allow generation of

PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a

non-inverted PWM and an inverted PWM output can be generated by setting the

COM1x1:0 to three (See Table 57 on page 118). The actual OC1x value will only be vis-

ible on the port pin if the data direction for th e port pin is set a s output (DDR_O C1x). The

PWM waveform is generated by setting (or clearing) the OC1x Register at the compare

match between OCR1x and TCNT1 when the counter increments, and clearing (or set-

ting) the OC1x Register at compare match between OCR1x and TCNT1 when the

counter decrements. The PWM frequency for the output when using phase and fre-

quency correct PWM can be calculated by the following equation:

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCR1x Register represents special cases when generating

a PWM waveform output in the phase and frequency correct PWM mode. If the OCR1x

is set equal to BOTTOM the output will be continuously low and if set equal to TOP the

output will be set to high for non-inverted PWM mode. For inverted PWM the output will

have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 =

9) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle.

fOCnxPFCPWM fclk_I/O

2NTOP⋅⋅

----------------------------=

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Timer/Counter Timing

Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore

shown as a clock enable signal in the following figures. The figures include information

on when Interrupt Flags are set, and when the OCR1x Register is updated with the

OCR1x buffer value (only for modes utilizing double buffering). Figure 49 shows a timing

diagram for th e set tin g of OCF1x.

Figure 49. Timer/Count er Timing Diagram, Setting of OCF1x, no Prescaling

Figure 50 shows the same timing data, but with the prescaler enabled.

Figure 50. Timer/Count er Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8)

Figure 51 shows the count sequence close to TOP in vari ous modes. When using phase

and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The

timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by

BOTTOM+1 and so on. The same renaming ap plies for modes that set the TOV1 Flag

at BOTTOM.

clk

(clkI/O/1)

CFnx

clk

I/O

CRnx

CNTn

OCRnx V alue

OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2

CFnx

CRnx

CNTn

OCRnx V alue

OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2

clk

I/O

clk

(clkI/O/8)

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Figure 51. Timer/Counter Timing Diagram, no Prescaling

Figure 52 shows the same timing data, but with the prescaler enabled.

Figure 52. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)

TOVn

(FPWM)

and ICFn

(if used

as T OP)

OCRnx

(Update at TOP)

TCNTn

(CTC and FPWM)

TCNTn

(

PC and PFC PWM)

TOP - 1 TOP TOP - 1 TOP - 2

Old OCRnx Value New OCRnx Value

TOP - 1 TOP BOTTOM BOTTOM + 1

clkTn

(clk

I/O

/1)

clkI/O

TOVn (FPWM)

nd ICFn (if used

as T OP)

OCRnx

(Update at TOP)

TCNTn

(CTC and FPWM)

TCNTn

(PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2

Old OCRnx Value New OCRnx Value

TOP - 1 TOP BOTTOM BOTTOM + 1

clk

I/O

clk

(clk

I/O

/8)

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16-bit Timer/Counter

Timer/Counter1 Control

• Bit 7:6 – COM1A1:0: Compare Output Mode for Unit A

• Bit 5:4 – COM1B1:0: Compare Output Mode for Unit B

The COM1A1:0 and COM1B1:0 control the Ou tput Compare pins (OC1A and OC1B

respectively) beh avior. If one or bot h of t he COM1A1 :0 b its a re writ ten t o one, th e OC1A

output overrides the normal port functionality of the I/O pin it is connected to. If one or

both of the COM1B1:0 bit are written to one, the OC1B output overrides the normal port

functionality of the I/O pin it is connected to. However, note that the Data Direction Reg-

ister (DDR) bit corresponding to the O C1A or OC1B pin must be set in order to enable

the output driver.

When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is

dependent of the WGM13:0 bits setting. Table 55 shows the COM1x1:0 bit functionality

when the WGM13:0 bits are set to a Normal or a CTC mode (non-PWM).

Table 56 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the

fast PWM mode.

Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is

set. In this case the compare match is ignored, but the set or clear is done at BOT-

TOM. See “Fast PWM Mode” on page 109. for more details.

Bit 7 6 5 43210

COM1A1 COM1A0 COM1B1 COM1B0 – – WGM11 WGM10 TCCR1A

Read/Write R/W R/W R/W R/W R R R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Table 55. Compare Output Mod e, non-PWM

COM1A1/COM1B1 COM1A0/COM1B0 Description

0 0 Normal port operation, OC1A/OC1B

disconnected.

0 1 Toggle OC1A/OC1B on Compare Match.

1 0 Clear OC1A/OC1B on Compare Match (Set

output to low level).

1 1 Set OC1A/OC1B on Compare Match (Set output

to high level).

Table 56. Compare Output Mod e, Fast PWM(1)

COM1A1/COM1B1 COM1A0/COM1B0 Description

0 0 Normal port operation, OC1A/OC1B

disconnected.

0 1 WGM13:0 = 14 or 15: Toggle OC1A on Compare

Match, OC1B disconnected (normal port

operation). For all other WGM1 settings, normal

port operation, OC1A/OC1B disconnected.

1 0 Clear OC1A/OC1B on Compare Match, set

OC1A/OC1B at BO TTOM (non-inverting mode)

1 1 Set OC1A/OC1B on Compare Match, clear

OC1A/OC1B at BO TTOM (inverting mode)

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Table 57 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the

phase correct or the phase and frequency correct, PWM mode.

Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is

set. See “Phase Correct PWM Mode” on page 111. for more details.

• Bit 1:0 – WGM11:0: Waveform Generation Mode

Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the

counting sequence of the counter, the sou rce for maximum (TOP) counter value, and

what type of waveform generation to be used, see Table 58. Modes of operation sup-

ported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare

match (CTC) mode, and three types of Pu lse Width Modulation (PWM) modes. (See

“Modes of Operation” on page 107.).

Tab le 57. Compare Output Mode, Phase Correct and Phase and Frequency Correct

PWM(1)

COM1A1/COM1B1 COM1A0/COM1B0 Description

0 0 Normal port operation, OC1A/OC1B

disconnected.

0 1 WGM13:0 = 9 or 11: Toggle OC1A on Compare

Match, OC1B disconnected (normal port

operation). For all other WGM1 settings, normal

port operation, OC1A/OC1B disconnected.

1 0 Clear OC1A/OC1B on Compare Match wh en up-

counting. Set OC1A/OC1B on Compare Match

when downcounting.

1 1 Set OC1A/OC1B on Compare Match when up-

counting. Clear OC1A/OC1B on Compare Match

when downcounting.

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Note: 1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and

location of these bits are compatible with previous versions of the timer.

Timer/Counter1 Control

• Bit 7 – ICNC1: Input Capture Noise Canceler

Setting this bit (to one) activates the Input Capture Noise Cancele r. When the no ise can-

celer is activated, the input from the Input Capture pin (ICP1) is filtered. The filter

function requires four successive equal valued samples of the ICP1 pin for changing its

output. The Input Capture is therefore delayed by four Oscillator cycles when the noise

canceler is enabled.

• Bit 6 – ICES1: Input Capture Edge Select

This bit selects which edge on the Inpu t Captur e pin (ICP1) tha t is used to tr igger a cap-

ture event. When the ICES1 bit is written to zer o, a falling (negative) edge is used as

trigger, and when the ICES1 bit is written to one, a rising (positive) edge will trigger the

capture.

When a capture is triggered according to the ICES1 setting, the counter value is copied

into the Input Capture Register (ICR1). The event will also set the Input Capture Flag

Table 58. Waveform Genera tion Mode Bit Description(1)

Mode WGM13 WGM12

(CTC1) WGM11

(PWM11) WGM10

(PWM10) Timer/Counter Mode of

Operation TOP Update of

OCR1x at TOV1 Flag

Set on

0 0 0 0 0 Normal 0xFFFF Immediate MAX

1 0 0 0 1 P WM, Phase Correct, 8-bit 0x00FF TOP BOTTOM

2 0 0 1 0 P WM, Phase Correct, 9-bit 0x01FF TOP BOTTOM

3 0 0 1 1 P WM, Phase Correct, 10-bit 0x03FF TOP BOTTOM

4 0 1 0 0 CTC OCR1A Immediate MAX

5 0 1 0 1 Fast PWM, 8-bit 0x00FF BOTTOM TOP

6 0 1 1 0 Fast PWM, 9-bit 0x01FF BOTTOM TOP

7 0 1 1 1 Fast PWM, 10-bit 0x03FF BOTTOM TOP

8 1 0 0 0 PWM, Phase and Frequency

Correct ICR1 BOTTOM BOTTOM

9 1 0 0 1 PWM, Phase and Frequency

Correct OCR1A BOTTOM BOTTOM

10 1 0 1 0 PWM, Phase Correct ICR1 TOP BOTTOM

11 1 0 1 1 PWM, Phase Correct OCR1A TOP BOTTOM

12 1 1 0 0 CTC ICR1 Immediate MAX

13 1 1 0 1 (Reserved) – – –

14 1 1 1 0 Fast PWM ICR1 BOTTOM TOP

15 1 1 1 1 Fast PWM OCR1A BOT TOM TOP

Bit 76543210

ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 TCCR1B

Read/Write R/W R/W R R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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(ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt is

enabled.

When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in

the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently

the Input Capture function is disabled.

• Bit 5 – Reserved Bit

This bit is reserved for future use. For ensuring compatibility with future devices, this bit

must be written to zero when TCCR1B is written.

• Bit 4:3 – WGM13:2: Waveform Generation Mode

See TCCR1A Register description.

• Bit 2:0 – CS12:0: Clock Se lect

The three Cloc k Select bits select the clock source to be used by the Time r/Counter, see

Figure 49 and Figure 50.

If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will

clock the counter even if the pin is configured as an output. This feature allows software

control of the co unting.

Timer/Counter1 Control

• Bit 7 – FOC1A: Force Output Compare for Unit A

• Bit 6 – FOC1B: Force Output Compare for Unit B

The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM

mode. However, for ensuring compatibility with future devices, these bits must be set to

zero when TCCR1A is written when operating in a PWM mode. When writing a logical

one to the FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform

Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits

setting. Note that the FOC1A/FOC1B b its are implemented as strobes. Therefore it is

the value present in the COM1x1:0 bits that determine the effect of the forced compare.

Table 59. Clock Select Bit Description

CS12 CS11 CS10 Description

0 0 0 No clock source (Timer/Counter stopped).

001clk

I/O/1 (No prescal i ng)

010clk

I/O/8 (From prescaler)

011clk

I/O/64 (From prescaler)

100clk

I/O/256 (From prescaler)

101clk

I/O/1024 (From prescaler)

1 1 0 Exter nal clock source on T1 pin. Clock on falling edge.

1 1 1 Exter nal clock source on T1 pin. Clock on risin g edge.

Bit 76543210

FOC1A FOC1B – – – – – – TCCR1C

Read/Write R/W R/W R R R R R R

Initial Value 0 0 0 0 0 0 0 0

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A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear

Timer on Compare match (CTC) mode using OCR1A as TOP.

The FOC1A/FOC1B bits are always rea d as zero.

Timer/Counter1 – TCNT1H

and TCNT1L

The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give

direct access, both for read and for write operations, to the Timer/Counter unit 16-bit

counter. To ensur e t hat bot h the h i gh an d lo w byte s are r ea d and wr it te n simulta ne ously

when the CPU accesses these registers, the access is performed using an 8-bit tempo-

rary High Byte Register (T EMP). Th is tem por ary re gister is sh are d by all the othe r 1 6-bit

registers. See “Accessing 16-bit Registers” on page 98.

Modifying the counter (TCNT1) while the counter is running introduces a risk of missing

a compare match between TCNT1 and one of the OCR1x Registers.

Writing to the TCNT1 Register blocks (removes) the compare match on the following

timer clock for all compare units.

Output Compare Re gister 1 A

– OCR1AH and OCR1AL

Output Compare Re gister 1 B

– OCR1BH and OCR1BL

The Output Compare Registers contain a 16-bit value that is continuously compared

with the counter value (TCNT1). A match can be used to generate an Output Compare

interrupt, or to generate a waveform output on the OC1x pin.

The Output Compare Registers are 16-bit in size. To ensure that both the high and low

bytes are written simultaneously when the CPU writes to these registers, the access is

performed using an 8- bit tempor ary High Byt e Register (TEMP) . This t emp orar y r egister

is shared by all the other 16-b it registers. See “Accessing 16-bit Registers” on page 98.

Bit 76543210

TCNT1[15:8] TCNT1H

TCNT1[7:0] TCNT1L

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

OCR1A[15:8] OCR1AH

OCR1A[7:0] OCR1AL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

OCR1B[15:8] OCR1BH

OCR1B[7:0] OCR1BL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

122

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Input Capture Register 1 –

ICR1H an d ICR1L

The Input Captu re is updated with the counter (TCNT1) value each time a n event occurs

on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1).

The Input Capture can be used for defining the counter TOP value.

The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes

are read simultaneou sly when the CPU accesses these regist ers, the access is per-

formed using an 8-bit temporary High Byte Register (TEMP). This temporary register is

shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 98.

Timer/Counter1 Interrupt

Mask Register – TIMSK1

• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-

bally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The

corresponding Interrupt Vector (See “Interrupts” on page 46.) is executed when the

ICF1 Flag, located in TIFR1, is set.

• Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-

bally enabled), the Timer/Counte r1 Output Compare B Match interrupt is enabled. The

corresponding Interrupt Vector (See “Interrupts” on page 46.) is executed when the

OCF1B Flag, locate d in TIFR1, is set.

• Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-

bally enabled), the Timer/Counte r1 Output Compare A Match interrupt is enabled. The

corresponding Interrupt Vector (See “Interrupts” on page 46.) is executed when the

OCF1A Flag, locate d in TIFR1, is set.

• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-

bally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding

Interrupt Vecto r (See “Int errupt s” on pa ge 46.) is ex ecuted wh en th e TOV1 Fla g, located

in TIFR1, is set.

Bit 76543210

ICR1[15:8] ICR1H

ICR1[7:0] ICR1L

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

––ICIE1–– OCIE1B OCIE1A TOIE1 TIMSK1

Read/Write R R R/W R R R/W R/W R/W

Initial Value00000000

123

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Timer/Counter1 Interrupt Flag

• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag

This flag is set wh en a capture event occurs on the ICP1 p in. When the Inpu t Capture

set when the counter reaches the TOP value.

ICF1 is automati cally cleared when th e Input Capture Int errupt Vector is execute d. Alter-

natively, ICF1 can be cleared by writing a logic one to its bit location.

• Bit 2 – OCF1B: Timer/Counter1, Output Compare B Match Flag

This flag is set in the timer clock cycle after the counter ( TCNT1) value match es the Ou t-

put Compare Register B (OCR1B).

Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag.

OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is

executed. Alternatively, OCF1B can be cleared by writing a logic one to its bit location.

• Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match Flag

This flag is set in the timer clock cycle after the counter ( TCNT1) value match es the Ou t-

put Compare Register A (OCR1A).

Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag.

OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is

executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.

• Bit 0 – TOV1: Timer/Counter1, Overflow Flag

The setting of this flag is dependent of the WGM13:0 bits setting. In Normal and CTC

modes, the TOV1 Flag is set when the timer overflows. Refer to Table 58 on page 119

for the TOV1 Flag behavior when using another WGM13:0 bi t setting.

TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is

executed. Alte rn at ive ly, TO V1 can be clea re d by writing a logic one to its bit loc at ion .

Bit 76543210

––ICF1–– OCF1B OCF1A TOV1 TIFR1

Read/Write R R R/W R R R/W R/W R/W

Initial Value00000000

124

ATmega169/V

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8-bit Timer/Counter2

with PWM and

Asynchronous

Operation

Timer/Counter2 is a general purpose, single compare unit, 8-bit Timer/Counter module.

The main featur es ar e:

•Single Compare Unit Counter

•Clear Timer on Compare Match (A uto Reload)

•Glitch-free, Phase Correct Pulse Width Modulator (PWM)

•Frequency Generator

•10-bit Clock Prescaler

•Overflow and Compare Match Interrupt Sources (TOV2 and OCF2A)

•Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock

Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 53. For the

actual placement of I/O pins, refer to “Pinout ATmega169” on pag e 2. CPU accessible

I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O

page 135.

Figure 53. 8-bit Timer/Counter Block Diagram

Registers The Timer/Counter (T CNT2) and Outpu t Compare Register (OCR2A) are 8-bit re gisters.

Interrupt request (shorten as Int.Re q.) signals are all visible in the Timer Interrupt Flag

The Timer/Counter can be clocked internally, via the prescaler, or asynchronously

clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous

operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select

logic block controls which clock source the Timer/Counter uses to increment (or decre-

Timer/Counter

DATA BUS

TCNTn

Waveform

Generation OCnx

= 0

Control Logic

= 0xFF

TOPBOTTOM

count

clear

direction

TOVn

(Int.Req.)

OCnx

(Int.Req.)

Synchronization Unit

OCRnx

TCCRnx

ASSRn

Status flags

clkI/O

clkASY

Synchronized Status flags

asynchronous mode

select (ASn)

TOSC1

T/C

Oscillator

TOSC2

Prescaler

clkTn

clkI/O

125

ATmega169/V

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ment) its value. The Timer/Counter is inactive when no clock source is selected. The

output from the Clock Select logic is referred to as the timer clock (clkT2).

The double buffered Output Compare Register (OCR2A) is compared with the

Timer/Counter value at all times. Th e result of the compare can be used by the Wave-

form Generat or to gener ate a PWM or vari able frequency ou tput on t he Output Co mpare

pin (OC2A). See “Output Compare Unit” on page 126. for details. The compare match

event will also set the Compare Flag (OCF2A) which can be used to generate an Output

Compare interrupt request.

Definitions Many register and bit references in this document are written in general form. A lower

case “n” replaces the Timer/Counter number, in this case 2. However, when using the

accessing Timer/Counter2 counter value and so on.

The definitions in Table 60 are also used extensively throughout the section.

Timer/Counter Clock

Sources The Timer/Counter can be clocked by an internal synchronous or an external asynchro-

nous clock source. The clock source clkT2 is by default equal to the MCU clock, clkI/O.

When the AS2 bit in the ASSR Register is written to logic one, the clock source is taken

from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For details on

asynchronous operation, see “Asynchronous Status Register – ASSR” on page 138. For

details on clock sources and prescaler, see “Timer/Counter Prescaler” on page 142.

Counter Unit The main part of t he 8-bit T imer/Co unter is the p rogramma ble bi-dire ctional cou nter unit.

Figure 54 shows a block diagram of the counter and its surrounding environment.

Figure 54. Counter Unit Block Diagr am

Signal description (internal signals):

count Increment or decrement TCNT2 by 1.

direction Selects between increment and decrement.

clear Clear TCNT2 (set all bits to zero).

clkT2Timer/Counter clock.

Table 60. Definitions

BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00).

MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255).

TOP The cou nter reaches the TOP when it becomes equal to the highest

value in the count sequence. The TOP value can be assigned to be the

fixed value 0xFF (MAX) or the value stored in the OCR2A Register. The

assignment is depen dent on the mode of opera tion.

DATA BUS

TCNTn Control Logic

count

TOVn

(Int.Req.)

topbottom

direction

clear

TOSC1

T/C

Oscillator

TOSC2

Prescaler

clkI/O

clk Tn

126

ATmega169/V

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top Signalizes that TCNT2 has reached maximum value.

bottom Signalizes that TCNT2 has reached minimum value (zero).

Depending on the mode of operation used, the counter is cleared, incremented, or dec-

remented at each timer clock (clkT2). clkT2 can be generated from an external or internal

clock source, selected by the Clock Select bits (CS22:0). When no clock source is

selected (CS22:0 = 0) t he timer is st opped. However, the TCNT2 value ca n be accessed

by the CPU, regardless of whether clkT2 is present or not. A CPU write overrides (has

priority over) all counter clear or count operations.

The counting sequence is determined by the setting of the WGM21 and WGM20 bits

located in the Timer/Counter Co ntrol Register (TCCR2A). There ar e close connections

between how the counter behaves (counts) and how waveforms are generated on the

Output Compare output OC2A. For more details about advanced counting sequences

and waveform gener ation, see “Modes of Operation” on page 129.

The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation

selected by the WGM21:0 bits. TOV2 can be used for generating a CPU int errupt.

Output Compare Unit The 8-bit comparator continuously compares TCNT2 with the Output Compare Register

(OCR2A). Whenever TCNT2 equals OCR2A, the comparator signals a match. A match

will set the Output Compare Flag (OCF2A) at the next timer clock cycle. If enabled

(OCIE2A = 1), the Output Compare Flag generates an Output Compare interrupt. The

OCF2A Flag is automatically cleared when the interrupt is executed. Alternatively, the

OCF2A Flag can be cleared by software by writing a logical one to its I/O bit location.

The Waveform Generator uses the match signal to generate an output according to

operating mode set by the WGM21:0 bits and Compare Output mode (COM2A1:0) bits.

The max and bottom signals are used by the Waveform Generator for handling the spe-

cial cases of the extreme values in some modes of operation (“Modes of Operation” on

page 129).

Figure 55 shows a block diagram of the Out put Compare unit.

Figure 55. Output Compare Unit, Block Diagram

OCFnx (Int.Req.)

= (8-bit Comparator )

OCRnx

OCnx

DATA BUS

TCNTn

WGMn1:0

Waveform Generator

top

FOCn

COMnx1:0

bottom

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The OCR2A Register is double buffered when using any of the Pulse Width Modulation

(PWM) modes. For the Nor mal and Clear Timer on Compare (CTC) mo des of operatio n,

the double bu ffering is disabled. The double buffering synchronizes the upd ate of the

OCR2A Compare Register to either top or bottom of the counting sequence. The syn-

chronization prevents the occurrence of odd-length, non-symmetrical PWM pulses,

thereby making the output glitch-free.

The OCR2A Register access may seem complex, but this is not case. When th e d ou b le

buffering is enabled, the CPU has access to the OCR2A Buffer Register, and if double

buffering is disabled the CPU will access the OCR2A directly.

Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be

forced by writin g a one to the Force Output Compare (FOC2A ) bit. Forcing compare

match will not set the OCF2A Flag or reload/clear the timer, but the OC2A pin will be

updated as if a real compare match had occurred (the COM2A1 :0 bits settings define

whether the OC2A pin is set, cleared or toggled).

Compare Match Bloc king by

TCNT2 Write All CPU write operations to the TCNT2 Register will block any compare match that

occurs in the next timer clock cycle, even when the timer is stopped. This feature allows

OCR2A to be initialized to the same value as TCNT2 without triggering an interrupt

when the Timer/Counter clock is enabled.

Using the Output Compare

Unit Since writing TCNT2 in any mode of operation will block all compare matches for one

timer clock cycle, there are risks involved when changing TCNT2 when using the Output

Compare unit, ind ependently of wheth er the Timer/ Counter is run ning or not. If the value

written to TCNT2 equals the OCR2A value, the compare match will be missed, resulting

in incorrect wavefor m generation . Similarly, do not write t he TCNT2 value eq ual to BOT-

TOM when the counter is downcounting.

The setup of the OC2A should be performed before setting the Data Direction Register

for the port pin to output. The easiest way of setting the OC2A value is to use the Force

Output Compare (FOC2A) strobe bit in Normal mode. The OC2A Register keeps its

value even when changing between Waveform Generation mod es.

Be aware that the COM2A1:0 bits are not double buffered together with the compare

value. Changing the COM2A1:0 bits will take effect immediately.

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Compare Match Output

Unit The Compare Out put mode ( COM2A1: 0) bits ha ve two f unctions. The Wavefor m Gener-

ator uses the COM2A1:0 bits for defining the Output Compare (OC2A) state at the next

compare match. Also, t he COM2A1:0 bits con trol the OC2A pin output source. Figure 56

shows a simplifie d schemat ic of the log ic affecte d by the COM 2A1:0 bit setting. The I/O

Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the

general I/O Port Control Regist ers ( DDR and PO RT) tha t are af fecte d by the CO M2A1:0

bits are shown. Wh en re ferring to the OC2A sta te, the re feren ce is for the in tern al OC2A

Figure 56. Compare Match Output Unit, Schematic

The general I/O port functio n is overridden by the Output Compare (OC2A) from the

Waveform Generator if either of the COM2A1:0 bits are set. However, the OC2A pin

direction (input or output) is still controlled by the Data Direction Register (DDR) for the

port pin. T he Data D irectio n Regis ter bit f or the OC2A pin (DDR_O C2A) m ust be se t as

output before t he OC2A value is visible on the pin. The port override function is indepen-

dent of the Waveform Generation mode.

The design of the Output Compare pin logic allows initialization of the OC2A state

before the output is enabled. Note that some COM2A1:0 bit settings are reserved for

certain modes of operation. See “8-bit Timer/Counter Register Description” on page

135.

Compare Output Mode and

Waveform Generat ion The Waveform Generator uses the COM2A1:0 bits differe ntly in normal, CTC, and PWM

modes. For a ll modes, setting the COM 2A1:0 = 0 tells the Waveform Genera tor that no

action on the OC2A Register is to be performed on the n ext compare match. For com-

pare output actions in the non-PWM modes refer to Table 62 on page 136. For fast

PWM mode, refer to Table 63 on page 136, a nd for phase co rrect PWM refer to T able

64 on page 136.

A change of the COM2A1:0 bits state will have effect at the first compare match after the

bits are written. For non-PWM mod es, the action can be forc ed to have immediate effect

by using the FOC2A strobe bits.

PORT

DDR

OCn

OCnx

Waveform

Generator

OMnx1

OMnx0

DATA BUS

OCnx

clkI/O

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Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Co mpare

pins, is defined by the combination of the Waveform Generation mode (WGM21:0) and

Compare Output mode (COM2A1:0) bits. The Compare Output mode bits do not affect

the counting sequence, while the Waveform Generation mode bits do. The COM2A1:0

bits control whether the PWM output genera ted should be inverted or not (inverte d or

non-inverted PWM). For non-PWM modes the COM2A1 :0 bits control whether the out-

put should be set, cleare d, or toggled at a compare match (See “Com pare Match Ou tput

Unit” on page 128.).

For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 133.

Normal Mode The simplest mode of operation is the Normal mode (WGM21:0 = 0). In this mode the

counting direction is a lways up (incrementing) , and no counte r clear is performe d. The

counter simply overrun s whe n it passes it s maximum 8-bit va lue (T OP = 0xFF) and t hen

restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag

(TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. The

TOV2 Flag in this case beha ves like a ninth bit, except that it is only set, not cleared.

However, combined with the timer overflow interrupt that automatically clears the TOV2

Flag, the timer resolution can be increase d by software. There are no special cases to

consider in the Normal mode, a new counter value can be written anytime.

The Output Compare unit can be used to generate interrupts at some given time. Using

the Output Compare to generate waveforms in Normal mode is not recommended,

since this will occupy too much of the CPU time.

Clear Timer on Compare

Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2A Register is used

to manipulate the counter resolution. In CTC mode the counter is cleared to zero when

the counter value (TCNT2) matches the OCR2A. The OCR2A defines the top value for

the counter, hence also its resolution. This mode allows greater control of the compare

match output frequency. It also simplifies the operation of counting external even ts.

The timing diagram for the CTC mode is shown in Figure 57. The counter value

(TCNT2) increases until a compare match occurs between TCNT2 and OCR2A, and

then counter (TCNT2) is cleared.

Figure 57. CTC Mode, Timing Diagram

An interrupt can be generated each time the counter value reaches the TOP value by

using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be

used for updating the TOP value. However, changing the TOP to a value close to BOT-

TOM when the counter is running with none or a low prescaler value must be done with

care since the CTC m ode does not ha ve the double buffer ing feature. If the n ew value

written to OCR2A is lower than the current value of TCNT2, the counter will miss the

CNTn

Cnx

(

Toggle)

OCnx Interrupt Flag Set

1 4

eriod

2 3

(COMnx1:0 = 1)

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compare match. The counter will then have to count to its maximum value (0xFF) and

wrap around starting at 0x00 before the compare match can occur.

For generating a waveform output in CTC mode, the OC2A output can be set to toggle

its logical level on each compa re match by setting th e Compare Output mode bits to tog-

gle mode (COM2A1:0 = 1). The OC2A value will not be visible on the port pin unless the

data direction for the pin is set to output. The waveform generated will have a maximum

frequency of fOC2A = fclk_I/O/2 when OCR2A is set to zero (0x00). The waveform fre-

quency is defined by the following equation:

The N variable represents the presca le factor (1, 8, 32, 64, 128, 256, or 1024).

As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cycle

that the counter counts from MAX to 0x00.

Fast PWM Mode Th e fast Pu lse Width Mo dulat ion or fast PWM mod e (WGM21:0 = 3) prov ides a high fre-

quency PWM waveform generation option. The fast PWM differs from the other PWM

option by its single-slope operation. The counter coun ts from BOTTO M to MAX then

restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare

(OC2A) is clear ed on the comp are match between TCNT2 an d OCR2A, and se t at BOT-

TOM. In inverting Compare Output mode, the output is set on compare match and

cleared at BOTTOM. Due to the single- slope operation, the operating frequ ency of the

fast PWM mode can be twice as high as the phase correct PWM mode that uses dual-

slope operation. This high frequency makes the fast PWM mode well suited for power

regulation, rectification, and DAC applications. High frequency allows physically small

sized external components (coils, capacitors), and therefor e reduces total system cost.

In fast PWM mode, th e co un ter is increme nt ed unt il the count er value mat c hes the MAX

value. The counter is then cleared at the following timer clock cycle. The timing diagram

for the fast PWM mode is shown in Figure 58. The TCNT2 value is in t he timi ng diag ram

shown as a histogram for illustrating the single-slope operation. The diagram includes

non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2

slopes represent compare matches between OCR2A and TCNT2.

Figure 58. Fast PWM Mode, Timing Diagram

fOCnx fclk_I/O

2N1OCRnx+()⋅⋅

----------------------------------------------

----

TCNTn

OCRnx Update and

TOVn Interrupt Flag Set

Period 2 3

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCRnx Interrupt Flag Se

4 5 6 7

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The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If

the interrupt is enabled, the interrupt handler routine can be used for updating the com-

pare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the

OC2A pin. Setting the COM2A1:0 bits to two will produce a non-inverted PWM and an

inverted PWM output can b e generated by set ting the COM2A1:0 to thr ee (See Table 63

on page 136) . The actu al OC2A value will on ly be visible on the port pin if the data dire c-

tion for the port pin is set as output. The PWM waveform is generated by setting (or

clearing) the OC2A Register at the compare match between OCR2A and TCNT2, and

clearing (or setting) the O C2A Register at the timer clock cycle the counter is cleared

(changes from MAX to BOTTOM).

The PWM frequency for th e output can be calculated by the following equation:

The N variable represents the presca le factor (1, 8, 32, 64, 128, 256, or 1024).

The extreme values for the OCR2A Register represent special cases when generating a

PWM waveform output in the fast PWM mode. If the OCR2A is set equal to BOTTOM,

the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR 2A

equal to MAX will result in a constantly high or low output (depending on the polarity of

the output set by the COM2A1:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved

by setting OC2A to toggle its logical level on each compare match (COM 2A1:0 = 1). The

waveform generate d will have a maximum frequenc y of foc2 = fclk_I/O/2 when OCR2A is

set to zero. This feature is similar to the OC2A toggle in CTC mode, except the double

buffer feature of the Output Compare unit is enabled in the fast PWM mode.

Phase Correct PWM Mode The phase correct PWM mode (WGM21:0 = 1) provides a high resolut ion phase correct

PWM waveform generation option. The phase correct PWM mode is based on a dual-

slope operation. The counter counts repeatedly from BOTTOM to MAX and then from

MAX to BOTTOM. In no n-inverting Compar e Output mode , the Output Compare (OC2A)

is cleared on the compare match between TCNT2 and OCR2A while upcounting, and

set on the compa re match while d owncounting . In inverting Outp ut Compare m ode, the

operation is inverted. The dual-slop e operation ha s lower maxim um operat ion frequency

than single slope operation. However, due to the symmetric feature of the dual-slope

PWM modes, these modes are preferred for motor control applications.

The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase

correct PWM mo de the counter is incr emented until the counte r value matches MAX.

When the counter reaches MAX, it changes the count direction. The TCNT2 value will

be equal to MAX for one timer clock cycle. The timing diagram for the phase correct

PWM mode is shown on Figure 59. The TCNT2 value is in the timing diagram shown as

a histogram for illustrating the dual-slope operation. The diagram includes non-inverted

and inverted PWM outputs. The sm all horizont al line marks on the TCNT2 slope s r epre-

sent compare matches between OCR2A and TCNT2.

fOCnxPWM fclk_I/O

N256⋅

------------------=

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Figure 59. Phase Correct PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOT-

TOM. The Interrupt Flag can be use d to generate an interrupt each time the counter

reaches the BOTTOM value.

In phase corr ect PWM mode, the compare uni t allows generation of PWM waveforms on

the OC2A pin. Setting the COM2A1:0 bits to two will produce a non-inverted PWM . An

inverted PWM output can b e generated by set ting the COM2A1:0 to thr ee (See Table 64

on page 136) . The actu al OC2A value will on ly be visible on the port pin if the data dire c-

tion for the port pin is set a s output. The PWM waveform is gen erated by clearing (or

setting) the OC2A Register at the compare match between OCR2A and TCNT2 when

the counter increments, and setting (or clearing) the OC2A Register at compare match

between OCR2A and TCNT2 when the counter decrements. The PWM frequency for

the output when using phase correct PWM can be calculated by the following equation:

The N variable represents the presca le factor (1, 8, 32, 64, 128, 256, or 1024).

The extreme values for the OCR2A Register represent special cases when generating a

PWM waveform output in the phase correct PWM mode. If the OCR2A is set equal to

BOTTOM, the output will be continuously low and if set equal to MAX the output will be

continuously high for non-inverted PWM mode. For inverted PWM the output will have

the opposite logic values.

At the very start of period 2 in Figure 59 OCn has a transition from high to low even

though there is no Compar e Match. The poi nt of th is transit ion is to gu arantee symmetr y

around BOTTOM. There are two cases that give a transition without Compare Match.

• OCR2A changes its value from MAX, like in Figure 59. When the OCR2A value is

MAX the OCn pin value is the same as the result of a d own-counting compare

match. To ensure symmetry around BOTTOM the OCn value at MAX must

correspond to t he result of an up-counting Compare Match.

TOVn Interrupt Flag Set

OCnx Interrupt Flag Set

1 2 3

TCNTn

Period

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCRnx Update

fOCnxPCPWM fclk_I/O

N510⋅

------------------=

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• The timer starts counting from a value higher than the one in OCR2A, and for that

reason misses the Compare Match and hence the OCn change that would have

happened on the way up.

Timer/Counter Timing

Diagrams The following figures show t he Timer/ Cou nter in syn chro nou s mo de, a nd t he ti mer clock

(clkT2) is therefore shown as a clock enable signal. In asynchronous mode, clkI/O should

be replaced by the Timer/Counter Oscillator clock. The figures include information on

when Interrupt Flags are set. Figure 60 contains timing data for basic Timer/Counter

operation. The fig ure shows the count sequence close to th e MAX value in all modes

other than phase correct PWM mode.

Figure 60. Timer/Counter Timing Diagram, no Prescaling

Figure 61 shows the same timing data, but with the prescaler enabled.

Figure 61. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)

Figure 62 shows the set ting of OCF2A in all modes except CTC mode.

clk

(clkI/O/1)

TOVn

clk

I/O

CNTn MAX - 1 MAX BOTTOM BOTTOM + 1

TOVn

CNTn MAX - 1 MAX BOTTOM BOTTOM + 1

clk

I/O

clk

(clkI/O/8)

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Figure 62. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (fclk_I/O/8)

Figure 63 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode .

Figure 63. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with

Prescaler (fclk_I/O/8)

OCFnx

OCRnx

CNTn

OCRnx V alue

OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2

clk

I/O

clk

(clkI/O/8)

OCFnx

OCRnx

CNTn

(CTC)

TOP

TOP - 1 TOP BOTTOM BOTTOM + 1

clkI/O

clkTn

(clk

I/O

/8)

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8-bit Timer/Counter

Timer/Counter Control

• Bit 7 – FOC2A: Force Output Compare A

The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However,

for ensuring compatibility with future devices, this bit must be set to zero when TCCR2A

is written when operating in PWM mode. When writing a logical one to the FOC2A bit,

an immediate compare match is forced on the Waveform Generation unit. The OC2A

output is changed accord ing to its COM2A1:0 bits setting. Note that the FOC2A bit is

implemented as a strobe. Therefore it is the value present in the COM2A1:0 bits that

determines the effect of the forced compare.

A FOC2A strobe will not generate a ny interrupt, nor will it clear the timer in CTC mode

using OCR2A as TOP.

The FOC2A bit is always read as zero.

• Bit 6, 3 – WGM21:0: Waveform Generation Mode

These bits control the coun ting sequence of the counter, the source for the maximum

(TOP) counter value , and what type of waveform generation to be use d. Modes of oper-

ation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare

match (CTC) mode, a nd two t ypes of Pulse Width Modulatio n (PWM) modes. See Table

61 and “Modes of Oper ation” on page 129.

Note: 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 def-

initions. However, the functionality and location of these bits are compatible with

previous versions of the timer.

Bit 7 6 5 4 3 2 1 0

FOC2A WGM20 COM2A1 COM2A0 WGM21 CS22 CS21 CS20 TCCR2A

Read/Write W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Table 61. Waveform Generation Mode Bit Description(1)

Mode WGM21

(CTC2) WGM20

(PWM2) Timer/Counter Mode

of Operation TOP Update of

OCR2A at TOV2 Flag

Set on

0 0 0 Normal 0xFF Immediate MAX

1 0 1 PWM, Phase Correct 0xFF TOP BO TTOM

2 1 0 CTC OCR2A Immediate MAX

3 1 1 Fast PWM 0xFF BOTTOM MAX

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• Bit 5:4 – COM2A1 :0: Compare Match Output Mode A

These bits control the Output Compare pin (OC2A) behavior. If one or both of the

COM2A1:0 bits are set, the OC2A output overrides the normal port functionality of the

I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit cor-

responding to OC2A pin must be set in order to enable the output drive r.

When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the

WGM21:0 bit setting. Table 62 shows the COM2A1:0 bit functionality when the

WGM21:0 bits are set to a normal or CTC mode (non-PWM).

Table 63 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast

PWM mode.

Note: 1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case,

the compare match is ignored, but the set or clear is done at TOP. See “Fast PWM

Mode” on page 130 for more details.

Table 64 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to

phase correct PWM mode.

Note: 1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case,

the compare match is ignored, but the set or clear is done at TOP. See “Phase Cor-

rect PWM Mode” on page 131 for more details.

Table 62. Compare Output Mode, non-PWM Mode

COM2A1 COM2A0 Description

0 0 Normal port operation, OC2A disconnected.

0 1 Toggle OC2A on compare match.

1 0 Clear OC2A on compare match.

1 1 Set OC2A on compare match.

Table 63. Compare Output Mode, Fast PWM Mode(1)

COM2A1 COM2A0 Description

0 0 Normal port operation, OC2A disconnected.

01Reserved

1 0 Clear OC2A on compare match, set OC2A at BOTTOM,

(non-inverting mode).

1 1 Set OC2A on compare match, clea r OC2A at BOTTOM,

(inverting mode ).

Table 64. Compare Output Mod e, Phase Correct PWM Mode(1)

COM2A1 COM2A0 Description

0 0 Normal port ope ration, OC2A disconnected.

01Reserved

1 0 Clear OC2A on compare match when up-counting. Set OC2A on

compare match when downcounting.

1 1 Set OC2A on compare match when up-counting. Clear OC2A on

compare match when downcounting.

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• Bit 2:0 – CS22:0: Clock Se lect

The three Cloc k Select bits select the clock source to be used by the Time r/Counter, see

Table 65.

Timer/Counter Register –

TCNT2

The Timer/Counter Register gives direct access, both for read and write operations, to

the Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes)

the compare match on the following timer clock. Modifying the counter (TCNT2) while

the counter is running, introduces a risk of missing a compare match between TCNT2

and the OCR2A Register.

Output Compare Re gister A –

OCR2A

The Output Compare Register A contains an 8-bit value that is continuously compared

with the counter value (TCNT2). A match can be used to generate an Output Compare

interrupt, or to generate a waveform output on the OC2A pin.

Table 65. Clock Select Bit Description

CS22 CS21 CS20 Description

0 0 0 No clock source (Timer/Counter stopped).

001clk

T2S/(No prescaling)

010clk

T2S/8 (From prescaler)

011clk

T2S/32 (From prescaler)

100clk

T2S/64 (From prescaler)

101clk

T2S/128 (From prescaler)

110clk

T2S/256 (From prescaler)

111clk

T2S/1024 (From prescaler)

Bit 76543210

TCNT2[7:0] TCNT2

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

OCR2A[7:0] OCR2A

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

138

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Asynchr onous operation

of the Timer/Counter

Asynchronous Status

• Bit 4 – EXCLK: Enable External Clock Input

When EXCLK is written to one, and asynchronous clock is selected, the external clock

input buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1)

pin instead of a 32 kHz crystal. Writing to EXCLK should be done before asynchronous

operation is selected. Note that the crystal Oscillator will only run when this bit is zero.

• Bit 3 – AS2: Asynchronous Timer/Counter2

When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When

AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to

the Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of

TCNT2, OCR2A, and TCCR2A mi ght be corrupted.

• Bit 2 – TCN2UB: Timer/Counter2 Update Busy

When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes

set. When TCNT2 has been updated from the temporary storage register, this bit is

cleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to be

updated with a new value.

• Bit 1 – OCR2UB: Output Compare Register2 Update Busy

When Timer/Coun ter2 operat es asynchronous ly and OCR2A is written, this bit becomes

set. When OCR2A has been updated from the temporary storage register, this bit is

cleared by hardware. A logical zero in this bit indicates that OCR2A is ready to be

updated with a new value.

• Bit 0 – TCR2UB: Timer/Counter Control Register2 Update Busy

When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit

becomes set. When TCCR2A has been up dated from the temporary storage register,

this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2A is ready

to be updated with a new value.

If a write is performed to any of the three Timer/Counter2 Registers while its update

busy flag is set, the updated value might ge t corrup te d an d cause an un int en tiona l inte r-

rupt to occur.

The mechanisms for reading TCNT2, OCR2A, and TCCR2A are different. When read-

ing TCNT2, the actual timer value is read. When reading OCR2A or TCCR2A, the value

in the temporar y storage register is read.

Bit 76543 2 1 0

– – – EXCLK AS2 TCN2UB OCR2UB TCR2UB ASSR

Read/Write R R R R/W R/W R R R

Initial Value 0 0 0 0 0 0 0 0

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Asynchronous Operation of

Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken.

• Warning: When switching between asynchronous and synchronous clocking of

Timer/Counter2, the Timer Registers TCNT2, OCR2A, and TCCR2A might be

corrupted. A safe procedure for switching clock source is:

1. Disable the Timer/Counter2 interrupts by clearing OCIE2A and TOIE2.

2. Select clock source by setting AS2 as appropriate.

3. Write new values to TCNT2, OCR2A, and TCCR2A.

4. To switch to asynchronous operation: Wait for TCN2UB, OCR2UB, and

TCR2UB.

5. Clear the Timer/Counter2 Interrupt Flags.

6. Enable interrupts, if needed.

• The CPU main clock frequency must be more than four times the Oscillator

frequency.

• When writing to one of the registers TCNT2, OCR2A, or TCCR2A, the value is

transferred to a te mpor ary register, and latched after two positiv e edges on TOSC1.

The user should not write a new value before the contents of the temporary register

have been t r ansferred to its destinatio n. Each of the three mention ed reg isters h a ve

their individual t empor ary register, which means that e .g. writing to TCNT2 does no t

disturb an OCR2A write in progress. To detect that a transfer to the destination

implemented.

• When entering Power- save or ADC Noise Re duction mode after having written to

TCNT2, OCR2A, or TCCR2A, the user must wait until the written register has been

updated if Timer/Counter2 is used to wake up the device. Otherwise, the MCU will

enter sleep mode before the chan ges are effective. This is particularly important if

the Output Compare2 interrupt is used to wake up the device, since the Output

Compare function is disabled during writing to OCR2A or TCNT2. If the write cycle

is not finished, and the MCU enters sleep mode before the OCR2UB bit returns to

zero, the device will never receive a compare match interrupt, and the MCU will not

wake u p.

• If Timer/Counter2 is used to wake the device up from Power-save or ADC Noise

Reduction mode, precautions must be taken if the user wants to re-enter one of

these modes: The interrupt logic needs one TOSC1 cycle to be reset. If the time

between wake-up and re-entering sleep mode is less than one TOSC1 cycle, the

interrupt will not occur, and the device will fail to wake up. If the user is in doubt

whether the time before re-entering Power-save or ADC Noise Reduction mode is

sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has

elapsed:

1. Write a v alue to TCCR2A, TCNT2, or OCR2A.

2. Wait until the corresponding Update Busy Flag in ASSR returns to zero.

3. Enter Power-save or ADC Noise Reduction mode.

• When the asynchronous operation is selected, the 32.768 kHz Oscillator for

Timer/Counter2 is alw a ys running, e xcept in Power- down and Standb y mod es. Aft er

a Power-up Reset or wake-up from Po wer-down or Standb y mode, the user should

be aw are of the fact that this Oscillator might tak e as long as one second to stabilize.

The user is advised to wait for at least one second before using Timer/Counter2

after power-up or wake-up fr om Power-down or Standby mode. The contents of all

Timer/Counter2 Registers must be considered lost after a wake-up from Power-

down or Standby mode due to unstable clock signal upon start-up, no matter

whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin.

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• Description of wake up from Power-save or ADC Noise Reduction mode when the

timer is clocked asynchronously: When the interrupt condition is met, the wake up

process is started on the following cycle of the timer clock, that is, the timer is

always advanced by at least one before the processor can read the counter v alue.

After wake-u p, the MCU is halted for four cycles, it exe cutes the interrupt routin e,

and resumes execution from the instruction following SLEEP.

• Reading of the TCNT2 Re gister shortly after wak e-up from Power-sa ve ma y g iv e an

incorrect result. Since TCNT2 is clocke d on t he asynchr onous TOSC clock, reading

TCNT2 must be done through a register synchronized to the internal I/O clock

domain. Synchronization takes place for e very rising TOSC1 edge. When waking up

from Power-save mode, and the I/O clock (clkI/O) again becomes active, TCNT2 will

read as the pre vious v alue (b ef ore entering sleep) until the next rising TOSC1 edge.

The phase of the TOSC clock after waking up from Power-save mode is essentially

unpredictab le , as it de pends on the w ak e- up time . The reco mmended pr ocedure for

reading TCNT2 is thus as follows:

1. Write any value to either of the registers OCR2A or TCCR2A.

2. Wait for the corresponding Update Busy Flag to be cleared.

3. Read TCNT2.

• During asynchronous operation, the synchronization of the Interrupt Flags for the

asynchronous timer takes 3 processor cycles plus one timer cycle. The timer is

therefore advanced by at least one before the processor can read the timer value

causing the sett ing of the Interrupt Flag . The Output Compare pin is changed on the

timer clock and is not synchronized to the processor clock.

Timer/Counter2 Interrupt

Mask Register – TIMSK2

• Bit 1 – OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable

When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one),

the Timer/C ounter 2 Comp are Matc h A interr upt is en abled. Th e corres pondin g interr upt

is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2A bit is

set in the Timer/Counter 2 Interrupt Flag Register – TIFR2.

• Bit 0 – TOIE2: Timer/Counter2 Overflow Interrupt Enable

When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the

Timer/Counter2 Over flow interr upt is enabled . The correspond ing interrupt is executed if

an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the

Timer/Counter2 Interrupt Flag Register – TIFR2.

Bit 76543210

–––––– OCIE2A TOIE2 TIMSK2

Read/WriteRRRRRRR/WR/W

Initial Value00000000

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Timer/Counter2 Interrupt Flag

• Bit 1 – OCF2A: Output Compare Flag 2 A

The OCF2A bit is set (one) when a compare match occurs between th e Timer/Counter2

and the data in OCR2A – Output Compare Register2. OCF2A is cleared by hardware

when executing the corresponding interru pt handling vecto r. Alternatively, OCF2A is

cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2A

(Timer/Counter2 Compare match Interrupt Enable), and OCF2A are set (one), the

Timer/Counter2 Compare match Interrupt is executed.

• Bit 0 – TOV2: Timer/Counter2 Overflow Flag

The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared

by hardware when executing the corresponding interrupt handling vector. Alternatively,

TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2A

(Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the

Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when

Timer/Counter2 changes counting direction at 0x00.

Bit 76543210

–––––– OCF2A TOV2 TIFR2

Read/WriteRRRRRRR/WR/W

Initial Value00000000

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Timer/Counter Prescaler Figure 64. Prescaler for Timer/Counter2

The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to

the main system I/O clock clkIO. By setting the AS2 bit in ASSR, Timer/Counter2 is asyn-

chronously clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real

Time Counter (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from

Port C. A crysta l can th en be connec ted be tween the TOSC 1 and TOSC2 p ins to se rve

as an independent clock source for Timer/Counter2. The Oscillator is optimized for use

with a 32.768 kHz crystal. If applying an external clock on TOSC1, the EXCLK bit in

ASSR must be set.

For Timer/Counter2, the possible prescaled selections are: clkT2S/8, clk T2S/32, clkT2S/64,

clkT2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be

selected. Setting the PSR2 bit in GTCCR resets the prescaler. This allows the user to

operate with a pred ictable prescaler .

General Timer/Counter

Control Register – GTCCR

• Bit 1 – PSR2: Prescaler Reset Timer/Counter2

When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally

cleared immediately by hardware. If the bit is written when Timer/Counter2 is operating

in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit

will not be cleared by hardware if the TSM bit is set. Refer to the description of the “Bit 7

– TSM: Timer/Counter Synchronization Mode” on page 94 for a description of the

Timer/Counter Synchronization mode.

10-BIT T/C PRESCALER

TIMER/COUNTER2 CLOCK SOURCE

clkI/O clkT2S

OSC1

AS2

CS20

CS21

CS22

clkT2S

/64

clkT2S

/128

clkT2S

/1024

clkT2S

/256

clkT2S

/32

PSR2

Clear

clkT2

Bit 7 6 5 4 3 2 1 0

TSM – – – – – PSR2 PSR10 GTCCR

Read/Write R/W R R R R R R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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Serial Peripheral

Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer

between the ATmega169 and peripheral devices or between several AVR devices. The

ATmega169 SPI includes the following features:

•Full-duplex, Three-wire Synchronous Data Transfer

•Master or Slave Operation

•LSB First or MSB First Data Transfer

•Seven Programmable Bit Rates

•End of Transmission Interru pt Flag

•Write Collision Flag Protection

•Wake-up from Idle Mode

•Double Speed (CK/2) Master SPI Mode

The PRSPI bit in “Power Reduction Register - PRR” on page 34 must be written to zero

to enable SPI module.

Figure 65. SPI Block Diagram(1)

Note: 1. Refer to Figure 1 on page 2, and Table 30 on page 63 for SPI pin placement.

The interconnection between Master and Slave CPUs with SPI is shown in Figure 66.

The system consists of two shift Registers, and a Master clock generator. The SPI Mas-

ter initiates the communication cycle when pulling low the Slave Select SS pin of the

desired Slave. M aster and Slave prepa re the data to be sent in their resp ective shift

Registers, and the Master generates the required clock pulses on the SCK line to inter-

change data. Data is always shifted from Master to Slave on the Master Out – Slave In,

MOSI, line, and fr om Slave to Master on th e Master In – Slave Out, M ISO, line. After

SPI2X

DIVIDER

/2/4/8/16/32/64/128

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each data packet, the Master will synchronize the Slave by pulling high the Slave Select,

SS, line.

When configured as a Master, the SPI interface has no automatic control of the SS line.

This must be handled by user software before communication can start. When this is

done, writing a byte to the SPI Data Register starts the SPI clock generator, and the

hardware shifts t he eight bits int o the Slave. Af te r sh ift ing on e byt e, t he SPI clo ck gene r-

ator stops, setting the end of Transmission Flag (SPIF). If the SPI Interrupt Enable bit

(SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue

to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high

the Slave Select, SS line. The last incoming byte will be kept in the Buffer Register for

later use.

When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated

as long as the SS pin is driven high. In this state, software may u pdate the contents of

the SPI Data Register, SPDR, but the data will not be shifted out by incoming clock

pulses on the SCK pin until the SS pin is driven low. As one b yte has been completely

shifted, the end of Transmission Flag , SPIF is set. If the SPI In terrupt Enable b it, SPIE,

in the SPCR Register is set, an interrupt is requested. The Slave may continue to place

new data to be sent into SPDR before readin g the incoming da ta. The last incom ing byte

will be kept in the Buffer Register for later use.

Figure 66. SPI Master-slave Interconnection

The system is single buff ered in th e transmit dir ection and doub le buffere d in the re ceive

direction. This means that bytes to be transmitted cannot be written to the SPI Data

received character must be read from the SPI Data Register before th e next character

has been completely shifted in. Otherwise, the first byte is lost.

In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To

ensure correct sampling of the clock signal, the minimum low and highperiod should be:

Low period: Longe r than 2 CPU clock cycles.

High period: Longer than 2 CPU clock cycles.

SHIFT

ENABLE

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When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is

overridden according to Table 66. For more details on automatic port overrides, refer to

“Alternate Port Functions” on page 60.

Note: 1. See “Alternate Functions of Port B” on page 63 for a detailed description of how to

define the direction of the user defined SPI pins.

The following code examples sho w how to init ial ize th e SPI as a Ma st er a nd h ow to pe r-

form a simple transmission. DDR_SPI in the examples must be replaced by the actual

Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK

must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed

on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB.

Table 66. SPI Pin Overrides(1)

Pin Direction, Master SPI Direction, Slave SPI

MOSI User Defined Input

MISO Input User Defined

SCK User Defined Input

SS User Defined Input

Assembly Code Example(1)

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Note: 1. See “About Code Examples” on page 6.

SPI_MasterInit:

; Set MOSI and SCK output, all others input

ldi r17,(1<<DD_MOSI)|(1<<DD_SCK)

out DDR_SPI,r17

; Enable SPI, Master, set clock rate fck/16

ldi r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0)

out SPCR,r17

ret

SPI_MasterTransmit:

; Start transmission of data (r16)

out SPDR,r16

Wait_Transmit:

; Wait for transmission complete

sbis SPSR,SPIF

rjmp Wait_Transmit

ret

C Code Example(1)

void SPI_MasterInit(void)

{

/* Set MOSI and SCK output, all others input */

DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK);

/* Enable SPI, Master, set clock rate fck/16 */

SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);

}

void SPI_MasterTransmit(char cData)

{

/* Start transmission */

SPDR = cData;

/* Wait for transmission complete */

while(!(SPSR & (1<<SPIF)))

;

}

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The following code examples show how to initialize the SPI as a Slave and how to per-

form a simple reception.

Note: 1. See “About Code Examples” on page 6.

Assembly Code Example(1)

SPI_SlaveInit:

; Set MISO output, all others input

ldi r17,(1<<DD_MISO)

out DDR_SPI,r17

; Enable SPI

ldi r17,(1<<SPE)

out SPCR,r17

ret

SPI_SlaveReceive:

; Wait for reception complete

sbis SPSR,SPIF

rjmp SPI_SlaveReceive

; Read received data and return

in r16,SPDR

ret

C Code Example(1)

void SPI_SlaveInit(void)

{

/* Set MISO output, all others input */

DDR_SPI = (1<<DD_MISO);

/* Enable SPI */

SPCR = (1<<SPE);

}

char SPI_SlaveReceive(void)

{

/* Wait for reception complete */

while(!(SPSR & (1<<SPIF)))

;

/* Return Data Register */

return SPDR;

}

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SS Pin Functionality

Slave Mode When the SPI is configur ed as a Slav e, the Slav e Se lect (SS) pin is always input. When

SS is held low, the SPI is activated, and MISO becomes an output if configured so by

the user. All other pins are in puts. When SS is driven high, all pins a re inputs, and the

SPI is passive, which means that it will not receive incoming data. Note that the SPI

logic will be reset once the SS pin is driven high.

The SS pin is useful for packet/byte synchronization to keep the slave bit counter syn-

chronous with the ma ster clock g enerat or. When the SS pin is driven high, the SPI slave

will immediately reset the send and receive logic, and drop any partially received data in

the Shift Register.

Master Mode When the SPI is configured as a Master (MST R in SPCR is set), the user can determine

the direction of the SS pin.

If SS is configured as an out p ut, the pin is a ge neral ou tp ut p in wh ich does n ot aff ect t he

SPI system. Typically, the pin will be driving the SS pin of the SPI Slave.

If SS is configured as an input, it must be held high to ensure Master SPI operation. If

the SS pin is driven low by peripheral circuitry when the SPI is configured as a Master

with the SS pin defined as an input, the SPI system interprets this as another master

selecting the SPI as a slave and starting to send data to it. To avoid bus contention, the

SPI system takes the following actions:

1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a

result of the SPI becoming a Slave, the MOSI and SCK pins become inputs.

2. The SPIF Flag in SPSR is set, and if the SPI inte rrupt is enabled, and the I- bit in

SREG is set, the interrupt routine will be executed.

Thus, when inte rrupt-dr iven SPI t ransmission is used in Master mode, and t here exists a

possibility that SS is driven low, the interrupt should always check that the MSTR bit is

still set. If the MSTR bit has been cleared by a slave select, it must be set by the user to

re-enable SPI Master mode.

SPI Control Register – SPCR

• Bit 7 – SPIE: SPI Interrupt Enable

This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set

and the if the Global Interrupt Enable bit in SREG is set.

• Bit 6 – SPE: SPI Enable

When the SPE bit is written to one, the SPI is ena bled. This bit must be set to enable

any SPI operation s.

• Bit 5 – DORD: Data Order

When the DORD bit is written to one, the LSB of the data word is transmitted first.

When the DORD bit is written to zero, the MSB of the data word is transmitted first.

Bit 76543210

SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 SPCR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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• Bit 4 – MSTR: Master/Slave Select

This bit selects Mast er SPI mode when writ ten to one, an d Slave SPI mode when wr itten

logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will

be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to

re-enable SPI Master mode.

• Bit 3 – CPOL: Clock Polarity

When this bit is written to one, SCK is high when idle. When CPOL is written to zero,

SCK is low when idle . Refer to F igure 67 a nd Figure 68 for an exa mple. The CPO L func-

tionality is summarized below:

• Bit 2 – CPHA: Clock Phase

The settings of the Clo ck Phase bit (CPHA) determ ine if data is sam pled on the lead ing

(first) or trailing (last) edge of SCK. Refer to Figure 67 and Figure 68 for an exam ple.

The CPOL functionality is summarized below:

• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0

These two bits control the SCK rate of the device configured as a Master. SPR1 and

SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator

Clock frequency fosc is shown in the following table:

Table 67. CPOL Functionality

CPOL Leading Edge Trailing Edge

0 Rising Falling

1 Falling Rising

Table 68. CPHA Functionality

CPHA Leading Edge Trailing Edge

0 Sample Setup

1 Setup Sample

Table 69. Relationship Between SCK and the Oscillator Frequency

SPI2X SPR1 SPR0 SCK Frequency

000

fosc/4

001

fosc/16

010

fosc/64

011

fosc/128

100

fosc/2

101

fosc/8

110

fosc/32

111

fosc/64

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SPI Status Register – SPSR

• Bit 7 – SPIF: SPI Interrupt Flag

When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if

SPIE in SPCR is set and global int errupts are en abled. If SS is an input and is driven low

when the SPI is in Master mode, this will also set the SPIF Flag. SPIF is cleared by

hardware when executing the corresponding interrupt handlin g vect or. Alter nativel y, th e

SPIF bit is cleared by first reading the SPI Status Register with SPIF set, then acce ssing

the SPI Data Register (SPDR).

• Bit 6 – WCOL: Write COLlision Flag

The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer.

The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register

with WCOL set, and then accessing the SPI Data Register.

• Bit 5..1 – Res: Reserved Bits

These bits are reserved bits in the ATmega169 and will always read as zero.

• Bit 0 – SPI2X: Double SPI Speed Bit

When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when

the SPI is in Master mode (see Table 69). This means that the minimum SCK period will

be two CPU clock periods. When the SPI is conf igured as Slav e, the SPI is only guar a n-

teed to work at fosc/4 or low er.

The SPI interface on the ATmega169 is also used for program memory and EEPROM

downloading or uploading. See page 281 for serial programming and verification.

SPI Data Register – SPDR

The SPI Data Registe r is a re ad /wri te register used fo r da ta transf er between t he Regis-

ter File and the SPI Shift Register. Writing to the register initiates data transmission.

Reading the register causes the Shift Register Receive buffer to be read.

Bit 76543210

SPIF WCOL – – – – – SPI2X SPSR

Read/WriteRRRRRRRR/W

Initial Value00000000

Bit 76543210

MSB LSB SPDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value X X X X X X X X Undefined

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Data Modes There are four combinations of SCK phase and polarity with respect to serial data,

which are determined by control bits CPHA and CPOL. The SPI data transfer formats

are shown in Figure 67 and Figure 68. Data bits are shifted out and latched in on oppo-

site edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is

clearly seen by summarizing Table 67 and Table 68, as done below:

Figure 67. SPI Transfer Format with CPHA = 0

Figure 68. SPI Transfer Format with CPHA = 1

Table 70. CPOL Functionality

Leading Edge Trailing eDge SPI Mode

CPOL=0, CPHA=0 Sample (Rising) Setup (Falling) 0

CPOL=0, CPHA=1 Setup (Rising) Sample (Falling) 1

CPOL=1, CPHA=0 Sample (Falling) Setup (Rising) 2

CPOL=1, CPHA=1 Setup (Falling) Sample (Rising) 3

Bit 1

Bit 6

LSB

MSB

SCK (CPOL = 0)

mode 0

SAMPLE I

MOSI/MISO

CHANGE 0

MOSI PIN

CHANGE 0

MISO PIN

SCK (CPOL = 1)

mode 2

MSB

LSB

Bit 6

Bit 1

Bit 5

Bit 2

Bit 4

Bit 3

Bit 4

Bit 2

Bit 5

MSB first (DORD = 0)

LSB first (DORD = 1)

SCK (CPOL = 0)

mode 1

SAMPLE I

MOSI/MISO

CHANGE 0

MOSI PIN

CHANGE 0

MISO PIN

SCK (CPOL = 1)

mode 3

MSB

LSB

Bit 6

Bit 1

Bit 5

Bit 2

Bit 4

Bit 3

Bit 4

Bit 2

Bit 5

Bit 1

Bit 6

LSB

MSB

MSB first (DORD = 0)

LSB first (DORD = 1)

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USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter

(USART) is a highly flexible serial communication device. The main features are:

•Full Duplex Operation (Independent Serial Receive and Transmit Registers)

•Asynchronous or Synchronous Operation

•Master or Slave Clocked Synchronous Operation

•High Resolution Baud Rate Generator

•Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits

•Odd or Even Parity Gene ration and Parity Check Supported by Hardware

•Data OverRun Detection

•Framing Error Detection

•Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter

•Three Separate Interrupts on TX Complete, TX Data Register Empty an d R X Comp le te

•Multi-processor Communication Mode

•Double Speed Asynchronous Communication Mode

The PRUSART0 bit in “Power Reduction Register - PRR” on page 34 must be written to

zero to enable USART module.

Overview A simplified block diagram of t he USART Transmitter is shown in Figure 69. CPU acces-

sible I/O Registers and I/O pins are shown in bold.

Figure 69. USART Block Diagram(1)

Note: 1. Refer to Figure 1 on page 2, Table 37 on page 69, and Table 31 on page 65 for

USART pin placement.

PARITY

GENERATOR

UBRR[H:L]

UDR (Transmit)

UCSRA UCSRB UCSRC

BAUD RATE GENERATOR

TRANSMIT SHIFT REGISTER

RECEIVE SHIFT REGISTER RxD

TxD

CONTROL

UDR (Receive)

CONTROL

XCK

DATA

RECOVERY

CLOCK

RECOVERY

CONTROL

PARITY

CHECKER

DATA BUS

OSC

SYNC LOGIC

Clock Generator

Transmitter

Receiver

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The dashed boxes in the block diagram separate the three main parts of the USART

(listed from the top): Clock Generator, Transmitter and Receiver. Control Registers are

shared by all units. The Clock Generation logic consists of synchronization logic for

external clock input used by synchronous slave operation, and the baud rate generator.

The XCK (Transfer Clock) pin is only used by synchronous transfer mode. The Trans-

mitter consists of a single write buffer, a serial Shift Register, Parity Generator and

Control logic for handling different serial frame formats. The write buffer allows a contin-

uous transfer of data without any delay between frames. The Receiver is the most

complex part of the USART m od u le du e to its clock and data recovery units. The recov-

ery units are used fo r asynchron ous data re ception . In additi on to the r ecovery unit s, the

Receiver includes a Parity Checker, Control logic, a Shift Register and a two level

receive buffer (UDR). The Receiver supports the same frame formats as the Transmit-

ter, and can detect Frame Error, Data OverRun and Parity Errors.

AVR USART vs. AVR UART –

Compatibility The USART is fully compatible with the AVR UART regarding:

• Bit locations inside all USART Registers.

• Baud Rate Generation.

• Transmitter Oper ation.

• Transmit Buffer Functionality.

• Receiver Operation.

However, the receive buffering has two improvements that will affect the compatibility in

some special cases:

• A second Buffer Register has been added. The two Buffer Registers operate as a

circular FIFO buffer. Therefore the UDR must only be read once for each incoming

data! More important is the fact that the Error Flags (FE and DOR) and the ninth

data bit (RXB8) ar e b uffered with the data in the receive b uf fer. Therefo re the stat us

bits must always be read before the UDR Register is read. Otherwise the error

status will be lost since the bu ffer state is lost.

• The Receiver Shift Register can now act as a third buffer level. This is done by

allowing th e receiv ed data to remain in the serial Shift Register (see Figure 69) if the

Buffer Registers are full, until a new start bit is detected. The USART is theref ore

more resistant to Data OverRun (DOR) error conditions.

The following control bits have changed name, but have same functionality and register

location:

• CHR9 is changed to UCSZ2.

• OR is changed to DOR.

Clock Generation The Clock Generation logic generates the base clock for the Transmitter and Receiver.

The USART supports four modes of clock operation: Normal asynchronous, Double

Speed asynchronous, Master synchronous and Slave synchronous mode. The UMSEL

bit in USART Control and Status Register C (UCSRC) selects between asynchronous

and synchronous operation. Double Speed (asynchronous mode only) is controlled by

the U2X found in the UCSRA Register. When using synchronous mode (UMSEL = 1),

the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clock

source is internal (Master mode) or external (Slave mode). The XCK pin is only active

when using synchronous mode.

Figure 70 shows a block diagram of the clock generation logic.

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Figure 70. Clock Generation Logic, Block Diagram

Signal description:

txclk Transmitter clock (Internal Signal).

rxclk Receiver base clock (Internal Signal).

xcki Input from XCK pin (internal Signal). Used for synchronous slave operation.

xcko Clock output to XCK pin (Internal Signal). Used for synchronous master

operation.

fosc XTAL pin frequency (System Clock).

Internal Clock Generation –

The Baud Rate Generator Internal clock generation is used for the asynchronous and the synchronous master

modes of operation. The description in this section refers to Figure 70.

The USART Baud Rate Register (UBRR) and the down-counter connected to it function

as a programmable prescaler or baud rat e generato r. The do wn-counter , running at sys-

tem clock (f osc), is loaded with the UBRR value each time the counter has counted down

to zero or when the UBRRL Register is written. A clock is generated each time the

counter reaches zero. This clock is the baud rate generator clock output (=

fosc/(UBRR+1)). The Transmitter divides the baud rate generator clock output by 2, 8 or

16 depending on mode. The baud rate generator output is used directly by the

Receiver’s clock and data recovery units. However, the recovery units use a state

machine that uses 2, 8 or 16 states depending on mode set by the state of the UMSEL,

U2X and DDR_XCK bits.

Table 71 contains equations for calculating the baud rate (in bits per second) and for

calculating the UBRR value for each mode of op eration using an internally generated

clock source.

Prescaling

Down-Counter /2

UBRR

/4 /2

fosc

UBRR+1

Sync

OSC

XCK

txclk

U2X

UMSEL

DDR_XCK

xcki

xcko

DDR_XCK rxclk

Edge

Detector

UCPOL

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Note: 1. The baud rate is defined to be th e transfer rate in bit per second (bps)

BAUD Baud rate (in bits per second, bps)

fOSC System Oscillator clock frequency

UBRR Contents of the UBRRH and UBRR L Registers, (0-4095)

Some examples of UBRR values for some system clock frequencies are found in Table

79 (see page 175).

Double Speed Operation

(U2X) The transfer rate can be doubled by setting the U2X bit in UCSRA. Setting this bit only

has effect for the asynchronous operation. Set this bit to zero when using synchronous

operation.

Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively

doubling the transfer rate for asynchronous communication. Note however that the

Receiver will in this case only use half the n umb er of samples ( reduce d f rom 16 t o 8) f or

data sampling and clock recovery, and therefore a more accurate baud rate setting and

system clock are required when this mode is used. For the T ransmitter, there are no

downsides.

External Clock External clocking is used by the synchronous slave modes of opera tio n. The descr ipt ion

in this section refers to Figure 70 for details.

External clock input from the XCK pin is sampled by a synchronization register to mini-

mize the chance of meta-stability. Th e output from the synchronization register must

then pass through an edge detector before it can be used by the Transmitter and

Receiver. This process introduces a two CPU clock perio d dela y and ther ef ore t he max-

imum external XCK clock frequency is limited by the following equation:

Note that fosc depends on the stability of the system clock source. It is therefore recom-

mended to add some margin to avoid possible loss of data due to frequency variations.

Table 71. Equations for Calculat ing Baud Rate Register Setting

Operating Mode Equation for Calculating

Baud Rate(1) Equatio n for Calculating

UBRR Value

Asynchronous Nor mal

mode (U2X = 0)

Asynchronous Double

Speed mode (U2X = 1)

Synchronous Master

mode

BAUD fOSC

16 UBRR 1+()

-----------------------------------

----

=UBRR fOSC

16BAUD

------------------------

–=

BAUD fOSC

8UBRR 1+()

--------------------------------

---

=UBRR fOSC

8BAUD

--------------------

–=

BAUD fOSC

2UBRR 1+()

--------------------------------

---

=UBRR fOSC

2BAUD

--------------------

–=

XCK fOSC

--------

---

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Synchronous Clock Operation When synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock

input (Slave) or clock output (Master). The dependency between the clock edges and

data sampling or data change is the same. The basic principle is that data input (on

RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is

changed.

Figure 71. Synchronous Mode XCK Timing.

The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and

which is used for data change. As Figure 71 shows, when UCPOL is zero the data will

be changed at rising XCK edge and sampled at falling XCK edge. If UCPOL is set, the

data will be changed at falling XCK edge and sampled at rising XCK edge.

Frame Formats A serial frame is defined to be one character of data bits with synchronization bits (start

and stop bits), and optiona lly a parity bit for error checking. The USART a ccepts all 30

combinations of the following as valid frame formats:

• 1 start bit

• 5, 6, 7, 8, or 9 data bits

• no, even or odd parity bit

• 1 or 2 stop bits

A frame starts with th e start bit followed by the least sig nificant data bit. Then the next

data bits, up to a total of nine, are succeeding, ending with the most significant bit. If

enabled, the parity bit is inserted after the data bits, before the stop bits. When a com-

plete frame is transmitted, it can be directly followed by a new frame, or the

communicatio n line can be set to an idle (high) state. Figure 72 illustrates the possible

combinations of the frame f ormats. Bits inside brackets are optional.

Figure 72. Frame Formats

St Start bit, always low.

(n) Data bits (0 to 8).

PParity bit. Can be odd or even.

RxD / TxD

XCK

RxD / TxD

XCK

UCPOL = 0

UCPOL = 1

Sample

10 2 3 4 [5] [6] [7] [8] [P]St Sp1 [Sp2] (St / IDLE)(IDLE)

FRAME

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Sp Stop bit, always high.

IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be

high.

The frame format used by the USART is set by the UCSZ2:0, UPM1:0 and USBS bits in

UCSRB and UCSRC. The Receiver and Transmitter use the same settin g. Note that

changing the setting of any of these bits w ill corrupt all ongoing communication for both

the Receiver and Transmitte r.

The USART Character SiZe (UCSZ2:0) bits select the number of data bits in the frame.

The USART Parity mode (UPM1:0) bits enable and set the type of parity bit. The selec-

tion between one or two stop bits is done by the USART Stop Bit Select (USBS) bit . The

Receiver ignores the second stop bit. An FE (Frame Error) will therefore only be

detected in the cases where the first stop bit is zero.

Parity Bit Calculation The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is

used, the result of the exclusive or is inverted. The relation between the parity bit and

data bits is as follows:

Peven Parity bit using even parity

Podd Parity bit using odd parity

dnData bit n of the character

If used, the parity bit is located between the last data bit and first stop bit of a serial

frame.

USART Initialization The USART has to be initia lized before any commun ication can take place. The initial-

ization process normally consists of setting the baud rate, setting frame format and

enabling the Transmitter or the Receiver depending on the usage. For interrupt driven

USART operation, the Global Interrupt Flag should be cleared (and interrupts globally

disabled) when doing the initialization.

Before doing a re-initialization with changed baud rate or frame format, be sure that

there are no ongoing transmissions during the period the registers are changed. The

TXC Flag can be used to check that the Transmitte r has complete d all transfer s, and the

RXC Flag can be used to check that there are no unread data in the receive buffe r. Note

that the TXC Flag must be cleared before each transmission (before UDR is written) if it

is used for this purpose.

Peven dn1–…d3d2d1d00

Podd

⊕⊕⊕⊕⊕⊕

dn1–…d3d2d1d01⊕⊕⊕⊕⊕⊕

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The following simple USART initialization code examples show one assembly and one

C function that are equal in functionality. The examples assume asynchronous opera-

tion using polling (no interrupts enabled) and a fixed frame format. The baud rate is

given as a function parameter. For the assembly code, the baud rate p arameter is

assumed to be stored in the r17:r16 Registers.

Note: 1. See “About Code Examp les” on page 6.

More advanced initialization rout ines ca n be made that in clude f rame fo rmat as pa rame-

ters, disable interrupts and so on. However, many applications use a fixed setting of the

baud and contro l registers, and for these types of applications the initialization code can

be placed directly in the main routine, or be combined with initialization code for other

I/O modules.

Assembly Code Example(1)

USART_Init:

; Set baud rate

sts UBRRH, r17

sts UBRRL, r16

; Enable receiver and transmitter

ldi r16, (1<<RXEN)|(1<<TXEN)

sts UCSRB,r16

; Set frame format: 8data, 2stop bit

ldi r16, (1<<USBS)|(3<<UCSZ0)

sts UCSRC,r16

ret

C Code Example(1)

#define FOSC 1843200// Clock Speed

#define BAUD 9600

#define MYUBRR FOSC/16/BAUD-1

void main( void )

{

...

USART_Init ( MYUBRR );

...

}

void USART_Init( unsigned int ubrr)

{

/* Set baud rate */

UBRRH = (unsigned char)(ubrr>>8);

UBRRL = (unsigned char)ubrr;

/* Enable receiver and transmitter */

UCSRB = (1<<RXEN)|(1<<TXEN);

/* Set frame format: 8data, 2stop bit */

UCSRC = (1<<USBS)|(3<<UCSZ0);

}

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Data Transmission – The

USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the

UCSRB Register. When the Tra nsmitter is enabled, the normal por t operation of the

TxD pin is overridden by the USART and given the function as the Transmitter’s serial

output. The baud rate, mode of operation and frame format must be set up once before

doing any transmissions. If synchronous operation is used, the clock on the XCK pin will

be overridden and used as transmission clock.

Sending Frames with 5 to 8

Data Bit A data transmission is initiated by loading the transmit buffer with the data to be trans-

mitted. The CPU can load the transmit buffer by writing to the UDR I/O location. The

buffered data in the transmit buffer will be moved to the Shift Register when the Shift

in idle state (no ongoing transmission) or immediately after the last stop bit of the previ-

ous frame is transmitted. When the Shift Register is loaded with new data, it will transfer

one complete frame at the rate given by the Baud Register, U2X bit or by XCK depend-

ing on mode of operation.

The following code examples show a simple USART transmit function based on polling

of the Data Register Empty (UDRE) Flag. When using frames with le ss than eight bits,

the most significant bit s writt en to th e UDR are ignore d. The USART has to be initialized

before the f un ctio n can be u sed. Fo r the assemb ly co de, t he dat a to be se nt is assumed

to be stored in Register R16

Note: 1. See “About Code Examp les” on page 6.

The function simply waits for the transmit buffer to be empty by checking the UDRE

Flag, before loading it with new data to be transmitted. If the Data Register Empty inter-

rupt is utilized, the interrupt routine writes the data into the buffer.

Assembly Code Example(1)

USART_Transmit:

; Wait for empty transmit buffer

sbis UCSRA,UDRE

rjmp USART_Transmit

; Put data (r16) into buffer, sends the data

sts UDR,r16

ret

C Code Example(1)

void USART_Transmit( unsigned char data )

{

/* Wait for empty transmit buffer */

while ( !( UCSRA & (1<<UDRE)) )

;

/* Put data into buffer, sends the data */

UDR = data;

}

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Sending Frames with 9 Data

Bit If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in

UCSRB before the low byte of the character is written to UDR. The following code

examples show a transmit function that handles 9-bit character s. For the assembly

code, the data to be sent is assumed to be stored in registers R17:R16.

Notes: 1. These transmit functions are written to be general functions. They can be optimized if

the contents of the UCSRB is static. For example, only the TXB8 bit of the UCSRB

2. See “About Code Examples” on page 6.

The ninth bit can be used for indicating an address frame when using multi processor

communication mode or for other protocol handling as for example synchronization.

Assembly Code Example(1)(2)

USART_Transmit:

; Wait for empty transmit buffer

sbis UCSRA,UDRE

rjmp USART_Transmit

; Copy 9th bit from r17 to TXB8

cbi UCSRB,TXB8

sbrc r17,0

sbi UCSRB,TXB8

; Put LSB data (r16) into buffer, sends the data

sts UDR,r16

ret

C Code Example(1)(2)

void USART_Transmit( unsigned int data )

{

/* Wait for empty transmit buffer */

while ( !( UCSRA & (1<<UDRE))) )

;

/* Copy 9th bit to TXB8 */

UCSRB &= ~(1<<TXB8);

if ( data & 0x0100 )

UCSRB |= (1<<TXB8);

/* Put data into buffer, sends the data */

UDR = data;

}

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Transmitter Flags and

Interrupts The USART Transmitter has two flags that indicate its state: USART Data Register

Empty (UDRE) and Transmit Complete (TXC). Both flags can be used for generating

interrupts.

The Data Register Empty (UDRE) Flag indicates whether the transmit buffer is ready to

receive new data. This bit is set when the transmit buffer is em pty, and cleared when t he

transmit buffer contai ns data to be transmitt ed that has not ye t been moved into t he Shift

the UCSRA Register.

When the Data Register Empty Interrupt Enable (UDRIE) bit in UCSRB is written to one,

the USART Data Register Empty Interrupt will be executed as long as UDRE is set (pro-

vided that global interrupts are enabled). UDRE is cleared by writing UDR. When

interrupt-driven d ata transmission is used, the Data Re gister Empty interrupt routine

must either write new data to UDR in order to clear UDRE or disable the Data Register

Empty interrupt, otherwise a new interrupt will occur once the interrupt routine

terminates.

The Transmit Complete (TXC) Flag bit is set one when the entire frame in the Transmit

Shift Register has been shifted out and there are no new data currently present in the

transmit buffer. The TXC Flag bit is automatically cleared when a transmit complete

interrupt is executed, or it can be cleared by writing a one to its bit location. The TXC

Flag is useful in half-duplex communication interfaces (like the RS-485 standard), where

a transmitting application must enter receive mode and free the communication bus

immediately after completing the transmission.

When the Transmit Com pete Interr upt Enable (TXCIE) bit in UCSRB is set, the USART

Transmit Complete Interrupt will be executed when the TXC Flag becomes set (pro-

vided that global interrupts are enabled). When the transmit complete interrupt is used,

the interrupt handlin g r out ine do es no t have to clear the TXC Flag , this is d on e aut oma t-

ically when the interrupt is executed.

Parity Generator The Parity Generator calculates the parity bit for the serial frame data. When parity bit is

enabled (UPM1 = 1), the transmitter control logic inserts the parity bit between the last

data bit and the first stop bit of the frame that is sent.

Disabling the Transmitter The disabling of the Transmitter (setting the TXEN to zero) will not become e ffective

until ongoing and pending transmissions are completed, i.e., when the Transmit Shift

abled, the Transmitter will no longer override the TxD pin.

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Data Reception – The

USART Receiver The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the

UCSRB Register to one. When the Receiver is enabled, the normal pin operation of the

RxD pin is overridd en by the USART and given the fu nction as the Receiver’s ser ial

input. The baud rate, mode of operation and frame format must be set up once before

any serial reception can be done. If synchronou s operation is used , the clock on the

XCK pin will be used as transfer clock.

Receiving Frames wi th 5 to 8

Data Bits The Receiver starts data reception when it detects a valid start bit. Each bit that follows

the start bit will be sampled at the baud rate or XCK clock, and shifted into the Receive

Shift Register until the first stop bit of a frame is received. A second stop bit will be

ignored by the Receiver. When the first stop bit is received, i.e., a complete serial frame

is present in the Receive S hift Register, the contents of the Shift Register will be moved

into the receive buffer. The receive buffer can then be read by reading the UDR I/O

location.

The following cod e example shows a simple USART receive function base d on polling

of the Receive Complete (RXC) Flag. When using frames with less than eight bits the

most significant bits of the data read from the UDR will be masked to z ero. The USART

has to be initialized before the function can be used.

Note: 1. See “About Code Examples” on page 6.

The function simply waits for data to be present in the receive buffer by checking the

RXC Flag, before reading the buffer and retu rning the value.

Assembly Code Example(1)

USART_Receive:

; Wait for data to be received

sbis UCSRA, RXC

rjmp USART_Receive

; Get and return received data from buffer

in r16, UDR

ret

C Code Example(1)

unsigned char USART_Receive( void )

{

/* Wait for data to be received */

while ( !(UCSRA & (1<<RXC)) )

;

/* Get and return received data from buffer */

return UDR;

}

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Receiving Frames with 9 Data

Bits If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in

UCSRB before reading the low bits from the UDR. This rule applies to the FE, DOR and

UPE Status Flags as well. Read status from UCSRA, then data from UDR. Reading the

UDR I/O location will change the state of the receive buffer FIFO and consequently the

TXB8, FE, DOR and UPE bits, which all are stored in the FIFO, will change.

The following code example shows a simple USART receive function that handles both

nine bit characters and the status bits.

Note: 1. See “About Code Examples” on page 6.

Assembly Code Example(1)

USART_Receive:

; Wait for data to be received

sbis UCSRA, RXC

rjmp USART_Receive

; Get status and 9th bit, then data from buffer

in r18, UCSRA

in r17, UCSRB

in r16, UDR

; If error, return -1

andi r18,(1<<FE)|(1<<DOR)|(1<<UPE)

breq USART_ReceiveNoError

ldi r17, HIGH(-1)

ldi r16, LOW(-1)

USART_ReceiveNoError:

; Filter the 9th bit, then return

lsr r17

andi r17, 0x01

ret

C Code Example(1)

unsigned int USART_Receive( void )

{

unsigned char status, resh, resl;

/* Wait for data to be received */

while ( !(UCSRA & (1<<RXC)) )

;

/* Get status and 9th bit, then data */

/* from buffer */

status = UCSRA;

resh = UCSRB;

resl = UDR;

/* If error, return -1 */

if ( status & (1<<FE)|(1<<DOR)|(1<<UPE) )

return -1;

/* Filter the 9th bit, then return */

resh = (resh >> 1) & 0x01;

return ((resh << 8) | resl);

}

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The receive function example rea ds all the I/O Registers into the Register File before

any computation is done. This gives an optimal receive buffer utilization since the buffer

location read will be free to accept new data as early as possible.

Receive Compete Flag and

Interrupt The USART Receiver has one flag that indicates the Receiver state.

The Receive Complete (RXC) Flag indicates if there are unread data present in the

receive buffer. This flag is one when unread data exist in the receive buffer, and zero

when the receive buffer is empty (i. e., does not contain any unre ad data). If the Receiver

is disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXC bit

will become zero.

When the Receive Com plete Interrupt Enable (RXCIE) in UCSRB is set, the USART

Receive Complete interrupt will be executed as long as the RXC Flag is set (provided

that global interrupts are enabled). When interrupt-driven data reception is used, the

receive complete routine must read the received data from UDR in order to clear the

RXC Flag, otherwise a new interrupt will occur once the interrupt routine terminates.

Receiver Error Flags The USART Receiver has th ree Error Flags: Frame Error (FE), Data OverRun (DO R)

and Parity Error (UPE). All can be accessed by reading UCSRA. Common for the Error

Flags is that they are located in the rece ive buf fer to geth er with the fra me for which th ey

indicate the error status. Due to the buffering of the Error Flags, the UCSRA must be

read before the receive buffer (UDR), since reading the UDR I/O location changes the

buffer read location. Another equality for the Error Flags is that they can not be altered

by software doing a write to the flag location. However, all flags must be set to zero

when the UCSRA is written for upward compatibility of future USART implementations.

None of the Error Flags can generate interrupts.

The Frame Error (FE) Flag indicates the state of the first stop bit of the next readable

frame stored in the receive buffer. The FE Flag is zero when the stop bit was correctly

read (as one), and the FE Flag will be one when the stop bit was incorrect (zero). This

flag can be used for detecting out-of-sync conditions, detecting break conditions and

protocol handling. The FE Flag is not affected by the setting of the USBS bit in UCSRC

since the Receiver ignores all, except for the first, stop bits. For compatibility with future

devices, always set this bit to zero when writing to UCSRA.

The Data O verRun (D OR) Flag in dicates dat a loss due to a receiver buffer full condition.

A Data OverRun occurs when the rece ive buffer is full (two characters), it is a new char-

acter waiting in the Receive Shift Register, and a new start bit is detected. If the DOR

Flag is set there was one or more serial frame lost between the frame last read from

UDR, and the next frame read from UDR. For compatibility with future devices, always

write this bit to zero when writing to UCSRA. The DOR Flag is cleared when the frame

received was successfully moved from the Shift Register to the receive buffer.

The Parity Error (UPE) Fl ag indicates that t he next frame in the r eceive buffer had a Par-

ity Error when received. If Parity Check is not enabled the UPE bit will always be read

zero. For compatibility with future devices, alwa ys set this bit to zero when writing to

UCSRA. For more details see “Parity Bit Calculation” on page 157 and “Parity Checker”

on page 165.

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Parity Checker The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type

of Parity Check to be performed (odd or even) is selected by the UPM0 bit. When

enabled, the Parit y Checke r calculates the parit y of the data b its in inco ming fram es and

compares the result with the parity bit from the serial frame. The result of the check is

stored in the receive buffer together with the received data and stop bits. The Parity

Error (UPE) Flag can then be read by software to check if the frame had a Parity Error.

The UPE bit is set if the next character that can be read from the receive buffer had a

Parity Error when received and the Parity Checking was enabled at that point (UPM1 =

1). This bit is valid until the receive buffer (UDR) is read.

Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from

ongoing receptions will therefore be lost. When disabled (i.e., th e RXEN is set to zero)

the Receiver will no longer override the normal function of the RxD port pin. The

Receiver buffer FIFO will be flushed when the Receiver is disabled. Remain ing data in

the buffer will be lost

Flushing the Receive Buffer The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer

will be emptied of its contents. Unread data will be lost. If the buffer has to be flushed

during normal operation, due to for instance an error condition, read the UDR I/O loca-

tion until the RXC Flag is cleared. The following code example shows how to flu sh the

receive buffer.

Note: 1. See “About Code Examples” on page 6.

Asynchronous Data

Reception The USART includes a clock recove ry and a data recovery unit for handling asynchro-

nous data reception. The clock recovery logic is used for synchronizing the internally

generated baud rate clock to the incoming asynchr onous serial frames at the RxD pin.

The data recovery logic samples and low pass filters each incoming bit, thereby improv-

ing the noise immunity of the Receiver. The asynchronous reception operational range

depends on the accuracy of the internal baud rate clock, the rate of the incoming

frames, and the frame size in number of bits.

Assembly Code Example(1)

USART_Flush:

sbis UCSRA, RXC

ret

in r16, UDR

rjmp USART_Flush

C Code Example(1)

void USART_Flush( void )

{

unsigned char dummy;

while ( UCSRA & (1<<RXC) ) dummy = UDR;

}

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Asynchronous Clock

Recovery The clock recovery logic synchronizes internal clock to the incoming serial frames. Fig-

ure 73 illustrates the sampling process of the start bit of an incoming frame. The sample

rate is 16 times the baud rate f or Normal mod e, and e ight times the baud ra te for Double

Speed mode. The horizon tal arrows illustrate the synchronization varia tion due to the

sampling process. Note the larger time variation when using the Double Speed mode

(U2X = 1) of operation. Samples denoted zero are samples done when the RxD line is

idle (i.e., no communicatio n ac tivit y).

Figure 73. Start Bit Sampling

When the clock recovery logic detects a high (idle) to low (start) transition on the RxD

line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sam-

ple as shown in the figure. The clock recovery logic then uses samples 8, 9, and 10 for

Normal mode, and samples 4, 5, and 6 for Double Speed mode (indicated with sample

numbers inside boxes on the figure), to decide if a valid start bit is received. If two or

more of these three samples have logical high levels (the majority wins), the start bit is

rejected as a noise spike and the Receiver starts looking for the next high to low-transi-

tion. If however , a va lid start bit is d etected, the clock recovery logic is synchr onized and

the data recovery can begin. The synchronization process is repeated for each start bit.

Asynchronous Data Recovery When the rece iver clock is synchron ized to the start bit, the data recovery can begin.

The data recovery unit uses a state machine that has 16 states for each bit in Normal

mode and eight states for each bit in Double Speed mode. Figure 74 shows the sam-

pling of the data bits and the parity bit. Each of the samples is given a number that is

equal to the state of the recovery unit.

Figure 74. Sampling of Data and Parity Bit

The decision of the logic level of the received bit is taken by doing a majority voting of

the logic value to the three samples in the center of the received bit. The center samples

are emphasized on the figure by having the sample number inside boxes. The majority

voting process is done as follows: If two or all three samples have high levels, the

received bit is r egistered to be a lo gic 1. If two or all three samples have low levels, the

received bit is registered to be a logic 0. This majority voting process acts as a low pass

filter for the incoming signa l on the RxD pin. The recove ry pro cess is then repeat ed unt il

a complete frame is received. Including the first stop b it. Note that the Receiver only

uses the first stop bit of a frame.

12345678 9 10 11 12 13 14 15 16 12

STARTIDLE

BIT 0

1234 5 678120

RxD

Sample

(U2X = 0)

Sample

(U2X = 1)

12345678 9 10 11 12 13 14 15 16 1

BIT n

1234 5 6781

RxD

Sample

(U2X = 0)

Sample

(U2X = 1)

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Figure 75 shows the sampling of the stop bit and the earliest possible beginning of the

start bit of the next fr am e .

Figure 75. Stop Bit Sampling and Next Start Bit Sampling

The same majority voting is done to the stop bit as done for the other bits in the frame. If

the stop bit is registered to have a logic 0 value, the Frame Error (FE) Flag will be set.

A new high to low transition indicating the start bit of a new frame can come right after

the last of the bits used for majority voting. For Normal Sp eed mode, the first low level

sample can be at point marked (A) in Figure 75. For Double Speed mode the first low

level must be delayed to (B). (C) marks a stop bit of full length. The early start bit detec-

tion influences the operational range of the Receiver.

Asynchronous Operational

Range The operational range of the Receiver is dependent on the mismatch between the

received bit rate and the internally generated baud rate. If the Transmitter is sending

frames at too fast or too slow bit rates, or the internally generated baud rate of the

Receiver does not have a similar (see Table 72) base frequency, the Receiver will not

be able to synchronize the frames to the start bit.

The following equations can be used to calculate the ratio of the incoming data rate and

internal receiver baud rate.

DSum of character size and parity size (D = 5 to 10 bit)

SSamples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed

mode.

SFFirst sample number used for majority voting. SF = 8 for normal speed and SF = 4

for Double Speed mode.

SMMiddle sample number used for majority voting. SM = 9 for normal speed and

SM= 5 for Double Speed mode.

Rslow is the ratio of th e slowest incoming data rate th at can be accepted in relation to the

receiver baud rate. Rfast is the ratio of the fastest incoming data rate that can be

accepted in relation to the receiver baud rate.

Table 72 and Table 73 list the maximum receiver baud rate error that can be tolerated.

Note that Norm al Speed mode has higher toler ation of baud rate variations.

12345678 9 10 0/1 0/1 0/1

STOP 1

1234 5 6 0/1

RxD

Sample

(U2X = 0)

Sample

(U2X = 1)

(A) (B) (C)

Rslow D

+()S

S1–DS⋅SF

----------------------------------------

---

=Rfast D

+()S

D1+()SS

--------------------------------

---

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The recommendations of the maximum receiver baud rate error was made under the

assumption that the Receiver and Transmitter equally divide s the maximum total error.

There are two po ssible sources fo r the receivers b aud ra te erro r. The Receiver’s syst em

clock (XTAL) will always have some minor instability over the supp ly voltage range and

the temperature range. When using a crystal to generate the system clock, this is rarely

a problem, but for a resonato r the system clock may differ more than 2% depending of

the resonat ors tolerance. The second source for the error is mo re controllable. The baud

rate generator can not always do an exact division of the system frequency to get the

baud rate wanted. In this case an UBRR value that gives an acceptable low error can be

used if possible.

Table 72. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode

(U2X = 0)

# (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max

Receiver Error (%)

5 93.20 106.67 +6.67/-6.8 ± 3.0

6 94.12 105.79 +5.79/-5.88 ± 2.5

7 94.81 105.11 +5.11/-5.19 ± 2.0

8 95.36 104.58 +4.58/-4.54 ± 2.0

9 95.81 104.14 +4.14/-4.19 ± 1.5

10 96.17 103.78 +3.78/-3.83 ± 1.5

Table 73. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode

(U2X = 1)

# (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max

Receiver Error (%)

5 94.12 105.66 +5.66/-5.88 ± 2.5

6 94.92 104.92 +4.92/-5.08 ± 2.0

7 95.52 104,35 +4.35/-4.48 ± 1.5

8 96.00 103.90 +3.90/-4.00 ± 1.5

9 96.39 103.53 +3.53/-3.61 ± 1.5

10 96.70 103.23 +3.23/-3.30 ± 1.0

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Multi-processor

Communication Mode Setting the Multi-pro cessor Communication mode (MPCM) bit in UCSRA enables a fil-

tering function of incoming frames received by the USART Receiver. Frames that do not

contain address information will be ignored and not put into the receive buffer. This

effectively reduces the number of incoming frames that has to be handled by the CPU,

in a system with multiple MCUs that communicate via the same serial bus. The Trans-

mitter is unaffected by the MPCM setting, but has to be used differently when it is a part

of a system utilizing the Multi-processor Communication mode.

If the Receiver is se t up to receive fram es that co ntain 5 to 8 data bit s, th en the firs t stop

bit indicates if the frame contains data or address information. If the Receiver is set up

for frames with nine data bits, then the ninth bit (RXB8) is used for identifying address

and data f rames. When t he frame type bit (the first st op or the ninth bit) is o ne, the frame

contains an address. When the frame ty pe bit is zero the frame is a data fra me.

The Multi-processor Communication mode enables several slave MCUs to receive data

from a master MCU. This is done by first decoding an address frame to find out which

MCU has been addressed. If a particular slave MCU has been addressed, it will receive

the following data frames as normal, while the other slave MCUs will ignore the received

frames until another address frame is received.

Using MPCM For an MCU to act as a master MCU, it can use a 9-bit character frame format (UCSZ =

7). The nint h bit ( TXB8) must b e set when an a ddress frame (TXB8 = 1) o r cleared when

a data frame (TXB = 0) is being t ransmitted. The slave MCUs must in th is case be set to

use a 9-bit character frame format.

The following procedure should be used to exchange d ata in Multi-processor Communi-

cation mode:

1. All Slav e MCUs ar e in Mult i-p roces so r Communication mode (MPCM in UCSRA

is set).

2. The Master MCU sends an address frame, and all slaves receive and read this

frame. In the Slave MCUs, the RXC Flag in UCSRA will be set as norm al.

3. Each Slave MCU reads the UDR Register and determines if it has been

selected. If so, it clears the MPCM bit in UCSRA, otherwise it waits for the next

address byte and keeps the MPCM setting.

4. The addressed MCU will receive all data frames until a new address frame is

received. The other Slave MCUs, which still have the MPCM bit set, will ignore

the data frames.

5. When the last data frame is received by the addressed MCU, the addressed

MCU sets the MPCM bit and waits for a new address frame from master. The

process then repeats from 2.

Using any of the 5- to 8- bit char act er fr ame for mats is possible, but impr act ica l since the

Receiver must change between using n and n+1 character frame formats. This makes

full-duplex operation difficult since the Transmitter and Receiver uses the same charac-

ter size setting. If 5- to 8-b it character frames are used, th e Transmitter must be set to

use two stop bit (USBS = 1) since the first stop bit is used for indicating the fr ame type.

Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCM bit.

The MPCM bit shares the same I/O loca tion as th e TXC Flag and this migh t accidentally

be cleared when using SBI or CBI instructions.

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USART Register

Description

USART I/O Data Register –

UDR

The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers

share the same I/O address referred to as USART Data Register or UDR. The Transmit

Data Buffer Register (TXB) will be the destination for data written to the UDR Register

location. Reading the UDR Register location will return the contents of the Receive Data

Buffer Register (RXB).

For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter

and set to zero by the Receiver.

The transmit buffer can only be written when the UDRE Flag in the UCSRA Register is

set. Data written to UDR when the UDRE Flag is not set, will be ignored by the USART

Transmitter. When data is written to the transmit buffer, and the Transmitter is enabled,

the Transmitter will load the data into the Transmit Shift Register when the Shift Register

is empty. Then the data will be serially transmitted on the TxD pin.

The receive buffer consists of a two level FIFO. The FIFO will change its state whenever

the receive buffer is accessed. Due to this behavior of the receive buffer, do not use

Read-Modify-Write inst ructio ns (SBI and CBI) on t his location. Be care ful wh en usin g bit

test instructions (SBIC and SBIS), since these also will change the state of the FIFO.

USART Control and Status

• Bit 7 – RXC: USART Receive Complete

This flag bi t is set wh en there a re unread data in the r eceive buffer and cleared when the

receive buffer is empty (i.e., does not contain any unread data). If the Receiver is dis-

abled, the receive buffer will be flushed and consequently the RXC bit will become zero.

The RXC Flag can be used to gen erate a Receive Complete interrupt (see d escription of

the RXCIE bit).

• Bit 6 – TXC: USART Transmit Complete

This flag bit is set when the entire frame in the Transmit Shift Register has been shifted

out and there are no new data currently present in the transmit buffer (UDR). The TXC

Flag bit is automatically cleared when a transmit complete interrupt is executed, or it can

be cleared by writing a one to its bit location. The TXC Flag can generate a Transmit

Complete interr up t (se e description of the TXCIE bit) .

Bit 7 6 5 4 3 2 1 0

RXB[7:0] UDR (Read)

TXB[7:0] UDR (Write)

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

RXC TXC UDRE FE DOR UPE U2X MPCM UCSRA

Read/Write R R/W R R R R R/W R/W

Initial Value00100000

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• Bit 5 – UDRE: USART Data Register Empty

The UDRE Flag indicates if the transmit buffer (UDR) is ready to receive new data. If

UDRE is one, the buf fer is empt y, and therefor e ready to be writte n. The UDRE Flag can

generate a Data Register Empty interrupt (see description of the UDRIE bit).

UDRE is set after a reset to indicate that the Transmitter is ready.

• Bit 4 – FE: Frame Error

This bit is set if the next character in the receive buffer had a Frame Error when

received. I.e., when the first stop bit of the next character in the receive buffer is zero.

This bit is valid until the receive buffer (UDR) is read. The FE bit is zero when the stop

bit of received data is one. Always set this bit to zero when writing to UCSRA.

• Bit 3 – DOR: Data OverRun

This bit is set if a Data OverRun condition is detect ed. A Da ta Over Run occurs whe n the

receive buffer is full (two characters), it is a new character waiting in the Receive Shift

read. Always set this bit to zero when writing to UCSRA.

• Bit 2 – UPE: USART Parity Error

This bit is set if the next character in the receive buffer had a Parity Error when received

and the Parity Checking was enabled at that point (UPM1 = 1). This bit is valid until the

receive buffer (UDR) is read. Always set this bit to zero when writing to UCSRA.

• Bit 1 – U2X: Double the USART Transmission Speed

This bit only has effect for the asynchronous operation. Write this bit to zero when using

synchronous operation.

Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effec-

tively doubling th e tra n sfe r ra te for as yn chr o no us com mu n ica tion .

• Bit 0 – MPCM: Multi- processor Communication Mod e

This bit enable s the Multi- processor Communica tion mode. Wh en the MP CM bit is writ-

ten to one, all the incoming frames received by the USART Receiver that do not contain

address information will be ignored. The Transmitter is unaffected by the MPCM setting.

For more detailed inf ormation see “Multi -proce ssor Commu nication Mode ” on pag e 169.

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USART Control and Status

• Bit 7 – RXCIE: RX Complete Interrupt Enable

Writing this bit to one enables interrupt on the RXC Flag. A USART Receive Complete

interrupt will be generated only if the RXCIE bit is written to one, the Global Interrupt

Flag in SREG is written to one and the RXC bit in UCSRA is set.

• Bit 6 – TXCIE: TX Complete Interrupt Enable

Writing this bit to one enables interrupt on the TXC Flag. A USART Transmit Complete

interrupt will be generated only if the TXCIE bit is written to one, the Global Interrupt

Flag in SREG is written to one and the TXC bit in UCSRA is set.

• Bit 5 – UDRIE: USART Data Register Empty Int errupt Enable

Writing this bit to one enables interrupt on the UDRE Flag. A Data Register Empty inter-

rupt will be generated only if the UDRIE bit is w ritten to one, the Global Interrupt Flag in

SREG is written to one and the UDRE bit in UCSRA is set.

• Bit 4 – RXEN: Receiver Enable

Writing this bit to one enables the USART Receiver. The Receiver will override normal

port operation for the RxD pin when enabled. Disabling the Receiver will flush the

receive buffer invalidating the FE, DOR, and UPE Flags.

• Bit 3 – TXEN: Transmitter Enable

Writing this bit to one enables the USART Transmitter. The Transmitter will override nor-

mal port operation for the TxD pin when enabled. The disabling of the Transmitter

(writing TXEN to zero) will not becom e effective until ongoing and pending transmis-

sions are completed, i.e ., when the Tra nsmit Shift Regist er and Tran smit Buffer Register

do not contain data to be transmitted. When disabled, the Transmitter will no longer

override the TxD port.

• Bit 2 – UCSZ2: Character Size

The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data bits

(Character SiZe) in a fr ame the Receiver and Transmitter use.

• Bit 1 – RXB8: Receive Data Bit 8

RXB8 is the ninth data bit of the received character when operating with serial frames

with nine data bits. Must be read before reading the low bits from UDR.

• Bit 0 – TXB8: Transmit Data Bit 8

TXB8 is the ninth data bit in the character to be transmitted when operating with s erial

frames with nine data bits. Must be written before writing the low bits to UDR.

Bit 76543210

RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 UCSRB

Read/Write R/W R/W R/W R/W R/W R/W R R/W

Initial Value00000000

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USART Control and Status

• Bit 6 – UMSEL: USART Mode Select

This bit selects be tween asynchronous and synchronous mode of operation.

• Bit 5:4 – UPM1:0: Parity Mode

These bits enable and set type of parity generation and check. If enabled, the Transmit-

ter will automatically generate and send the parity of the transmitted data bits within

each frame. The Receiver will generate a parity value for the incoming data and com-

pare it to the UPM0 setting. If a mismatch is detected, the UPE Flag in UCSRA will be

set.

• Bit 3 – USBS: Stop Bit Select

This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver

ignores this setting.

Bit 76543210

– UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL UCSRC

Read/Write R R/W R/W R/W R/W R/W R/W R/W

Initial Value00000110

Table 74. UMSEL Bit Settings

UMSEL Mode

0 Asynchronous Operation

1 Synchronous Operation

Table 75. UPM Bits Settings

UPM1 UPM0 P arity Mode

0 0 Disabled

01Reserved

1 0 Enabled, Even Parity

1 1 Enabled, Odd Parity

Table 76. USBS Bit Settings

USBS Stop Bit(s)

01-bit

12-bit

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• Bit 2:1 – UCSZ1:0: Character Size

The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits

(Character SiZe) in a fr ame the Receiver and Transmitter use.

• Bit 0 – UCPOL: Clock Polarity

This bit is used for synchronous mode only. Write this bit to zero when asynchronous

mode is used. The UCPOL bit sets the relationship between data output change and

data input sample, and the synchronous clock (XCK).

USART Baud Rate Registers –

UBRRL and UBRRH

• Bit 15:12 – Reserved Bits

These bits are reserved for future use. For compatibility with future devices, these bit

must be written to zero when UBRRH is written.

• Bit 11:0 – UBRR11:0: USART Baud Rate Register

This is a 12-bit register which contains the USART baud rate. The UBRRH contains the

four most significant bits, and the UBRRL contains the eight least significant bits of the

USART baud rate. Ongoing transmissions by the Transmitter and Receiver will be cor-

rupted if the baud rate is changed. Writing UBRRL will trigger an immediate update of

the baud rate prescaler.

Table 77. UCSZ Bits Settings

UCSZ2 UCSZ1 UCSZ0 Character Size

0005-bit

0016-bit

0107-bit

0118-bit

100Reserved

101Reserved

110Reserved

1119-bit

Table 78. UCPOL Bit Settings

UCPOL Transmitted Data Changed (Output of

TxD Pin) R eceived Data Sampled (Input on

RxD Pin)

0 Rising XCK Edge Falling XCK Edge

1 F alling XCK Edge Rising XCK Edge

Bit 151413121110 9 8

–––– UBRR[11:8] UBRRH

UBRR[7:0] UBRRL

76543210

Read/Write R R R R R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

00000000

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Examples of Baud Rate

Setting For standard crysta l and reso nator fr equen cies, th e most commonly used ba ud rates for

asynchronous operation can be generated by using the UBRR settings in Table 79.

UBRR values which yie ld an actual baud rate differing less than 0.5 % from the target

baud rate, are bold in the table. Higher error ratings are acceptable, but the Receiver will

have less noise resistance when the error ratings are high, especially for large serial

frames (see “Asynchrono us O perat ional Rang e” on p age 167) . The e rror valu es are cal-

culated using the following equation:

Error[%] BaudRateClosest Match

BaudRate

-------------------------------------------------------- 1–

⎝⎠

⎛⎞

100%•=

Table 79. Examples of UBRR Settings for Commonly Used Oscillator Frequencies

Baud

Rate

(bps)

fosc = 1.0000 MHz fosc = 1.8432 MHz fosc = 2.0000 MHz

U2X = 0 U 2X = 1 U2X = 0 U2X = 1 U2X = 0 U2X = 1

UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error

2400 250.2%510.2%470.0%950.0%510.2%1030.2%

4800 120.2%250.2%230.0%470.0%250.2%510.2%

9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2%

14.4k 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.1%

19.2k 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 6 -7.0% 12 0.2%

28.8k 1 8.5% 3 8.5% 3 0.0% 7 0.0% 3 8.5% 8 -3.5%

38.4k 1 -18.6% 2 8.5% 2 0.0% 5 0.0% 2 8.5% 6 -7.0%

57.6k 0 8.5% 1 8.5% 1 0.0% 3 0.0% 1 8.5% 3 8.5%

76.8k – – 1 -18.6% 1 -25.0% 2 0.0% 1 -18.6% 2 8.5%

115.2k – – 0 8.5% 0 0.0% 1 0.0% 0 8.5% 1 8.5%

230.4k––––––00.0%––––

250k––––––––––00.0%

Max. (1) 62.5 kbps 125 kbps 115.2 kbps 230.4 kbps 125 kbps 250 kbps

1. UBRR = 0, Error = 0.0%

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Table 80. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)

Baud

Rate

(bps)

fosc = 3.6864 MHz fosc = 4.0000 MHz fosc = 7.3728 MHz

U2X = 0U2X = 1U2X = 0U2X = 1U2X = 0U2X = 1

UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error

2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0%

4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0%

9600 230.0%470.0%250.2%510.2%470.0%950.0%

14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0%

19.2k 11 0.0% 23 0.0% 12 0.2% 25 0.2% 23 0.0% 47 0.0%

28.8k 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 15 0.0% 31 0.0%

38.4k 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 11 0.0% 23 0.0%

57.6k 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 7 0.0% 15 0.0%

76.8k 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 5 0.0% 11 0.0%

115.2k 1 0.0% 3 0.0% 1 8.5% 3 8.5% 3 0.0% 7 0.0%

230.4k 0 0.0% 1 0.0% 0 8.5% 1 8.5% 1 0.0% 3 0.0%

250k 0 -7.8% 1 -7.8% 0 0.0% 1 0.0% 1 -7.8% 3 -7.8%

0.5M – – 0 -7.8% – – 0 0.0% 0 -7.8% 1 -7.8%

1M ––––––––––0-7.8%

Max. (1) 230.4 kbps 460.8 kbps 250 kbps 0.5 Mbps 460.8 kbps 921.6 kbps

1. UBRR = 0, Error = 0.0%

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Table 81. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)

Baud

Rate

(bps)

fosc = 8.0000 MHz fosc = 11.0592 MHz fosc = 14.7456 MHz

U2X = 0 U 2X = 1 U2X = 0 U2X = 1 U2X = 0 U2X = 1

UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error

2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0%

4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0%

9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0%

14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0%

19.2k 25 0.2% 51 0.2% 35 0.0% 71 0.0% 47 0.0% 95 0.0%

28.8k 16 2.1% 34 -0.8% 23 0.0% 47 0.0% 31 0.0% 63 0.0%

38.4k 12 0.2% 25 0.2% 17 0.0% 35 0.0% 23 0.0% 47 0.0%

57.6k 8 -3.5% 16 2.1% 11 0.0% 23 0.0% 15 0.0% 31 0.0%

76.8k 6 -7.0% 12 0.2% 8 0.0% 17 0.0% 11 0.0% 23 0.0%

115.2k 3 8.5% 8 -3.5% 5 0.0% 11 0.0% 7 0.0% 15 0.0%

230.4k 1 8.5% 3 8.5% 2 0.0% 5 0.0% 3 0.0% 7 0.0%

250k 1 0.0% 3 0.0% 2 -7.8% 5 -7.8% 3 -7.8% 6 5.3%

0.5M 0 0.0% 1 0.0% – – 2 -7.8% 1 -7.8% 3 -7.8%

1M – – 0 0.0% – – – – 0 -7.8% 1 -7.8%

Max. (1) 0.5 Mbps 1 Mbps 691.2 kbps 1.3824 Mbps 921.6 kbps 1.8432 Mbps

1. UBRR = 0, Error = 0.0%

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Table 82. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)

Baud

Rate

(bps)

fosc = 16.0000 MHz fosc = 18.4320 MHz fosc = 20.0000 MHz

U2X = 0 U 2X = 1 U2X = 0 U2X = 1 U2X = 0 U2X = 1

UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error

2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0%

4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0%

9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2%

14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.2%

19.2k 51 0.2% 103 0.2% 59 0.0% 119 0.0% 64 0.2% 129 0.2%

28.8k 34 -0.8% 68 0.6% 39 0.0% 79 0.0% 42 0.9% 86 -0.2%

38.4k 25 0.2% 51 0.2% 29 0.0% 59 0.0% 32 -1.4% 64 0.2%

57.6k 16 2.1% 34 -0.8% 19 0.0% 39 0.0% 21 -1.4% 42 0.9%

76.8k 12 0.2% 25 0.2% 14 0.0% 29 0.0% 15 1.7% 32 -1.4%

115.2k 8 -3.5% 16 2.1% 9 0.0% 19 0.0% 10 -1.4% 21 -1.4%

230.4k 3 8.5% 8 -3.5% 4 0.0% 9 0.0% 4 8.5% 10 -1.4%

250k 3 0.0% 7 0.0% 4 -7.8% 8 2.4% 4 0.0% 9 0.0%

0.5M 1 0.0% 3 0.0% – – 4 -7.8% – – 4 0.0%

1M 0 0.0% 1 0.0% – – – – – – – –

Max. (1) 1 Mbps 2 Mbps 1.152 Mbps 2.304 Mbps 1.25 Mbps 2.5 Mbps

1. UBRR = 0, Error = 0.0%

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USI – Universal Serial

Interface The Universal Serial Interface, or USI, provides the basic hardware resources needed

for serial communication. Combined with a minimum of control software, the USI allows

significantly higher transfer rate s and uses less code space than solutions based on

software only. In te rrup ts a re inclu ded t o minim ize t he proce ssor lo ad . The main fe at ures

of the USI are:

•Two-wire Synchronous Data Transfer (Master or Slave)

•Three-wire Synchronous Data Transfer (Master or Slave)

•Data Received Interrupt

•Wakeup from Idle Mode

•In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode

•Two-wire Start Condition Detector with Interrupt Capability

Overview A simplified block diagram of the USI is shown on Figure 76 . For the actual placemen t of

I/O pins, refer to “Pinout ATmega169” on page 2. CPU accessible I/O Registers, includ-

ing I/O bits and I/O pins, a re shown in bold. The device-specific I/O Regi ster and bit

locations are listed in the “USI Register Descriptions” on page 185.

Figure 76. Universal Serial Interface, Block Diagram

The 8-bit Shift Register is directly accessible via the data bus and contains the incoming

and outgoing data. The register has no buffering so the data must be read as quickly as

possible to ensure that no da ta is lost. The mo st significa nt bit is connected to o ne of two

output pins depending of the wire mode configuration. A transparent latch is inserted

between the Se rial Register Output an d output pin, which delays the ch ange of dat a out-

put to the opposite clock edge of the data input sampling. The serial input is always

sampled from the Data Input (DI) pin independent of the configuration.

The 4-bit counter can be both read and written via the data bus, and can generate an

overflow interrupt. Both the Serial Register and the counter are clocked simultaneously

by the same clock source. This allows the counter to count the number of bits received

or transmitted and generate an interrupt when the transfer is complete. Note that when

an external clock source is selected the counter counts both clock edges. In this case

the counter counts the number of edges, and not the number of bits. The clock can be

selected from three different so urces: The USCK pin, Timer/Counter0 Comp are Match

or from software.

DATA BUS

USIPF

USITC

USICLK

USICS0

USICS1

USIOIFUSIOIE

USIDC

USISIF

USIWM0

USIWM1

USISIE Bit7

Two-wire Clock

Control Unit

DO (Output only)

DI/SDA (Input/Open Drain)

USCK/SCL (Input/Open Drain)

4-bit Counter

USIDR

USISR

USICR

CLOCK

HOLD

TIM0 COMP

Bit0

[1]

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The Two-wire clock control unit can generate an interrupt when a start condition is

detected on the Two-wire bus. It can also generate wait states by holding the clock pin

low after a start condition is detected, or after the counter overflows.

Functional Descriptions

Three-wire Mode The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0

and 1, but does not have the slave select (SS) pin functionality. However, this feature

can be implemented in softwa re if necessary. Pin na mes used by this mode are: DI, DO,

and USCK.

Figure 77. Three-wire Mode Operation, Simplified Diagram

Figure 77 shows two USI u nits op erating in Thr ee-wire mo de, o ne as Maste r and o ne as

Slave. The two Shift Registers are interconnected in such way that after eight USCK

clocks, the data in each register are interchanged. The same clock also increments the

USI’s 4-bit counter. The Counter Overflow (interrupt) Flag, or USIOIF, can therefore be

used to determine when a transfer is completed. The clock is generated by the Master

device software by toggling the USCK pin via the PORT Register or by writing a one to

the USITC bit in USICR.

Figure 78. Three-wire Mode, Timing Diagram

SLAVE

MASTER

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

USCK

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

USCK

PORTxn

MSB

654321LSB

1 2 3 4 5 6 7 8

654321LSB

USCK

DCBA E

CYCLE ( Reference )

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The Three-wire mode timing is shown in Figu re 78. At the top of the figure is a USCK

cycle referen ce. One bit is shifted into the USI Shift Register (USIDR) for ea ch of these

cycles. The USCK timing is sh own for both external clock modes. In External Clock

mode 0 (USICS0 = 0), DI is sampled at positive edges, and DO is changed (Data Regis-

ter is shifted by one) at negative edges. External Clock mode 1 (USICS0 = 1) uses the

opposite edg es versus mod e 0, i.e. , sample s data at negative and change s the out put at

positive edges. The USI clock modes corresponds to the SPI data mode 0 and 1.

Referring to the timing diagram (Figure 78.), a bus transfer involves the following steps:

1. The Slave de vice and Master device sets up its data output and, depending on

the protocol used, enables its output driver (mark A and B). The output is set up

by writing the data to be transmitted to the Serial Data Register. Enabling of the

output is done by setting the corres po nd in g bit in th e po rt Data Direction Regis-

ter. Note that point A and B does not have an y specific o rder, but both m ust be at

least one half USCK cycle before point C where the data is sampled. This must

be done to ensu re that th e da ta se tup r equ ire men t is sati sfie d. The 4-b it cou nt er

is reset to zero.

2. The Master generates a clock pulse by softw ar e toggling t he USCK line twice (C

and D). The bit value on the slav e an d mast er’s data input (DI) pi n is sampled by

the USI on the first edge (C), and the data output is changed on the opposite

edge (D). The 4-bit counter will count both edges.

3. Step 2. is repeated eight times for a complete register (byte) transfer.

4. After eight cloc k pulses (i.e., 16 clock edges) the counter will overflow and indi-

cate that the transfer is completed. The data bytes transferred must now be

processed bef ore a new transf er can be initiated. The o verflow interrupt will wak e

up the processor if it is set to Idle mode. Depending of the protocol used the

sla ve device can now set its output to high impedance.

SPI Master Operation

Example The following code demonstrates how to use the USI module as a SPI Master:

SPITransfer:

sts USIDR,r16

ldi r16,(1<<USIOIF)

sts USISR,r16

ldi r16,(1<<USIWM0)|(1<<USICS1)|(1<<USICLK)|(1<<USITC)

SPITransfer_loop:

sts USICR,r16

lds r16, USISR

sbrs r16, USIOIF

rjmp SPITransfer_loop

lds r16,USIDR

ret

The code is size optimized using only eight instructions (+ ret). The code example

assumes that the DO and USCK pins are enabled as output in the DDRE Register. The

value stored in register r16 prior to the function is called is transferred to the Slave

device, and when the transfer is completed the data received from the Slave is stored

back into the r16 Register.

The second and third instructions clears the USI Counter Overflow Flag and the USI

counter value. T he fourth and fifth instruction set Th ree-wire mode, positive edge Shift

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The following code demonstr ates how to use t he USI module as a SPI Mast er with max-

imum speed (fsck = fck/4):

SPITransfer_Fast:

sts USIDR,r16

ldi r16,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)

ldi r17,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)|(1<<USICLK)

sts USICR,r16 ; MSB

sts USICR,r17

sts USICR,r16

sts USICR,r17

sts USICR,r16

sts USICR,r17

sts USICR,r16

sts USICR,r17

sts USICR,r16

sts USICR,r17

sts USICR,r16

sts USICR,r17

sts USICR,r16

sts USICR,r17

sts USICR,r16 ; LSB

sts USICR,r17

lds r16,USIDR

ret

SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave:

init:

ldi r16,(1<<USIWM0)|(1<<USICS1)

sts USICR,r16

...

SlaveSPITransfer:

sts USIDR,r16

ldi r16,(1<<USIOIF)

sts USISR,r16

SlaveSPITransfer_loop:

lds r16, USISR

sbrs r16, USIOIF

rjmp SlaveSPITransfer_loop

lds r16,USIDR

ret

The code is size optimized using only eight instructions (+ ret). The code example

assumes that the DO is configur ed as output and USCK pin is conf igu red as input in the

DDR Register. The value stored in register r16 prior to the function is called is trans-

ferred to the master device, and when the transfer is completed the data received from

the Master is stored back into the r16 Regist er.

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Note that the first two instruct ions is for initialization only and needs only to be executed

once.These instructions sets Three-wire mode and positive edge Shift Register clock.

The loop is repeated until the USI Counter Overflow Flag is set.

Two-wire Mode The USI Two-wir e mode is com plian t to th e Int er I C (TWI ) bus pr otocol, bu t witho ut slew

rate limiting on outputs and input noise filtering. Pin names used by this mode are SCL

and SDA.

Figure 79. Two-wire Mode Operation, Simplified Diagram

Figure 79 shows two USI units operating in Two-wire mode, one as Master and one as

Slave. It is only the physical layer that is shown since the system operation is highly

dependent of the communicatio n scheme use d. The main dif ferences be tween th e Mas-

ter and Slav e operat ion at t his level, is the serial clock generation which is always done

by the Master, and only the Slave uses the clock control unit. Clock generation must be

implemented in software, but the shift operation is done automatically by both devices.

Note that only clockin g on negat ive edge for shi fting data is of practical use in this mod e.

The slave can insert wait states at start or end of transfer by forcing the SCL clock low.

This means that the Master must alwa ys check if the SCL line was actually released

after it has generated a positive edge.

Since the clock als o increm ent s the counte r, a counter overflow can be used to indicate

that the transfer is completed. The clock is generated by the master by toggling the

USCK pin via the PORT Regis ter .

The data direction is no t g ive n by t he physical laye r. A pro t ocol, like t he one u sed b y the

TWI-bus, must be implemented to control the data flow.

MASTER

SLAVE

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SDA

SCL

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Two-wire Clock

Control Unit

HOLD

SCL

PORTxn

SDA

SCL

VCC

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Figure 80. Two-wire Mode, Typical Timing Diagram

Referring to the timing diagram (Figure 80.), a bus transfer involves the following steps:

1. The a start condition is generated b y the Master b y f orcing the SD A low line while

the SCL line is high (A). SDA can be forced lo w eith er b y writing a ze ro to bit 7 of

the Shift Register, or by setting the corresponding bit in the PORT Register to

zero. Note that the Data Direction Reg ister bit m ust be set to one f or the output to

be enabled. The slave device’s start detector logic (Figure 81.) detects the start

condition and sets the USISIF Flag. The flag can generate an interrupt if

necessary.

2. In addition, the start detector will hold the SCL line lo w after the Master has

forced an negative edge on this line (B). This allows the Slave to wa ke up from

sleep or complete its other tasks before setting up the Shift Register to receive

the address. This is done by clearing the start condition flag and reset the

counter.

3. The Master set the first bit to be transferred and releases the S CL line (C) . Th e

Slav e samples the data and shift it int o the Serial Register at the posi tiv e edge of

the SCL clock.

4. After eight bits are tr ansferred containing sla ve address a nd dat a dir ection (r ea d

or write), the Slave counter ov erflows and the SCL line is forced low (D). If the

sla ve is not the one the Master has addressed, it re leases the SCL line an d waits

for a new start condition.

5. If the Slave is addressed it holds the SDA line low during the acknowledgment

cycle before holding the SCL line low again (i.e., the Counter Register must be

set to 14 before releasing SCL at (D)). Depending of the R/W bit the Master or

Slave enables its output. If the bit is set, a master read operation is in progress

(i.e., t he slave drives the SDA line) The slave can hold the SCL line low after the

acknowledge (E).

6. Multiple bytes can now be tr ansmitted, all in same direction, until a stop condition

is given by the Master (F). Or a new start condition is given.

If the Slave is not able to r eceive more da ta it d oes not ackn owledge the data by te it has

last received. When the Ma ster does a read o perat ion it must t erminat e the o peration by

force the acknowledge bit low after the last byte transmitted.

Figure 81. Start Condition Detector, Logic Diagram

PS ADDRESS

1 - 7 8 9

R/W ACK ACK

1 - 8 9

DATA ACK

1 - 8 9

DATA

SDA

SCL

A B D EC F

SDA

SCL

Write( USISIF)

CLOCK

HOLD

USISIF

CLR

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Start Condition Detector The start condition detector is shown in Figure 81. The SDA lin e is delayed (in the range

of 50 to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is

only enabled in Two-wire mode.

The start condition detector is working asynchronously and can therefore wake up the

processor from the Power-down sleep mode. However, the protocol used might have

restrictions on the SCL hold time. Therefore, when using this feature in this case the

Oscillator start-up time set by the CKSEL Fuses (see “Clock Systems and their Distribu-

tion” on page 23) must also be taken into the consideration. Refer to the USISIF bit

description on page 186 for further details.

Clock speed considerations. Maximum frequency for SCL and SCK is fCK /4. This is also the maximu m data tr ansmit

and receieve rate in both two- and thr ee-wire mode. In two-wire slave mode the Two-

wire Clock Control Unit will hold the SCL low until the slave is ready to receive more

data. This may reduce the actual data rate in two-wire mode.

Alternative USI Usage When the USI unit is not used f or serial communica tion, it ca n be set up to d o altern ative

tasks due to its flexible design.

Half-duplex Asynchronous

Data Transfer By utilizing the Shift Register in Three-wire mode, it is possible to implement a more

compact and higher performance UART than by software only.

4-bit Counter The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note

that if the counter is clocked externally, both clock edges will generate an increment.

12-bit Timer/Counter Combining the USI 4-bit counter and Timer/Counter0 allows them to be used as a 12-bit

counter.

Edge Triggered External

Interrupt By setting the counter to maximum value (F) it can function as an additional external

interrupt. Th e Over flow Fla g and I nte rrupt Enable bit are the n used f or the exter nal in ter-

rupt. This feature is selected by the USICS1 bit.

Software Interrupt The counter overflow interrupt can be used as a software interrupt triggered by a clock

strobe.

USI Register

Descriptions

USI Data Register – USIDR

The USI uses no bufferin g of th e Seri al Re gist er, i. e., whe n accessing t he Da ta Regist er

(USIDR) the Serial Register is accessed directly. If a serial clock occurs at the same

cycle the register is written, the register will contain the value written and no shift is per-

formed. A (le ft) shift oper ation is perf ormed dependin g of the USICS1.. 0 bits sett ing. The

shift operation can be controlled by an external clock edge, by a Timer/Counter0 Com-

pare Match, or directly by software using t he USICLK st robe bit. Not e that even when no

wire mode is selected (USIWM1..0 = 0) both the external data input (DI/SDA) and the

external clock input (USCK/SCL) can still be used by the Shift Register.

Bit 7 6 5 4 3 2 1 0

MSB LSB USIDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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The output pin in use, DO or SDA depen ding on the wire mode, is connected via the out-

put latch to the most significant bit (bit 7) of the Data Register. The output latch is open

(transparent) during the first half of a serial clock cycle when an external clock source is

selected (USICS1 = 1), and constantly open when an internal clock source is used

(USICS1 = 0). The output will be changed immediately when a new MSB written as long

as the latch is open. The latch e nsures that data input is sampled and data output is

changed on opposite clock edges.

Note that the corresponding Data Direction Register to the pin must be set to one for

enabling data output from the Shift Regi ster.

USI Status Register – USISR

The Status Regist er contains Interrupt Flags, line Status Flags and the counter value.

• Bit 7 – USISIF: Start Condition Interrupt Flag

When Two-wire mode is selected, the USISIF Flag is set (to one) when a start condition

is detected. When output disable mode or Three-wire mode is selected and (USICSx =

0b11 & USICLK = 0) or (USICS = 0b10 & USICLK = 0), any edge on the SCK pin sets

the flag.

An interrupt will be generated when the flag is set while the USISIE bit in USICR and the

Global Interrupt Enable Flag are set. The flag will only be cleared by writing a logical one

to the USISIF bit. Clearing this bit will release the start detection hold of USCL in Two-

wire mode.

A start condition interrupt will wakeup the processor from all sleep modes.

• Bit 6 – USIOIF: Counter Overflow Interrupt Flag

This flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to

0). An interrupt will be generated when the flag is set while the USIOIE bit in USICR and

the Global Interrupt Enable Flag are set. The flag will only be cleared if a one is written

to the USIOIF bit. Clearing this bit will release the counter overflow hold of S CL in Two-

wire mode.

A counter overflow interrupt will wakeup the processor from Idle sleep mode.

• Bit 5 – USIPF: Stop Condition Flag

When Two-wire mode is selected, the USIPF Flag is set (one) when a stop condition is

detected. The flag is cleared by writing a one to this bit. Note that this is not an Interrupt

Flag. This signal is useful when implementing Two-wire bus master arbitration.

• Bit 4 – USIDC: Data Output Collision

This bit is logical one when bit 7 in the Shift Register differs from the physical pin value.

The flag is only valid when Two-wire mode is used. This signal is useful when imple-

menting Two-wire bus master arbitration.

• Bits 3..0 – USICNT3..0: Counter Value

These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be

read or written by the CPU.

Bit 76543210

USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 USISR

Read/Write R/W R/W R/W R R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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The 4-bit counter increments by one for each clock generated either by the external

clock edge detector, by a T imer/Counter0 Compare Match, or by software using USI-

CLK or USITC strobe bits. The clock source depends of the setting of the USICS1..0

bits. For external clock operation a special feature is added that allows the clock to be

generated by writing to the USITC strobe bit. This feature is enabled by write a one to

the USICLK bit while setting an external clock source (USICS1 = 1).

Note that even when no wire mode is selected (USIWM1..0 = 0) the extern al clock input

(USCK/SCL) are can still be used by the counter.

USI Control Register – USICR

The Control Register includes interrupt enable control, wire mode setting, Clock Select

setting, and clock strobe.

• Bit 7 – USISIE: Start Condition Interrupt Enable

Setting this bit to one enables the Start Condition detector interrupt. If there is a pending

interrupt when the USISIE and the Glob al Interrupt Enable Flag is set to one, this will

immediately be executed. Refer to the USISIF bit description on page 186 for further

details.

• Bit 6 – USIOIE: Counter Overflow Interrupt Enable

Setting this bit to one enables the Counter Overflow interrupt. If there is a pending inter-

rupt when the USIOIE and the Global Interrupt Enable Flag is set to one, this will

immediately be executed. Refer to the USIOIF bit description on page 186 for further

details.

• Bit 5..4 – USIWM1..0: Wire Mode

These bits set the type of wire mode to be used. Basically only the function of the

outputs are affected by these bits. Data and clock inputs are not affected by the mode

selected and will always have the same functi on. The counter and Shift Register can

therefore be clocked externally, and data input sampled, even when outputs are

disabled. The relations between USIWM1..0 and the USI operation is summarized in

Table 83.

Bit 7 6 5 4 3 2 1 0

USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC USICR

Read/Write R/W R/W R/W R/W R/W R/W W W

Initial Value 0 0 0 0 0 0 0 0

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Note: 1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL)

respectively to avoid confusion between the modes of operation.

Table 83. Relations between USIWM1..0 and the USI Operation

USIWM1 USIWM0 Description

0 0 Outputs, clock hold, and start detector disabled. Port pins operates as

normal.

0 1 Three-wire mode. Uses DO, DI, and USCK pins.

The Data Output (DO) pin ov errides the corresponding bit in the PORT

controls the data direction. Whe n the port pin is set as input the pins

pull-up is controlled by the PORT bit.

The Data Input (DI) and Serial Cl ock (USCK) pins do not affect the

nor m al port operation. When operating as master, clock pulses are

software generated by toggling the PORT Register, while the data

direction is set to output. The USITC bit in the USICR Register can be

used for this purpose.

1 0 Two-wire mode. Uses SDA (DI) and SCL (USCK) pins(1).

The Serial Data (SDA) and the Serial Clock (SCL) pins are bi-

directional and uses open-collector output drives. The output drivers

are enabled by setting the corresponding bit for SDA and SCL in the

DDR Register.

When the output driver is enabled f or the SDA pin, the output driver will

force the line SDA low if the output of the Shift Register or the

corresponding bit in the PORT Register is zero. Otherwise the SDA

line will not be driven (i.e., it is released). When the SCL pin output

driver is enabled the SCL line will be forced low if the corresponding bit

in the PORT Register is zero, or by the start detector. Otherwise the

SCL line will not be driven.

The SCL line is held low when a start detector detects a start condition

and the output is enabled. Clearing the Start Condition Flag (USISIF)

releases the line. The SDA and SCL pin inputs is not affected by

enabling this mode. Pull-ups on the SDA and SCL port pin are

disabled in Two-wire mode.

1 1 Two-wire mode. Uses SDA and SCL pins.

Same operation as for the Two-wire mode described above, e xcept

that the SCL line is also held low when a counter overflo w occurs , and

is held low until the Counter Overflow Flag (USIOIF) is cleared.

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• Bit 3..2 – USICS1..0: Clock Source Select

These bits set the clock source for the Shift Register and counter. The data output latch

ensures that the output is changed at the opposite edge of the sampling of the data

input (DI/SDA) when using external clock source (USCK/SCL). When software strobe or

Timer/Counter0 Compare Match clock option is selected, the output latch is transparent

and therefore the output is changed immediately. Clearing the USICS1..0 bits enables

software strobe option. When using this option, writing a one to the USICLK bit clocks

both the Shift Register and the counter. For external clock source (USICS1 = 1), the

USICLK bit is no longer used as a strobe, but selects between external clocking and

software clocking by the USITC strobe bit.

Table 84 shows the relationship between the USICS1..0 and USICLK setting and clock

source used for the Shift Register and the 4-bit counter.

• Bit 1 – USICLK: Clock Strobe

Writing a one to this bit location strobes the Shift Register to shift one step and the

counter to increment by one, provided that the USICS1..0 bits are set to zero and by

doing so the software clock strobe option is selected. The ou tput will change immedi-

ately when the cloc k strobe is executed, i.e., in the sam e instruction cycle. The value

shifted into the Shift Register is sampled the previous instruction cycle. The bit will be

read as zero.

When an external clock source is selected (USICS1 = 1), the USICLK function is

changed from a clock strobe to a Clock Select Register. Setting the USICLK bit in this

case will select the USITC strobe bit as clock source for the 4-bit counter (see Table 84).

• Bit 0 – USITC: Toggle Clock Port Pin

Writing a one to this bit location toggles the USCK/SCL value either from 0 to 1, or from

1 to 0. The t oggling is indepe ndent of t he setting in the Da ta Directio n Register, but if the

PORT value is to be shown on the pin the DDRE4 must be set as output (to one). This

feature allows easy clock generation when implementing master devices. The bit will be

read as zero.

When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to

one, writing to the USITC strobe bit will directly clock the 4-bit counter. This allows an

early detection of when the transfer is done when operating as a master device.

Table 84. Relations between the USICS1..0 and USICLK Setting

USICS1 USICS0 USICLK Shift Register Clock

Source 4-bit Counter Cloc k

Source

0 0 0 No Clock No Clock

0 0 1 Software clock strobe

(USICLK) Software clock strobe

(USICLK)

0 1 X Timer/Counter0 Compare

Match Timer/Counter0 Compare

Match

1 0 0 External, positive edge External, both edges

1 1 0 External, negative edge External, both edges

1 0 1 External, positive edge Software clock strobe

(USITC)

1 1 1 External, negative edge Software clock strobe

(USITC)

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Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and nega-

tive pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on

the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’s

output can be set to trigger the Timer/Counter1 Input Capture functio n. In addition, the

comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The

user can select Interrupt triggering on comparator output rise, fall or toggle. A block dia-

gram of the comparator and its surrounding logic is shown in Figure 82.

The Power Reduction ADC bit, PRADC, in “Power Reduction Register - PRR” on page

34 must be disabled by writing a logical zero to be able to use the ADC input MUX.

Figure 82. Analog Comparator Block Diagram(2)

Notes: 1. See Table 86 on page 192.

2. Refer to Figure 1 on page 2 and Table 29 on page 63 for Analog Comparator pin

placement.

ADC Control and Status

• Bit 6 – ACME: Analog Compar ator Multiplexer Enable

When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is

zero), the ADC multiplexer selects the negative input to the Analog Comparator. When

this bit is written logic zero, AIN1 is applied to the negative input of the Analog Compar-

ator. For a detailed descript io n of this bit, see “Analog Comp ara tor Mu ltip lexed Inp ut” on

page 192.

Analog Comparator Control

and Status Regi st er – ACSR

• Bit 7 – ACD: Analog Comparator Disable

When this bit is wr itten logic one, the po wer to the Analog Comparator is switch ed off.

This bit can be set at any time to turn off the Analog Comparator. This will reduce power

ACBG

BANDGAP

REFERENCE

ADC MULTIPLEXER

OUTPUT

ACME

ADEN

(1)

Bit 76543210

– ACME – – – ADTS2 ADTS1 ADTS0 ADCSRB

Read/Write R R/W R R R R/W R/W R/W

Initial Value00000000

Bit 76543210

ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 ACSR

Read/Write R/W R/W R R/W R/W R/W R/W R/W

Initial Value 0 0 N/A 0 0 0 0 0

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consumption in Active and Idle mode. When changing the ACD bit, the Analog Compar-

ator Interr upt must be disabl ed by cleari ng t he ACI E bit in ACSR. Ot herwise an int erru pt

can occur when the bit is changed.

• Bit 6 – ACBG: Analog Comparator Bandgap Select

When this bit is set, a fixed bandgap reference voltage replaces the positive input to the

Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the

Analog Comparator. When the bandgap reference is used as input to the Analog Com-

parator, it will take a certain time for the voltage to stabilize. If not stabilized, the first

conversion may give a wrong value. See “Internal Voltage Reference” on page 42.

• Bit 5 – ACO: Analog Comparator Output

The output of the Analog Comparator is synchronized and then directly connected to

ACO. The synchronization introduces a delay of 1 - 2 clock cycles.

• Bit 4 – ACI: Analog Comparator Interrupt Flag

This bit is set by hardware when a comparator output event triggers the interrupt mode

defined by ACIS1 and ACIS0. The An alog Comparator interrupt routine is execu ted if

the ACIE bit is set and t he I-bit in SREG is set. ACI is cl eared by har dware when execut-

ing the corresponding interrupt handling vector. Alternativel y, ACI is cleared by writing a

logic one to the flag.

• Bit 3 – ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Ana-

log Comparator interrupt is activated. When written logic zero, the interrupt is disabled.

• Bit 2 – ACIC: Analog Comparator Input Capture Enable

When written logic one, this bit enables the Input Capture function in Timer/Counter1 to

be triggered by the Analog Comparator. The comparator output is in this case directly

connected to the Input Capture front-end logic, making the comparator utilize the noise

canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When

written logic zero , no conne ction b etwe en the Analog Com parat or and the I nput Capture

function exists . To make th e comparator trigger the Timer/Counter1 Input Capture inter-

rupt, the ICIE1 bit in th e Time r Int erru pt Mas k Reg iste r (TIM SK1 ) mu st be set .

• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits deter mine which compa rator event s that tr igger th e Analog Com parator in ter-

rupt. The different settings are shown in Table 85.

When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be dis-

abled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt

can occur when the bits are changed.

Table 85. ACIS1/ACIS0 Settings

ACIS1 ACIS0 Interrupt Mode

0 0 Comparator Interrupt on Output Toggle.

01Reserved

1 0 Comparator Interrupt on F a lling Output Edge.

1 1 Comparator Interrupt on Rising Output Edge.

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Analog Comparator

Multiplexed Input It is possible to select any of the ADC7..0 pins to replace the negative input to the Ana-

log Comparator. The ADC multiplexer is used to select this input, and consequently, the

ADC must be switched o ff to utilize this feature. If the Analog Comparator Multiplexer

Enable bit (ACME in ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is

zero), MUX2..0 in ADMUX select the input pin to replace the negative input to the Ana-

log Comparator, as shown in Table 86. If ACME is cleared or ADEN is set, AIN1 is

applied to the negative input to the Analog Comparator.

Digital Input Disable Register

1 – DIDR1

• Bit 1, 0 – AIN1D, AIN0D: AI N1, AIN0 Digital Input Disable

When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled.

The corresponding PIN Register bit will always read as zero when this bit is set. When

an analog signal is applied to the AIN1/0 pin an d the digital input from this pin is not

needed, this bit should be written logic one to reduce power consumption in the digital

input buffer.

Table 86. Analog Comparator Multiplexed Input

ACME ADEN MUX2..0 Analog Comparator Negative Input

0 x xxx AIN1

1 1 xxx AIN1

1 0 000 ADC0

1 0 001 ADC1

1 0 010 ADC2

1 0 011 ADC3

1 0 100 ADC4

1 0 101 ADC5

1 0 110 ADC6

1 0 111 ADC7

Bit 76543210

–––––– AIN1D AIN0D DIDR1

Read/WriteRRRRRRR/WR/W

Initial Value00000000

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Analog to Digital

Converter

Features •10-bit Resolution

•0.5 LSB Integral Non-linearity

•± 2 LSB Absolute Accuracy

•13 µs - 260 µs Conversion Time (50 kHz to 1 MHz ADC clock)

•Up to 15 kSPS at Maximum Resolution (200 kHz ADC cloc k)

•Eight Multiplexed Single Ended Input Channels

•Optional Left Adjustment for ADC Result Readout

•0 - VCC ADC Input Voltage Range

•Selectable 1.1V ADC Reference Voltage

•Free Running or Single Conversion Mode

•ADC Start Conversion by Auto Triggering on Interrupt Sources

•Interrupt on ADC Conversion Complete

•Sleep Mode Noise Canceler

The ATmega169 features a 10-bit successive approximation ADC. The ADC is con-

nected to an 8-channel Analog Multiplexer which allows eight single-ended voltage

inputs constructed from the pins of Port F . The single-end ed voltage inputs refer to 0V

(GND).

The ADC contains a Sample and Hold circuit which ensures that the input voltage to the

ADC is held at a constant le ve l during co nv er sion. A block d iagr am of th e ADC is shown

in Figure 83.

The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ more

than ± 0.3 V fr om VCC. See t he par agr ap h “ADC No ise Ca ncele r” on page 200 on h ow to

connect this pin.

Internal reference voltages of nominally 1.1V or AVCC a re provided On-chip. T he volt-

age reference may be externally decoupled at the AREF pin by a capacitor for better

noise performance.

The Power Reduction ADC bit, PRADC, in “Power Reduction Register - PRR” on page

34 must be written to zero to enable the ADC module.

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ATmega169/V

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Figure 83. Analog to Digital Converter Block Schematic

Operation The ADC converts an analog input voltage to a 10-bit digital value through successive

approximation. Th e minimum value represent s GND and t he maximum value represent s

the voltage on the AREF pin minus 1 LSB. Optionally, AVCC or an internal 1.1V refer-

ence voltage may be connected to the AREF pin by writing to the REFSn bits in the

ADMUX Register. The internal voltage reference may thus be decoupled by an external

capacitor at the AREF pin to improve noise immunity.

The analog input channel is selected by writing to the MUX bits in ADMUX. Any of the

ADC input pins, as well as GND and a fixed b andgap voltage reference, can be selected

as single ended inputs to the ADC. The ADC is enabled by setting the ADC Enable bit,

ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect

until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is

recommended to switch off the ADC before entering power saving sleep modes.

The ADC generates a 10-bit result which is presented in the ADC Data Registers,

ADCH and ADCL. By default, the result is presented right adjusted, but can optionally

be presented left adjusted by setting the ADLAR bit in ADMUX.

If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to

read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content

of the Data Registers belongs to the same conversion. Once ADCL is read, ADC access

ADC CONVERSION

COMPLETE IRQ

8-BIT DATA BUS

15 0

ADC MULTIPLEXER

SELECT (ADMUX) ADC CTRL. & STATUS

(ADCH/ADCL)

MUX2

ADIE

ADATE

ADSC

ADEN

ADIF ADIF

MUX1

MUX0

ADPS0

ADPS1

ADPS2

MUX3

CONVERSION LOGIC

10-BIT DAC

SAMPLE & HOLD

COMPARATOR

INTERNAL

REFERENCE

MUX DECODER

MUX4

AVCC

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

REFS0

REFS1

ADLAR

CHANNEL SELECTION

ADC[9:0]

ADC MULTIPLEXER

OUTPUT

DIFFERENTIAL

AMPLIFIER

AREF

BANDGAP

REFERENCE

PRESCALER

SINGLE ENDED / DIFFERENTIAL SELECTION

GND

POS.

INPUT

MUX

NEG.

INPUT

MUX

TRIGGER

SELECT

ADTS[2:0]

INTERRUPT

FLAGS

START

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ATmega169/V

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to Data Registers is blocked. This means that if ADCL has been read, and a conversion

completes before ADCH is read, neither register is updated and the result from the con-

version is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers is

re-enabled.

The ADC has its own interrupt which can be triggered when a conversion completes.

When ADC access to the Data Registers is prohibited between reading of ADCH an d

ADCL, the interrupt will trigger even if the result is lost.

Starting a Conversion A sin gle conversion is started by writing a logical one to the ADC St art Conversion bit,

ADSC. This bit stays high as long as the conversion is in progress and will be cleared by

hardware wh en the con version is co mplete d. If a dif ferent dat a channel is se lected while

a conversion is in progress, the ADC will finish the current conversion before performing

the channel change.

Alternatively, a conversion can be trigg ered auto matically by variou s sources. Auto Tr ig-

gering is enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The

trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB

(See description of the ADTS bits for a list of the t rigger sources). When a positive edge

occurs on the selected trigger signal, the ADC prescaler is reset and a conversion is

started. This provides a method of starting conversions at fixed intervals. If the trigger

signal still is set when the conversion completes, a new conversion will not be started. If

another positive edge occurs on the trigger signal during conversion, the edge will be

ignored. Note that an Interrupt Flag will be set even if the specific interrupt is disabled or

the Global Interrupt Enable bit in SREG is cleared. A conversion can thus be triggered

without causing an int errupt. However, th e Interrupt F lag must be cleared in order to tr ig-

ger a new conversion at the next interrupt event.

Figure 84. ADC Auto Trigger Logic

Using the ADC Inter rupt Fla g as a t rigger sour ce make s the ADC start a new con version

as soon as the ongoing conv ersion has finished. The ADC then operates in Free Run-

ning mode, constantly sampling and updating the ADC Data Register. The first

conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In this

mode the ADC will perform successive conversions independently of whether the ADC

Interrupt Flag, ADIF is cleared or not.

If Auto Triggering is enabled, single conve rsions can be started by writing ADSC in

ADCSRA to one. ADSC can also be used to determine if a conversion is in progress.

DSC

ADIF

SOURCE 1

SOURCE n

ADTS[2:0]

CONVERSION

LOGIC

PRESCALER

START CLKADC

.EDGE

DETECTOR

ADATE

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The ADSC bit will be read as one during a conversion, independently of how the conver-

sion was started.

Prescaling and

Conversion Timing Figure 85. ADC Prescaler

By default, the successive approximation circuitry requires an input clock frequency

between 50 kHz and 20 0 kHz to get maximum resolution. If a lower resolution than 10

bits is needed, t he input clo ck frequ ency to the ADC ca n be higher th an 200 kHz t o get a

higher sample rate.

The ADC module contains a prescaler, which generates an acceptable ADC clock fre-

quency from any CPU freque ncy above 100 kHz. The p rescaling is set by the ADPS bits

in ADCSRA. The prescaler starts counting from the moment the ADC is switched on by

setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN

bit is set, and is continuously reset when ADEN is low.

When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the con-

version starts at the following rising edge of the ADC clock cycle.

A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is

switched on (ADEN in ADCSRA is set) takes 25 ADC cloc k cycles in order to initialize

the analog circuitry.

When the bandgap reference voltage is used as input to the ADC, it will take a certain

time for the voltage to stabilize. If not stabilized, the first value read after the first conver-

sion may be wrong.

The actual sample- and -hold ta ke s place 1. 5 ADC clock cycles a fter the st art of a no rma l

conversion and 13.5 ADC clock cycles after th e star t of an fir st conversion . When a co n-

version is complete, the result is written to the ADC Data Registers, and ADIF is set. In

Single Conversion mod e, ADSC is cleared simultaneously. Th e software may then set

ADSC again, and a new conversion will be initiated on the first rising ADC clock edge.

When Auto Triggering is used , th e p resca ler is rese t wh en the t rigge r e vent occur s . This

assures a fixed delay from the trigger event to the start of conversion. In this mode, the

sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger

source signal. Three additional CPU clock cycles are used for synchronization logic.

When using Differential mode, along with Auto triggering from a source other than the

ADC Conversion Complete, each conversion will require 25 ADC clocks. This is

because the ADC must be disabled and re-enabled after every conversion.

7-BIT ADC PRESCALER

ADC CLOCK SOURCE

ADPS0

ADPS1

ADPS2

CK/128

CK/2

CK/4

CK/8

CK/16

CK/32

CK/64

Reset

DEN

TART

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In Free Running mode, a new conversion will be started immediately after the conver-

sion completes, while ADSC remains high. For a summary of conversion times, see

Table 87.

Figure 86. ADC Timing Diagram, First Conversion (Single Conversion Mode)

Figure 87. ADC Timing Diagram, Single Conversion

Figure 88. ADC Timing Diagram, Auto Triggered Conversion

Sign and MSB of Result

LSB of Result

DC Clock

DSC

Sample & Hold

DIF

DCH

DCL

ycle Number

DEN

1212

13 14 15 16 17 18 19 20 21 22 23 24 25 1 2

First Conversion Next

Conversion

MUX and REFS

Update MUX and REF

Update

Conversion

Complete

123456789 10 11 12 13

Sign and MSB of Result

LSB of Result

DC Clock

DSC

DIF

DCH

DCL

ycle Number 12

One Conversion Next Conversion

Sample & Hold

MUX and REFS

Update

Conversion

Complete MUX and REF

Update

1 2 3 4 5 6 7 8 910 11 12 13

Sign and MSB of Resul

LSB of Result

DC Clock

rigger

ource

DIF

DCH

DCL

ycle Number 12

One Conversion Next Conversio

Conversion

Complete

Prescaler

Reset

DATE

Prescaler

Reset

Sample &

Hold

MUX and REFS

Update

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Figure 89. ADC Timing Diagram, Free Running Conversion

Table 87. ADC Conversion Time

Condition Sample & Hold (Cycles

from Start of Conversion) Conversion Time

(Cycles)

First conversion 13.5 25

Nor m al conversions, single ended 1.5 13

A uto Triggered conversions 2 13.5

11 12 13

Sign and MSB of Result

LSB of Result

DC Clock

DSC

DIF

DCH

DCL

ycle Number 12

One Conversion Next Conversion

Conversion

Complete Sample & Ho

MUX and REFS

Update

199

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Changing Channel or

Reference Selection The MUXn and REFS1:0 bits in t he ADMUX Reg iste r are single buff er ed t hr ough a t em-

porary register to which the CPU has random access. This ensu res that the channels

and reference selection only takes place at a safe point during the conversio n. The

channel and reference selection is continuously updated until a co nversion is started.

Once the conversion starts, the channel and reference selection is locked to ensure a

sufficient sampling time for the ADC. Continuous updating resumes in the last ADC

clock cycle before the conversion completes (ADIF in ADCSRA is set). Note that the

conversion starts on the following rising ADC clock edge after ADSC is written. The user

is thus advised not to write new channel or reference selection values to ADMUX until

one ADC clock cycle after ADSC is written.

If Auto Triggering is used, the exact time of the triggering event can be indeterministic.

Special care must be taken when updating the ADMUX Register, in order to control

which conversion will be affected by the new settings.

If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If

the ADMUX Register is changed in this period, the u ser cannot t ell if the n ext conversion

is based on the old or the new settings. ADMUX can be safely updated in the following

ways:

1. When ADATE or ADEN is cleared.

2. During conversion, minimum one ADC cloc k cycle after the trigger event.

3. After a conversion, before the Interrupt Flag used as trigger source is

cleared.

When updating ADMUX in one of these conditions, the new settings will affect the next

ADC conversion.

ADC Input Channels When changing channel selections, the user should observe the following guidelines to

ensure that the correct channel is selected:

In Single Conversion mode, always select the cha nnel before starting the conversion.

The channel selection may be changed one ADC clock cycle after writing one to ADSC.

However, the simplest method is to wait for the conversion to complete before changing

the channel selection.

In Free Running mode, always select the channe l before starting the first conversion.

The channel selection may be changed one ADC clock cycle after writing one to ADSC.

However, the simplest method is to wait for the first conversion to complete, and then

change the channel selection. Since the next conversion has already started automati-

cally, the next result will reflect the previous channel selection. Subsequent conversions

will reflect the new channel selection.

ADC Voltage Reference The reference voltage for the ADC (VREF) indicates the conversion range for the ADC.

Single ended channels t hat exceed VREF will result in codes close to 0x3FF. VREF can be

selected as either AVCC, internal 1.1V reference, or external AREF pin.

AVCC is connected to the ADC through a passive switch. The internal 1.1V reference is

generated fr om the intern al bandgap re ference (VBG) through an internal buff er. In either

case, the external AREF p in is d ire ctly con nected to t he ADC, an d th e ref erence volt age

can be made more immune to noise by connecting a capacitor between the AREF pin

and ground. VREF can also be measured at the AREF pin with a high impedant voltme-

ter. Note that VREF is a high impedant source, and only a capacitive load should be

connected in a system.

If the user ha s a fixed vo ltage sour ce conn ected to the AREF pin, the use r may no t use

the other reference voltage options in the application, as they will be shorted to the

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ATmega169/V

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external voltage. If no external voltage is applied to the AREF pin, the user may switch

between AVCC and 1.1V as reference selection. The first ADC conversion result after

switching reference voltage source may be inaccurate, and the user is advised to dis-

card this result.

ADC Noise Canceler The ADC features a noise canceler that enables conversion during sleep mode to

reduce no ise induced from the CPU core and othe r I/O pe ripherals. T he noise canceler

can be used with ADC Noise Reduction and Idle mode. To make use of this featu re, the

following procedure should be used:

1. Make sure that the ADC is enabled and is not busy converting. Single Con-

version mode must be selected and the ADC conversion complete interrupt

must be enabled.

2. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a con-

version once the CPU has been halted.

3. If no other interrupts occur before the ADC conversion completes, the ADC

interrupt will wake up the CPU and execute the ADC Conversion Complete

interrupt routine. If another interrupt wakes up the CPU before the ADC con-

version is complete, that interrupt will be executed, and an ADC Conversion

Complete interrupt request will be generated when the ADC conversion

completes. The CPU will remain in active mode until a new sleep command

is executed.

Note that the ADC will not be automatically turned off when entering other sleep modes

than Idle mode and ADC Noise Reduction mode. The user is advised to write zero to

ADEN before entering such sleep modes to avoid excessive power consumption.

Analog Input Circuitry The analog input circuitr y for single ended channe ls is illustr ated in Figu re 90. An an alog

source applied to ADCn is subjected to the pin capacitance and input leakage of that

pin, regardless of whet her that channel is selecte d as input for the ADC. When the chan-

nel is selected, the source must drive the S/H capacitor throug h the series resistance

(combined resistan ce in the input path).

The ADC is optimized for analog signals with an ou tput impedance of approximately

10 kΩ or less. If such a source is used, the sampling time will be negligible. If a source

with higher impedance is used, the sampling time will depend on how long time the

source needs to charge the S/H capacitor, with can vary widely. The user is recom-

mended to only use low impedant sources with slowly varying signals, since this

minimizes the required charge transfer to the S/H capacitor.

Signal components higher than the Nyquist frequency (fADC/2) should not be present for

either kind of channels, to avoid distortion from unpredictable signal convolution. The

user is advised to remove high frequency components with a low-pass filter before

applying the signals as inputs to the ADC.

Figure 90. Analog Input Circuitry

ADCn

1..100 kW

S/H

= 14 pF

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Analog Noise Canceling

Techniques Digital circuitry inside and outside the device generates EMI which might affect the

accuracy of analog measurements. If conversion accuracy is critical, the noise level can

be reduced by applyin g th e follo win g te ch niq ues:

1. Keep analog signal paths as short as possible. Make sure analog tracks run

over the analog ground plane, and keep them well away from high-speed

switching digital tracks.

2. The AVCC pin on the device sh ould be connected to the digital VCC supply

voltage via an LC network as show n in Figure 91.

3. Use the ADC noise canceler functio n to reduce indu ced noise fr om the CPU.

4. If any ADC port pins are used as digital outputs, it is essential that these do

not switch while a conversion is in progress.

Figure 91. ADC Power Connections

VCC

GND

100nF

Analog Ground Plane

(ADC0) PF0

(ADC7) PF7

(ADC1) PF1

(ADC2) PF2

(ADC3) PF3

(ADC4) PF4

(ADC5) PF5

(ADC6) PF6

AREF

GND

AVCC

6161

6262

6363

6464

LCDCAP

PA0

10µΗ

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ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n

steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1.

Several parameters describe the deviation from the ideal behavior:

• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal

transition (at 0.5 LSB). Ideal value: 0 LSB.

Figure 92. Offset Error

• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the

last transition (0x3FE to 0x 3F F ) comp ar e d to th e ide al transiti on (at 1.5 LSB below

maximum). Ideal value: 0 LSB

Figure 93. Gain Error

• Integral Non-linearity (INL): After adjusting for off set and gain error, the INL is the

maximum deviation of an actual transition compared to an ideal transition for any

code. Ideal value: 0 LSB.

Output Code

VREF Input Voltage

Ideal ADC

Actual ADC

Offset

Error

Output Code

VREF Input Voltage

Ideal ADC

Actual ADC

Gain

Error

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Figure 94. Integral Non-linearity (INL)

• Differential Non-linearity (DNL): The maximum deviation of the actual code width

(the interval between two adjacent transitions) from the ideal code width (1 LSB).

Ideal value: 0 LSB.

Figure 95. Differential Non-linearity (DNL)

• Quantization Erro r: Due to the quantization of the input voltage into a finite number

of codes, a range of input v oltages (1 LSB wide) will code to the same value. Alw a ys

± 0.5 LSB.

• Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition

compared to an ide al transition for any code. This is the compound effect of offset,

gain error, diff erential error, non-linearity, and quantization error. Ideal value: ± 0.5

LSB.

Output Code

VREF Input Voltage

Ideal ADC

Actual ADC

INL

Output Code

0x3FF

0x000

0VREF Input Voltage

DNL

1 LSB

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ADC Conversion Result

After the conversion is complete (ADIF is high), the conversion result can be found in

the ADC Result Registers (ADCL, ADCH).

For single ended conversion, the result is

where VIN is the voltage on the selected input pin and VREF the selected voltage refer-

ence (see Table 89 on page 205 and Table 90 on page 206). 0x000 represents analog

ground, and 0x3FF represents the selected reference voltage minus one LSB.

Figure 96. Differential Measurement Range

ADC VIN 1024⋅

VREF

--------------------------=

ADC VPOS VNEG

–()512⋅

VREF

-----------------------------------------------------=

Output Code

0x1FF

0x000

VREF Differential Inp

Voltage (Volts)

0x3FF

0x200

VREF

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ATmega169/V

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ADMUX = 0xFB (ADC3 - ADC2, 1.1V reference, left adjusted result)

Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV.

ADCR = 512 * (300 - 500) / 1100 = -93 = 0x3A3.

ADCL will thus read 0xC0, and ADCH will read 0xD8. Writing zero to ADLAR right

adjusts the result: ADCL = 0xA3, ADCH = 0x03.

ADC Multiplexer Select ion

• Bit 7:6 – REFS1:0 : Reference Selection Bits

These bits select the voltage reference for the ADC, as shown in Table 89. If these bits

are changed during a conversion, the change will not go in effect until this conversion is

complete (ADIF in ADCSRA is set). The internal voltage reference option s may not be

used if an external reference voltage is being applied to the AREF pin.

• Bit 5 – ADLAR: ADC Left Adjust Result

The ADLAR bit af fects the presenta tion of the ADC conver sion result in the ADC Dat a

adjusted. Changing the ADLAR bit will affect the ADC Data Register immediately,

regardless of any ongoing conversions. For a complete description of this bit, see “The

ADC Data Register – ADCL and ADCH” on page 208.

Table 88. Correlation Between I nput Voltage and Output Codes

VADCn Read Code Corresponding Decimal Value

VADCm + VREF 0x1FF 511

VADCm + 511/512 VREF 0x1FF 511

VADCm + 510/512 VREF 0x1FE 510

... ... ...

VADCm + 1/512 VREF 0x001 1

VADCm 0x000 0

VADCm - 1/512 VREF 0x3FF -1

... ... ...

VADCm - 511/512 VREF 0x201 -511

VADCm - VREF 0x200 -512

Bit 76543210

REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 ADMUX

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Table 89. Voltage Refere nce Selections for ADC

REFS1 REFS0 Voltag e Reference Selection

0 0 AREF, Internal Vref turned off

0 1 AVCC with external capacito r at AREF pin

10Reserved

1 1 Internal 1.1V Voltage Reference with external capacitor at AREF pin

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• Bits 4:0 – MUX4:0: Analog Channel Selection Bits

The value of these bits selects which combination of analog inputs are connected to the

ADC. See Table 90 for details. If these bits are changed during a conversion, the

change will not go in effect until this conversion is complete (ADIF in ADCSRA is set).

Table 90. Input Channel Selections

MUX4..0 Single Ended Input Positive Differential Input Negativ e Differential Input

00000 ADC0

N/A

00001 ADC1

00010 ADC2

00011 ADC3

00100 ADC4

00101 ADC5

00110 ADC6

00111 ADC7

01000

01001

01010

01011

01100

01101

01110

01111

10000 ADC0 ADC1

10001 ADC1 ADC1

10010 N/A ADC2 ADC1

10011 ADC3 ADC1

10100 ADC4 ADC1

10101 ADC5 ADC1

10110 ADC6 ADC1

10111 ADC7 ADC1

11000 ADC0 ADC2

11001 ADC1 ADC2

11010 ADC2 ADC2

11011 ADC3 ADC2

11100 ADC4 ADC2

11101 ADC5 ADC2

11110 1.1V (VBG) N/A

11111 0V (GND)

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ADC Control and Status

• Bit 7 – ADEN: ADC Enable

Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turn-

ing the ADC off while a conversion is in progress, will terminate this conversion.

• Bit 6 – ADSC: ADC Start Conversion

In Single Conversion mode, write this bit to one to start each conversion. In Free Run-

ning mode, write this bit to one to start the first conversion. The first conversion after

ADSC has been written after the ADC has been enabled, or if ADSC is written at the

same time as the ADC is e nabled, will take 25 ADC clock cycle s instead of the normal

13. This first conversion performs initialization of the ADC.

ADSC will read as one as long as a conversion is in progress. When the conversio n is

complete, it returns to zero. Writing zero to this bit has no effect.

• Bit 5 – ADATE: ADC Auto Trigger Enable

When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start

a conversion on a positive edge of the selected trigger signal. The trigger source is

selected by setting the ADC Trigger Select bits, ADTS in ADCSRB.

• Bit 4 – ADIF: ADC Interrupt Flag

This bit is set when an ADC conversion completes and the Data Registers are updated.

The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in

SREG are set. ADIF is cleare d by har dwar e whe n executing the co rr espondin g int erru pt

handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag.

Beware that if doing a Read-Modify-Write on ADCSRA, a pending interrupt can be dis-

abled. This also applies if the SBI and CBI instructions are used.

• Bit 3 – ADIE: ADC Interrupt Enable

When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Com-

plete Interrupt is activated.

Bit 76543210

ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADCSRA

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits

These bits determine the division factor between the XTAL frequency and the input

clock to the ADC.

The ADC Data Register –

ADCL and ADCH

ADLAR = 0

ADLAR = 1

When an ADC convers ion is complete, the resu lt is found in these two r egisters.When

ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently,

if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to

read ADCH. Otherwise, ADCL must be read first, then ADCH.

The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is

read from the registers. If ADLAR is set, the result is left ad justed. If ADLAR is cleared

(default), the result is right adjusted.

• ADC9:0: ADC Conversion Result

These bits represent the result from the conversion, as detailed in “ADC Conversion

Result” on page 204.

Table 91. ADC Prescaler Selections

ADPS2 ADPS1 ADPS0 Division Factor

000 2

001 2

010 4

011 8

100 16

101 32

110 64

1 1 1 128

Bit 151413121110 9 8

– – – – – – ADC9 ADC8 ADCH

ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL

76543210

Read/WriteRRRRRRRR

RRRRRRRR

Initial Value00000000

00000000

Bit 151413121110 9 8

ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH

ADC1 ADC0 – –––––ADCL

76543210

Read/WriteRRRRRRRR

RRRRRRRR

Initial Value00000000

00000000

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ADC Control and Status

• Bit 7 – Res: Reserved Bit

This bit is reserved for future use. To ensu re compatibility with future devices, this bit

must be written to zero w hen ADCS RB is written.

• Bit 2:0 – ADTS2:0: ADC Auto Trigger Source

If ADATE in ADCSRA is written to one, the value of these bits selects which source will

trigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no

effect. A conversion will be triggered by the rising edge of the selected Interrupt Flag.

Note that switching from a trigger source that is cleared to a trigger source that is set,

will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will

start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trig-

ger event, even if the ADC Interrupt Flag is set.

Digital Input Disable Register

0 – DIDR0

• Bit 7..0 – ADC7D..ADC0D: ADC7..0 Digital Input Disable

When this bit is written logic one, the digita l input buffer on the corre sponding ADC pin is

disabled. The corresponding PIN Register bit will always read as zero when this bit is

set. When an analog signal is applied to the ADC7..0 pin and the digital input from this

pin is not needed, this bit should be written logic one to reduce power consumption in

the digital input buffer.

Bit 76543210

–ACME – – – ADTS2 ADTS1 ADTS0 ADCSRB

Read/Write R R/W R R R R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Table 92. ADC Auto Trigger Source Selections

ADTS2 ADTS1 ADTS0 Trigger Source

0 0 0 Free Running mode

0 0 1 Analog Comparator

0 1 0 External Interrupt Request 0

0 1 1 Timer/Counter0 Compare Match

1 0 0 Timer/Counter0 Overflow

1 0 1 Timer/Counter Compare Match B

1 1 0 Timer/Counter1 Overflow

1 1 1 Timer/Counter1 Capture Event

Bit 76543210

ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D DIDR0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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LCD Controller The LCD Controller/driver is intended for monochrome passive liquid crystal display

(LCD) with up to four common terminals and up to 25 segment terminals.

Features •Display Capacity of 25 Segments and Four Common Terminals

•Support Static, 1/2, 1/3 and 1/4 Duty

•Support Static, 1/2, 1/3 Bias

•On-chip LCD Power Supply, only One External Capacitor needed

•Display Possible in Power-save Mode for Low Power Consumption

•Software Selectable Low Power Waveform Capability

•Flexible Selection of Frame Frequency

•Software Selection between System Clock or an External Asynchronous Clock Source

•Equal Source and Sink Capability to maximize LCD Life Time

•LCD Interrupt Can be Used for Display Data Update or Wake-up from Sleep Mode

•Segment and Common Pins not Needed for Driving the Display Can be Used as Ordinary

I/O Pins

•Latching of Disp lay Data gives Full Freedom in Reg ister Update

Overview A simplified block diagram of the LCD Controller/Driver is shown in Figure 97. For the

actual placement of I/O pins, see “Pinout ATmega169” on page 2.

An LCD consists of several segments (pixels or complete symbols) which can be visible

or non visible. A segment has two electrodes with liquid crystal between them. When a

voltage above a threshold voltage is app lied across the liquid crystal, the segment

becomes visible.

The voltage must alternate to avoid an electrophoresis effect in the liquid crystal, which

degrades the display. Hence the waveform across a segment must not have a DC-

component.

The PRLCD bit in “Power Reduction Regist er - PRR” on page 34 must be written to zero

to enable the LCD mo dule.

Definitions Several terms are used when describing LCD. The definitions in Table 93 are used

throughout th is doc um e nt .

Table 93. Definitions

LCD A passive display panel with terminals leading directly to a segment

Segment The least viewing element (pixel) which can be on or off

Common Denotes how many segments are connected to a segment terminal

Duty 1/(Number of common terminals on a actual LCD display)

Bias 1/(Number of voltage levels used driving a LCD display -1)

Frame Rate Number of times the LCD segments is energized per second.

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Figure 97. LCD Module Block Diagram

LCD Clock Sources The LCD Controller can be cloc ke d by an int er nal synch ronou s or an e xter nal asynchro-

nous cloc k source . The cloc k source clkLCD is by default equal to the system clock, clkI/O.

When the LCDCS bit in the LCDCRB Register is written to logic one, the clock source is

taken from the TOSC1 pin.

The clock source must be stable to obtain accu ra te LC D tim ing an d he nc e m inim ize DC

voltage offset across LCD segment s.

LCD Prescaler The prescaler consist of a 12-bit ripple counter and a 1- to 8-clock divider. The

LCDPS2:0 bits selects clkLCD divided by 16, 64, 128, 256, 512, 1024, 2048, or 409 6.

If a finer resolution rate is required, the LC DCD2:0 bits can be used to divide the clock

further by 1 to 8.

Output from the clock divider clkLCD_PS is used as clock source for the LCD timing.

LCD Memory The display memory is availab le th ro ugh I/O Regist er s grou pe d fo r each common termi-

nal. When a bit in the display memory is written to one, the corresponding segment is

energized (on), and non-energized when a bit in the display memory is written to ze ro.

To energize a segment, an absolute voltage above a certain threshold must be applied.

This is done by letting the output voltage on corresponding COM pin and SEG pin have

opposite phase. For display with more than one common, one (1/2 bias) or two (1/3

bias) additional voltage levels must be applied. Otherwise, non-energized segments on

COM0 would be energized for all non-selected common.

Clock

Multiplexer

12-bit Prescaler

Divide by 1 to 8

LCD

Timing

LCDCRB

LCDFRR

clk

i/o

TOSC

LCDCRA

clk

LCD

/4096

clk

LCD

/2048

clk

LCD

/128

clk

LCD

/1024

clk

LCD

/512

clk

LCD

/256

clk

LCD

/64

clk

LCD

/16

Analog

Switch

Array

lcdcs

lcdcd2:0

lcdps2:0

clk

LCD

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

COM0

COM1

COM2

COM3

LCD Buffer/

Driver

LCD

LCDDR 18 -15

LCDDR 13 -10

LCDDR 8 - 5

LCDDR 3 - 0

LATCH

array LCD Ouput

Decoder

LCDCCR lcdcc3:0 Contrast Controller/

Power Supply

clk

LCD_PS

LCD

CAP

25 x

4:1

MUX

LCD_voltage_ok

2/3 V

LCD

1/2 V

LCD

1/3 V

LCD

Display

Configuration

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Addressing COM0 starts a frame by driving opposite phase with large amplitude out on

COM0 compared to none addressed COM lines. Non-energized segments are in phase

with the addressed COM0, and energized segments have opposite phase and large

amplitude. For waveform figures refer to “Mode of Operation” on page 212. Latched

data from LCDDR4 - LCDDR0 is multiplexed into the decoder. The decoder is controlled

from the LCD timing a nd sets up signals controlling the analog switches to produce an

output waveform. Next, COM1 is addressed, and latched data from LCDDR9 - LCDDR5

is input to decoder. Addressing continuous until all COM lines are addressed according

to number of common (duty). The display data are latched before a new frame start.

LCD Contrast

Controller/Power Supply The peak value (VLCD) on the output waveform determines the LCD Contrast. VLCD is

controlled by softwar e fr om 2.6V to 3.3 5V ind epend ent of V CC. An internal signal inhibits

output to the LCD until VLCD has reached its target value.

LCDCAP An external capacitor (typical > 470 nF) must be connected to the LCDCAP pin as

shown in Figure 98. This capacitor acts as a reservoir for LCD power (VLCD). A large

capacitance reduces ripple on VLCD but increases the time until VLCD reaches its target

value.

Figure 98. LCDCAP Connection

LCD Buffer Driver Intermediate voltage leve ls are generated from buffers/drive rs. The buffers are active

the amount of time specified by LCDDC[2:0] in “LCD Contrast Control Register – LCD-

CCR” on page 223. Then LCD output pins are tri-stated and buffers are switched off.

Shortening the drive time will reduce power consumption, but displays with high internal

resistance or capacitance may need longer drive time to achieve sufficient contrast.

Mode of Operation

Static Duty and Bias If all segments on a LCD have one electrode common, then each segment must have a

unique terminal.

This kind of display is driven with the waveform shown in Figure 99. SEG0 - COM0 is

the voltage across a segment that is on, and SEG1 - COM0 is t he vo ltage across a seg-

ment that is off.

321

LCDCAP

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Figure 99. Driving a LCD with One Common Terminal

1/2 Duty and 1/ 2 Bia s For LCD with two common terminals ( 1/2 du ty) a more comp lex wavef orm must be used

to individually control segments. Although 1/3 bias can be selected 1/2 bias is most

common for these displays. Waveform is shown in Figure 100. SEG0 - COM0 is the volt-

age across a segment that is on, and SEG0 - COM1 is the voltag e across a segment

that is off.

Figure 100. Driving a LCD with Two Common Term in als

VLCD

GND

VLCD

GND

VLCD

GND

-VLCD

SEG0

COM0

SEG0 - COM0

Frame Frame

VLCD

GND

VLCD

GND

SEG1

COM0

SEG1 - COM0

Frame Frame

VLCD

GND

VLCD

1/2VLCD

GND

VLCD

1/2VLCD

GND

-1/2VLCD

-VLCD

SEG0

COM0

SEG0 - COM0

Frame Frame

VLCD

GND

VLCD

1/2VLCD

GND

VLCD

1/2VLCD

GND

-1/2VLCD

-VLCD

SEG0

COM1

SEG0 - COM1

Frame Frame

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1/3 Duty and 1/ 3 Bia s 1/3 bia s is usually recommended for LCD with three common terminals (1/3 d uty).

Waveform is shown in Figure 1 01. SEG0 - COM0 is the voltage a cross a segment that is

on and SEG0-COM1 is the voltage across a segmen t that is off.

Figure 101. Driving a LCD with Three Common Terminals

1/4 Duty and 1/ 3 Bia s 1/3 bias is optimal for LCD displays with four common terminals (1/4 duty). Waveform is

shown in Figure 102. SEG0 - COM0 is the voltage across a segment that is on and

SEG0 - COM1 is the voltag e acro ss a segment that is off.

Figure 102. Driving a LCD with Four Commo n Terminals

VLCD

2/3VLCD

1/3VLCD

GND

VLCD

2/3VLCD

1/3VLCD

GND

VLCD

2/3VLCD

1/3VLCD

GND

-1/3VLCD

-2/3VLCD

-VLCD

SEG0

COM0

SEG0 - COM0

Frame Frame

VLCD

2/3VLCD

1/3VLCD

GND

VLCD

2/3VLCD

1/3VLCD

GND

VLCD

2/3VLCD

1/3VLCD

GND

-1/3VLCD

-2/3VLCD

-VLCD

SEG0

COM1

SEG0 - COM1

Frame Frame

LCD

GND

LCD

GND

LCD

GND

LCD

-V

LCD

SEG0

COM0

SEG0 - COM0

Frame Frame

LCD

GND

LCD

GND

LCD

GND

LCD

-V

LCD

SEG0

COM1

SEG0 - COM1

Frame Frame

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Low Power Waveform To reduce toggle activity and hence power consumption a low power waveform can be

selected by writing LCDAB to one. Low power waveform requires two subsequent

frames with the same display data to obtain zero DC voltage. Consequently data latch-

ing and Interrupt Flag is only set every second frame. Default and low power waveform

is shown in Figure 103 for 1/3 duty and 1/3 bias. For othe r selections of duty and bias,

the effect is similar.

Figure 103. Default and Low Power Waveform

Operation in Sleep Mode When synchronous LCD clock is selected (LCDCS = 0) the LCD display will operate in

Idle mode and Power-save mode with any clock source.

An asynchronous clock from TOSC1 can be selected as LCD clock by writing the

LCDCS bit to one when Calibrated Internal RC Oscillator is selected as system clock

source. The LCD will then operate in Idle mode, ADC Noise Reduction mode and

Power-save mod e.

When EXCLK in ASSR Register is written to one, and asynchronous clock is selected,

the external clock input buffer is enabled and an external clock can be input on Timer

Oscillator 1 (TOSC1) pin instead of a 32 kHz crystal. See “Asynchronous operation of

the Timer/Counter” on page 138 for further details.

Before entering Power-down mode, Standby mode or ADC Noise Reduction mode with

synchronous LCD clock selected, the user have to disable the LCD. Refer to “Disabling

the LCD” on page 21 8.

Display Blanking When LCDBL is written to one, the LCD is blanked after completing the current frame.

All segments and common pins are connected to GND, discharging the LCD. Display

memory is preserved. Display blanking should be used before disabling the LCD to

avoid DC voltage across segments, and a slowly fading image.

Port Mask Fo r LCD with less than 25 segment termin als, it is possible to mask some of the unused

pins and use them as ordi nary port pins instead. Refer to Table 95 for details. Unu sed

common pins are automatically configured as port pins.

VLCD

2/3VLCD

1/3VLCD

GND

VLCD

2/3VLCD

1/3VLCD

GND

VLCD

2/3VLCD

1/3VLCD

GND

-1/3VLCD

-2/3VLCD

-VLCD

SEG0

COM0

SEG0 - COM0

Frame Frame

VLCD

2/3VLCD

1/3VLCD

GND

VLCD

2/3VLCD

1/3VLCD

GND

VLCD

2/3VLCD

1/3VLCD

GND

-1/3VLCD

-2/3VLCD

-VLCD

SEG0

COM0

SEG0 - COM

Frame Frame

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LCD Usage The following se ctio n describes how to use the LCD .

LCD Initialization Prior to enabling the LCD some initialization must be preformed. The initialization pro-

cess normally consists of setting the frame rate, duty, bias and port mask. LCD contrast

is set initially, but can also be adjusted during operation.

Consider the following LCD as an example:

Figure 104. LCD usage example.

Display: TN Positive, Reflective

Number of common ter minals: 3

Number of segment terminals: 21

Bias system: 1/3 Bias

Drive system: 1/3 Duty

Operating voltage: 3.0 ± 0.3 V

2c2e

COM3

COM0 COM1 COM2

SEG0

SEG1

SEG2

1b,1c

COM2

SEG0

SEG1

SEG2

ATmega169

COM1

COM0

Connection table

LCD

51 50 49

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Note: 1. See “About Code Examples” on page 6.

Before a re-initialization is done, the LCD controller/driver should be disabled

Updating the LCD Display memory (LCDDR0, LCDDR1, ..), LCD Blanking (LCDBL), Low power w aveform

(LCDAB) and contrast control (LCDCCR) are latched prior to every new frame. There

are no restr ictions on writing these LCD Register loca tions, but an LCD d ata update may

be split between two frames if data are latched while an update is in progress. To avoid

this, an interrupt routine can be used to update Display memory, LCD Blanking, Low

power waveform , an d co ntrast control, just after dat a ar e lat ch ed .

Assembly Code Example(1)

LCD_Init:

; Use 32 kHz crystal oscillator

; 1/3 Bias and 1/3 duty, SEG21:SEG24 is used as port pins

ldi r16, (1<<LCDCS) | (1<<LCDMUX1)| (1<<LCDPM2)

sts LCDCRB, r16

; Using 16 as prescaler selection and 7 as LCD Clock Divide

; gives a frame rate of 49 Hz

ldi r16, (1<<LCDCD2) | (1<<LCDCD1)

sts LCDFRR, r16

; Set segment drive time to 125 µs and output voltage to 3.3 V

ldi r16, (1<<LCDDC1) | (1<<LCDCC3) | (1<<LCDCC2) | (1<<LCDCC1)

sts LCDCCR, r16

; Enable LCD, default waveform and no interrupt enabled

ldi r16, (1<<LCDEN)

sts LCDCRA, r16

ret

C Code Example(1)

Void LCD_Init(void);

{

/* Use 32 kHz crystal oscillator */

/* 1/3 Bias and 1/3 duty, SEG21:SEG24 is used as port pins */

LCDCRB = (1<<LCDCS) | (1<<LCDMUX1)| (1<<LCDPM2);

/* Using 16 as prescaler selection and 7 as LCD Clock Divide */

/* gives a frame rate of 49 Hz */

LCDFRR = (1<<LCDCD2) | (1<<LCDCD1);

/* Set segment drive time to 125 µs and output voltage to 3.3 V*/

LCDCCR = (1<<LCDDC1) | (1<<LCDCC3) | (1<<LCDCC2) | (1<<LCDCC1);

/* Enable LCD, default waveform and no interrupt enabled */

LCDCRA = (1<<LCDEN);

}

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In the example below we assume SEG10 and COM1 and SEG4 in COM 0 are the only

segments changed from frame to frame. Data are stored in r20 and r21 for simplicity

Note: 1. See “About Code Examples” on page 6.

Disabling the LCD In some application it may be necessary to disable the LCD. This is the case if the MCU

enters Power-down mode where no clock source is present.

The LCD should be completely discharge d befor e being disabled. No DC voltage sh ould

be left across any seg ment. The best way to a chieve this is to use the LCD Blanking fea-

ture that drives all segment pins and common pins to GND.

When the LCD is disabled, port function is activated again. Therefore, the user must

check that port pins connected to a LCD terminal are either tri-state or output low (sink).

Assembly Code Example(1)

LCD_update:

; LCD Blanking and Low power waveform are unchanged.

; Update Display memory.

sts LCDDR0, r20

sts LCDDR6, r21

ret

C Code Example(1)

Void LCD_update(unsigned char data1, data2);

{

/* LCD Blanking and Low power waveform are unchanged. */

/* Update Display memory. */

LCDDR0 = data1;

LCDDR6 = data2;

}

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ATmega169/V

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Note: 1. See “About Code Examples” on page 6.

LCD Control and Status

• Bit 7 – LCDEN: LCD Enable

Writing this bit to one en able s the LCD Cont roller/Driver. By writing it to zero, the LCD is

turned off immediately. Turning the LCD Controller/Driver off while driving a display,

Assembly Code Example(1)

LCD_disable:

; Wait until a new frame is started.

Wait_1:

lds r16, LCDCRA

sbrs r16, LCDIF

rjmp Wait_1

; Set LCD Blanking and clear interrupt flag

; by writing a logical one to the flag.

ldi r16, (1<<LCDEN)|(1<<LCDIF)|(1<<LCDBL)

sts LCDCRA, r16

; Wait until LCD Blanking is effective.

Wait_2:

lds r16, LCDCRA

sbrs r16, LCDIF

rjmp Wait_2

; Disable LCD.

ldi r16, (0<<LCDEN)

sts LCDCRA, r16

ret

C Code Example(1)

Void LCD_disable(void);

{

/* Wait until a new frame is started. */

while ( !(LCDCRA & (1<<LCDIF)) )

;

/* Set LCD Blanking and clear interrupt flag */

/* by writing a logical one to the flag. */

LCDCRA = (1<<LCDEN)|(1<<LCDIF)|(1<<LCDBL);

/* Wait until LCD Blanking is effective. */

while ( !(LCDCRA & (1<<LCDIF)) )

;

/* Disable LCD */

LCDCRA = (0<<LCDEN);

}

Bit 76543210

LCDEN LCDAB – LCDIF LCDIE – – LCDBL LCDCRA

Read/Write R/W R/W R R/W R/W R R R/W

Initial Value00000000

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ATmega169/V

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enables ordinary port function, and DC voltage can be applied to the display if ports are

configured as output. It is r ecommended to drive output to ground if the LCD Control-

ler/Driver is disabled to discharge the display.

• Bit 6 – LCDAB: LCD Low Power Waveform

When LCDAB is written logic zero, the default waveform is output on the LCD pins.

When LCDAB is written logic one, the Low Power Waveform is output on the LCD pins.

If this bit is modified during display operation the change takes place at the beginning of

a new frame.

• Bit 5 – Res: Reserved Bit

This bit is reserved bit in the ATmega169 and will always read as zero.

• Bit 4 – LCDIF: LCD Interrupt Flag

This bit is set by hardware at the begin ning of a new frame, at the same time as the dis-

play data is updated. The LCD Start of Frame Interrupt is executed if the LCDIE bit and

the I-bit in SREG are set. LCDIF is cleared by hardware when executing the corre-

sponding Interrupt Handling Vector. Alternatively, writing a logical one to the flag clears

LCDIF. Beware that if doing a Read-Modify-Write on LCDCRA, a pending interrupt can

be disabled. If Low Power Wavefo rm is selected the Interrup t Flag is set every secon d

frame.

• Bit 3 – LCDIE: LCD Interrupt Enable

When this bit is wr it te n to on e a nd the I - bit in SREG is set , th e L CD Sta rt of F ra me In ter-

rupt is enabled.

• Bits 2:1 – Res: Reserved Bits

These bits are reserved bits in the ATmega169 and will always read as zero.

• Bit 0 – LCDBL: LCD Blanking

When this bit is written to one, the display will be blanked after completion of a frame. All

segment and common pins will be driven to ground.

LCD Control and Status

• Bit 7 – LCDCS: LCD Clock Select

When this bit is written to zero, the system clock is used. When this bit is written to one,

the external asynchronous clock source is used. The asynchronous clock source is

either Timer/Counter Oscillator or external clock, depending on EXCLK in ASSR. See

“Asynchronous operation of the Timer/Counte r” on page 138 for further details.

• Bit 6 – LCD2B: LCD 1/2 Bias Select

When this bit is written to zero, 1/3 bias is u sed. When this bit is written to one, ½ bia s is

used. Refer to the LCD Manufacture for recommended bias selection.

• Bit 5:4 – LCDMUX1:0: LCD Mux Select

The LCDMUX1:0 bits determine th e duty cycle. Common p ins that are no t used are ordi-

nary port pins. The different duty selections are shown in Table 94.

Bit 7 6 5 4 3 2 1 0

LCDCS LCD2B LCDMUX1 LCDMUX0 – LCDPM2 LCDPM1 LCDPM0 LCDCRB

Read/Write R/W R/W R/W R/W R R/W R/W R/W

Initial Val-

ue 000 0 0000

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Note: 1. 1/2 bias when LCD2B is written to one and 1/3 otherwise.

• Bit3 – Res: Reserved Bit

This bit is reserved bit in the ATmega169 and will always read as zero.

• Bits 2:0 – LCDPM2:0: LCD Port Mask

The LCDPM2:0 bits determine the nu mber of port pins to be used as segment drive rs.

The different selections are shown in Table 95. Unused pins can be used as ordinary

port pins.

LCD Frame Rate Register –

LCDFRR

• Bit 7 – Res: Reserved Bit

This bit is reserved bit in the ATmega169 and will always read as zero.

• Bits 6:4 – LCDPS2:0: LCD Prescaler Sel ect

The LCDPS2:0 bits selects tap point from a prescaler. The prescaled output can be fur-

ther divided by setting the clock divide bits (LCDCD2:0). The different selections are

shown in Table 96. Together they determine the prescaled LCD clock (clkLCD_PS), which

is clocking the LCD module.

Table 94. LCD Duty Select

LCDMUX1 LCDMUX0 Duty Bias COM Pin I/O Port Pin

0 0 Static Static COM0 COM1:3

0 1 1/2 1/2 or 1/3(1) COM0:1 COM2:3

101/31/2

or 1/3(1) COM0:2 COM3

111/41/2

or 1/3(1) COM0:3 None

Table 95. LCD Port Mask

LCDPM2 LCDPM1 LCDPM0 I/O Port in Use as

Segment Driver Maximum Number of

Segments

0 0 0 SEG0:12 13

0 0 1 SEG0:14 15

0 1 0 SEG0:16 17

0 1 1 SEG0:18 19

1 0 0 SEG0:20 21

1 0 1 SEG0:22 23

1 1 0 SEG0:23 24

1 1 1 SEG0:24 25

Bit 76543210

– LCDPS2 LCDPS1 LCDPS0 – LCDCD2 LCDCD1 LCDCD0 LCDFRR

Read/Write R R/W R/W R/W R R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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• Bit 3 – Res: Reserved Bit

This bit is reserved bit in the ATmega169 and will always read as zero.

• Bits 2:0 – LCDCD2:0: LCD Clock Divide 2, 1, and 0

The LCDCD2:0 bits determine division ratio in the clock divider. The various selections

are shown in Table 97. This Clock Divider gives extra flexibility in frame rate selection.

The frame frequency can be calculated by the following equation:

Where:

N = prescaler divider (16, 64, 128, 256, 512, 1024, 2048, or 4096).

K = 8 for duty = 1/4, 1/2, and static.

K = 6 for duty = 1/3.

D = Division factor (see Table 97).

Table 96. LCD Prescaler Select

LCDPS2 LCDPS1 LCDPS0

Output from

Prescaler

clkLCD/N

Applied Prescaled LCD Clock

Frequency when LCDCD2:0 = 0,

Duty = 1/4, and Frame Rate = 64 Hz

000clk

LCD/16 8.1 kHz

001clk

LCD/64 33 kHz

010clk

LCD/128 66 kHz

011clk

LCD/256 130 kHz

100clk

LCD/512 260 kHz

101clk

LCD/1024 520 kHz

110clk

LCD/2048 1 MHz

111clk

LCD/4096 2 MHz

Table 97. LCD Clock Divide

LCDCD2 LCDCD1 LCDCD0

Output from

Prescaler divided by

(D):

clkLCD = 32.768 kHz, N = 16,

and Duty = 1/4, gives a frame

rate of:

0 0 0 1 256 Hz

0 0 1 2 128 Hz

0 1 0 3 85.3 Hz

0 1 1 4 64 Hz

1 0 0 5 51.2 Hz

1 0 1 6 42.7 Hz

1 1 0 7 36.6 Hz

1 1 1 8 32 Hz

fframe

fclkLCD

KND⋅⋅()

--------------------------=

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This is a very flexible scheme, and users are encouraged to calculate their own table to

investigate the possible frame rates from the formula abo ve. Note when using 1/3 duty

the frame r ate is increase d with 33% when Fr ame Rate Registe r is constant . Example of

frame rate ca lculation is shown in Table 98.

LCD Contrast Control

• Bits 7:5 – LCDDC2:0: LDC Display Configuration

The LCDDC2:0 bits determine the amount of time the LCD drivers are turned on for

each voltage transitio n on segment and common pins. A short drive time will lead to

lower power consum ption, but displays with high internal resistance may need longer

drive time to achieve satisfactory contrast. Note that the drive time will never be longer

than one half prescaled LCD clock period, eve n if the selected drive time is longer.

When using static bias or blanking, drive time will always be one half prescaled LCD

clock period.

Note: These bits are not available in ATmega169 revisions A to D

• Bit 4 – Res: Reserved Bit

This bit is reserved in the ATmega169 and will always read as zero.

• Bits 3:0 – LCDCC3:0: LCD Cont rast Control

Table 98. Example of frame rate calculation

clkLCD duty K N LCDCD2:0 D Frame Rate

4 MHz 1/4 8 2048 0 11 4 4000000/(8*2048*4) = 61 Hz

4 MHz 1/3 6 2048 0 11 4 4000000/(6*2048*4) = 81 Hz

32.768 kHz Static 8 16 000 1 3 2768/(8*16*1) = 256 Hz

32.768 kHz 1/2 8 16 100 5 32768/(8*16*5) = 51 Hz

Bit 76543210

LCDDC2 LCDDC1 LCDDC0 – LCDCC3 LCDCC2 LCDCC1 LCDCC0 LCDCCR

Read/Write R/W R/W R/W R R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Table 99. LCD Display Configuration

LCDDC2 LCDDC1 LCDDC0 Nominal drive time

0 0 0 300 µs

00170 µs

0 1 0 150 µs

0 1 1 450 µs

1 0 0 575 µs

1 0 1 850 µs

1 1 0 1150 µs

1 1 1 50% of clkLCD_PS

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The LCDCC3:0 bits determine the maximum voltage VLCD on segment and common

pins. The different selections are shown in Table 100. New values take effect every

beginning of a new fra m e.

Table 100. LCD Contrast Control

LCDCC3 LCDCC2 LCDCC1 LCDCC0 Maximum Voltage VLCD

0 0 0 0 2.60 V

0 0 0 1 2.65 V

0 0 1 0 2.70 V

0 0 1 1 2.75 V

0 1 0 0 2.80 V

0 1 0 1 2.85 V

0 1 1 0 2.90 V

0 1 1 1 2.95 V

1 0 0 0 3.00 V

1 0 0 1 3.05 V

1 0 1 0 3.10 V

1 0 1 1 3.15 V

1 1 0 0 3.20 V

1 1 0 1 3.25 V

1 1 1 0 3.30 V

1 1 1 1 3.35 V

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LCD Memory Mapping Write a LCD memory bit to one and the corresponding segment will be energized (visi-

ble). Unused LCD Memory bits for the actual display can be used freely as storage.

Bit 76543210

––––––––LCDDR19

COM3 –––––––SEG324LCDDR18

COM3 SEG323 SEG322 SEG321 SEG320 SEG319 SEG318 SEG317 SEG316 LCDDR17

COM3 SEG315 SEG314 SEG313 SEG312 SEG311 SEG310 SEG309 SEG308 LCDDR16

COM3 SEG307 SEG306 SEG305 SEG304 SEG303 SEG302 SEG301 SEG300 LCDDR15

––––––––LCDDR14

COM2 –––––––SEG224LCDDR13

COM2 SEG223 SEG222 SEG221 SEG220 SEG219 SEG218 SEG217 SEG216 LCDDR12

COM2 SEG215 SEG214 SEG213 SEG212 SEG211 SEG210 SEG209 SEG208 LCDDR11

COM2 SEG207 SEG206 SEG205 SEG204 SEG203 SEG202 SEG201 SEG200 LCDDR10

––––––––LCDDR9

COM1 –––––––SEG124LCDDR8

COM1 SEG123 SEG122 SEG121 SEG120 SEG119 SEG118 SEG117 SEG116 LCDDR7

COM1 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 LCDDR6

COM1 SEG107 SEG106 SEG105 SEG104 SEG103 SEG102 SEG101 SEG100 LCDDR5

––––––––LCDDR4

COM0 –––––––SEG024LCDDR3

COM0 SEG023 SEG022 SEG021 SEG020 SEG019 SEG018 SEG017 SEG016 LCDDR2

COM0 SEG015 SEG014 SEG013 SEG012 SEG011 SEG010 SEG009 SEG008 LCDDR1

COM0 SEG007 SEG006 SEG005 SEG004 SEG003 SEG002 SEG001 SEG000 LCDDR0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 00000000

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JTAG Interface and

On-chip Debug

System

Features •JTAG (IEEE std. 1149.1 Compliant) Interface

•Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard

•Debugger Access to:

– All Internal Peripheral Units

– Internal and External RAM

– The Internal Register File

–Program Counter

– EEPROM and Flash Memories

•Extensive On-chip Debug Support for Break Conditions, Including

– AVR Break Instruction

– Break on Change of Program Memory Flow

– Single Step Break

– Program Memory Break Points on Single Address or Address Range

– Data Memory Break Points on Single Address or Address Range

•Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

•On-chip Debugging Supported by AVR Studio®

Overview The AVR IEEE std. 1149.1 compliant JTAG interface can be used for

• Testing PCBs by using the JTAG Boundary-scan capability

• Programming the non-volatile memories, Fuses an d Lock bits

• On-chip debugging

A brief description is given in the following sections. Detailed descriptions for Program-

ming via the JTAG interface, an d using the Boundary-scan Chain can be found in the

sections “Programming via the JTAG Interface” on page 285 and “IEEE 1149.1 (JTAG)

Boundary-scan” on page 232, respectively. The On-chip Debug support is considered

being private JTAG instructions, and distributed within ATMEL and to selected third

party vendors only.

Figure 105 shows a block diagram of the JTAG interface and the On-chip Debug sys-

tem. The TAP Controller is a state machine controlled by t he TCK and TMS signals. The

TAP Controller selects either the JTAG Instruction Register or one of several Data Reg-

isters as the scan chain (Shift Register) between the TDI – input and TDO – output. The

Instruction Register holds JTAG instructions controlling the behavior of a Data Register.

The ID-Registe r, Bypass Register , and t he Boundary- scan Chain are the Dat a Register s

used for board-level testing. The JTAG Programming Interface (actually consisting of

several physical and virt ual Data Re gisters) is used for serial prog ramming via th e JTAG

interface. The Internal Scan Chain and Break Point Scan Ch ain are used for On-chip

debugging only.

Test Access Port – TAP The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology,

these pins const itu te the Test Access Port – TAP. These pins are:

• TMS: Test mode select. This pin is used for na vigating through the TAP-controller

state machin e.

• TCK: Test Clock. JTAG operation is synchronous to TCK.

• TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data

• TDO: Test Data Out. Serial output data from Instruction Register or Data Register.

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The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT –

which is not provided.

When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins

and the TAP controller is in reset. When programmed and the JTD bit in MCUCSR is

cleared, the TAP pins are internally pulled high and the JTAG is enabled for Boundary-

scan and program ming. The device is shipped with this fuse programmed.

For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is

monitored by the debugger to be able to detect external reset sources. Th e debugger

can also pull the RESET pin low to reset the whole system, ass uming only open collec-

tors on the reset line are used in the application.

Figure 105. Block Diagram

TAP

CONTROLLER

FLASH

MEMORY

AVR CPU

DIGITAL

PERIPHERAL

UNITS

JTAG / AVR CORE

COMMUNICATION

INTERFACE

BREAKPOINT

UNIT FLOW CONTROL

UNIT

OCD STATUS

AND CONTROL

INTERNAL

SCAN

CHAIN

INSTRUCTION

BYPASS

JTAG PROGRAMMING

INTERFACE

Instruction

Address

Data

BREAKPOINT

SCAN CHAIN

ADDRESS

DECODER

ANALOG

PERIPHERIAL

UNITS

I/O PORT 0

I/O PORT n

BOUNDARY SCAN CHAIN

Analog inputs

Control & Clock line

DEVICE BOUNDARY

228

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Figure 106. TAP Controller State Diagram

TAP Controller The TAP controller is a 16-state finite state machine that controls the operation of the

Boundary-scan circuitry, JTAG pr ogramming circuitry, or On-chip Debug system. Th e

state transitions depicted in Figure 106 depend on the signal present on TMS (shown

adjacent to each state transition) at the time of the rising edge at T CK. The initial state

after a Power-on Reset is Test-Logic-Reset.

As a definition in this docum e nt , the LSB is shifte d in an d out firs t for all Shift Re gist er s.

Assuming Run-Test /Id le is th e p rese nt st at e, a typical scenario for using the JT AG in ter-

face is:

• At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter

the Shift Instruction Register – Shift-IR state. While in this state, shift the four bits of

the JTAG instructions into the JTAG Instruction Register from the TDI input at the

rising edge of TCK. The TMS input must be held low during input of t he 3 LSBs in

order to remain in the Shift-IR state. The MSB of the instruction is shifted in when

this state is left by setting TMS high. While the instruction is shifted in from the TDI

pin, the captured IR-state 0x01 is shifted out on the TDO pin. The JTAG Instruction

selects a particula r Data Register as path between TDI and TDO and controls the

circuitry surrounding the selected Data Regist er.

• Apply the TMS sequence 1, 1, 0 t o re-enter the Run-Test/Idle state. The instruction

is latched onto the parallel output from the Shift Register path in the Update-IR

Test-Logic-Reset

Run-Test/Idle

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

Select-IR Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

Select-DR Scan

Capture-DR

011 1

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state . The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the

state machin e.

• At the TMS input , app ly the se quence 1 , 0, 0 at t he rising edges of TCK to ent er the

Shift Data Register – Shift-DR state. While in this state, upload the selected Data

from the TDI input at the rising edge of TCK. In order to remain in the Shift-DR state,

the TMS input must be held low during input of all bits except the MSB. The MSB of

the data is shifted in when this state is left by setting TMS hi gh. While the Data

captured in the Capture-DR state is shifted out on the TDO pi n.

• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected

Data Register has a latched parallel-output, the latching takes place in the Update-

DR state. The Exit-DR, P ause -DR, and Exit2- DR states are only used for navigating

the state machine.

As shown in the state diagram, the Run-Test/Idle state need not be entered between

selecting JTAG instruction and using Data Registers, and some JTAG instructions may

select certain functions to be performed in the Run-Test/Idle, making it unsuitable as an

Idle state.

Note: Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can

always be entered by holding TMS high for five TCK clock periods.

For detailed information on the JTAG specification, refer to the literature listed in “Bibli-

ography” on page 231.

Using the Boundary-

scan Chain A complete description of the Boundary-scan c apabilities are giv en in the section “IEEE

1149.1 (JTAG) Boundary-scan” on page 232.

Using the On-chip Debug

System As shown in Figure 105, the hardwar e support f or On-chip Debu gging consists mainly of

• A scan chain on the int er face between the internal AV R CPU an d the int ernal

peripheral units.

• Break Point unit.

• Communication interface between the CPU and JTAG system.

All read or modify/write operations needed for implementing the Debugger are done by

applying AVR instructions via the internal AVR CPU Scan Chain. The CPU sends the

result to an I/O memory mapped location which is part of the communication interface

between the CPU and the JTAG system.

The Break Point Unit implements Break on Change of Program Flow, Single Step

Break, two Program Mem ory Break Points, and two combin ed Break Points. Together,

the four Break Points can be configured as either:

• 4 single Program Memory Break Points.

• 3 Single Program Memory Break Point + 1 single Data Memory Break Point.

• 2 single Progr am Memory Break Points + 2 single Data Memory Break Points.

• 2 single Progr am Memory Break P oints + 1 Pro gram Memory Break Point with mask

(“range Break Point”).

• 2 single Program Memory Break Points + 1 Data Memory Break Point with mask

(“range Break Point”).

A debugger, like the AVR Studio, may however use one or more of these resources for

its internal purpose, leaving less flexibility to the end-user.

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A list of the On-chip Debug specific JTAG instructions is given in “On-chip Debug Spe-

cific JTAG Instructions” on page 230.

The JTAGEN Fuse must be p ro gramme d to ena ble the JTAG Test Access Po rt . In ad di-

tion, the OCDEN Fuse must be programmed and no Lock bits must be set for the On-

chip debug system to work. As a securit y f eature, the On-chip debug system is disabled

when either of the LB1 or LB2 Lock bits are set. Otherwise, the On-chip debug system

would have provided a back-door into a secured device.

The AVR Studio enables the user to fully control execution of programs on an AVR

device with On-chip Debug capability, AVR In-Circuit Emulator, or the built-in AVR

Instruction Set Simulator. AVR Studio® supports source level execu tion of Assembly

programs assembled with Atmel Corporation’s AVR Assembler and C programs com-

piled with third party vendors’ compilers.

AVR Studio runs under Microsoft® Windows® 95/98/2000, Windows NT® and Windows

XP®.

For a full description of the AVR Stud io, please refer to the AVR Studio User Guide.

Only highlights ar e pr es en te d in this doc um e nt .

All necessary execution commands are available in AVR Studio, both on source level

and on disassembly level. The user can execute the program, single step through the

code either by tracing into or stepping over functions, step out of functions, place the

cursor on a statement and execute until the statement is reached, stop the execution,

and reset the execution target. In addition, the user can have an unlimited number of

code Break Points (using the BREAK instruction) and up to two data memory Break

Points, alternatively combined as a mask (range) Break Point.

On-chip Debug Specific

JTAG Instructions The O n-chip debug support is conside red being private JTAG instruction s, and distrib-

uted within ATMEL and to selected third party vendors only. Instruction opcodes are

listed for reference.

PRIVATE0; 0x8 Private JTAG instruction for accessing On-chip debug system.

PRIVATE1; 0x9 Private JTAG instruction for accessing On-chip debug system.

PRIVATE2; 0xA Private JTAG inst ruction for accessing On-chip debug system.

PRIVATE3; 0xB Private JTAG inst ruction for accessing On-chip debug system.

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On-chip Debug Related

On-chip Debug Register –

OCDR

The OCDR Register provides a communica tion chann el from the runn ing progr am in t he

microcontroller t o the de bugge r. The CPU can tr an sfer a byt e to th e debu gg er by writing

to this location. At the same time, an internal flag; I/O Debug Register Dirty – IDRD – is

set to indicate to the debugger that the register has been written. When the CPU reads

the OCDR Register the 7 LSB will be from the OCDR Reg ister, while the MSB is the

IDRD bit. The debugger clears the IDRD bit when it has read the information.

In some AVR devices, this register is shared with a standard I/O location. In th is case,

the OCDR Register can only be accessed if the OCDEN Fuse is programmed, and the

debugger enables access to the OCDR Register. In all other cases, the standard I/O

location is accessed.

Refer to the debugger documentation for further information on how to use this register.

Using the JTAG

Programming

Capabilities

Programming of AVR parts via JTAG is performed via the 4-pin JTAG port, TCK, TMS,

TDI, and TDO. These ar e the only pins that need to be controlled/ob served to perform

JTAG programming (in add ition t o power p ins). It is not r eq uired to apply 12 V ext ernally.

The JTAGEN Fuse must be programmed and the JTD bit in the MCUCR Register must

be cleared to enable the JTAG Test Access Port.

The JTAG programming capability supports:

• Flash programming and verifying.

• EEPROM programming and verifying.

• Fuse programming and verifying.

• Lock bit programming and verifying.

The Lock bit security is exactly as in parallel programming mode. If the Lock bits LB1 or

LB2 are programmed, the OCDEN Fuse cannot be programmed unless first doing a

chip erase. This is a security feature that ensures no ba ck-door exists for re ading out the

content of a secured device.

The details on programming through the JTAG interface and programming specific

JTAG instructions are given in the section “Programming via the JTAG Interface” on

page 285.

Bibliography For more information about general Boundary-scan, the following litera ture can be

consulted:

• IEEE: IEEE Std. 1149.1-1990. IEEE Standard Test Access P ort and Boundary-scan

Architecture, IEEE, 1993.

• Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison-

Wesley, 1992.

Bit 7 6543210

MSB/IDRD LSB OCDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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IEEE 1149.1 (JTAG)

Boundary-scan

Features •JTAG (IEEE std. 1149.1 compliant) Interface

•Boundary-scan Capabilities According to the JTAG Standard

•Full Scan of all Port Functions as well as Analog Circuitry having Off-chip Connections

•Supports the Optional IDCODE Instruction

•Additional Public AVR_RESET Instruction to Reset the AVR

System Overview The Boundary-scan chain has the capability of driving and observing the logic levels on

the digital I/O pins, as well as the boundary between digital and analog logic for analog

circuitry having off-chip connections. At system level, all ICs having JTAG capabilities

are connected serially by the TDI/TDO signals to form a long Shift Register. An external

controller sets up the devices to drive values at their output pins, and observe the input

values received from other devices. The controller compares the received data with the

expected result. In this way, Boundary-scan provides a mechanism for testing intercon-

nections and integrity of components o n Printed Circuits Boards by using the four TAP

signals only.

The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAM-

PLE/PRELOAD, and EXTEST, as well as the AVR specific public JTAG instruction

AVR_RESET can be used for testing the Printed Circuit Board. Initial scanning of the

Data Register path will show the ID-Code of the device, since IDCODE is the default

JTAG instruction. It may be desirable to have the AVR device in reset during test mode.

If not reset, inputs to the device may be determined by the scan operations, and the

internal software may be in an undetermined state when exiting the test mode. Entering

reset, the outputs of any port pin will instantly enter the high impedance state, making

the HIGHZ instruction redundant. If needed, the BYPASS instruction can be issued to

make the shortest possible scan chain through the device. The device can be set in the

reset state either by pulling the external RESET pin low, or issuing the AVR_RESET

instruction with appropriate setting of the Reset Data Register.

The EXTEST instruction is used for sampling external pins and loading output pins with

data. The data from the output latch will be driven out on the pins as soon as the

EXTEST instruction is loaded into the JTAG IR-Register. Therefore, the SAMPLE/PRE-

LOAD should also be used for setting initial values to the scan ring, to avoid damaging

the board when issuing the EXTEST instruction for the first time. SAMPLE/PRELOAD

can also be used for taking a snapshot of the external pins during normal operation of

the part.

The JTAGEN Fuse must be programmed and the JTD bit in the I/O Register MCUCR

must be cleared to enable the JTAG Test Access Port.

When using the JTAG interface for Boundary-scan, using a JTAG TCK clock frequency

higher than the internal chip f requency is possible. The chip clock is not required to run.

Data Registers The Data Registers relevant for Boundary-scan operations are:

• Bypass Register

• Device Identification Register

• Reset Register

• Boundary-scan Chain

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Bypass Register The Bypass Register consists of a single Shift Register stage. When the Bypass Regis-

ter is selected as path between TDI and TDO, the register is reset to 0 when leaving the

Capture-DR controller state. The Bypass Register can be used to shorten the scan

chain on a system when the other devices are to be tested.

Device Identificat io n Re gi st er Figure 107 shows the structure of the Device Identification Register.

Figure 107. The Format of the Device Identification Register

Version Version is a 4-bit number identifying the revision of the co mponent. The JTAG ve rsion

number follows t he revision o f the device . Revision A is 0x0, revision B is 0x1 and so o n.

Part Number The part number is a 16-bit code identifying the component. The JTAG Part Number for

ATmega169 is listed in Table 101.

Manufacturer ID The Manufacturer ID is a 11-bit code identifying the manufacturer. The JTAG manufac-

turer ID for ATMEL is listed in Ta b le 10 2 .

Reset Register The Reset Register is a test Data Register used to reset the part. Since th e AVR tri-

states Port Pins when reset, the Reset Register can also replace the function of the

unimplemented op tional JTAG instruction HIGHZ.

A high value in the Reset Register corresponds to pulling the external Reset low. The

part is reset as long as there is a high valu e present in the Reset Register. Depending

on the fuse settings for the clock options, the part will remain reset for a reset time-out

period (refer to “Clock Sources” on page 2 4) after re leasing the Reset Register. The out-

put from this Data Register is not latched, so the reset will take place immediately, as

shown in Figure 108.

MSB LSB

Bit 31 28 27 12 11 1 0

Device ID Version Part Number Manufacturer ID 1

4 bits 16 bits 11 bits 1-bit

Table 101. AVR JTAG Part Number

Part Number JTAG Part Number (Hex)

ATmega169 0x9405

Table 102. Manufacturer ID

Manufacturer JTAG Manufactor ID (Hex)

ATMEL 0x01F

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Figure 108. Reset Register

Boundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic levels on

the digital I/O pins, as well as the boundary between digital and analog logic for analog

circuitry having off-chip connections.

See “Boundary-scan Chain” on page 236 for a complete description.

Boundary-scan Specific

JTAG Instructions The Instruction Re gister is 4-bit wide, supporting u p to 16 instructio ns. Listed belo w are

the JTAG instructions useful for Boun dary-scan op eration . Note that the optio nal HIGHZ

instruction is not implemented, but all outputs with tri-state capability can be set in high-

impedant state by using the AVR_RESET instruction, since the initial state for all port

pins is tri-state.

As a definition in this datasheet, the LSB is shifted in a nd out first for all Shift Registers.

The OPCODE for each instruction is shown behind the instruction name in hex format.

The text describes which Data Register is selected as path between TDI and TDO for

each instruction.

EXTEST; 0x0 Mandatory JTAG instru ct ion fo r selecting the Boun dar y-scan Cha in as Da ta Registe r f or

testing circuitry external to the AVR package. For port-pins, Pull-up Disable, Output

Control, Output Data, and Input Data are all accessib le in the scan chai n. For Analog cir-

cuits having off-chip connections, the interface between the analog and the digital logic

is in the scan chain. The contents of the latched outputs of the Boundary-scan chain is

driven out as soon as the JTAG IR-Register is loaded with the EXTEST instruction.

The active states are:

• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.

• Shift-DR: The Internal Scan Chain is shift ed by the TCK input.

• Update-DR: Data from the scan chain is applied to output pins.

IDCODE; 0x1 Optional JTAG instruction selecting the 32 bit ID-R egister as Data Register. The ID-

chosen by JEDEC. This is the default instruction after power-up.

The active states are:

• Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan

Chain.

• Shift-DR: The IDCO DE scan ch ain is shifte d by the TCK input.

From

TDI

ClockDR · AVR_RESET

TDO

From Other Internal and

External Reset Sources

Internal reset

235

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SAMPLE_PRELOAD; 0x2 Mandatory JTAG instruction for pr e- load ing the outpu t latc hes an d t aking a snap- shot of

the input/output pins without affecting the system operation. However, the output latches

are not connected to the pins. The Boundary-scan Chain is selected as Data Register.

The active states are:

• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.

• Shift-DR: The Boundary-scan Chain is shifted by the TCK input.

• Update-DR: Data from the Boundary-scan chain is applied to the output latches.

However, the output latches are not connected to the pins.

AVR_RESET; 0xC The AVR specific public JTAG instruction for forcing the AVR device into the Re set

mode or releasing the JTAG reset source. The TAP controller is not reset by this instruc-

tion. The one bit Reset Register is selected as Data Register. Note that the reset will be

active as long as there is a logic “one” in the Reset Chain. The output from this chain is

not latched.

The active states are:

• Shift-DR: The Reset Register is shifted by the TCK input.

BYPASS; 0xF Mandatory JTAG instruction selecting the Bypass Register for Data Register.

The active states are:

• Capture-DR: Loads a logic “0” into the Bypass Register.

• Shift-DR: The Bypass Register cell between TDI and TDO is shifted.

Boundary-scan Related

MCU Control Register –

MCUCR The MCU Control Register contains control bits for general MCU functions.

• Bit 7 – JTD: JTAG Interface Disable

When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed.

If this bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling

or enabling of the JTAG interface, a timed sequence must be followed when changing

this bit: The application software must write this bit to the desired value twice within four

cycles to change its value. Note that th is bit must not be altered when using the On-chip

Debug system.

If the JTAG interface is left unconnected to other JTAG circuitry, the JTD bit should be

set to one. The reason for this is to avoid static current at the TDO pin in the JTAG

interface.

Bit 76543210

JTD – – PUD – – IVSEL IVCE MCUCR

Read/Write R/W R R R/W R R R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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MCU Status Register –

MCUSR The MCU Status Register provides information on which reset source caused an MCU

reset.

• Bit 4 – JTRF: JTAG Reset Flag

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register

selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or

by writing a logic zero to the flag.

Boundary-scan Chain The Boundary-scan chain has the capability of driving and observing the logic levels on

the digital I/O pins, as well as the boundary between digital and analog logic for analog

circuitry having off-chip connection.

Scanning the Digital Port Pins Figure 109 shows the Boundary-scan Cell for a bi-directional port pin with pull-up func-

tion. The cell consists of a standard Boundary-scan cell for the Pull-up Enable – PUExn

– function, and a bi-directional pin cell that combines the three signals Output Control –

OCxn, Output Data – ODxn, and Input Data – IDxn, into only a two-stage Shift Register.

The port and pin indexes are not used in the following description

The Boundary-scan logic is not included in the figures in the datasheet. Figu re 110

shows a simple digital port pin as described in the section “I/O-Ports” on page 55. The

Boundary-scan details from Figure 109 replaces the dashed box in Figure 110.

When no alternate port function is prese nt, the Input Data – ID – corresponds to the

PINxn Register value (but ID has no synchronizer), Output Data corresponds to the

PORT Register, Output Control corresponds to the Data Direction – DD Register, and

the Pull-up Enable – PUExn – corresponds to logic expression PUD · DDxn · PORTxn.

Digital alternate port functions are connected outside the dotted box in Figure 110 to

make the scan chain read the actual pin value. For Analog function, there is a direct

connection from the external pin to the analog circuit, and a scan chain is inserted on

the interface between the digital logic and the analog circuitry.

Bit 76543210

–––JTRFWDRF BORF EXTRF PORF MCUSR

Read/Write R R R R/W R/W R/W R/W R/W

Initial Value 0 0 0 See Bit Description

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Figure 109. Boundary-scan Cell for Bi-directional Port Pin with Pull-up Function.

DQ DQ

Port Pin (PXn)

VccEXTESTTo Next CellShiftDR

Output Control (OC)

Pullup Enable (PUE)

Output Data (OD)

Input Data (ID)

From Last Cell UpdateDRClockDR

FF2 LD2

FF1 LD1

LD0FF0

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Figure 110. General Port Pin Schematic Diagram

Scanning the RESET Pin The RESET pi n accepts 5V active low log ic for standard reset oper ation , and 12V acti ve

high logic for High Voltage Parallel p rogram ming. An ob serv e-on ly cell as sh own in Fig -

ure 111 is inserted both for the 5V reset signal; RSTT, and the 12V reset signal;

RSTHV.

Figure 111. Observe-only Cell

CLK

RPx

RDx

WDx

PUD

SYNCHRONIZER

WDx: WRITE DDRx

WRx: WRITE PORTx

RRx: READ PORTx REGISTER

WPx: WRITE PINx REGISTER

PUD: PULLUP DISABLE

CLK : I/O CLOCK

RDx: READ DDRx

RESET

CLR

DDxn

PINxn

DATA BUS

SLEEP

SLEEP: SLEEP CONTROL

Pxn

I/O

See Boundary-scan

Description for Details!

PUExn

OCxn

ODxn

IDxn

PUExn: PULLUP ENABLE for pin Pxn

OCxn: OUTPUT CONTROL for pin Pxn

ODxn: OUTPUT DATA to pin Pxn

IDxn: INPUT DATA from pin Pxn RPx: READ PORTx PIN

RRx

RESET

CLR

PORTxn

WPx

WRx

From

Cell

ClockDR

ShiftDR

Cell

From System Pin To System Logic

FF1

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Scanning the Clock Pins The AVR devices have many clock options selectable by fuses. These are: Internal RC

Oscillator, External Clock, (High Frequency) Crystal Oscillator, Low-frequency Crystal

Oscillator, and Ceramic Resonator.

Figure 112 shows how each Oscillator with external connection is supported in the scan

chain. The Enable signal is supported with a general Boundary-scan cell, while the

Oscillator/clock output is attached to an observe-only cell. In addition to the main clock,

the timer Oscillator is scanned in the same way. The output from the internal RC Oscilla-

tor is not scanned, as this Oscillator does not have external connections.

Figure 112. Boundary-scan Cells for Oscillators and Clock Options

Table 103 summaries the scan registers for the external clock pin XTAL1, oscillators

with XTAL1/XTAL2 connections as well as 32kHz Timer Oscillator.

Notes: 1. Do not enable more than one clock source as main clock at a time.

2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift

between the internal Oscillator and the JTAG TCK clock. If possible, scanning an

e x t e rnal clock is preferred.

3. The clock configuration is programmed by fuses. As a fuse is not changed run-time,

the clock configuration is considered fixed for a given application. The user is advised

to scan the same clock option as to be used in the final system. The enable signals

are suppor ted in the scan chain because the system logic can disable clock options

in sleep modes, thereby disconnecting the Oscillator pins from the scan path if not

provided.

Table 103. Scan Signals for the Oscillator(1)(2)(3)

Enable Signal Scanned Clock Line Clock Option

Scanned Clock

Line when not

Used

EXTCLKEN EXTCLK (XTAL1) External Clock 0

OSCON OSCCK External Crystal

Exter nal Ceramic Resonator 1

OSC32EN OSC32CK Low Freq. External Crystal 1

From

Cell

ClockDR

ShiftDR

Cell

To System Logic

FF1

DQ DQ

From

Cell

ClockDR UpdateDR

ShiftDR

Cell EXTEST

From Digital Logic

XTAL1/TOSC1 XTAL2/TOSC2

Oscillator

ENABLE OUTPUT

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Scanning the Analog

Comparator The relevant Comparator signals regarding Boundary-scan are shown in Figure 113.

The Boundary-sc an cell from Figure 114 is attached to each of these sign als. The sig-

nals are described in Table 104.

The Comparator need not be used for pure connectivity testing, since all analog inputs

are shared with a digital port pin as well.

Figure 113. Analog Comparator

Figure 114. General Boundary-scan cell Used for Signals for Comparator and ADC

ACBG

BANDGAP

REFERENCE

ADC MULTIPLEXER

OUTPUT

ACME

AC_IDLE

ACO

ADCEN

ACD

DQ DQ

From

Cell

ClockDR UpdateDR

ShiftDR

Cell EXTEST

To Analog Circuitry/

To Digital Logic

From Digital Logic/

From Analog Ciruitry

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Scanning the ADC Figure 115 shows a block diagram of the ADC with all relevant control and observe sig-

nals. The Boundary-scan cell from Figure 111 is attached to each of these signals. The

ADC need not be used for pure connectivity testing, since all analog inputs are shared

with a digital port pin as well.

Figure 115. Analog to Digital Converter

The signals ar e described briefly in Table 105.

Table 104. Boundary-scan Signals for the Analog Comparator

Signal

Name

Directio n as

Seen from the

Comparator Description

Recommended

Input when Not

in Use

Output V alues when

Recommended

Inputs are Used

AC_IDLE input Turns off Analog

Comparator when

true

1 Depends upon µC

code being executed

ACO output Analog

Comparator Output Will become

input to µC code

being executed

A CME input Uses output signal

from ADC mux

when true

0 Depends upon µC

code being executed

ACBG input Bandgap

Reference enable 0 Depends upon µC

code being executed

10-bit DAC +

AREF

PRECH

DACOUT

COMP

MUXEN_7

ADC_7

MUXEN_6

ADC_6

MUXEN_5

ADC_5

MUXEN_4

ADC_4

MUXEN_3

ADC_3

MUXEN_2

ADC_2

MUXEN_1

ADC_1

MUXEN_0

ADC_0

NEGSEL_2

ADC_2

NEGSEL_1

ADC_1

NEGSEL_0

ADC_0

EXTCH

ACLK

AMPEN

1.11V

ref

IREFEN

AREF

VCCREN

DAC_9..0

ADCEN

HOLD

PRECH

GNDEN

PASSEN

COMP

SCTEST ADCBGEN

To Comparator

1.22V

ref

ACTEN

AREF

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Table 105. Boundary-scan Signals for the ADC(1)

Signal

Name

Direction

as Seen

from the

ADC Description

Recommen-

ded Input

when not

in Use

Output Values when

Recommended Inputs

are Used, and CPU is

not Using the ADC

COMP Output Comparator Output 0 0

ACLK Input Clock signal to

differential amplifier

implemented as

Switch-cap filters

A CTEN Input Enable path from

differential amplifier to

the comparator

ADCBGEN Input Enable Band-gap

reference as negative

input to comparator

ADCEN Input Power-on signal to the

ADC 00

AMPEN Input Power-on signal to the

differential amplifier 00

DAC_9 Input Bit 9 of digital value to

DAC 11

DAC_8 Input Bit 8 of digital value to

DAC 00

DAC_7 Input Bit 7 of digital value to

DAC 00

DAC_6 Input Bit 6 of digital value to

DAC 00

DAC_5 Input Bit 5 of digital value to

DAC 00

DAC_4 Input Bit 4 of digital value to

DAC 00

DAC_3 Input Bit 3 of digital value to

DAC 00

DAC_2 Input Bit 2 of digital value to

DAC 00

DAC_1 Input Bit 1 of digital value to

DAC 00

DAC_0 Input Bit 0 of digital value to

DAC 00

EXTCH Input Connect ADC

channels 0 - 3 to by-

pass path around

differential amplifier

GNDEN Input Ground the negative

input to comparator

when true

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HOLD Input Sample & Hold signal.

Sample analog signal

when low. Hol d signal

when high. If

differential amplifier is

used, this signal must

go active when ACLK

is high.

IREFEN Input Enabl es Ba nd -g ap

reference as AREF

signal to DAC

MUXEN_7 Input Input Mux bit 7 0 0

MUXEN_6 Input Input Mux bit 6 0 0

MUXEN_5 Input Input Mux bit 5 0 0

MUXEN_4 Input Input Mux bit 4 0 0

MUXEN_3 Input Input Mux bit 3 0 0

MUXEN_2 Input Input Mux bit 2 0 0

MUXEN_1 Input Input Mux bit 1 0 0

MUXEN_0 Input Input Mux bit 0 1 1

NEGSEL_2 Input Input Mux for negative

input for differential

signal, bit 2

NEGSEL_1 Input Input Mux for negative

input for differential

signal, bit 1

NEGSEL_0 Input Input Mux for negative

input for differential

signal, bit 0

PASSEN Input Enable pass-gate of

differential amplifier. 11

PRECH Input Precharge output latch

of comparator. (Active

low)

Table 105. Boundary-scan Signals for the ADC(1) (Continued)

Signal

Name

Direction

as Seen

from the

ADC Description

Recommen-

ded Input

when not

in Use

Output Values when

Recommended Inputs

are Used, and CPU is

not Using the ADC

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Note: 1. Incorrect setting of the switches in Figure 115 will make signal contention and may

damage the part. There are sev eral input choices to the S&H circuitry on the negative

input of the output comparator in Figure 115. Make sure only one path is selected

from either one ADC pin, Bandgap reference source, or Ground.

If the ADC is not to be used during sca n, the recom mended inpu t values fro m Table 105

should be used. The user is recommended not to use the Differential Amplifier during

scan. Switch-Cap based different ial amplifier requ ires fast operation and accurat e timing

which is difficult to obtain when used in a scan chain. Details concerning op erations of

the differential amplifier is therefore not provided.

The AVR ADC is based on the analog circuitry shown in Figure 115 with a successive

approximation algorithm implemented in the digital logic. When used in Boundary-scan,

the problem is usually t o ensure that an applied analog voltage is measur ed within some

limits. This can easily be done without running a successive approximation algorithm:

apply the lower limit on the digital DAC[9:0] lines, make sure the output from the com-

parator is low, then app ly the uppe r limit on the digital DAC[9:0] lines, and verify the

output from the comparator to be hig h.

The ADC need not be used for pure connectivity testing, since all analog inputs are

shared with a digital port pin as well.

When using the ADC, remember the following

• The port pin fo r th e ADC ch an ne l in use must be config ur ed to be an input with pu ll-

up disabled to avoid signal contention.

• In Normal mode, a dummy conversion (consisting o f 10 comparisons) is performed

when enablin g the ADC. The user is advised to wait at least 200ns after enab ling the

ADC before controlling/observing any ADC signal, or perform a dummy conversion

before using the first result.

• The D AC v alues m ust be stab le at the midpoint v alue 0x200 when ha ving the HO LD

signal low (Sample mode).

SCTEST Input Switch-cap TEST

enable. Output from

differential amplifier is

sent out to Port Pin

having ADC_4

ST Input Output of differential

amplifier will settle

faster if this signal is

high first two ACLK

periods after AMPEN

goes high.

VCCREN Input Selects Vcc as the

ACC reference

voltage.

Table 105. Boundary-scan Signals for the ADC(1) (Continued)

Signal

Name

Direction

as Seen

from the

ADC Description

Recommen-

ded Input

when not

in Use

Output Values when

Recommended Inputs

are Used, and CPU is

not Using the ADC

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As an example, consider the task of veri fying a 1.5V ± 5% input signa l at ADC channel 3

when the power supply is 5.0V and AREF is externally connected to V CC.

The recommended values from Table 105 are used unless other values are given in the

algorithm in Table 106. Only the DAC and port pin values of the Scan Chain are shown.

The column “Actions” describes what JTAG instruction to be used before filling the

Boundary-scan Register with the succeeding columns. The verification should be done

on the data scanned out when scanning in the data on the same row in the table.

Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock

frequency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency

has to be at least five times the number of scan bits divided by the maximum hold time,

thold,max

Table 106. Algorithm for Using the ADC

Step Actions ADCEN DAC MUXEN HOLD PRECH PA3.

Data PA3.

Control

PA3.

Pull-

up_

Enable

1SAMPLE_

PRELOAD 1 0x200 0x08 1 1 0 0 0

2 EXTEST 1 0x200 0x08 0 1 0 0 0

31 0x200 0x08 1 1 0 0 0

41 0x123 0x08 1 1 0 0 0

51 0x123 0x08 1 0 0 0 0

Verify the

COMP bit

scanned

out to be 0

1 0x200 0x08 1 1 0 0 0

71 0x200 0x08 0 1 0 0 0

81 0x200 0x08 1 1 0 0 0

91 0x143 0x08 1 1 0 0 0

10 1 0x143 0x08 1 0 0 0 0

Verify the

COMP bit

scanned

out to be 1

1 0x200 0x08 1 1 0 0 0

The lower limit is: 1024 1.5V0,95 5V⁄⋅⋅ 291 0x123==

The upper limit is: 1024 1.5V1.05 5V⁄⋅⋅ 323 0x143==

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ATmega169 Boundary-

scan Order Table 107 shows the Scan order between TDI and TDO when the Boundary-scan chain

is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit

scanned ou t. Th e sca n or der f ollows the p in-o ut or der a s far as po ss ible. Th eref ore, the

bits of Port A is scanned in the opposite bit order of the other ports. Exceptions from the

rules are the Scan chains for the analog circ uits, which constitute the most significant

bits of the scan chain regardless of which physical pin they are connected to. In Figure

109, PXn. Data corresponds to FF0, PXn. Control corresponds to FF1, and PXn. Pull-

up_enable corresponds to FF2. Bit 4, 5, 6, and 7of Port F is not in the scan chain, since

these pins constitute the TAP pins whe n the JTAG is enabled.

Table 107. ATmega169 Boundary-scan Order

Bit Number Signal Name Module

197 AC_IDLE Comparator

196 ACO

195 ACME

194 AINBG

193 COMP ADC

192 ACLK

191 ACTEN

190 PRIVATE_SIGNAL1(1)

189 ADCBGEN

188 ADCEN

187 AMPEN

186 DAC_9

185 DAC_8

184 DAC_7

183 DAC_6

182 DAC_5

181 DAC_4

180 DAC_3

179 DAC_2

178 DAC_1

177 DAC_0

176 EXTCH

175 GNDEN

174 HOLD

173 IREFEN

172 MUXEN_7

171 MUXEN_6

170 MUXEN_5

169 MUXEN_4

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168 MUXEN_3 ADC

167 MUXEN_2

166 MUXEN_1

165 MUXEN_0

164 NEGSEL_2

163 NEGSEL_1

162 NEGSEL_0

161 PASSEN

160 PRECH

159 ST

158 VCCREN

157 PE0.Data Port E

156 PE0.Control

155 PE0.Pull-up_Enable

154 PE1.Data

153 PE1.Control

152 PE1.Pull-up_Enable

151 PE2.Data

150 PE2.Control

149 PE2.Pull-up_Enable

148 PE3.Data

147 PE3.Control

146 PE3.Pull-up_Enable

145 PE4.Data

144 PE4.Control

143 PE4.Pull-up_Enable

142 PE5.Data

141 PE5.Control

140 PE5.Pull-up_Enable

139 PE6.Data

138 PE6.Control

137 PE6.Pull-up_Enable

136 PE7.Data

135 PE7.Control

134 PE7.Pull-up_Enable

133 PB0.Data Port B

Table 107. ATmega169 Boundary-scan Order (Continued)

Bit Number Signal Name Module

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132 PB0.Control Port B

131 PB0.Pull-up_Enable

130 PB1.Data

129 PB1.Control

128 PB1.Pull-up_Enable

127 PB2.Data

126 PB2.Control

125 PB2.Pull-up_Enable

124 PB3.Data

123 PB3.Control

122 PB3.Pull-up_Enable

121 PB4.Data

120 PB4.Control

119 PB4.Pull-up_Enable

118 PB5.Data

117 PB5.Control

116 PB5.Pull-up_Enable

115 PB6.Data

114 PB6.Control

113 PB6.Pull-up_Enable

112 PB7.Data

111 PB7.Control

110 PB7.Pull-up_Enable

109 PG3.Data Por t G

108 PG3.Control

107 PG3.Pull-up_Enable

106 PG4.Data

105 PG4.Control

104 PG4.Pull-up_Enable

103 PG5 (Obser ve Only)

102 RSTT Reset Logic

(Observe-only)

101 RSTHV

100 EXTCLKEN Enable signals for main Clock/Oscillators

99 OSCON

98 RCOSCEN

97 OSC32EN

Table 107. ATmega169 Boundary-scan Order (Continued)

Bit Number Signal Name Module

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96 EXTCLK (XTAL1) Clock input and Oscillators for the main

clock

(Observe-only)

95 OSCCK

94 RCCK

93 OSC32CK

92 PD0.Data Port D

91 PD0.Control

90 PD0.Pull-up_Enable

89 PD1.Data

88 PD1.Control

87 PD1.Pull-up_Enable

86 PD2.Data

85 PD2.Control

84 PD2.Pull-up_Enable

83 PD3.Data

82 PD3.Control

81 PD3.Pull-up_Enable

80 PD4.Data

79 PD4.Control

78 PD4.Pull-up_Enable

77 PD5.Data

76 PD5.Control

75 PD5.Pull-up_Enable

74 PD6.Data

73 PD6.Control

72 PD6.Pull-up_Enable

71 PD7.Data

70 PD7.Control

69 PD7.Pull-up_Enable

68 PG0.Data Port G

67 PG0.Control

66 PG0.Pull-up_Enable

65 PG1.Data

64 PG1.Control

63 PG1.Pull-up_Enable

62 PC0.Data Port C

61 PC0.Control

Table 107. ATmega169 Boundary-scan Order (Continued)

Bit Number Signal Name Module

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60 PC0.Pull-up_Enable Port C

59 PC1.Data

58 PC1.Control

57 PC1.Pull-up_Enable

56 PC2.Data

55 PC2.Control

54 PC2.Pull-up_Enable

53 PC3.Data

52 PC3.Control

51 PC3.Pull-up_Enable

50 PC4.Data

49 PC4.Control

48 PC4.Pull-up_Enable

47 PC5.Data

46 PC5.Control

45 PC5.Pull-up_Enable

44 PC6.Data

43 PC6.Control

42 PC6.Pull-up_Enable

41 PC7.Data

40 PC7.Control

39 PC7.Pull-up_Enable

38 PG2.Data Port G

37 PG2.Control

36 PG2.Pull-up_Enable

35 PA7.Data Port A

34 PA7.Control

33 PA7.Pull-up_Enable

32 PA6.Data

31 PA6.Control

30 PA6.Pull-up_Enable

29 PA5.Data

28 PA5.Control

27 PA5.Pull-up_Enable

26 PA4.Data

25 PA4.Control

Table 107. ATmega169 Boundary-scan Order (Continued)

Bit Number Signal Name Module

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Note: 1. PRIVATE_SIGNAL1 should always be scanned in as zero.

Boundary-scan

Description Language

Files

Boundary-scan Description Language (BSDL) files describe Boundary-scan capable

devices in a standard format used by automated test-generation software. The order

and function of bits in the Boundary-scan Data Register are included in this description.

A BSDL file for ATmega169 is available.

24 PA4.Pull-up_Enable Port A

23 PA3.Data

22 PA3.Control

21 PA3.Pull-up_Enable

20 PA2.Data

19 PA2.Control

18 PA2.Pull-up_Enable

17 PA1.Data

16 PA1.Control

15 PA1.Pull-up_Enable

14 PA0.Data

13 PA0.Control

12 PA0.Pull-up_Enable

11 PF3.Data Port F

10 PF3.Control

9 PF3.Pull-up_Enable

8PF2.Data

7 PF2.Control

6 PF2.Pull-up_Enable

5PF1.Data

4 PF1.Control

3 PF1.Pull-up_Enable

2PF0.Data

1 PF0.Control

0 PF0.Pull-up_Enable

Table 107. ATmega169 Boundary-scan Order (Continued)

Bit Number Signal Name Module

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Boot Loader Support

– Read-While-Write

Self-Programming

The Boot Loader Supp ort provides a re al Read-While-Write Self-Programm ing mecha-

nism for downloading and uploading program code by the MCU itself. This feature

allows flexible application software updates controlled by the MCU using a Flash-resi-

dent Boot Loader program. The Boot Loader program can use any available data

interface and associated protocol to read code and write (program) th at code into the

Flash memory, or read the code from the progra m memory. The program code within

the Boot Loader section has the capability to write into the entire Flash, including the

Boot Loader memory. The Boot Loader can thus even modify itself, and it can also

erase itself from the code if the feature is not needed anymore. The size of the Boot

Loader memory is con figurab le with fu ses a nd the Boot Load er has two separat e sets of

Boot Lock bits which can be set independently. This gives the user a unique flexibility to

select different levels of protection.

Boot Loader Features •Read-While-Write Self-Programming

•Flexible Boot Memory Size

•High Securi ty (Separ a t e Boot Lock Bits for a Fle xi ble Protec tion)

•Separate Fuse to Select Reset Vector

•Optimized Page(1) Size

•Code Efficient Algorithm

•Efficient Read-Modify-Write Support

Note: 1. A page is a section in the Flash consisting of several bytes (see Table 121 on page

269) used during programming. The page organization does not affect normal

operation.

Application and Boot

Loader Flash Sections The Flash memory is organized in two main sections, the Application section and the

Boot Loader section (see Figure 117). The size of the different sections is configured by

the BOOTSZ Fuses as shown in Table 113 on page 264 and Figure 117 . These two

sections can have differ ent level o f prot ection since th ey h ave di ffer en t se ts o f Lo ck b its.

Application Section The Application section is the section of the Flash that is used for stor ing the ap plication

code. The protection level for the Application section can be selected by the application

Boot Lock bits (Boot Lock bits 0), see Table 109 on page 256. The Application section

can never store any Boot Loader code since the SPM instruction is disabled when exe-

cuted from the Application section.

BLS – Boot Loader Sect ion While the Application section is used for storing the application code, the The Boot

Loader software must be locat ed in the BLS sin ce the SPM instruct ion can initiat e a pro-

gramming when executing from the BLS only. The SPM instruction can access the

entire Flash, including the BLS itse lf. The protection level for the Boot Loader section

can be selected by the Boot Loader Lock bits (Boot Lock bits 1), see Table 110 on page

256.

Read-While-Write and No

Read-While-Write Flash

Sections

Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot

Loader software update is depende nt on which address that is being programmed. In

addition to the two sections that are configurable by the BOOTSZ Fuses as described

above, the Flash is also divided into two fixed sections, the Read-While-Write (RWW)

section and the No Read-While-Write (NRWW) section. The limit between the RWW-

and NRWW sections is given in Table 114 on page 264 and Figure 117 on page 255.

The main difference between the two sections is:

• When eras ing or writing a page located in side the R WW section, the NR WW section

can be read during the operation.

• When erasing or writing a page located inside the NR WW section, the CPU is halted

during the entire operation.

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Note that the user software can never read any code that is located inside the RWW

section during a Boot Loader software operation. The syntax “Read-While-Write sec-

tion” refers to which section that is being pro grammed (erased or written), not which

section that actually is being read during a Boot Loader software update.

RWW – Read-While-Write

Section If a Boot Loader software update is pr ogramming a page inside the RWW section, it is

possible to read code from the Flash, but only code that is located in the NRWW sec-

tion. During an on-going programming, the software must ensure that the RWW section

never is being read. If the user software is trying to read code that is located inside the

RWW section (i.e., by a call/jmp/lpm or an interrupt) during prog ramming, the software

might end up in an unknown st ate. T o av oid this, th e interr upts should eith er be disa bled

or moved to the Boot Loader section. The Boot Loader section is always located in the

NRWW section. The RWW Section Busy bit (RWWSB) in the Store Program Memory

Control and Status Register (SPMCSR) will be read as logical one as long as the RWW

section is blocked for reading. After a programming is completed, the RWWSB must be

cleared by software before reading code located in the RWW section. See “Store Pro-

gram Memory Control and Status Register – SPMCSR” on page 257. for details on how

to clear RWWSB.

NR WW – No Read-While-Write

Section The code located in the NRWW section can be read when the Boot Loader software is

updating a page in the RWW section. When the Boot Loader code updates the NRWW

section, the CPU is halted during the entire Page Erase or Page Write operation.

Table 108. Read-While-Write Features

Which Section does the Z-

pointer Address During the

Programming?

Which Section Can

be Read During

Programming? Is the CPU

Halted? Read-While-Write

Supported?

RWW Section NRWW Section N o Yes

NRWW Section None Yes No

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Figure 116. Read-While-Write vs. No Read-While-Write

Read-While-Write

(RWW) Section

No Read-While-Write

(NRWW) Section

Z-pointer

Addresses RWW

Section

Z-pointer

Addresses NRWW

Section

CPU is Halted

During the Operation

Code Located in

NRWW Section

Can be Read During

the Operation

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Figure 117. Memory Sections

Note: 1. The parameters in the figure above are given in Table 113 on page 264.

Boot Loader Lock Bits If no Boot Loader capability is needed, the entire Flash is availabl e for application code.

The Boot Loader has two separate set s of Boot Lock bits which can be set indepen -

dently. This gives the user a unique flexibility to select different levels of protection.

The user can select:

• To protect the entire Flash from a software update by the MCU.

• To protect only the Boot Loader Flash section from a softwar e update by the MCU.

• To protect only the Application Flash section from a software update by the MCU.

• Allow sof tware update in the entire Flash.

See Table 109 and Table 110 for further details. The Boot Lock bits and general Lock

bits can be set in software and in Serial or Parallel Programming mode, but they can be

cleared by a Ch ip Erase com mand only. The g enera l Wr ite Lock ( Lock Bit mode 2 ) do es

not contro l the programming o f the Flash memor y by SPM instruction. Similarly, the gen-

eral Read/Write Lock (Lock Bit mode 1) does not control reading nor writing by

LPM/SPM, if it is attempted.

0x0000

Flashend

Program Memory

BOOTSZ = '11'

Application Flash Section

Boot Loader Flash Section

Flashend

Program Memory

BOOTSZ = '10'

0x0000

Program Memory

BOOTSZ = '01'

Program Memory

BOOTSZ = '00'

Application Flash Section

Boot Loader Flash Section

0x0000

Flashend

Application Flash Section

Flashend

End RWW

Start NRWW

Application Flash Section

Boot Loader Flash Section

End RWW

Start NRWW

End RWW

Start NRWW

0x0000

End RWW, End Application

Start NRWW, Start Boot Loader

Application Flash SectionApplication Flash Section

Application Flash Section

Read-While-Write SectionNo Read-While-Write Section Read-While-Write SectionNo Read-While-Write Section

Read-While-Write SectionNo Read-While-Write SectionRead-While-Write SectionNo Read-While-Write Section

End Application

Start Boot Loader

End Application

Start Boot Loader

End Application

Start Boot Loader

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Note: 1. “1” means unprogrammed, “0” means programmed

Entering the Boot Loader

Program Entering the Boot Loader takes place by a jump or call from the application program.

This may be initiated b y a trigg er su ch as a com mand r eceived via USART, or SPI in te r-

face. Alternatively, the Boot Re set Fuse can be programmed so that the Reset Vector is

pointing to the Boot Flash start address after a reset. In this case, the Boot Loader is

started after a reset. After the application code is loaded, the program can start execut-

ing the application code. Note that the fuses cannot be changed by the MCU itself. This

means that once the Boot Reset Fuse is programmed, the Reset Vector will always

point to the Boot Loader Reset and the fuse can on ly be changed through the serial or

parallel program ming interface.

Note: 1. “1” means unprogrammed, “0” means programmed

Table 109. Boot Lock Bit0 Protection Modes (Application Section)(1)

BLB0 Mode BLB02 BLB01 Protection

1 1 1 No restrictions for SPM or LPM accessing the App l i cation

section.

2 1 0 SPM is not allowed to write to the Application section.

3 0 0 SPM is not allowed to write to the Application section, and

LPM executing from the Boot Loader section is not

allowed to read from the Application section. If Interrupt

Vectors are placed in the Boot Loader section, interrupts

are disabled while executing from the Application section.

4 0 1 LPM executing from the Boot Loader section is not

allowed to read from the Application section. If Interrupt

Vectors are placed in the Boot Loader section, interrupts

are disabled while executing from the Application section.

Table 110. Boot Lock Bit1 Protection Modes (Boot Loader Section)(1)

BLB1 Mode BLB12 BLB11 Protection

1 1 1 No restrictions for SPM or LPM accessing the Boot Loader

section.

2 1 0 SPM is not allowed to write to the Boot Loader section.

3 0 0 SPM is not allowed to write to the Boot Loader section,

and LPM executing from the Application section is not

allowed to read from the Boot Loader section. If Interrupt

Vectors are placed in the Applicati on section, interrupts

are disabled while ex ecuting from the Boot Loader section.

4 0 1 LPM executing from the Application section is not allowed

to read from the Boot Loader section. If Interr upt Vectors

are placed in the Application section, interrupts are

disabled while executing from the Boot Loader section.

Table 111. Boot Reset Fuse(1)

BOOTRST Reset Address

1 Reset Vector = Application Reset (address 0x0000)

0 Reset Vector = Boot Loader Reset (see Table 113 on page 264)

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Store Program Memory

Control and Status Register –

SPMCSR

The Store Program Memory Control and Status Register contains the control bits

needed to control the Boot Loader operations.

• Bit 7 – SPMIE: SPM Interrupt Enable

When the SPMIE b it is written to one, and th e I-bit in the Stat us Register is set (o ne), the

SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long

as the SPMEN bit in the SPMCSR Register is cleared.

• Bit 6 – RWWSB: Read-While-Write Section Busy

When a Self-Progra mming ( Page Erase or Page Writ e) operat ion to t he RWW se ction is

initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the

RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit

is written to one after a Self-Programming operation is completed. Alternatively the

RWWSB bit will automatically be cleared if a page load operation is initiated.

• Bit 5 – Res: Reserved Bit

This bit is a reserved bit in t he ATmega169 and always read as zero.

• Bit 4 – RWWSRE: Read-While-Write Section Read Enable

When programming (Page Erase or Page Write) to the RWW section, the RWW section

is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW

section, the user software must wait until the programming is completed (SPMEN will be

cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the

next SPM instruction within four clock cycles re-enables the RWW section. The RWW

section cannot be re-ena bled while t he Fla sh is b usy with a Pag e Eras e or a Pa ge Wr ite

(SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, th e Flash

load operation will abort and the data loaded will be lost.

• Bit 3 – BLBSET: Boot Lock Bit Set

If this bit is written to one at the same time as SPMEN, the next SPM instruction within

four clock cycles sets Boot Lock bits and general Lock bits, according to the data in R0.

The data in R1 and the address in the Z-pointer are ignored. The BLBSET bit will auto-

matically be clea red upon completion of the Lo ck bit set, or if no SPM instruction is

executed within four clock cycles.

An LPM instruction within three cycles after BLBSET and SPMEN are set in the

SPMCSR Register, will read either the Lock bits or the Fuse bits (depending on Z0 in

the Z-pointer) into the destination register. See “Reading the Fuse and Lock Bits from

Software” on page 261 for details.

• Bit 2 – PGWRT: Page Write

If this bit is written to one at the same time as SPMEN, the next SPM instruction within

four clock cycles executes Page Write, with the data stored in the temporary bu ffer. The

page addres s is taken from the high pa rt of the Z-pointer. The d ata in R1 and R0 are

ignored. The PGWRT bit will auto-clear upon completion of a Pa ge Write, or if no SPM

instruction is executed within four clock cycles. The CPU is halted during the entire

Page Write operation if the NRWW section is addressed.

Bit 7 6 5 4 3 2 1 0

SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN SPMCSR

Read/Write R/W R R R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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• Bit 1 – PGERS: Page Erase

If this bit is written to one at the same time as SPMEN, the next SPM instruction within

four clock cycles executes Page Erase. The page ad dr ess is taken from th e h igh part of

the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon

completion of a Page Erase, or if no SPM instruction is executed within four clock

cycles. The CPU is halte d during the entir e Page Write o peration if t he NRWW section is

addressed.

• Bit 0 – SPMEN: Store Program Memory Enable

This bit enables the SPM instruction for the next four clock cycles. If written to one

together with either RWWSRE, BLBSET, PGWRT’ or PGERS, the following SPM

instruction will have a special meaning, see description above. If only SPMEN is written,

the following SPM instruction will store the value in R1:R0 in the temporary page buffer

addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit will

auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed

within four clock cycles. During Page Erase and Page Write, the SPMEN bit remains

high until the operation is completed.

Writing any other combin at ion than “ 100 01” , “01 001 ”, “0 010 1” , “ 00011 ” or “00 001” in the

lower five bits will have no effect.

Addressing the Flash

During Self-

Programming

The Z-pointer is used to address the SPM commands.

Since the Flash is organized in pages (see Table 121 on page 269), the Program

Counter can be treated as having two different sections. One section, consisting of the

least significant bits, is addressing the words within a page, while the most significant

bits are addressing the pages. This is shown in Figure 118. Note that the Page Erase

and Page Write operations are addressed independently. Therefore it is of major impor-

tance that the Boot Loader software addresses the same page in both the Page Erase

and Page Write operation. Once a programming operation is initiated, the address is

latched and th e Z-pointer can be used for other operations.

The only SPM operation tha t does not use the Z-po inter is Setting th e Boot Loa der Lock

bits. The content of the Z-poin ter is ignore d and will have no ef fect on the operatio n. The

LPM instruction does also use the Z-pointer to store the address. Since this instruction

addresses the Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used.

Bit 151413121110 9 8

ZH (R31) Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8

ZL (R30) Z7Z6Z5Z4Z3Z2Z1Z0

76543210

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Figure 118. Addressing the Flash During SPM(1)

Note: 1. The different variables used in Figure 118 are listed in Table 115 on page 265.

2. PCPAGE and PCWORD are listed in Table 121 on page 269.

Self-Programming the

Flash The program memory is updated in a page by page fashion. Before programming a

page with the data stored in the tempo rary page buffer, the page must be erased. The

temporary page buffer is filled one word at a time using SPM and the buffer can be filled

either before the Page Erase command or between a Page Erase and a Page Write

operation:

Alternative 1, fill the buffer before a Page Erase

• Fill temporary page buffer

• Perform a Page Erase

• Perform a Page Write

Alternative 2, fill the buffer after Page Erase

• Perform a Page Erase

• Fill temporary page buffer

• Perform a Page Write

If only a part of the page needs to be changed, the rest of the page must be stored (for

example in the temporary page buffer) before the erase, and then be rewritten. When

using alternative 1, the Boot Loader provides an effective Read-Modify-Write feature

which allows the user software to first read the page, do th e necessary changes, and

then write back the modified data. If alternative 2 is used, it is not possible to read the

old data w hile load ing sin ce th e pa ge is a lrea dy er ased . Th e tem por ary p age bu ffer can

be accessed in a random sequence. It is essential that the page address used in both

the Page Erase and Page Wr ite operation is addressing the s ame page. See “Simple

Assembly Code Example for a Boot Loader” on page 263 for an assembly code

example.

PROGRAM MEMORY

0115

Z - REGISTER

BIT

ZPAGEMSB

WORD ADDRESS

WITHIN A PAGE

PAGE ADDRESS

WITHIN THE FLASH

ZPCMSB

INSTRUCTION WORD

PA G E PCWORD[PAGEMSB:0]:

PAGEEND

PA G E

PCWORDPCPAGE

PCMSB PAGEMSB

PROGRAM

COUNTER

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Performing Page Erase by

SPM To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to

SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in

R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register.

Other bits in the Z-pointer will be ignored during this operation.

• Page Erase to the RWW section: The NRWW section can be read during the Page

Erase.

• Page Erase to the NRWW section: The CPU is halted during the operation.

Filling the Temporary Buffer

(Page Loading) To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write

“00000001” to SPMCSR and execute SPM within four clock cycles after writing

SPMCSR. The content of PCWORD in the Z-register is used to address the data in the

temporary buffer. The temporary buffer will auto-erase after a Page Write operation or

by writing the RWWSRE bit in SPMCSR. It is also erased after a system reset. Note that

it is not possible to writ e more tha n one time to each a ddress withou t erasing t he temp o-

rary buffer.

If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded

will be lost.

Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “X0000101” to

SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in

R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the

Z-pointer must be written to zero during this operation.

• Page Write to the RWW section: The NRWW section can be read during the Page

Write.

• Page Write to the NRWW section: The CPU is halted during the operation.

Using the SPM Interrupt If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt

when the SPMEN bit in SPMCSR is cleared. This means that the interrupt can be used

instead of polling the SPMCSR Register in software. When using the SPM interrupt, the

Interrupt Vectors should be moved to the BLS section to avoid that an interrupt is

accessing the RWW section when it is blocked for reading. How to move the interrupts

is described in “Interrupts” on page 46.

Consideration While Updati ng

BLS Special care must be taken if the user allows the Boot Loader section to be updated by

leaving Boot Lock b it11 unpro grammed. An accid ental write to the Boot Loade r itself can

corrupt the entire Boot Loader, and further software updates might be impossible. If it is

not necessary to change the Boot Loader software itself, it is recommended to program

the Boot Lock bit11 to protect the Boot Loader software from any internal software

changes.

Prevent Reading the RWW

Section During Self-

Programming

During Self-Programming (either Page Erase or Page Write), the RWW section is

always blocked for reading. The user software itself must preve nt that this section is

addressed during the self programming operation. The RWWSB in the SPMCSR will be

set as long as the RWW section is busy. During Self-Programming the Interrupt Vector

table should be moved to the BLS as described in “Interrupts” on page 46, or the inter-

rupts must be disabled. Before addressing the RWW section after the programming is

completed, the user software must clear the RWWSB by writing the RWWSRE. See

“Simple Assembly Code Example for a Boot Loader” on page 263 for an example.

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Setting the Boot Loader Lock

Bits by SPM To set the Boot Loader Lock bits and general Lock bits, write the desired data to R0,

write “X0001001” to SPMCSR and execute SPM within four clock cycles after writing

SPMCSR.

See Table 109 a nd Table 11 0 for how t he differ ent settin gs of th e Boot Load er bits a ffect

the Flash access.

If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed

if an SPM instruction is executed within four cycles after BLBSET and SPMEN are set in

SPMCSR. The Z-pointer is don’t care during this operation, but for future compatibility it

is recommended to load the Z-pointer with 0x0001 (same as used for reading the Lock

bits). For future compatibility it is also recommended to set bits 7 and 6 in R0 to “1” when

writing the Lock bits. When progra mming the Lock bits th e entire Flash can be read dur-

ing the operation.

EEPROM Write Prevents

Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash.

Reading the Fuses and Lock bits from software will also be prevented during the

EEPROM write operation. It is recommended that the user checks the status bit (EEWE)

in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR

Reading the Fuse and Lock

Bits from Software It is possible to read b oth the Fuse and Lock bits from software. T o read the Lock bits,

load the Z-pointer with 0x0001 and set the BL BSET and SPMEN bits in SPMCSR.

When an LPM instruction is executed within three CPU cycles after the BLBSET and

SPMEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the destina-

tion register. The BLBSET and SPMEN bits will auto-clear upon completion of reading

the Lock bits or if no LPM instruction is executed within three CPU cycles or no SPM

instruction is executed wit hin fo ur CPU cycles. When BLBSET and SPMEN are cleare d,

LPM will work as described in the Instruction set Manual.

The algorithm for reading the Fuse Low byte is similar to the one described above for

reading the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and

set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruction is executed

within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value

of the Fuse Low byte (FLB) will be loaded in the destination register as shown below.

Refer to Table 120 on page 268 for a detailed description and mapping o f the Fuse Low

byte.

Similarly, when reading the Fuse High byte, load 0x000 3 in the Z-p ointer. When an LPM

instruction is executed within three cycles after the BLBSET and SPMEN bits are set in

the SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination

mapping of the Fuse High byte.

When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an LPM

instruction is executed within three cycles after the BLBSET and SPMEN bits are set in

Bit 76543210

R0 1 1 BLB12 BLB11 BLB02 BLB01 LB2 LB1

Bit 76543210

Rd – – BLB12 BLB11 BLB02 BLB01 LB2 LB1

Bit 76543210

Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0

Bit 76543210

Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0

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the SPMCSR, the value of the Extended Fuse byte (EFB) will be loaded in the destina-

tion register as shown below. Refer to Table 118 on page 267 for detailed description

and mapping of the Extended Fuse byte.

Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that

are unprogrammed, will be read as one.

Preventing Flash Corruption During periods of low VCC, th e Fla sh p rogra m ca n be cor rupt ed be cause the su pply vol t-

age is too low for t he CPU and the Flash to operat e properly. T hese issues are the same

as for board level systems using the Flash, and the same design solutions should be

applied.

A Flash program cor ruption can b e caused by two situ ations when the voltag e is too low.

First, a regular write sequence to the Flash requires a minimum voltage to operate cor-

rectly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage

for executing instructions is too low.

Flash corruption ca n easily be avoide d by following th ese design recomme ndations (one

is sufficient):

1. If there is no need for a Boot Loader update in the system, program the Boot

Loader Lock bits to prevent any Boot Loader software updates.

2. Keep the AVR RESET active (low) during periods of insufficient power supply

voltage. This can be done by enabling the internal Brown-out Detecto r (BOD) if

the operating voltage matches the detection level. If not, an external low VCC

reset protecti on circuit can be used. I f a reset occurs while a write oper ation is in

progress, the write operation will be completed provided that the power supply

v oltage is sufficient.

3. Keep the AVR core in Power-down sleep mode during periods of low VCC. This

will prevent the CPU from attempting to decode and execute instructions, effec-

tively protecting the SPMCSR Register and thus the Flash fr om unintentional

writes.

Programming Time for Flash

when Using SPM The calibrated RC Oscillator is used to time Flash accesses. Table 112 shows the typi-

cal programming time for Flash accesses from the CPU.

Bit 76543210

Rd – – – – EFB3 EFB2 EFB1 EFB0

Table 112. SPM Programming Time

Symbol Min Programming Time Max Programming Time

Flash write (Page Erase, Page Write,

and write Lock bits by SPM) 3.7 ms 4.5 ms

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Simple Assembly Code

Example for a Boot Loader ;-the routine writes one page of data from RAM to Flash

; the first data location in RAM is pointed to by the Y pointer

; the first data location in Flash is pointed to by the Z-pointer

;-error handling is not included

;-the routine must be placed inside the Boot space

; (at least the Do_spm sub routine). Only code inside NRWW section can

; be read during Self-Programming (Page Erase and Page Write).

;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),

; loophi (r25), spmcrval (r20)

; storing and restoring of registers is not included in the routine

; register usage can be optimized at the expense of code size

;-It is assumed that either the interrupt table is moved to the Boot

; loader section or that the interrupts are disabled.

.equ PAGESIZEB = PAGESIZE*2 ;PAGESIZEB is page size in BYTES, not words

.org SMALLBOOTSTART

Write_page:

; Page Erase

ldi spmcrval, (1<<PGERS) | (1<<SPMEN)

call Do_spm

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)

call Do_spm

; transfer data from RAM to Flash page buffer

ldi looplo, low(PAGESIZEB) ;init loop variable

ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256

Wrloop:

ld r0, Y+

ld r1, Y+

ldi spmcrval, (1<<SPMEN)

call Do_spm

adiw ZH:ZL, 2

sbiw loophi:looplo, 2 ;use subi for PAGESIZEB<=256

brne Wrloop

; execute Page Write

subi ZL, low(PAGESIZEB) ;restore pointer

sbci ZH, high(PAGESIZEB) ;not required for PAGESIZEB<=256

ldi spmcrval, (1<<PGWRT) | (1<<SPMEN)

call Do_spm

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)

call Do_spm

; read back and check, optional

ldi looplo, low(PAGESIZEB) ;init loop variable

ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256

subi YL, low(PAGESIZEB) ;restore pointer

sbci YH, high(PAGESIZEB)

Rdloop:

lpm r0, Z+

ld r1, Y+

cpse r0, r1

jmp Error

sbiw loophi:looplo, 1 ;use subi for PAGESIZEB<=256

brne Rdloop

; return to RWW section

; verify that RWW section is safe to read

Return:

in temp1, SPMCSR

sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet

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ret

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)

call Do_spm

rjmp Return

Do_spm:

; check for previous SPM complete

Wait_spm:

in temp1, SPMCSR

sbrc temp1, SPMEN

rjmp Wait_spm

; input: spmcrval determines SPM action

; disable interrupts if enabled, store status

in temp2, SREG

cli

; check that no EEPROM write access is present

Wait_ee:

sbic EECR, EEWE

rjmp Wait_ee

; SPM timed sequence

out SPMCSR, spmcrval

spm

; restore SREG (to enable interrupts if originally enabled)

out SREG, temp2

ret

ATmega169 Boot Loader

Parameters In Table 113 through Table 115, the parameters used in the description of the Self-Pro-

gramming are given.

Note: 1. The different BOOTSZ Fuse configurations are shown in Figure 117

Note: 1. For details ab out these two section, see “NRWW – No Read-While-Write Section” on

page 253 and “RWW – Read-While-W rite Section” on page 253.

Table 113. Boot Size Configuration(1)

BOOTSZ1

BOOTSZ0

Boot Size

Pages

Application

Flash

Section

Boot Loader

Flash

Section

End Applicat ion

Section

Boot Reset

Address

(Start Boot

Loader Section)

1 1 128

words 2 0x0000 -

0x1F7F 0x1F80 -

0x1FFF 0x1F7F 0x1F80

1 0 256

words 4 0x0000 -

0x1EFF 0x1F00 -

0x1FFF 0x1EFF 0x1F00

0 1 512

words 8 0x0000 -

0x1DFF 0x1E00 -

0x1FFF 0x1DFF 0x1E00

0 0 1024

words 16 0x0000 -

0x1BFF 0x1C00 -

0x1FFF 0x1BFF 0x1C00

Table 114. Read-While-Write Limit(1)

Section Pages Address

Read-While-Wr ite section (RWW) 112 0 x 0000 - 0x1BFF

No Read-While-Write section (NRWW) 16 0x1C00 - 0x1FFF

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Note: 1. Z15:Z14: always ignored

Z0: should be zero for all SPM commands, byte select for the LPM instruction.

See “Addressing the Flash During Self-Prog ramming” on page 258 for details about

the use of Z-pointer during Self-Programming.

Table 115. Explanation of differen t vari ables used in Fig ure 1 18 an d t he ma pp ing to the

Z-pointer(1)

Variable Corresponding

Z-value Description

PCMSB 12 Most significant bit in the Program Counter.

(The Program Counter is 13 bits PC[12:0])

PA GEMSB 5 Most significant bit which is used to address the

words within one page (64 words in a page

requires six bits PC [5:0]).

ZPCMSB Z13 Bit in Z-register that is mapped to PCMSB.

Because Z0 is not used, the ZPCMSB equals

PCMSB + 1.

ZPAGEMSB Z6 Bit in Z-register that is mapped to PAGEMSB.

Because Z0 is not used, the ZPAGEMSB equals

PAGEMSB + 1.

PCPAGE PC[12:6] Z13 :Z7 Program Counter page address: Page select,

for Page Erase and Page Write

PCWORD PC[5:0 ] Z6:Z1 Program Counter word address: Word select,

f or filling temporary buffer (must be zero during

Page Write operation)

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Memory

Programming

Program And Data

Memory Lock Bits The ATmega169 provides six Lock bits which can be left unprogrammed (“1”) or can be

programmed ( “0” ) to obt ain th e a dditi on al fe atures listed in Table 117 . The Lock b its can

only be erased to “1 ” with the Chip Erase command.

Note: 1. “1” means unprogrammed, “0” means programmed

Table 116. Lock Bit Byte(1)

Lock Bit Byte Bit No Description Default Value

7 – 1 (unprogrammed)

6 – 1 (unprogrammed)

BLB12 5 Boot Lock bit 1 (unprogrammed)

BLB11 4 Boot Lock bit 1 (unprogrammed)

BLB02 3 Boot Lock bit 1 (unprogrammed)

BLB01 2 Boot Lock bit 1 (unprogrammed)

LB2 1 Lock bit 1 (unp rogrammed)

LB1 0 Lock bit 1 (unp rogrammed)

Table 117. Lock Bit Protection Modes(1)(2)

Memory Lock Bi ts Protectio n Type

LB Mode LB2 LB1

1 1 1 No memory lock features enabled.

210

Further programming of the Flash and EEPROM is

disabled in Parallel and Serial Programming mode. The

Fuse bits are locked in both Serial and Pa rallel

Programming mode.(1)

300

Further programming and verification of the Flash and

EEPROM is disabled in Parallel and Serial Programming

mode. The Boot Lock bits and Fuse bits are lock ed in both

Serial and Parallel Programming mo de.(1)

BLB0 Mode BLB02 BLB01

111

No restrictions for SPM or LPM accessing the Application

section.

2 1 0 SPM is not allowed to write to the Application section.

300

SPM is not allowed to write to the Application section, and

LPM executing from the Boot Loader section is not

allowed to read from the Application section. If Interrupt

Vectors are placed in the Boot Loader section, interrupts

are disabled while executing from the Application section.

401

LPM executing from the Boot Loader section is not

allowed to read from the Application section. If Interrupt

Vectors are placed in the Boot Loader section, interrupts

are disabled while executing from the Application section.

BLB1 Mode BLB12 BLB11

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Notes: 1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.

2. “1” means unprogrammed, “0” means programmed

Fuse Bits The ATmega169 has three Fuse bytes. Table 118 - Table 120 describe briefly the func-

tionality of all the fuses and how they are mapped into the Fuse bytes. Note that the

fuses are read as logical zero, “0”, if they are programmed.

Notes: 1. See Table 17 on page 40 for BODLEVEL Fuse decoding.

2. This bit should never be programmed.

111

No restrictions for SPM or LPM accessing the Boot Loader

section.

2 1 0 SPM is not allowed to write to the Boot Loader section.

300

SPM is not allowed to write to the Boot Loader secti on,

and LPM executing from the Application section is not

allowed to read from the Boot Loader section. If Interrupt

Vectors are placed in the Applicati on section, interrupts

are disabled while ex ecuting from the Boot Loader section.

401

LPM executing from the Application section is not allowed

to read from the Boot Loader section. If Interr upt Vectors

are placed in the Application section, interrupts are

disabled while executing from the Boot Loader section.

Table 117. Lock Bit Protection Modes(1)(2) (Continued)

Memory Lock Bi ts Protectio n Type

Table 118. Extended Fuse Byte

Fuse Low Byte Bit No Description Default Value

–7– 1

–6– 1

–5– 1

–4– 1

BODLEVEL2(1) 3 Brown-out Detector trigger level 1 (unprogrammed)

BODLEVEL1(1) 2 Brown-out Detector trigger level 1 (unprogrammed)

BODLEVEL0(1) 1 Brown-out Detector trigger level 1 (unprogrammed)

RESERVED(2) 0 1 (unprogrammed)

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Note: 1. The SPIEN Fuse is not accessible in serial programming mode.

2. The default value of BOOTSZ1..0 results in maximum Boot Size. See Table 113 on

page 264 for details.

3. See “Watchdog Timer Control Register – WDTCR” on pag e 43 for details.

4. Never ship a product with the OCDEN Fuse programmed regardless of the setting of

Lock bits and JTAGEN Fuse. A programmed OCDEN Fuse enab les some parts of the

clock system to be running in all sleep modes. This may increase the power

consumption.

5. If the JTAG interface is left unconnected, the JTAGEN fuse should if possible be dis-

abled. This to avoid static current at the TDO pin in the JTAG interface.

Note: 1. The default value of SUT1..0 results in maximum start-up time for the default clock

source. See Table 16 on page 38 for details.

2. The default setting of CKSEL3..0 results in internal RC Oscillator @ 8 MHz. See

Table 6 on page 26 for details.

3. The CKOUT Fuse allow the system clock to be output on PORTE7. See “Clock Out-

put Buffer” on page 29 for details.

4. See “System Clock Prescaler” on page 29 for details.

Table 119. Fuse High Byte

Fuse High

Byte Bit

No Description Default Value

OCDEN(4) 7Enable OCD 1 (unprogrammed, OCD

disabled)

JTAGEN(5) 6Enable JTAG 0 (programmed, JTAG

enabled)

SPIEN(1) 5Enable Serial Pro gram and Data

Downloading 0 (programmed, SPI prog.

enabled)

WDTON(3) 4 Watchdog Timer always on 1 (unprogrammed)

EESAVE 3 EEPROM memory is preserved

through the Chip Erase 1 (unprogrammed, EEPROM

not preserved)

BOOTSZ1 2 Select Boot Size (see Table 113 for

details) 0 (programmed)(2)

BOOTSZ0 1 Select Boot Size (see Table 113 for

details) 0 (programmed)(2)

BOOTRST 0 Select Reset Vector 1 (unprogrammed)

Table 120. Fuse Low Byte

Fuse Low Byte Bit No Description Default Value

CKDIV8(4) 7 Divide clock by 8 0 (programmed)

CKOUT(3) 6 Clock output 1 (unprogrammed)

SUT1 5 Select start-up time 1 (unprogrammed)(1)

SUT0 4 Select star t-up time 0 (programmed)(1)

CKSEL3 3 Select Clock source 0 (programmed)(2)

CKSEL2 2 Select Clock source 0 (programmed)(2)

CKSEL1 1 Select Clock source 1 (unprogrammed)(2)

CKSEL0 0 Select Clock source 0 (programmed)(2)

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The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are

locked if Lock bit1 (LB1) is program med. Program t he Fuse bits before pr ogramming the

Lock bits.

Latching of Fuses The fuse values are latched when the device enters pr ogramm ing mod e and change s of

the fuse values will have no effect until the part leaves Programming mode. This does

not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses

are also latched on Power-up in Normal mode.

Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device.

This code can be read in both serial and parallel mode, also when the device is locked.

The three bytes reside in a separate address space.

For the ATmega169 the signature bytes are:

1. 0x000: 0x1E (indicates manufactured by Atmel).

2. 0x001: 0x94 (indicates 16KB Flash memory).

3. 0x002: 0x05 (indicates ATmega169 device when 0x001 is 0x94).

Calibration Byte The ATmega169 has a byte calibration value for the internal RC Oscillator. This byte

resides in the high byte of address 0x000 in the signature address space. During reset,

this byte is autom atically written into the OSC CAL Register to ensure co rrect freque ncy

of the calibrated RC Oscillator.

Page Size

Parallel Programming

Parameters, Pin

Mapping, and

Commands

This section describes h ow to parallel program and verify Flash Program memory,

EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATmega169. Pulses

are assumed to be at least 250 ns unless otherwise noted.

Signal Names In this section, some pins of the ATme ga169 are refere nced by sign al name s de scr ibing

their functionality during parallel programming, see Figure 119 and Table 123. Pins not

described in the following table are referenced by pin names.

The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a posi-

tive pulse. The bit coding is shown in Table 125.

When pulsing WR or OE , the com mand loa ded dete rmines t he action e xecut ed. The di f-

ferent Commands are shown in Table 126.

Table 121. No. of Words in a Page and No. of Pages in the Flash

Flash Size Page Size PCWORD No. of Pages PCPAGE PCMSB

8K words (16K bytes) 64 words PC[5:0] 128 PC[12:6] 12

Table 122. No. of Words in a Page and No. of Pages in the EEPROM

EEPROM Size Page Size PCWORD No. of Pages PCPAGE EEAMSB

512 bytes 4 bytes EEA[1:0] 128 EEA[8:2] 8

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Figure 119. Parallel Programming

VCC

+5V

GND

XTAL1

PD1

PD2

PD3

PD4

PD5

PD6

PB7 - PB0 DAT

RESET

PD7

+12 V

BS1

XA0

XA1

DY/BSY

PAGEL

PA0

BS2

AVCC

+5V

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Table 123. Pin Name Mapping

Signal Name in

Programming Mode Pin Name I/O Functi on

RDY/BSY PD1 O 0: De vic e is busy progr amming, 1: De vice is ready

f or new command.

OE PD2 I Output Enable (Active low).

WR PD3 I Wr ite Pulse (Active low).

BS1 PD4 I Byte Select 1 (“0” selects low b yte, “1” selects high

byte).

XA0 PD5 I XTAL Action Bit 0

XA1 PD6 I XTAL Action Bit 1

PAGEL PD7 I Program Memory and EEPROM data Page Load.

BS2 PA0 I Byte Select 2 (“0” selects low byte , “1” selects 2’nd

high byte).

DATA PB7-0 I/O Bi-directional Data bus (Output when OE is low).

Table 124. Pin Values Used to Enter Programming Mode

Pin Symbol Value

PAGEL Prog_enable[3] 0

XA1 Prog_enable[2] 0

XA0 Prog_enable[1] 0

BS1 Prog_enable[0] 0

Table 125. XA1 and XA0 Coding

XA1 XA0 Action when XTAL1 is Pulsed

0 0 Load Flash or EEPROM Address (High or low address byte

determined by BS1).

0 1 Load Data (High or Low data byte for Flash determined by BS1).

1 0 Load Command

1 1 No Acti on, Idle

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Serial Programming Pin

Mapping

Table 126. Command Byte Bit Coding

Command Byte Command Executed

1000 0000 Chip Erase

0100 0000 Write Fuse bits

0010 0000 Write Lock bits

0001 0000 Write Flash

0001 0001 Write EEPROM

0000 1000 Read Signature Bytes and Calibration byte

0000 0100 Read Fuse and Lock bits

0000 0010 Read Flash

0000 0011 Read EEPROM

Table 127. Pin Mapping Serial Programming

Symbol Pins I/O Description

MOSI PB2 I S erial Data in

MISO PB3 O Serial Data out

SCK PB1 I Serial Clock

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Parallel Programming

Enter Programming Mode The following algorithm puts the device in parallel programming mod e:

1. Apply 4.5 - 5.5V between VCC and GND.

2. Set RESET to “0” and toggle XTAL1 at least six times.

3. Set the Prog_enable pins listed in Table 124 on page 271 to “0000” and wait at

least 100 ns.

4. Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns

after +12V has been applied to RESET, will cause the device to fail entering pro-

gramming mode.

5. Wait at least 50 µs before sending a new command.

Considerations for Efficient

Programming The loaded command and address are retained in the device during programming. For

efficient pr ogramming, the following should be considered.

• The command need s only be loaded on ce when writing or reading multiple memory

locations.

• Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless

the EESAVE Fuse is programmed) and Flash after a Chip Erase.

• Address high byte needs only be loaded before programming or reading a new 256

word windo w in Flash or 256 byte EEPROM. This consideration also applies to

Signature bytes reading.

Chip Erase The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lock

bits are not reset until the program memory has been completely erased. The Fuse bits

are not changed. A Chip Erase must be performed befo re the Flash and/or EEPROM

are reprogrammed.

Note: 1. The EEPRPOM memory is preserved during Chip Erase if the EESAVE Fuse is

programmed.

Load Command “Chip Erase”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS1 to “0”.

3. Set DATA to “1000 0000”. This is the command for Chip Erase.

4. Give XTAL1 a positive pulse. This loads the comma nd.

5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low.

6. Wait until RDY/BSY goes high before loading a new command.

Programming the Flash The Flas h is organized in pages, se e Table 121 on page 26 9. When programming th e

Flash, the program data is latched into a page buffer. This allows one page of program

data to be programmed simultaneously. The following procedure describes how to pro-

gram the entire Flash memory:

A. Load Command “Write Flash”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS1 to “0”.

3. Set DATA to “0001 0000”. This is the command for Write Flash.

4. Give XTAL1 a positive pulse. This loads the comma nd.

B. Load Address Low byte

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1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS1 to “0”. This selects low address.

3. Set DATA = Address low byte (0x00 - 0xFF).

4. Give XTAL1 a positive pulse. This loads the address low byte.

C. Load Data Low Byte

1. Set XA1, XA0 to “01”. This enables data loading.

2. Set DATA = Data low byte (0x00 - 0xFF).

3. Give XTAL1 a positive pulse. This loads the data byte.

D. Load Data High Byte

1. Set BS1 to “1”. Th is selects high data byte.

2. Set XA1, XA0 to “01”. This enables data loading.

3. Set DATA = Data hig h byte (0x00 - 0xFF).

4. Give XTAL1 a positive pulse. This loads the data byte.

E. Latch Data

1. Set BS1 to “1”. Th is selects high data byte.

2. Give PAGEL a positive pulse . This latches the data bytes. (See Figure 121 for

signal waveform s)

F. Repeat B through E until the entire buffer is filled or until all data within the page is

loaded.

While the lower bits in th e address are mapped to words within the page, the higher bits

address the pages within the FLASH. This is illustrated in Figure 120 on page 275. Note

that if less than eight bit s are required to address word s in the page (pagesize < 256 ),

the most significant bit(s) in the address low byte are used to address the page when

performing a Page Write.

G. Load Address High byte

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS1 to “1”. This selects high address.

3. Set DATA = Address high byte (0x00 - 0xFF).

4. Give XTAL1 a positive pulse. This loads the address hig h byte.

H. Program Page

1. Give WR a negative pulse. This starts programming of the entire page of data.

RDY/BSY goes low.

2. Wait until RDY/BSY goes high (See Figure 121 for signal waveforms).

I. Repeat B through H until the entire Flash is programmed or until all data has been

programmed.

J. End Page Programming

1. 1. Set XA1, XA0 to “10”. This enables command loading.

2. Set DATA to “0000 0000”. This is the command for No Operation.

3. Give XTAL1 a positive pulse . This lo ads th e com mand, and t he inte rnal write sig-

nals are reset.

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Figure 120. Addressing the Flash Which is Organized in Pages(1)

Note: 1. PCPAGE and PCW ORD are listed in Table 121 on page 269.

Figure 121. Programming the Flash Waveforms(1)

Note: 1. “XX” is don’t care. The letters refer to the programming description above.

Programming the EEPROM The EEPROM is organized in pa ges, see Table 122 on page 269. When programming

the EEPROM, the program data is latched into a page buffer. This allows one page of

data to be programmed simultaneously. The programming algorithm for the EEPROM

data memory is as follows (refer to “Programming the Flash” on page 273 for details on

Command, Address and Data loading):

1. A: Load Command “0001 0001”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. C: Load Data (0x00 - 0xFF).

5. E: Latch data (give PAGEL a posit ive pulse).

PROGRAM MEMORY

WORD ADDRESS

WITHIN A PAGE

PAGE ADDRESS

WITHIN THE FLASH

INSTRUCTION WORD

PA G E PCWORD[PAGEMSB:0]:

PAGEEND

PA G E

PCWORDPCPAGE

PCMSB PAGEMSB

PROGRAM

COUNTER

RDY/BSY

ESET +12V

PAGEL

BS2

0x10 ADDR. LOW ADDR. HIGH

DATA DATA LOW DATA HIGH ADDR. LOW DATA LOW DATA HIGH

XA1

XA0

BS1

XTAL1

XX XX XX

ABCDEBCDEGH

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K: Repeat 3 through 5 until the entire buffer is filled.

L: Program EEPROM page

1. Set BS to “0”.

2. Give WR a negative pulse. This starts programming of the EEPROM page.

RDY/BSY goes low.

3. Wait until to RDY/BSY goes high bef or e progr ammin g the ne xt page (See Figure

122 for signal waveforms).

Figure 122. Programming the EEPROM Waveforms

Reading the Flash The algorithm for reading the Flash memory is as follows (refer to “Programming the

Flash” on page 273 for details on Command and Address loading):

1. A: Load Command “0000 0010”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. Set OE to “0”, and BS1 to “0”. The Flas h word lo w b yte can no w be read at DATA.

5. Set BS to “1”. The Flash word high byte can now be read at DATA.

6. Set OE to “1”.

Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to “Programming the

Flash” on page 273 for details on Command and Address loading):

1. A: Load Command “0000 0011”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at

DATA.

5. Set OE to “1”.

RDY/BSY

ESET +12V

PAGEL

BS2

0x11 ADDR. HIGH

DATA ADDR. LOW DATA ADDR. LOW DATA XX

XA1

XA0

BS1

XTAL1

AGBCEB C EL

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Programming the Fuse Low

Bits The algorithm for programming the Fuse Low bits is as follows (refer to “Programming

the Flash” on pag e 273 for details on Command and Data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. Give WR a negative pulse and wait for RDY/BSY to go high.

Programming the Fuse High

Bits The algorithm for programming the Fuse Hig h bits is as follows (refer to “Programming

the Flash” on pag e 273 for details on Command and Data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. Set BS1 to “1” and BS2 to “0”. This selects high fuse byte.

4. Give WR a negative pulse and wait for RDY/BSY to go high.

5. Set BS1 to “0”. This selects low data byte.

Programming the Extended

Fuse Bits The algorithm for programming the Extended Fuse bits is as follows (refer to “Program-

ming the Flash” on page 273 for details on Command and Data loading):

1. 1. A: Load Command “0100 0000”.

2. 2. C: Load Data Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. 3. Set BS1 to “0” and BS2 to “1”. This selects extended fuse byte.

4. 4. Give WR a negative pulse and wait for RDY/BSY to go high.

5. 5. Set BS2 to “0”. This selects low data byte.

Figure 123. Programming the FUSES Waveforms

Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to “Programming the

Flash” on page 273 for details on Command and Data loading):

1. A: Load Command “0010 0000”.

2. C: Load Data Low Byte. Bit n = “0” prog rams the Lock bit. If LB mode 3 is pro-

grammed (LB1 and LB2 is programmed), it is not possible to program the Boot

Lock bits by any External Programming mode.

3. Give WR a negative pulse and wait for RDY/BSY to go high.

The Lock bits can only be cleared by executing Chip Erase.

RDY/BSY

RESET +12V

PAGEL

0x40

DATA DATA XX

XA1

XA0

BS1

XTAL1

0x40 DATA XX

Write Fuse Low byte Write Fuse high byte

0x40 DATA XX

Write Extended Fuse byte

BS2

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Reading the Fuse and Lock

Bits The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming

the Flash” on pag e 273 for details on Command loading):

1. A: Load Command “0000 0100”.

2. Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can

now be read at DATA (“0” means programmed).

3. Set OE to “0”, BS2 to “1” and BS1 to “1”. The status of the Fuse High bits can

now be read at DATA (“0” means programmed).

4. Set OE to “0”, BS2 to “1”, and BS1 to “0”. The status of the Exte nded Fuse bits

can now be read at DATA (“0” means programmed).

5. Set OE to “0”, BS2 to “0” and BS1 to “1”. The status of the Lock bits can now be

read at DATA (“0” means programmed).

6. Set OE to “1”.

Figure 124. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read

Reading the Signature Byte s The algorithm for reading the Signature bytes is as follows (refer to “Programming the

Flash” on page 273 for details on Command and Address loading):

1. A: Load Command “0000 1000”.

2. B: Load Address Low Byte (0x00 - 0x02).

3. Set OE to “0”, and BS to “0”. The selected Signature byte can now be read at

DATA.

4. Set OE to “1”.

Reading the Calibration Byte The algorithm for reading the Calibration byte is as follows (refer to “Programming the

Flash” on page 273 for details on Command and Address loading):

1. A: Load Command “0000 1000”.

2. B: Load Address Low Byte, 0x00.

3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.

4. Set OE to “1”.

Lock Bits 0

BS2

Fuse High Byte

BS1

DATA

Fuse Low Byte 0

BS2

Extended Fuse Byte

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Parallel Programming

Characteristics Figure 125. Parallel Programming Timing, Including some General Timing

Requirements

Figure 126. Parallel Programming Timing, Loading Sequence with Timing

Requirements(1)

Note: 1. The timing requirements shown in Figure 125 (i.e., tDVXH, tXHXL, and tXLDX) also apply

to loading operation.

Data & Contol

(

DATA, XA0/1, BS1, BS2)

XTAL1

XHXL

WLWH

DVXH

XLDX

PLWL

WLRH

RDY/BSY

PAGEL

PHPL

PLBX

BVPH

XLWL

WLBX

BVWL

WLRL

XTAL1

AGEL

PLXH

XLXH

XLPH

ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)

DATA

BS1

XA0

XA1

LOAD ADDRESS

(LOW BYTE) LOAD DATA

(HIGH BYTE)

LOAD DATA

LOAD ADDRESS

(LOW BYTE)

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Figure 127. Parallel Programming Timing, Reading Sequence (within the Same Page)

with Timing Requirements(1)

Note: 1. The timing requirements shown in Figure 125 (i.e., tDVXH, tXHXL, and tXLDX) also apply

to reading operation.

Table 128. Parallel Programming Characteristics, VCC = 5V ± 10%

Symbol Parameter Min Typ Max Units

VPP Programming Enable Voltage 11.5 12.5 V

IPP Programming Enable Current 250 µA

tDVXH Data and Control Valid before XTAL1 High 67 ns

tXLXH XTAL1 Low to XTAL1 High 200 ns

tXHXL XTAL1 Pulse Width High 150 ns

tXLDX Data and Control Hold after XTAL1 Low 67 ns

tXLWL XTAL1 Low to WR Low 0 ns

tXLPH XTAL1 Low to PAGEL high 0 ns

tPLXH PAGEL low to XTAL1 high 150 ns

tBVPH BS1 Valid before PAGEL High 67 ns

tPHPL PAGEL Pulse Width High 150 ns

tPLBX BS1 Hold after PAGEL Lo w 67 ns

tWLBX BS2/1 Hold after WR Low 67 n s

tPLWL PAGEL Low to WR Low 67 ns

tBVWL BS1 Valid to WR Low 67 ns

tWLWH WR Pulse Width Low 150 ns

tWLRL WR Low to RDY/BSY Low 0 1 µs

tWLRH WR Low to RDY/BSY High(1) 3.7 4.5 ms

tWLRH_CE WR Low to RDY/BSY High for Chip Erase(2) 7.5 9 ms

tXLOL XTAL1 Low to OE Low 0 ns

TAL1

ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)

DATA

BS1

XA0

XA1

LOAD ADDRESS

(LOW BYTE) READ DATA

(HIGH BYTE) LOAD ADDRESS

(LOW BYTE)

BVDV

OLDV

XLOL

OHDZ

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Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock

bits commands.

2. tWLRH_CE is v alid for the Chip Erase command.

Serial Downloading Both the Flash and EEPROM memo ry arrays can be progra mmed using the serial SPI

bus while RESET is pulled to GND. The serial interface co nsists of pins SCK, MOSI

(input) and MISO (output). After RESET is set low, the Programming Enable instruction

needs to be executed first before program/erase operations can be executed. NOTE, in

Table 127 on page 27 2, the p i n mapp ing f o r SPI pr ogr amm ing i s listed. Not all part s use

the SPI pins dedicated for the internal SPI interface.

Figure 128. Serial Programming and Verify(1)

Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock

source to the XTAL1 pin.

2. VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 1.8 - 5.5V

When programming the EEPROM, an auto-erase cy cle is built into the self-timed pro-

gramming operation (in the Serial mode ONLY) and there is no need to first execute the

Chip Erase instruction. The Chip Erase operation turns the content of every m emory

location in both the Program and EEPROM arrays into 0xFF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high

periods for the serial clock (SCK) input are defined as follows:

Low:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

High:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

tBVDV BS1 Valid to DATA valid 0 250 ns

tOLDV OE Low to DATA Valid 250 ns

tOHDZ OE High to DATA Tri-stated 250 ns

Table 128. Parallel Programming Characteristics, VCC = 5V ± 10% (Continued)

Symbol Parameter Min Typ Max Units

VCC

GND

XTAL1

SCK

MISO

MOSI

RESET

+1.8 - 5.5V

AVCC

+1.8 - 5.5V

(2)

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Serial Pro gramming

Algorithm When writing serial data to the ATmega169, data is clocked on the rising edge of SCK.

When reading data from the ATm ega169, data is clocked on the falling edge of SCK.

See Figure 129 for timing details.

To program and verify the ATmega169 in the serial pro gramming mode, the following

sequence is recommended (See four byte instruction formats in Table 130):

1. Power-up sequence:

Apply power between VCC and GND while RESET and SCK are set to “0”. In

some systems, the programmer can not guarantee that SCK is held low during

power-up. In this case, RESET must be given a positive pulse of at least two

CPU clock cycles duration after SCK has been set to “0”.

2. Wait for at least 20 ms and enable serial programming by sending the Program-

ming Enab le serial instruction to pin MOSI.

3. The ser ial programming instructions will not work if the communication is out of

synchronization. When in sync. the second byte (0x53), will echo back when

issuing the third byte of the Programming Enable instruction. Whether the echo

is correct or not, all four bytes of the instruction must be transmitted. If the 0x53

did not echo back, give RESET a positive pulse and issue a new Programming

Enable command.

4. The Flash is programmed one page at a time. The page size is found in Table

121 on page 269. The memory page is loaded one byte at a time by supplying

the 6 LSB of the address and data together with the Load Program Memory

Page instruction. To ensure correct loading of the page, the data low byte must

be loaded before data high byte is applied for a given address. The Program

Memor y Page is stored by loading the Write Program Memory Page instr uction

with the 7 MSB of the address. If polling (RDY/BSY) is not used, the user must

wait at least tWD_FLASH before issuing the next page. (See Table 129.) Accessing

the serial programming interface before the Flash write operation completes can

result in incorrect programming.

5. A: The EEPROM array is programmed one byte at a time by supplying the

address and data together with the appropriate Write instruction. An EEPROM

memory location is first automatically erased before new data is written. If polling

(RDY/BSY) is not used, the user must wait at least tWD_EEPROM before issuing the

next byte (See Table 129). In a chip erased device, no 0xFFs in the data file(s)

need to be programmed.

B: The EEPROM array is programmed one page at a time. The Memory page is

loaded one byte at a time by supplying the 2 LSB of the address and data

together with the Load EEPROM Memory Page instruction. The EEPROM Mem-

or y Page is stored by loading the Write EEPROM Memory Page Instruction with

the 4 MSB of the address. When using EEPROM page access only byte loca-

tions loaded with the Load EEPROM Memory Page instruction is altered. The

remaining locations remain unchanged. If polling (RDY/BSY) is not used, the user

must wait at least tWD_EEPROM before issuing the next page (See Table 129). In a

chip erased device, no 0xFF in the data file(s) need to be programmed.

6. Any memory location can be verified by using the Read instruction which returns

the content at the selected address at serial output MISO.

7. At the end of the programming session, RESET can be set high to commence

normal operation.

8. Power-off sequence (if needed):

Set RESET to “1”.

Turn VCC power off

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Figure 129. Serial Programming Waveforms

Table 129. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location

Symbol Minimum Wait Delay

tWD_FUSE 4.5 ms

tWD_FLASH 4.5 ms

tWD_EEPROM 9.0 ms

tWD_ERASE 9.0 ms

MSB

LSB

SERIAL CLOCK INPUT

(SCK)

SERIAL DATA INPUT

(MOSI)

(MISO)

SAMPLE

ERIAL DATA OUTPUT

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Table 130. Serial Programming Instruction Set

Instruction

Instruction Format

OperationByte 1 Byte 2 Byte 3 Byte4

Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after

RESET goes low.

Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash.

Read Program Memory 0010 H000 000a aaaa bbbb bbbb oooo oooo Read H (high or low) data o from

Program memory at word address a:b.

Load Program Memory Page 0100 H000 000x xxxx xxbb bbbb iiii iiii Write H (high or lo w) data i to Prog r am

Memory page at word address b. Data

low byte must be loaded before Data

high byte is applied within the same

address.

Write Program Memory Page 0100 1100 000a aaaa bbxx xxxx xxxx xxxx Write Program Memory Page at

address a:b.

Read EEPROM Memory 1010 0000 000x xxaa bbbb bbbb oooo oooo Read data o from EEPROM memory at

address a:b.

Write EEPROM Memory 1100 0000 000x xxaa bbbb bbbb iiii iiii Write data i to EEPROM memory at

address a:b.

Load EEPROM Memory

Page (page access) 1100 0001 0000 0000 0000 00bb iiii iiii Load data i to EEPROM memory page

buffer. After data is loaded, program

EEPROM page.

Write EEPROM Memory

Page (page access) 1100 0010 00xx xxaa bbbb bb00 xxxx xxxx Wr ite EEPROM page at address a:b.

Read Lock bits 0101 1000 0000 0000 xxxx xxxx xxoo oooo Read Lock bits . “0” = programmed, “1”

= unprogrammed. See Table 116 on

page 266 for details.

Write Lock bits 1010 1100 111x xxxx xxxx xxxx 11ii iiii Write Lock bits. Set bits = “0” to

program Lock bits. See Table 116 on

page 266 for details.

Read Signatu re Byte 0011 0000 000x xxxx xxxx xxbb oooo oooo Read Signature Byte o at address b.

Write Fuse bits 1010 1100 1010 0000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to

unprogram. See Table 88 on page 205

for details.

Write Fuse High bits 1010 1100 1010 1000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to

unprogram. See Table 87 on page 198

for details.

Write Extended Fuse Bits 1010 1100 1010 0100 xxxx xxxx xxxx iii1Set bits = “0” to program, “1” to

unprogram. See Table 118 on page

267 for details.

Read Fuse bits 0101 0000 0000 0000 xxxx xxxx oooo oooo Read Fuse bits. “0” = prog r ammed, “1”

= unprogrammed. See Table 88 on

page 205 for details.

Read Fuse High bits 0101 1000 0000 1000 xxxx xxxx oooo oooo Read Fuse High bits. “0” = pro-

grammed, “1” = unprogrammed. See

Table 87 on page 198 for details.

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Note: a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care

SPI Serial Programming

Characteristics For characteristics of the SPI module see “SPI Timing Characteristics” on page 301.

Programming via the

JTAG Interface Programming through the JTAG interface requires control of the four JTAG specific

pins: TCK, TMS, TDI, and TDO. Control of the reset and clock pins is not required.

To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The

device is default shipp ed with the fuse progra mmed. In additio n, the JTD bit in MCUCSR

must be cleare d. Alter natively , if the J TD bit is set, th e exte rnal reset ca n be f orced lo w.

Then, the JTD bit will be cleared after two chip cloc ks, and the JTAG pins are available

for programming. This provides a means of using the JTAG pins as normal port pins in

Running mode while still allowing In-System Programming via the JTAG interface. Note

that this techni que can not be used when us ing the JTAG pins f or Boundary-scan or On-

chip Debug. In these cases the JTAG pins must be dedicated for this purpose.

During programming the clock frequency of the TCK Input must be less than the maxi-

mum frequency of the chip. The System Clock Prescaler can not be used to divide the

TCK Clock Input into a sufficiently low frequency.

As a definition in this datasheet, the LSB is shifted in and out first of all Shift Registers.

Programming Specific JTAG

Instructions The Instruction Register is 4-bit wide, supporting up to 16 instructions. The JTAG

instructions us ef ul for prog ra mmi n g are liste d be lo w.

The OPCODE for each instruction is shown behind the instruction name in hex format.

The text describes which Data Register is selected as path between TDI and TDO for

each instruction.

The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can

also be used as an idle state between JTAG sequences. T he state machine sequence

for changing the instruction word is shown in Figure 130.

Read Extended Fuse Bits 0101 0000 0000 1000 xxxx xxxx oooo oooo Read Extended Fuse bits. “0” = pro-

grammed, “1” = unprogrammed. See

Table 118 on page 267 for details.

Read Calibration Byte 0011 1000 000x xxxx 0000 0000 oooo oooo Read Calibration Byte

Poll RDY/BSY 1111 0000 0000 0000 xxxx xxxx xxxx xxxoIf o = “1”, a programming operation is

still busy. Wait until this bit return s to

“0” before applying another command.

Table 130. Serial Programming Ins truction Set (Con tinued )

Instruction

Instruction Format

OperationByte 1 Byte 2 Byte 3 Byte4

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Figure 130. State Machine Sequence for Chang ing the Instruction Word

AVR_RESET (0xC) The AVR specific public JTAG instruction for setting the AVR device in the Reset mode

or taking the device out from the Reset mode. The TAP controller is not reset by this

instruction. The one bit Reset Register is selected as Data Register. Note that the reset

will be active as long as there is a logic “one” in the Reset Chain. The output from this

chain is not latched.

The active states are:

• Shift-DR: The Reset Register is shifted by the TCK input.

PROG_ENABLE (0x4) The AVR specific public JTAG instruction for enabling programming via the JTAG port.

The 16-bit Programmin g Enable Register is select ed as Data Register. The active states

are the following:

• Shift-DR: The programming enable signature is shifted into the Data Register.

• Update-DR: The programming enable signat ure is compared to the correct value,

and Programming mode is entered if the signature is valid.

Test-Logic-Reset

Run-Test/Idle

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

Select-IR Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

Select-DR Scan

Capture-DR

011 1

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PROG_COMMANDS (0x5) The AVR specific public JTAG instruction for entering programming comman ds via the

JTAG port. The 15-bit Programming Command Register is selected as Data Register.

The active states are the following:

• Capture-DR: The result of the previous command is loaded into the Data Register.

• Shift-DR: The Dat a Register is shift ed b y the TCK input , shifting out the result of the

previous command and shifting in the new command.

• Update-DR: The pr ogramming co mmand is applied to the Flash inputs

• Run-Test/Idle: One clock cycle is generated, executing the applied command (not

always required, se e Ta b le 13 1 be low).

PROG_PAGELOAD (0x6) The AVR specific public JTAG instruction to directly load the Flash data page via the

JTAG port. An 8-bit Flash Data Byte Register is selected as the Data Register. This is

ph ysically t he 8 LSBs of the Prog r amming Co mmand Registe r. The a ctive states ar e the

following:

• Shift-DR: The Flash Data Byte Register is shifted by the TCK input.

• Update-DR: The cont en t of th e Fl ash Dat a Byte Reg iste r is cop ied into a te mpo r ary

the temporary registe r into the Flash page buffer. The AVR automatically alternates

between writing the low and the high byte for each new Update-DR state, starting

with the low byte for the first Update-DR enco un te re d afte r en te ring the

PROG_PAGELOAD command. The Program Counter is pre- incremented before

writing the low byte , except f or the first written byte. This ensures that the first data is

writte n to the ad d ress set up by PROG_COMMANDS, and loading the last location

in the page buffer does not make the program counter increment into the next page.

PROG_PAGEREAD (0x7) The AVR specific public JTAG instruction to directly capture the Flash content via the

JTAG port. An 8-bit Flash Data Byte Register is selected as the Data Register. This is

ph ysically t he 8 LSBs of the Prog r amming Co mmand Registe r. The a ctive states ar e the

following:

• Capture-DR: The content of the selected Flash byte is captured into the Flash Data

Byte Register. The AVR automatically alternates between reading the low and the

high byte for each new Capture-DR state, starting with the low byte for the first

Capture-DR encountered after en tering the PROG_PAGEREAD comman d. The

Program Counter is post-incremented after reading each high byte, including the

first read byte. This ensures that the first data is captured from the first address set

up by PROG_COMMANDS, and reading the la st location in the page makes the

program counter increment into the next page.

• Shift-DR: The Flash Data Byte Register is shifted by the TCK input.

Data Registers The Data Registers are selected by the JTAG instruction registers described in section

“Programming Spec ific JTAG Instructions” on page 285. The Dat a Registers rele vant for

programming operations are:

• Reset Register

• Programming Enable Register

• Programming Command Register

• Flash Data Byte Register

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Reset Register The Reset Register is a Test Data Register used to reset the part during programming. It

is required to reset the part before entering Programming mode.

A high value in the Reset Register corresponds to pulling the external reset low. The

part is reset as long as there is a high valu e present in the Reset Register. Depending

on the Fuse settings for the clock options, the part will remain reset for a Reset Time-out

period (refer to “Clock Sources” on page 2 4) after re leasing the Reset Register. The out-

put from this Data Register is not latched, so the reset will take place immediately, as

shown in Figure 108 on page 234.

Programming Enable Register The Programming Enable Register is a 16-b it register. The conten ts of this register is

compared to the programming enable signature, binary code

0b1010_0011_0111_0000. When the contents of the register is equal to the program-

ming enable signature, programming via the JTAG port is enabled. The register is reset

to 0 on Power-on Reset, and should always be reset when leaving Programming mode.

Figure 131. Programming Enable Register

TDI

TDO

=DQ

ClockDR & PROG_ENABLE

Programming Enable

0xA370

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Programming Command

ally shift in programming commands, and to serially shift out the result of the previous

command, if any. The JTAG Programming Instruction Set is shown in Table 131. The

state sequence when shifting in the programming commands is illustrated in Figure 133.

Figure 132. Programming Command Register

TDI

TDO

Flash

EEPROM

Fuses

Lock Bits

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Table 131. JTAG Programming Instruction

Set

a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don ’t care

Instruction TDI Sequence TDO Sequence Notes

1a. Chip Erase 0100011_10000000

0110001_10000000

0110011_10000000

xxxxxxx_xxxxxxxx

1b. Poll for Chip Erase Complete 0110011_10000000 xxxxxox_xxxxxxxx (2)

2a. Enter Flash Write 0100011_00010000 xxxxxxx_xxxxxxxx

2b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (9)

2c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx

2d. Load Data Low Byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx

2e. Load Data High Byte 0010111_iiiiiiii xxxxxxx_xxxxxxxx

2f. Latch Data 0110111_0000000 0

1110111_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

(1)

2g. Write Flash Page 0110111_00000000

0110101_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

(1)

2h. Poll for Page Write Complete 0110111_0000000 0 xxxxxox_xxxxxxxx (2)

3a. Enter Flash Read 0100011_00000010 xxxxxxx_xxxxxxxx

3b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (9)

3c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx

3d. Read Data Low and High Byte 0110010_00000000

0110110_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

xxxxxxx_oooooooo Low byte

High byte

4a. Enter EEPROM Write 0100011_00010001 xxxxxxx_xxxxxxxx

4b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (9)

4c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx

4d. Load Data Byte 0 010011_iiiiiiii xxxxxxx_xxxxxxxx

4e. Latch Data 0110111_0000000 0

1110111_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

(1)

4f. Wr ite EEPROM Page 0110011_ 00000000

0110001_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

(1)

4g. Poll for Page Write Complete 0110011_0000000 0 xxxxxox_xxxxxxxx (2)

5a. Enter EEPROM Read 0100011_00000011 xxxxxxx_xxxxxxxx

5b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (9)

5c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx

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5d. Read Data Byte 0110011_bbbbbbbb

0110010_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

6a. Enter Fuse Write 0100011_01000000 xxxxxxx_xxxxxxxx

6b. Load Data Low Byte(6) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3)

6c. Write Fuse Extended Byte 0111011_00000000

0111001_00000000

0111011_00000000

xxxxxxx_xxxxxxxx

(1)

6d. Poll for Fuse Write Complete 0110111_00000000 xxxxxox_xxxxxxxx (2)

6e. Load Data Low Byte(7) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3)

6f. Write Fuse High Byte 0110111_00000000

0110101_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

(1)

6g. Poll for Fuse Write Complete 0110111_00000000 xxxxxox_xxxxxxxx (2)

6h. Load Data Low Byte(7) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3)

6i. Write Fuse Low Byte 0110011_00000000

0110001_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

(1)

6j. Poll for Fuse Write Complete 0110011_000 00000 xxxxxox_xxxxxxxx (2)

7a. Enter Lock Bit Write 0100011_00100000 xxxxxxx_xxxxxxxx

7b. Load Data Byte(9) 0010011_11iiiiii xxxxxxx_xxxxxxxx (4)

7c. Write Lock Bits 0110011_0000000 0

0110001_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

(1)

7d. Poll for Lock Bit Write complete 0110011_00000000 xxxxxox_xxxxxxxx (2)

8a. Enter Fuse/Lock Bit Read 0100011_00000100 xxxxxxx_xxxxxxxx

8b. Read Extended Fuse Byte(6) 0111010_00000000

0111011_00000000 xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

8c. Read Fuse High Byte(7) 0111110_00000000

0111111_00000000 xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

8d. Read Fuse Low Byte(8) 0110010_00000000

0110011_00000000 xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

8e. Read Lock Bits(9) 0110110_00000000

0110111_00000000 xxxxxxx_xxxxxxxx

xxxxxxx_xxoooooo (5)

Table 131. JTAG Programming Instruction (Continued)

Set (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte , o = da ta ou t, i = data in, x = don’t care

Instruction TDI Sequence TDO Sequence Notes

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Notes: 1. This command sequence is not req uired if the seven MSB are correctly set by the previous command sequence (which is

nor mally the case).

2. Repeat until o = “1”.

3. Set bits to “0” to program the corresponding Fuse, “1” to unprogram the Fuse.

4. Set bits to “0” to program the corresponding Lock bit, “1” to leave the Lock bit unchanged.

5. “0” = programmed, “1” = unprogrammed.

6. The bit mapping for Fuses Extended byte is listed in Table 118 on page 267

7. The bit mapping for Fuses High byte is listed in Table 119 on page 268

8. The bit mapping for Fuses Low byte is listed in Table 120 on page 268

9. The bit mapping for Lock bits byte is listed in Table 116 on page 266

10.Address bits exceeding PCMSB and EEAMSB (Table 121 and Table 122) are don’t care

11.All TDI and TDO sequences are represented by binar y digits (0b...).

8f . Read Fuses and Lock Bits 0111010_00000000

0111110_00000000

0110010_00000000

0110110_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

(5)

Fuse Ext. byte

Fuse High byte

Fuse Low byte

Lock bits

9a. Enter Signature Byte Read 0100011_00001000 xxxxxxx_xxxxxxxx

9b. Load Address Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx

9c. Read Signature Byte 0110010_00000000

0110011_00000000 xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

10a. Enter Calibration Byte Read 0100011_00001000 xxxxxxx_xxxxxxxx

10b. Load Address Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx

10c. Read Calibration Byte 0110110_00000000

0110111_00000000 xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

11a. Load No Operation Command 0100011_00000000

0110011_00000000 xxxxxxx_xxxxxxxx

xxxxxxx_xxxxxxxx

Table 131. JTAG Programming Instruction (Continued)

Set (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte , o = da ta ou t, i = data in, x = don’t care

Instruction TDI Sequence TDO Sequence Notes

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Figure 133. State Machine Sequence for Chang ing/Reading the Data Word

Flash Data Byte Register The Flash Data Byte Register provides an efficient way to load the entire Flash page

buffer before executing Page Write, or to read out/verify t he content of the Flash. A state

machine sets up the control signals to the Flash and senses the strobe signals from the

Flash, thus only the data words need to be shifted in/out.

The Flash Data Byte Register actually consists of the 8-bit scan chain and a 8- bit tempo-

rary register. During page load, the Update-DR state copies the content of the scan

chain over to the temporar y register and initiates a write sequence that within 11 TCK

cycles loads the content of the temporary register into the Flash page buffer. The AVR

automatically alternates betwe en writing the lo w a nd the hig h b y te for each new Update-

DR state, star ting with the low byte for the first Update-DR encountered after entering

the PROG_PAGELOAD command. The Program Counter is pre-incremented before

writing the low byte, except for the first written byte. This ensures that the first data is

written to the address set up by PROG_COMMANDS, and loading the last location in

the page buffer does not make the Program Counter increment into the next page.

During Page Read, the content of the selected Flash byte is captured into the Flash

Data Byte Register during the Capture-DR state. The AVR automatically alternates

between reading the low and the high byte for each new Capture-DR state, starting with

the low byte for the first Capture-DR encountered after entering the PROG_PAGEREAD

command. The Program Counter is post-incremented after reading each high byte,

Test-Logic-Reset

Run-Test/Idle

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

Select-IR Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

Select-DR Scan

Capture-DR

011 1

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including the first read byte. This ensures that the first data is captured from the first

address set up b y PR OG_COMMANDS , an d reading the last location in the page mak es

the program counter increment into the next page.

Figure 134. Flash Data Byte Register

The state machine controlling the Flash Data Byte Regis ter is clocked by TCK. During

normal operation in which eight bits are shifted for each Flash byte, the clock cycles

needed to na vigate through the TAP controlle r automa tically feeds th e state m achine for

the Flash Data Byte Register with sufficien t number of clock pulses to complete its ope r-

ation transparently for the user. However, if too few bits are shifted between each

Update-DR state during page load, the TAP controller should stay in the Run-Test/Idle

state for some TCK cycles to ensure that there are at least 11 TCK cycles between each

Update-DR state.

Programming Algorithm All references below of type “1a”, “1b”, and so on, refer to Table 131.

Entering Programming Mode 1. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register.

2. Enter instruction PROG_ENABLE and shift 0b1010_0011_0111_0000 in the

Programming Enable Register.

Leaving Programming Mode 1. Enter JTAG instruction PROG_COMMANDS.

2. Disable all programming instructions by using no oper ation instruction 11a.

3. Enter instruction PROG_ENABLE and shift 0b0000_0000_0000_0000 in the

programming Enable Register.

4. Enter JTAG instruction AVR_RESET and shift 0 in the Reset Register.

Performing Chip Erase 1. Enter JTAG instruction PROG_COMMANDS.

2. Start Chip Erase using programming ins truction 1a.

3. Poll for Chip Erase complete using programming instruction 1b, or wait for

tWLRH_CE (refer to Table 128 on page 280).

TDI

TDO

Flash

EEPROM

Fuses

Lock Bits

STROBES

ADDRESS

State

Machine

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Programming the Flash Before programming the Flash a Chip Erase must be performed, see “Performing Chip

Erase” on page 294.

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Flash write using programming instruction 2a.

3. Load address High byte using programming instruction 2b.

4. Load address Low byte using programming instruction 2c.

5. Load data using programming instructions 2d, 2e and 2f.

6. Repeat steps 4 and 5 for all instruction words in the page.

7. Write the page using programming instruction 2g.

8. Poll for Flash write complete using programming instruction 2h, or wait for tWLRH

(refer to Table 128 on page 280).

9. Repeat steps 3 to 7 until all data have been programmed.

A more efficient data transfer can be achieved using the PROG_PAGELOAD

instruction:

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Flash write using programming instruction 2a.

3. Load the page address using programming instructions 2b and 2c. PCWORD

(ref er to Table 121 on page 269) is used to add ress within one page an d must be

writte n as 0.

4. Enter JTAG instruction PROG_PAGELOAD.

5. Load the entire page by shifti ng in all instruction wor ds in the pag e byte-b y-byte ,

starting with the L SB of the fir st inst ruction in the page an d e nding wit h th e MS B

of the last instruction in the page. Use Update-DR to copy the contents of the

Flash Data Byte Regist e r into th e Flash pag e loca tio n an d to a ut o-i ncre ment t he

Program Counter before each new word.

6. Enter JTAG instruction PROG_COMMANDS.

7. Write the page using programming instruction 2g.

8. Poll for Flash write complete using programming instruction 2h, or wait for tWLRH

(refer to Table 128 on page 280).

9. Repeat steps 3 to 8 until all data have been programmed.

Reading the Flash 1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Flash read using programming instruction 3a.

3. Load address using programming instructions 3b and 3c.

4. Read data using programming instruction 3d.

5. Repeat steps 3 an d 4 un til all da ta have been read.

A more efficient data transfer can be achieved using the PROG_PAGEREAD

instruction:

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Flash read using programming instruction 3a.

3. Load the page address using programming instructions 3b and 3c. PCWORD

(ref er to Table 121 on page 269) is used to add ress within one page an d must be

writte n as 0.

4. Enter JTAG instruction PROG_PAGEREAD.

5. Read the entire page (or Flash) by shifting out all instruction words in the page

(or Flash), starting with the LSB of the first instruction in the page (Flash) and

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ending with the MSB of the last instruction in the page (Flash). The Capture-DR

state both captures the data from the Flash , and also auto-increments th e pro-

gram counter after each word is read. Note that Capture-DR comes before the

shift-DR state. Hence, the first byte which is shifted out contains valid data.

6. Enter JTAG instruction PROG_COMMANDS.

7. Repeat steps 3 to 6 until all data have been read.

Programming the EEPROM Before programming the EEPROM a Chip Erase must be performed, see “Performing

Chip Erase” on page 294.

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable EEPROM write using programming instruction 4a.

3. Load address High byte using programming instruction 4b.

4. Load address Low byte using programming instruction 4c.

5. Load data using programming instructions 4d and 4e.

6. Repeat steps 4 and 5 for all data bytes in the page.

7. Write the data using programming instruction 4f.

8. Poll for EEPROM write complete using programming instruction 4g, or wait for

tWLRH (refer to Table 128 on page 280).

9. Repeat steps 3 to 8 until all data have been programmed.

Note that the PROG_PAGELOAD instruction can not be used when programming the

EEPROM.

Reading the EEPROM 1. Enter JTAG instruction PROG_COMMANDS.

2. Enable EEPROM read using programming instruction 5a.

3. Load address using programming instructions 5b and 5c.

4. Read data using programming instruction 5d.

5. Repeat steps 3 an d 4 un til all da ta have been read.

Note that the PROG_PAGEREAD instruction can not be used when reading the

EEPROM.

Programming the Fuses 1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Fuse write using programming instruction 6a.

3. Load data high byte using progr amming instructions 6b. A bit v alue of “0” will pro-

gram the corresponding fuse, a “1” will unprogram the fuse.

4. Write Fuse High byte using programming instruction 6c.

5. Poll for Fuse write complete using programming instruction 6d, or wait for tWLRH

(refer to Table 128 on page 280).

6. Load data low byte using programming instructions 6e. A “0” will program the

fuse, a “1” will unprogram the fuse.

7. Write Fuse low byte using progr amming instruction 6f.

8. Poll for Fuse write complete using programming instruction 6g, or wait for tWLRH

(refer to Table 128 on page 280).

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Programming the Lock Bits 1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Lock bit write using progra mming instruction 7a.

3. Load data using programming instructions 7b. A bit value of “0” will program the

corresponding lock bit, a “1” will leave the lock bit unchanged.

4. Write Lock bits using progr amming instruction 7c.

5. Poll for Lock bit write complete using programming instruction 7d, or wait for

tWLRH (refer to Table 128 on page 280).

Reading the Fuses and Lock

Bits 1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Fuse/Lock bit read using programming instruction 8a.

3. To read all Fuses and Lock bits, use programming instruction 8e.

To only read Fuse High byte, use programming instruction 8b.

To only read Fuse Low byte, use programming instruction 8c.

To only read Lock bits, use programming instruction 8d.

Reading the Signature Byte s 1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Signature byte read using programming instruction 9a.

3. Load address 0x00 using programming instruction 9b.

4. Read first signature byte using programming instruction 9c.

5. Repeat steps 3 and 4 with address 0x01 and address 0x02 to read the second

and third signature bytes, respectively.

Reading the Calibration Byte 1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Calibr ation byte read using programming instruction 10a.

3. Load address 0x00 using programming instruction 10b.

4. Read the calibration byte using programming instruction 10c.

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Electrical Characteristics

Absolute Maximum Ratings*

DC Characteristics

Operating Te mperature.................................. -55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

Storage Temperature..................................... -65°C to +150°C

Voltage on any Pin except RESET

with respect to Ground ................................-0.5V to VCC+0.5V

Voltage on RESET with respect to Ground......-0.5V to +13.0V

Maximum Operating Voltage ............................................ 6.0V

DC Current per I/O Pin............................................... 40.0 mA

DC Current VCC and GND Pins................................ 400.0 mA

TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted)

Symbol Parameter Condition Min. Typ. Max. Units

VIL Input Low Voltage except

XTAL1 and RESET pins VCC = 1.8V - 2.4V

VCC = 2.4V - 5.5V -0.5

-0.5 0.2VCC(1)

0.3VCC(1) V

VIH Input High V oltage e xcept

XTAL1 and RESET pins VCC = 1.8V - 2.4V

VCC = 2.4V - 5.5V 0.7VCC(2)

0.6VCC(2) VCC + 0.5

VCC + 0.5 V

VIL1 Input Low Voltage

XTAL1 pins VCC = 1.8V - 5.5V -0.5 0.1VCC(1) V

VIH1 Input High Voltage,

XTAL1 pin VCC = 1.8V - 2.4V

VCC = 2.4V - 5.5V 0.8VCC(2)

0.7VCC(2) VCC + 0.5

VCC + 0.5 V

VIL2 Input Low Voltage,

RESET pins VCC = 1.8V - 5.5V -0.5 0.1VCC(1)

0.2VCC(1) V

VIH2 Input High Voltage,

RESET pins VCC = 1.8V - 5.5V 0.9VCC(2) VCC + 0.5 V

VOL Output Low Voltage(3),

Port A, C, D, E, F, G IOL = 10mA, VCC = 5V

IOL = 5mA, VCC = 3V 0.7

0.5 V

VOL1 Output Low Voltage(3),

Port B IOL = 20mA, VCC = 5V

IOL = 10mA, VCC = 3V 0.7

0.5 V

VOH Output High Voltage(4),

Port A, C, D, E, F, G IOH = -10mA, VCC = 5V

IOH = -5mA, VCC = 3V 4.2

2.3 V

VOH1 Output High Voltage(4),

Port B IOH = -20mA, VCC = 5V

IOH = -10mA, VCC = 3V 4.2

2.3 V

IIL Input Leakage

Current I/O Pin VCC = 5.5V, pin low

(absolute value) 1µA

IIH Input Leakage

Current I/O Pin VCC = 5.5V, pin high

(absolute value) 1µA

RRST Reset Pull-up Resistor 30 60 kΩ

RPU I/O Pin Pull-up Resistor 20 50 kΩ

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Note: 1. “Max” means the highest value where the pin is guaranteed to be read as low

2. “Min” means the lowest value where the pin is guaranteed to be read as high

3. Although each I/O port can sink mo re than the test condition s (20 mA at VCC = 5V, 10 mA at VCC = 3V for Por t B and 10 mA

at VCC = 5V, 5 mA at VCC = 3V for all other ports) under steady state conditions (non-transient), the following must be

observed:

TQFP and QFN/MLF Package:

1] The sum of all IOL, for all ports, should not exceed 400 mA.

2] The sum of all IOL, for ports A0 - A7, C4 - C7, G2 should not exceed 100 mA.

3] The sum of all IOL, for ports B0 - B7, E0 - E7, G3 - G5 should not exceed 100 mA.

4] The sum of all IOL, for ports D0 - D7, C0 - C3, G0 - G1 should not exceed 100 mA.

5] The sum of all IOL, for ports F0 - F7, should no t exceed 100 mA.

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test condition.

4. Although each I/O port can source more than the test conditions (20 mA at VCC = 5V, 10 mA at VCC = 3V f or Port B and 10mA

at VCC = 5V, 5 mA at VCC = 3V for all other ports) under steady state conditions (non-transient), the following must be

observed:

TQFP and QFN/MLF Package:

1] The sum of all IOH, for all ports, should not exceed 400 mA.

2] The sum of all IOH, for ports A0 - A7, C4 - C7, G2 should not exceed 100 mA.

3] The sum of all IOH, for ports B0 - B7, E0 - E7, G3 - G5 should not exceed 100 mA.

4] The sum of all IOH, for ports D0 - D7, C0 - C3, G0 - G1 should not exceed 100 mA.

5] The sum of all IOH, for ports F0 - F7, should not exceed 100 mA.

If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current

greater than the listed test condition.

ICC

Power Supply Current

(All bits set in the “Power

Reduction Register” on

page 34)

Active 1MHz, VCC = 2V 0.44 mA

Active 4MHz, VCC = 3V 2.5 mA

Active 8MHz, VCC = 5V 9.5 mA

Idle 1MHz, VCC = 2V 0.2 mA

Idle 4MHz, VCC = 3V 0.8 mA

Idle 8MHz, VCC = 5V 3.3 mA

Power-down mode WDT enabled, VCC = 3V <8 10 µA

WDT disabled, VCC = 3V <1 2 µA

VACIO Analog Comparator

Input Offset Voltage VCC = 5V

Vin = VCC/2 <10 40 mV

IACLK Analog Comparator

Input Leakage Current VCC = 5V

Vin = VCC/2 -50 50 nA

tACPD Analog Comparator

Propagation Delay VCC = 2.7V

VCC = 4.0V 750

500 ns

TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) (Continued)

Symbol Parameter Condition Min. Typ. Max. Units

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External Cloc k Drive

Waveforms Figure 135. External Clock Drive Waveforms

External Cloc k Drive

Maximum Speed vs. VCC Maximum frequency is depending on VCC. As shown in Figure 136 and Figure 137, the

Maximum Frequency vs. VCC curve is linear between 1.8V < VCC < 4.5V. To calculate

the maximum freque ncy at a given voltage in this interval, use this equation:

To calculate required voltage for a given frequency, use this equation::

At 3 Volt, this gives:

Thus, when VCC = 3V, maximum frequency will be 9.33 MHz.

At 6 MHz this gives:

Thus, a maximum freque ncy of 6 MHz requires VCC = 2.25V.

VIL1

VIH1

Table 132. External Clock Drive

Symbol Parameter

VCC=1.8-5.5V VCC=2.7-5.5V VCC=4.5-5.5V

UnitsMin. Max. Min. Max. Min. Max.

1/tCLCL

Oscillator

Frequency 0108016MHz

tCLCL Clock Period 1000 125 62.5 ns

tCHCX High Time 400 50 25 ns

tCLCX Low Time 400 50 25 ns

tCLCH Rise Time 2.0 1.6 0.5 µs

tCHCL Fall Time 2.0 1.6 0.5 µs

∆tCLCL

Change in period

from one clock

cycle to the ne xt 222%

Table 133. Constants used to calculate ma ximum speed vs. VCC

Vo ltag e and Frequency rang e abVxFy

2.7 < VCC < 4.5 or 8 < Frq < 16 8/1.8 1.8/8 2.7 8

1.8 < VCC < 2.7 or 4 < Frq < 8 1.8 4

Frequency a V Vx

–

()•Fy

Voltage b F Fy

–

()•Vx

Frequency

1.8

--------32.7–()•8+9.3

Voltage

1.8

--------64–()•1.8+2.2

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Figure 136. Maximum Frequency vs. VCC, ATmega169V

Figure 137. Maximum Frequency vs. VCC, ATmega169

SPI Timing

Characteristics See Figure 138 and Figure 139 for details.

MHz

1.8V 2.7V 5.5V

Safe Operating Area

6 MHz

8 MHz

2.7V 4.5V 5.5V

Safe Operating Area

Table 134. SPI Timing Parameters

Description Mode Min Typ Max

1 SCK period Master See Table 69

2 SCK high/low Master 50% duty cycle

3 Rise/Fall time Master 3.6

4 Setup Master 10

5HoldMaster 10

6 Out to SCK Master 0.5 • tsck

7 SCK to out Master 10

8 SCK to out high Master 10

9SS

low to out Slave 15

10 SCK period Slave 4 • tck

11 SCK high/low(1) Slave 2 • tck

12 Rise/F all time Slave 1.6 µs

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Note: 1. In SPI Programming mode the minimum SCK high/low period is:

- 2 tCLCL for fCK < 12 MHz

- 3 tCLCL for fCK > 12 MHz

Figure 138. SPI Interface Timing Requirements (Master Mode)

Figure 139. SPI Interface Timing Requirements (Slave Mode)

13 Setup Slave 10

14 Hold Slave tck

15 SCK to out Slave 15

16 SCK to SS high Slave 20

17 SS high to tri-state Slave 10

18 SS low to SCK Slave 20 • tck

Table 134. SPI Timing Parameters

Description Mode Min Typ Max

MOSI

(

Data Output)

SCK

(CPOL = 1)

MISO

(Data Input)

SCK

(CPOL = 0)

MSB LSB

LSBMSB

...

345

MISO

(

Data Output)

SCK

(CPOL = 1)

MOSI

(Data Input)

SCK

(CPOL = 0)

MSB LSB

LSBMSB

...

11 11

1213 14

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ADC Characteristics – Preliminary Data

Note: 1. VDIFF must be below VREF

Table 135. ADC Characteristics

Symbol Parameter Condition Min Typ Max Units

Resolution Single Ended Conversion 10 Bits

Differential Conversion 8 Bits

Absolute accuracy (Including

INL, DNL, quantization error,

gain and offset error)

Single Ended Conversion

VREF = 4V, VCC = 4V,

ADC clock = 200 kHz 22.5LSB

Single Ended Conversion

VREF = 4V, VCC = 4V,

ADC clock = 1 MHz 4.5 LSB

Single Ended Conversion

VREF = 4V, VCC = 4V,

ADC clock = 200 kHz

Noise Reduction Mode

2LSB

Single Ended Conversion

VREF = 4V, VCC = 4V,

ADC clock = 1 MHz

Noise Reduction Mode

4.5 LSB

Integral Non-Linearity (INL) Single End ed Conversion

VREF = 4V, VCC = 4V,

ADC clock = 200 kHz 0.5 LSB

Differential Non-Linearity (DNL) Single Ended Conversion

VREF = 4V, VCC = 4V,

ADC clock = 200 kHz 0.25 LSB

Gain Error Single End ed Conversion

VREF = 4V, VCC = 4V,

ADC clock = 200 kHz 2LSB

Offset Error Sin gle Ended Conversion

VREF = 4V, VCC = 4V,

ADC clock = 200 kHz 2LSB

Conversion Time Free Running Conversion 13 260 µs

Clock Frequency Single Ended Conversion 50 1000 kHz

AVCC Analog Supply Voltage VCC - 0.3 VCC + 0.3 V

VREF Reference Voltage Single Ended Conversion 1.0 AVCC V

Differential Conversion 1.0 AVCC - 0.5 V

VIN Input Voltage Single ended channels GND V REF V

Differential Conversion 0 AVCC(1) V

Input Bandwidth Single Ended Channels 38 ,5 kHz

Differential Channels 4 kHz

VINT Internal Voltage Reference 1.0 1.1 1.2 V

RREF Reference Input R esistance 32 kΩ

RAIN Analog Input Resistance 100 MΩ

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LCD Controller Characteristics – Preliminary Data

Table 136. LCD Controller Characteristics

Symbol Parameter Condition Min Typ Max Units

ILCD LCD Driver Current Total for All COM and SEG pins 10 0 µA

RLCD LCD Driver Output Resistance Per COM or SEG pin 10 kΩ

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ATmega169 Typical

Characteristics The following charts show typical behavior. These figures are not tested during manu-

facturing. All current consumption measurements are performed with all I/O pins

configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-

to-rail output is used as clock source.

All Active- and Idle curre nt consumption mea surements a re done with all bits in th e PRR

Comparator is disabled during these measurements. Table 137 and Table 138 on page

310 show the additional current consumption compared to ICC Active and ICC Idle for

every I/O module controlled by the Power Reduction Register. See “Power Reduction

The power consumption in Power-down mode is independent of clock selection.

The current consumption is a function of several factors such as: operating voltage,

operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and

ambient temper ature. The dominating factors are operating voltage and frequency.

The current drawn from capacitive loaded pins may be estimated (for one pin) as

CL*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switch-

ing frequency of I/O pin.

The parts are characterized at frequencies higher than test limits. Parts are not guaran-

teed to function properly at frequencies hig her than the ordering code indicat es.

The difference between current consumption in Power-down mode with Watchdog

Timer enabled a nd Power-down m ode with Watc hdog Timer disabled repr esents the di f-

ferential curr en t dr aw n by th e Wat c h do g Time r.

Active Supply Current Figure 140. Active Supply Current vs. Frequency (0.1 - 1.0 MHz)

ACTIVE SUPPLY CURRENT vs. FREQUENCY

0.1 - 1.0 MHz

5.5 V

5.0 V

4.5 V

4.0 V

3.3 V

2.7 V

1.8 V

0.2

0.4

0.6

0.8

1.2

1.4

1.6

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Frequency (MHz)

(mA)

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Figure 141. Active Sup ply Current vs. Frequency (1 - 20 MHz)

Figure 142. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz

ACTIVE SUPPLY CURRENT vs. FREQUENCY

1 - 20 MHz

5.5 V

5.0 V

4.5 V

02468101214161820

Frequency (MHz)

(mA)

4.0 V

3.3 V

2.7 V

1.8 V

ACTIVE SUPPLY CURRENT vs. V

INTERNAL RC OSCILLATOR, 8 MHz

85 ˚C

25 ˚C

-40 ˚C

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

(mA)

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Figure 143. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)

Figure 144. Active Supply Current vs. VCC (32 kHz Watch Crystal)

ACTIVE SUPPLY CURRENT vs. V

INTERNAL RC OSCILLATOR, 1 MHz

85 ˚C

25 ˚C

-40 ˚C

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

(mA)

ACTIVE SUPPLY CURRENT vs. VCC

32 kHz Watch Crystal

25 ˚C

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

(uA)

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Idle Supply Current Figure 145. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz)

Figure 146. Idle Supply Curr ent vs. Frequency (1 - 20 MHz)

IDLE SUPPLY CURRENT vs. FREQUENCY

0.1 - 1.0 MHz

5.5 V

5.0 V

4.5 V

4.0 V

3.3 V

2.7 V

1.8 V

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Frequency (MHz)

(mA)

IDLE SUPPLY CURRENT vs. FREQUENCY

1 - 20 MHz

5.5 V

5.0 V

4.5 V

02468101214161820

Frequency (MHz)

(mA)

4.0 V

3.3 V

2.7 V

1.8 V

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Figure 147. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)

Figure 148. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)

IDLE SUPPLY CURRENT vs. V

INTERNAL RC OSCILLATOR, 8 MHz

85 ˚C

25 ˚C

-40 ˚C

0.5

1.5

2.5

3.5

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

(mA)

IDLE SUPPLY CURRENT vs. V

INTERNAL RC OSCILLATOR, 1 MHz

85 ˚C

25 ˚C

-40 ˚C

0.1

0.2

0.3

0.4

0.5

0.6

0.7

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

(mA)

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Figure 149. Idle Supply Current vs. VCC (32 kHz Crystal)

Supply Current of I/O

modules The tables and for mulas below can be used t o calculate the ad ditional cu rrent consump-

tion for the different I/O modules in Active and Idle mode. The enabling or disabling of

the I/O modules are controlled by the Power Reduction Re gister. See “Power Redu ction

IDLE SUPPLY CURRENT vs. V

32 kHz Crystal

25 ˚C

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

(uA)

Table 137.

Additional Current Consumption for the different I/O modules (absolute values)

PRR bit Typical numbers

VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz

PRADC 18 µA 116 µA 495 µA

PRUSART0 11µA 79 µA 313 µA

PRSPI 10 µA 72 µA 283 µA

PRTIM1 19 µA 117 µA 481 µA

PRLCD 19 µA 124 µA 531 µA

Table 138.

Additional Current Consumption (percentage) in Active and Idle mode

PRR bit

Additional Current consumption

compared to Active with external

clock

(see Figure 140 and Figure 141)

Additional Current consumption

compared to Idle with external

clock

(see Figure 145 and Figure 146)

PRADC 5.6% 18.7%

PRUSART0 3.7% 12.4%

PRSPI 3.2% 10.8%

PRTIM1 5.6% 18.6%

PRLCD 5.9% 19.9%

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It is possible to calculate the typical current consumption based on the numbers from

Table 138 for oth er VCC and frequency settings than listed in Table 137.

Example 1 Calculate the expected current consumption in idle mode with USART0, TIMER1, and

SPI enabled at VCC = 3. 0V an d F = 1 MHz. Fr om Tabl e 138, secon d colum n, we see th at

we need to add 12.4% for the USART0, 10.8% for the SPI, and 18.6% for the TIMER1

module. Reading from Figure 145, we find that the idle current consumption is ~0.18mA

at VCC = 3.0V and F = 1MHz. The t otal cu rren t consumption in idle mode with USART0,

TIMER1, and SPI enabled , gives:

Example 2 Same conditions as in example 1, but in active mode instead. From Table 138, second

column we see that we need to add 3.7% for the USART0, 3.2% for the SPI, and 5.6%

for the TIMER1 module. Reading from Figure 140, we find that the active current con-

sumption is ~0.6mA at VCC = 3.0V and F = 1MHz. The total current consumption in idle

mode with USART0, TIMER1, and SPI enabled, gives:

Example 3 All I/O modules should be enabled. Calculate the expected current consumption in

active mode at V CC = 3.3V and F = 10MHz. We find the active current consumpt ion with-

out the I/O modules to be ~ 5.6mA (from Figure 141). Then, by using the numbers from

Table 138 - first column , we find the total current consumption:

Power-down Supply

Current Figure 150. Power-down Supply Current vs. VCC (Watchdog Timer Disabled)

CCtotal

0.18

1 0.124 0.108 0.186+++

()•

0.26

mA≈≈

CCtotal

0.6

1 0.037 0.032 0.056+++

()•

0.68

mA≈≈

CCtotal

5.6

1 0.056 0.037 0.032 0.056 0.059+++++

()•

6.9

mA≈≈

POWER-DOWN SUPPLY CURRENT vs. V

WATCHDOG TIMER DISABLED

0.5

1.5

2.5

3.5

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

85°

25°

-40°

312

ATmega169/V

2514P–AVR–07/06

Figure 151. Power-down Supply Current vs. VCC (Watchdog Timer Enabled)

Power-save Supply

Current Figure 152. Power-save Supply Current vs. VCC (Watchdo g Tim e r Disa ble d )

The different ial curr ent consump tion bet ween Powe r-save wit h WD disab led and 32 kHz

TOSC represents the current drawn by Timer/Counter2.

POWER-DOWN SUPPLY CURRENT vs. V

WATCHDOG TIMER ENABLED

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

85°

25°

-40°

POWER-SAVE SUPPLY CURRENT vs. V

WATCHDOG TIMER DISABLED

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

85°C

25°C

313

ATmega169/V

2514P–AVR–07/06

Standb y Supply Current Figure 153. Standby Supply Curren t vs. VCC (455 kHz Resonator, W atchdog Timer

Disabled)

Figure 154. Standby Supply Current vs. VCC (1 MHz Resonator, Watchdog Timer

Disabled)

STANDBY SUPPLY CURRENT vs. V

455 kHz RESONATOR, WATCHDOG TIMER DISABLED

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

STANDBY SUPPLY CURRENT vs. V

1 MHz RESONATOR, WATCHDOG TIMER DISABLED

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

314

ATmega169/V

2514P–AVR–07/06

Figure 155. Standby Supply Current vs. VCC (2 MHz Resonator, Watchdog Timer

Disabled)

Figure 156. Standby Supply Current vs. VCC (2 MHz Xtal, Watchdog Timer Disabled)

STANDBY SUPPLY CURRENT vs. V

2 MHz RESONATOR, WATCHDOG TIMER DISABLED

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

STANDBY SUPPLY CURRENT vs. V

2 MHz XTAL, WATCHDOG TIMER DISABLED

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

315

ATmega169/V

2514P–AVR–07/06

Figure 157. Standby Supply Current vs. VCC (4 MHz Resonator, Watchdog Timer

Disabled)

Figure 158. Standby Supply Current vs. VCC (4 MHz Xtal, Watchdog Timer Disabled)

STANDBY SUPPLY CURRENT vs. V

4 MHz RESONATOR, WATCHDOG TIMER DISABLED

100

120

140

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

STANDBY SUPPLY CURRENT vs. V

4 MHz XTAL, WATCHDOG TIMER DISABLED

100

120

140

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

316

ATmega169/V

2514P–AVR–07/06

Figure 159. Standby Supply Current vs. VCC (6 MHz Resonator, Watchdog Timer

Disabled)

Figure 160. Standby Supply Current vs. VCC (6 MHz Xtal, Watchdog Timer Disabled)

STANDBY SUPPLY CURRENT vs. V

6 MHz RESONATOR, WATCHDOG TIMER DISABLED

100

120

140

160

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

STANDBY SUPPLY CURRENT vs. V

6 MHz XTAL, WATCHDOG TIMER DISABLED

100

120

140

160

180

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

317

ATmega169/V

2514P–AVR–07/06

Pin Pull-up Figure 161. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)

Figure 162. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V)

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

Vcc = 5V

100

120

140

160

012345

(V)

(uA)

85°C 25°C

-40°C

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

Vcc = 2.7V

0 0.5 1 1.5 2 2.5 3

VIO (V)

IIO (uA)

85°C 25°C

-40°C

318

ATmega169/V

2514P–AVR–07/06

Figure 163. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V)

Figure 164. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

Vcc = 1.8V

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

VOP (V)

IOP (uA)

85°C 25°C

-40°C

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

Vcc = 5V

100

120

012345

RESET

(V)

RESET

(uA)

-40°C 25°C

85°C

319

ATmega169/V

2514P–AVR–07/06

Figure 165. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)

Figure 166. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V)

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

Vcc = 2.7V

0 0.5 1 1.5 2 2.5 3

VRESET (V)

IRESET (uA)

-40°C 25°C

85°C

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

Vcc = 1.8V

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

VRESET (V)

IRESET (uA)

-40°C

25°C

85°C

320

ATmega169/V

2514P–AVR–07/06

Pin Driver Strength Figure 167. I/O Pin Source Current vs. Output Voltage, Ports A, C, D, E, F, G

(VCC =5V)

Figure 168. I/O Pin Source Current vs. Output Voltage, Ports A, C, D, E, F, G

(VCC =2.7V)

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE, PORTS A, C, D, E, F, G

Vcc = 5V

0123456

VOH (V)

IOH (mA)

85°C

25°C

-40°C

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE, PORTS A, C, D, E, F, G

Vcc = 2.7V

0 0.5 1 1.5 2 2.5 3

VOH (V)

IOH (mA)

85°C

25°C

-40°C

321

ATmega169/V

2514P–AVR–07/06

Figure 169. I/O Pin Source Current vs. Output Voltage, Ports A, C, D, E, F, G

(VCC =1.8V)

Figure 170. I/O Pin Source Current vs. Output Voltage, Port B (VCC= 5V)

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE, PORTS A, C, D, E, F, G

Vcc = 1.8V

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

VOH (V)

IOH (mA)

85°C

25°C -40°C

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE, PORT B

Vcc = 5V

01234

VOH (V)

IOH (mA)

85°C

25°C

-40°C

322

ATmega169/V

2514P–AVR–07/06

Figure 171. I/O Pin Source Current vs. Output Voltage, Port B (VCC = 2.7V)

Figure 172. I/O Pin Source Current vs. Output Voltage, Port B (VCC = 1.8V)

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE, PORT B

Vcc = 2.7V

0 0.5 1 1.5 2 2.5 3

VOH (V)

IOH (mA)

85°C

25°C

-40°C

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE, PORT B

Vcc = 1.8V

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

VOH (V)

IOH (mA)

85°C

25°C

-40°C

323

ATmega169/V

2514P–AVR–07/06

Figure 173. I/O Pin Sink Current vs. Output Voltage, Ports A, C, D, E, F, G (VCC = 5V)

Figure 174. I/O Pin Sink Current vs. Output Voltage, Ports A, C, D, E, F, G (VCC = 2.7V)

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE, PORTS A, C, D, E, F, G

Vcc = 5V

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

VOL (V)

IOL (mA)

85°C

25°C

-40°C

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE, PORTS A, C, D, E, F, G

Vcc = 2.7V

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

VOL (V)

IOL (mA)

85°C

25°C

-40°C

324

ATmega169/V

2514P–AVR–07/06

Figure 175. I/O Pin Sink Cur rent vs. Output Voltage, Por ts A, C, D, E, F, G (VCC = 1. 8V)

Figure 176. I/O Pin Sink Current vs. Output Voltage, Port B (VCC = 5V)

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE, PORTS A, C, D, E, F, G

Vcc = 1.8V

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

VOL (V)

IOL (mA)

85°C

25°C

-40°C

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE, PORT B

Vcc = 5V

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

VOL (V)

IOL (mA)

85°C

25°C

-40°C

325

ATmega169/V

2514P–AVR–07/06

Figure 177. I/O Pin Sink Current vs. Output Voltage, Port B (VCC = 2.7V)

Figure 178. I/O Pin Sink Current vs. Output Voltage, Port B (VCC = 1.8V)

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE, PORT B

Vcc = 2.7V

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

VOL (V)

IOL (mA)

85°C

25°C

-40°C

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE, PORT B

Vcc = 1.8V

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

VOL (V)

IOL (mA)

85°C

25°C

-40°C

326

ATmega169/V

2514P–AVR–07/06

Pin Thresholds and

hysteresis Figure 179. I/O Pin Input Thresh o l d Volta g e vs. VCC (VIH, I/O Pin Read as “1”)

Figure 180. I/O Pin Input Threshold V olta g e vs. VCC (VIL, I/O Pin Read as “0”)

I/O PIN INPUT THRESHOLD VOLTAGE vs. V

VIH, I/O PIN READ AS '1'

0.5

1.5

2.5

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

Threshold (V)

85°

25°

-40°

I/O PIN INPUT THRESHOLD VOLTAGE vs. V

VIL, I/O PIN READ AS '0'

0.5

1.5

2.5

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

Threshold (V)

85°

25°

-40°

327

ATmega169/V

2514P–AVR–07/06

Figure 181. I/O Pin Input Hysteresis vs. V CC

Figure 182. Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”)

I/O PIN INPUT HYSTERESIS vs. V

0.1

0.2

0.3

0.4

0.5

0.6

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

Input Hysteresis (V)

85°C

25°C

-40°C

RESET INPUT THRESHOLD VOLTAGE vs. V

VIH, RESET PIN READ AS '1'

0.5

1.5

2.5

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

Threshold (V)

85°C

25°C

-40°C

328

ATmega169/V

2514P–AVR–07/06

Figure 183. Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”)

Figure 184. Reset Input Pin Hysteresis vs. VCC

RESET INPUT THRESHOLD VOLTAGE vs. V

VIL, RESET PIN READ AS '0'

0.5

1.5

2.5

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

Threshold (V)

85°

25°

-40°

RESET INPUT PIN HYSTERESIS vs. V

0.1

0.2

0.3

0.4

0.5

0.6

0.7

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

Input Hysteresis (V)

85°C

25°C

-40°C

329

ATmega169/V

2514P–AVR–07/06

BOD Thresholds and

Analog Comparator

Offset

Figure 185. BOD Thresholds vs. Temperature (BOD Level is 4.3V)

Figure 186. BOD Thresholds vs. Temperature (BOD Level is 2.7V)

BOD THRESHOLDS vs. TEMPERATURE

BODLEVEL IS 4.3V

4.1

4.2

4.3

4.4

4.5

4.6

-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

Temperature (˚C)

Threshold (V)

Rising VCC

Falling VCC

BOD THRESHOLDS vs. TEMPERATURE

BODLEVEL IS 2.7V

2.4

2.5

2.6

2.7

2.8

2.9

-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

Temperature (˚C)

Threshold (V)

Rising VCC

Falling VCC

330

ATmega169/V

2514P–AVR–07/06

Figure 187. BOD Thresholds vs. Temperature (BOD Level is 1.8V)

Figure 188. Bandgap Voltage vs. VCC

BOD THRESHOLDS vs. TEMPERATURE

BODLEVEL IS 1.8V

1.5

1.6

1.7

1.8

1.9

2.1

-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

Temperature (˚C)

Threshold (V)

Rising VCC

Falling VCC

BANDGAP VOLTAGE vs. V

1.08

1.09

1.1

1.11

1.12

1.13

1.14

1.5 2 2.5 3 3.5 4 4.5 5 5.5

Vcc (V)

Bandgap Voltage (V)

85°C

25°C

-40°C

331

ATmega169/V

2514P–AVR–07/06

Figure 189. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 5V)

Figure 190. Analog Comparator Offset Voltage vs. Common Mode Voltage

(VCC =2.7V)

ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE

VCC = 5V

-0.004

-0.002

0.002

0.004

0.006

0.008

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Common Mode Voltage (V)

Comparator Offset Voltage (V)

85°C

25°C

-40°C

ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE

VCC = 2.7V

-0.004

-0.003

-0.002

-0.001

0.001

0.002

0.003

0 0.5 1 1.5 2 2.5 3

Common Mode Voltage (V)

Comparator Offset Voltage (V)

85°C

25°C

-40°C

332

ATmega169/V

2514P–AVR–07/06

Internal Oscillator Speed Figure 191. Watchdog Oscillator Frequency vs. VCC

Figure 192. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature

WATCHDOG OSCILLATOR FREQUENCY vs. V

800

850

900

950

1000

1050

1100

1150

1200

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

FRC (kHz)

85°

25°

-40°

CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE

7.2

7.4

7.6

7.8

8.2

8.4

8.6

8.8

-60 -40 -20 0 20 40 60 80 100

Ta (˚C)

FRC (MHz)

5.5V

4.0V

2.7V

1.8V

333

ATmega169/V

2514P–AVR–07/06

Figure 193. Calibrated 8 MHz RC Oscillator Frequency vs. VCC

Figure 194. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value

CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. V

6.5

7.5

8.5

9.5

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

FRC (MHz)

85°

25°

-40°

CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE

0 163248648096112

OSCCAL VALUE

FRC (MHz)

334

ATmega169/V

2514P–AVR–07/06

Current Consumption of

Peripheral Units Figure 195. Brownout Detector Current vs. VCC

Figure 196. ADC Current vs. VCC (AREF = AVCC)

BROWNOUT DETECTOR CURRENT vs. V

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

25°C

85°C

-40°C

ADC CURRENT vs. V

AREF = AVCC

100

150

200

250

300

350

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

85°

25°

-40°

335

ATmega169/V

2514P–AVR–07/06

Figure 197. AREF External Reference Current vs. VCC

Figure 198. 32 kHZ TOSC Curr ent vs. VCC (Watchdog Timer Disable d )

The different ial curr ent consump tion bet ween Powe r-save wit h WD disab led and 32 kHz

TOSC represents the current drawn by Timer/Counter2.

AREF EXTERNAL REFERENCE CURRENT vs. V

100

120

140

160

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

IAREF (uA)

85°

25°

-40°

32kHz TOSC CURRENT vs. V

WATCHDOG TIMER DISABLED

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

85°C

25°C

336

ATmega169/V

2514P–AVR–07/06

Figure 199. Watchdog Timer Current vs. V CC

Figure 200. Analog Comparator Current vs. VCC

WATCHDOG TIMER CURRENT vs. V

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

85°

25°

-40°

ANALOG COMPARATOR CURRENT vs. V

100

120

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

85°C

25°C

-40°C

337

ATmega169/V

2514P–AVR–07/06

Figure 201. Programming Current vs. VCC

Current Consumption in

Reset and Reset

Pulsewidth

Figure 202. Reset Supply Cu rrent vs. VCC (0.1 - 1.0 MHz, Excluding Current Through

The Reset Pull-up)

PROGRAMMING CURRENT vs. Vcc

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (mA)

85°C

25°C

-40°

RESET SUPPLY CURRENT vs. FREQUENCY

0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

0.18

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Frequency (MHz)

ICC (mA)

5.5V

4.5V

4.0V

3.3V

2.7V

1.8V

5.0V

338

ATmega169/V

2514P–AVR–07/06

Figure 203. Reset Supply Current vs. VCC (1 - 20 MHz, Excluding Current Through The

Reset Pull-up)

Figure 204. Minimum Reset Pulse Width vs. VCC

RESET SUPPLY CURRENT vs. FREQUENCY

1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP

0.5

1.5

2.5

3.5

02468101214161820

Frequency (MHz)

ICC (mA)

5.5V

4.5V

4.0V

3.3V

2.7V

1.8V

5.0V

MINIMUM RESET PULSE WIDTH vs. V

500

1000

1500

2000

2500

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

Pulsewidth (ns)

85°C

25°C

-40°C

339

ATmega169/V

2514P–AVR–07/06

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

(0xFF) Reserved – – – – – – – –

(0xFE) LCDDR18 – – – – – – – SEG324 225

(0xFD) LCDDR17 SEG323 SEG322 SEG321 SEG320 SEG319 SEG318 SEG317 SEG316 225

(0xFC) LCDDR16 SEG315 SEG314 SEG313 SEG312 SEG311 SEG310 SEG309 SEG308 225

(0xFB) LCDDR15 SEG307 SEG306 SEG305 SEG304 SEG303 SEG302 SEG301 SEG300 225

(0xFA) Reserved – – – – – – – –

(0xF9) LCDDR13 – – – – – – – SEG224 225

(0xF8) LCDDR12 SEG223 SEG222 SEG221 SEG220 SEG219 SEG218 SEG217 SEG216 225

(0xF7) LCDDR11 SEG215 SEG214 SEG213 SEG212 SEG211 SEG210 SEG209 SEG208 225

(0xF6) LCDDR10 SEG207 SEG206 SEG205 SEG204 SEG203 SEG202 SEG201 SEG200 225

(0xF5) Reserved – – – – – – – –

(0xF4) LCDDR8 – – – – – – – SEG124 225

(0xF3) LCDDR7 SEG123 SEG122 SEG121 SEG120 SEG119 SEG118 SEG117 SEG116 225

(0xF2) LCDDR6 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 225

(0xF1) LCDDR5 SEG107 SEG106 SEG105 SEG104 SEG103 SEG102 SEG101 SEG100 225

(0xF0) Reserved – – – – – – – –

(0xEF) LCDDR3 – – – – – – – SEG024 225

(0xEE) LCDDR2 SEG023 SEG022 SEG021 SEG020 SEG019 SEG018 SEG017 SEG016 225

(0xED) LCDDR1 SEG015 SEG014 SEG013 SEG012 SEG011 SEG010 SEG09 SEG008 225

(0xEC) LCDDR0 SEG007 SEG006 SEG005 SEG004 SEG003 SEG002 SEG001 SEG000 225

(0xEB) Reserved – – – – – – – –

(0xEA) Reserved – – – – – – – –

(0xE9) Reserved – – – – – – – –

(0xE8) Reserved – – – – – – – –

(0xE7) LCDCCR LCDCD2 LCDCD1 LCDCC0 – LCDCC3 LCDCC2 LCDCC1 LCDCC0 223

(0xE6) LCDFRR – LCDPS2 LCDPS1 LCDPS0 – LCDCD2 LCDCD1 LCDCD0 221

(0xE5) LCDCRB LCDCS LCD2B LCDMUX1 LCDMUX0 – LCDPM2 LCDPM1 LCDPM0 220

(0xE4) LCDCRA LCDEN LCDAB – LCDIF LCDIE –– LCDBL 219

(0xE3) Reserved – – – – – – – –

(0xE2) Reserved – – – – – – – –

(0xE1) Reserved – – – – – – – –

(0xE0) Reserved – – – – – – – –

(0xDF) Reserved – – – – – – – –

(0xDE) Reserved – – – – – – – –

(0xDD) Reserved – – – – – – – –

(0xDC) Reserved – – – – – – – –

(0xDB) Reserved – – – – – – – –

(0xDA) Reserved – – – – – – – –

(0xD9) Reserved – – – – – – – –

(0xD8) Reserved – – – – – – – –

(0xD7) Reserved – – – – – – – –

(0xD6) Reserved – – – – – – – –

(0xD5) Reserved – – – – – – – –

(0xD4) Reserved – – – – – – – –

(0xD3) Reserved – – – – – – – –

(0xD2) Reserved – – – – – – – –

(0xD1) Reserved – – – – – – – –

(0xD0) Reserved – – – – – – – –

(0xCF) Reserved – – – – – – – –

(0xCE) Reserved – – – – – – – –

(0xCD) Reserved – – – – – – – –

(0xCC) Reserved – – – – – – – –

(0xCB) Reserved – – – – – – – –

(0xCA) Reserved – – – – – – – –

(0xC9) Reserved – – – – – – – –

(0xC8) Reserved – – – – – – – –

(0xC7) Reserved – – – – – – – –

(0xC6) UDR USART I/O Data Register 170

(0xC5) UBRRH USART Baud Rate Register High 174

(0xC4) UBRRL USART Baud Rate Register Low 174

(0xC3) Reserved – – – – – – – –

(0xC2) UCSRC – UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL 170

(0xC1) UCSRB RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 170

(0xC0) UCSRA RXC TXC UDRE FE DOR UPE U2X MPCM 170

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(0xBF) Reserved – – – – – – – –

(0xBE) Reserved – – – – – – – –

(0xBD) Reserved – – – – – – – –

(0xBC) Reserved – – – – – – – –

(0xBB) Reserved – – – – – – – –

(0xBA) USIDR USI Data Register 185

(0xB9) USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 186

(0xB8) USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC 187

(0xB7) Reserved – – – – – – –

(0xB6) ASSR – – – EXCLK AS2 TCN2UB OCR2UB TCR2UB 138

(0xB5) Reserved – – – – – – – –

(0xB4) Reserved – – – – – – – –

(0xB3) OCR2A Timer/Counter2 Output Compare Register A 137

(0xB2) TCNT2 Timer/Counter2 (8-bit) 137

(0xB1) Reserved – – – – – – – –

(0xB0) TCCR2A FOC2A WGM20 COM2A1 COM2A0 WGM21 CS22 CS21 CS20 135

(0xAF) Reserved – – – – – – – –

(0xAE) Reserved – – – – – – – –

(0xAD) Reserved – – – – – – – –

(0xAC) Reserved – – – – – – – –

(0xAB) Reserved – – – – – – – –

(0xAA) Reserved – – – – – – – –

(0xA9) Reserved – – – – – – – –

(0xA8) Reserved – – – – – – – –

(0xA7) Reserved – – – – – – – –

(0xA6) Reserved – – – – – – – –

(0xA5) Reserved – – – – – – – –

(0xA4) Reserved – – – – – – – –

(0xA3) Reserved – – – – – – – –

(0xA2) Reserved – – – – – – – –

(0xA1) Reserved – – – – – – – –

(0xA0) Reserved – – – – – – – –

(0x9F) Reserved – – – – – – – –

(0x9E) Reserved – – – – – – – –

(0x9D) Reserved – – – – – – – –

(0x9C) Reserved – – – – – – – –

(0x9B) Reserved – – – – – – – –

(0x9A) Reserved – – – – – – – –

(0x99) Reserved – – – – – – – –

(0x98) Reserved – – – – – – – –

(0x97) Reserved – – – – – – – –

(0x96) Reserved – – – – – – – –

(0x95) Reserved – – – – – – – –

(0x94) Reserved – – – – – – – –

(0x93) Reserved – – – – – – – –

(0x92) Reserved – – – – – – – –

(0x91) Reserved – – – – – – – –

(0x90) Reserved – – – – – – – –

(0x8F) Reserved – – – – – – – –

(0x8E) Reserved – – – – – – – –

(0x8D) Reserved – – – – – – – –

(0x8C) Reserved – – – – – – – –

(0x8B) OCR1BH Timer/Counter1 - Output Compare Register B High Byte 121

(0x8A) OCR1BL Timer/Counter1 - Output Compare Register B Low Byte 121

(0x89) OCR1AH Timer/Counter1 - Output Compare Register A High Byte 121

(0x88) OCR1AL Timer/Counter1 - Output Compare Regist er A Low Byte 121

(0x87) ICR1H Timer/Counter1 - Input Capture Register High Byte 122

(0x86) ICR1L Timer/Counter1 - Input Capture Register Low Byte 122

(0x85) TCNT1H Timer/Counter1 - Counter Register High Byte 121

(0x84) TCNT1L Timer/Counter1 - Counter Register Low Byte 12 1

(0x83) Reserved – – – – – – – –

(0x82) TCCR1C FOC1A FOC1B – – – – – – 120

(0x81) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 119

(0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 –– WGM11 WGM10 117

(0x7F) DIDR1 – – – – – – AIN1D AIN0D 192

(0x7E) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 209

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

341

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(0x7D) Reserved – – – – – – – –

(0x7C) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 205

(0x7B) ADCSRB –ACME– – – ADTS2 ADTS1 ADTS0 190, 209

(0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 207

(0x79) ADCH ADC Data Register High byte 208

(0x78) ADCL ADC Data Register Low byte 208

(0x77) Reserved – – – – – – – –

(0x76) Reserved – – – – – – – –

(0x75) Reserved – – – – – – – –

(0x74) Reserved – – – – – – – –

(0x73) Reserved – – – – – – – –

(0x72) Reserved – – – – – – – –

(0x71) Reserved – – – – – – – –

(0x70) TIMSK2 – – – – – – OCIE2A TOIE2 140

(0x6F) TIMSK1 ––ICIE1–– OCIE1B OCIE1A TOIE1 122

(0x6E) TIMSK0 – – – – – – OCIE0A TOIE0 92

(0x6D) Reserved – – – – – – – –

(0x6C) PCMSK1 PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 54

(0x6B) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 54

(0x6A) Reserved – – – – – – – –

(0x69) EICRA – – – – – –ISC01ISC00 52

(0x68) Reserved – – – – – – – –

(0x67) Reserved – – – – – – – –

(0x66) OSCCAL Oscillator Calibration Register 28

(0x65) Reserved – – – – – – – –

(0x64) PRR – – – PRLCD PRTIM1 PRSPI PRUSART0 PRADC 34

(0x63) Reserved – – – – – – – –

(0x62) Reserved – – – – – – – –

(0x61) CLKPR CLKPCE ––– CLKPS3 CLKPS2 CLKPS1 CLKPS0 30

(0x60) WDTCR – – – WDCE WDE WDP2 WDP1 WDP0 43

0x3F (0x5F) SREG I T H S V N Z C 9

0x3E (0x5E) SPH – – – – – SP10 SP9 SP8 11

0x3D (0x5D) SPL SP7 SP6 S P5 SP4 SP3 SP2 SP1 SP0 11

0x3C (0x5C) Reserved

0x3B (0x5B) Rese rved

0x3A (0x5A) Rese rved

0x39 (0x59) Reserved

0x38 (0x58) Reserved

0x37 (0x57) SPMCSR SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN 257

0x36 (0x56) Reserved – – – – – – – –

0x35 (0x55) MCUCR JTD ––PUD–– IVSEL IVCE 235

0x34 (0x54) MCUSR – – – JTRF WDRF BORF EXTRF PORF 236

0x33 (0x53) SMCR ––––SM2SM1SM0SE 32

0x32 (0x52) Reserved – – – – – – – –

0x31 (0x51) OCDR IDRD/OCD OCDR6 OCDR5 OCDR4 OCDR3 OCDR2 OCDR1 OCDR0 231

0x30 (0x50) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 190

0x2F (0x4F) Reserved – – – – – – – –

0x2E (0x4E) SPDR SPI Data Register 150

0x2D (0x4D) SPSR SPIF WCOL – – – – – SPI2X 150

0x2C (0x4C) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 148

0x2B (0x4B) GPIOR2 General Purpose I/O Register 2 22

0x2A (0x4A) GPIOR1 General Purpose I/O Register 1 22

0x29 (0x49) Reserved – – – – – – – –

0x28 (0x48) Reserved – – – – – – – –

0x27 (0x47) OCR0A Timer/Counter0 Output Compare Register A 92

0x26 (0x46) TCNT0 Timer/Counter0 (8 Bit) 91

0x25 (0x45) Reserved – – – – – – – –

0x24 (0x44) TCCR0A FOC0A WGM00 COM0A1 COM0A0 WGM01 CS02 CS01 CS00 89

0x23 (0x43) GTCCR TSM – – – – – PSR2 PSR10 94

0x22 (0x42) EEARH – – – – – – –EEAR8 18

0x21 (0x41) EEARL EEPROM Address Register Low Byte 18

0x20 (0x40) EEDR EEPROM Data Registe r 18

0x1F (0x3F) EECR –––– EERIE EEMWE EEWE EERE 18

0x1E (0x3E) GPIOR0 General Purpose I/O Register 0 22

0x1D (0x3D) EIMSK PCIE1 PCIE0 – – – – –INT0 53

0x1C (0x3C) EIFR PCIF1 PCIF0 – – – – – INTF0 53

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

342

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Note: 1. For comp atibility with future devices, reser ved bits shoul d be written to zero if accessed. Reser ved I/O memory addresses

should never be written.

2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these

registers, the value of single bits can be checked by using the SBIS and SBIC instructio ns.

3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI

instructions will on ly operate on the speci fied bit, and ca n there fore be used on registers containing such Status Flags. The

CBI and SBI instructions work with registers 0x00 to 0x1F only.

4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O

Registers as data sp ace usin g LD and ST in structions, 0x20 must be added to these addresses. The ATmega169 i s a com-

plex microcontroller with more per ipheral units than can be sup por ted within the 64 location reser ved in Opcode for the IN

and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD

instructions can be used .

0x1B (0x3B) Rese rved – – – – – – – –

0x1A (0x3A) Rese rved – – – – – – – –

0x19 (0x39) Reserved – – – – – – – –

0x18 (0x38) Reserved – – – – – – – –

0x17 (0x37) TIFR2 – – – – – – OCF2A TOV2 141

0x16 (0x36) TIFR1 ––ICF1–– OCF1B OCF1A TOV1 123

0x15 (0x35) TIFR0 – – – – – – OCF0A TOV0 92

0x14 (0x34) PORTG – – – PORTG4 PORTG3 PORTG2 PORTG1 PORTG0 78

0x13 (0x33) DDRG – – – DDG4 DDG3 DDG2 DDG1 DDG0 78

0x12 (0x32) PING – – – PING4 PING3 PING2 PING1 PING0 78

0x11 (0x31) PORTF PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTF0 77

0x10 (0x30) DDRF DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 77

0x0F (0x2F) PINF PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 78

0x0E (0x2E) PORTE PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 77

0x0D (0x2D) DDRE DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 77

0x0C (0x2C) PINE PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 77

0x0B (0x2B) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 77

0x0A (0x2A) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 77

0x09 (0x29) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 77

0x08 (0x28) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 76

0x07 (0x27) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 76

0x06 (0x26) PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 77

0x05 (0x25) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 76

0x04 (0x24) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 76

0x03 (0x23) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 76

0x02 (0x22) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 76

0x01 (0x21) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 76

0x00 (0x20) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 76

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

343

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Instruction Set Summary

Mnemonics Operands Description Operation Flags #Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1

ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1

ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2

SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1

SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1

SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1

SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1

SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2

AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1

ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1

OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1

ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1

EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1

COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1

NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1

SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1

CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1

INC Rd Increment Rd ← Rd + 1 Z,N,V 1

DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1

TST Rd Test f or Zero or Minus Rd ← Rd • Rd Z,N,V 1

CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1

SER Rd Set Register Rd ← 0xFF None 1

MUL Rd , Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2

MULS Rd, Rr Multiply Signed R1:R0 ← Rd x Rr Z,C 2

MULSU Rd, Rr Multiply Signed with Unsign ed R1:R0 ← Rd x Rr Z,C 2

FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2

FMULS Rd, Rr Fractional Multiply Signed R1:R0 ← (Rd x Rr) << 1 Z,C 2

FMULSU Rd, Rr Fractional Multiply Sign ed with Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2

BRANCH INSTRUCTIONS

RJMP k Relative Jump PC ← PC + k + 1 None 2

IJMP Indirect Jump to (Z) PC ← Z None 2

JMP k Direct Jump PC ← kNone3

RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3

ICALL Indirect Call to (Z) PC ← ZNone3

CALL k Direct Subroutine Call PC ← kNone4

RET Subroutine Return PC ← STACK None 4

RETI Interrupt Return PC ← STACK I 4

CPSE Rd,Rr Compare , Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3

CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1

CPC Rd,R r Compare with Carry Rd − Rr − C Z, N,V,C,H 1

CPI Rd,K Compare Register wi th Immediate Rd − K Z, N,V,C,H 1

SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3

SBRS Rr, b Skip if Bit in Registe r is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3

SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3

SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3

BRBS s, k Branch if Stat us Flag Set if (SREG(s) = 1) then PC←PC+k + 1 N one 1/2

BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2

BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2

BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 N one 1/2

BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2

BRCC k Branc h if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2

BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2

BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2

BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/ 2

BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2

BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2

BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2

BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2

BRHC k Bran c h if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2

BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2

BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2

BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2

BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2

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BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2

BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1 /2

BIT AND BIT-TEST INSTRUCTIONS

SBI P ,b Set Bit in I/O Register I/O(P,b) ← 1None2

CBI P,b Clear Bit in I/O Register I/O(P ,b) ← 0None2

LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1

LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1

ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1

ROR Rd Rotate Right Through Carry Rd(7) ←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1

ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1

SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1

BSET s Flag Set SREG(s) ← 1 SREG(s) 1

BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1

BST Rr, b Bit Store from Register to T T ← Rr(b) T 1

BLD Rd, b Bit load from T to Register Rd(b) ← TNone1

SEC Set Carry C ← 1C1

CLC Clear Carry C ← 0 C 1

SEN Set Negative Flag N ← 1N1

CLN Clear Negative Flag N ← 0 N 1

SEZ Set Zero Flag Z ← 1Z1

CLZ Clear Zero Flag Z ← 0 Z 1

SEI Global Interrupt Enable I ← 1I1

CLI Global Interrupt Disable I ← 0 I 1

SES Set Signed Test Flag S ← 1S1

CLS Clear Signed Test Flag S ← 0 S 1

SEV Set Twos Complement Overflow. V ← 1V1

CLV Clear Twos Complement Overflow V ← 0 V 1

SET Set T in SREG T ← 1T1

CLT Clear T in SR EG T ← 0 T 1

SEH Set Half Carry Flag in SREG H ← 1H1

CLH Clear Half Carry Flag in SREG H ← 0 H 1

DATA TRANSFER INSTRUCTIONS

MOV Rd, Rr Move Between Registers Rd ← Rr None 1

MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1

LDI Rd, K Load Immediate Rd ← KNone1

LD Rd, X Load Indirect Rd ← (X) None 2

LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2

LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2

LD Rd, Y Load Indirect Rd ← (Y) None 2

LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2

LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2

LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) N one 2

LD Rd, Z Load Indirect Rd ← (Z) None 2

LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+ 1 None 2

LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2

LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2

LDS Rd, k Load Direct from SRAM Rd ← (k) None 2

ST X, Rr Store Indirect (X) ← Rr None 2

ST X+, Rr Store Indirect and Post -In c. (X) ← Rr, X ← X + 1 Non e 2

ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2

ST Y, Rr Store Indirect (Y) ← Rr None 2

ST Y+, Rr Store Indirect and Post -In c. (Y) ← Rr, Y ← Y + 1 None 2

ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2

STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2

ST Z, Rr Store Indirect (Z) ← Rr None 2

ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2

ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2

STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2

STS k, Rr Store Direct to SRAM (k) ← Rr None 2

LPM Load Program Memory R0 ← (Z) None 3

LPM Rd, Z Load Program Memory Rd ← (Z) None 3

LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3

SPM Store Program Memory (Z) ← R1:R0 None -

IN Rd, P In Port Rd ← PNone1

OUT P, Rr Out Port P ← Rr None 1

PUSH Rr Push Register on Stack STACK ← Rr None 2

Mnemonics Operands Description Operation Flags #Clocks

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POP Rd Pop Register from Stack Rd ← STACK N one 2

MCU CONTROL INSTRUCTIONS

NOP No Operation None 1

SLEEP Sleep (see specific descr. for Sleep function) None 1

WDR Watchdog Reset (see specific descr. for WDR/timer) None 1

BREAK Break For On-chip Debug Only None N/A

Mnemonics Operands Description Operation Flags #Clocks

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Ordering Information

Notes: 1. This device can also be supplied in wafer f orm. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc-

tive). Also Halide free and fully Green.

3. For Speed vs. VCC, see Figure 136 on page 301 and Figure 137 on page 301.

Speed (MHz)(3) Power Supply Ordering Code Package(1) Operation Range

8 1.8 - 5.5V

ATmega169V-8AI

ATmega169V-8AU(2)

ATmega169V-8MI

ATmega169V-8MU(2)

64A

64M1

Industrial

(-40°C to 85°C)

16 2.7 - 5.5 V

ATmega169-16AI

ATmega169-16AU(2)

ATmega169-16MI

ATmega169-16MU(2)

64A

64M1

Industrial

(-40°C to 85°C)

Package Type

64A 64-Lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

64M1 64-pad, 9 x 9 x 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

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Packaging Information

64A

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) B

64A

10/5/2001

PIN 1 IDENTIFIER

0˚~7˚

PIN 1

A1 A2 A

eE1 E

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

Notes: 1. This package conforms to JEDEC reference MS-026, Variation AEB.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

3. Lead coplanarity is 0.10 mm maximum.

A – – 1.20

A1 0.05 – 0.15

A2 0.95 1.00 1.05

D 15.75 16.00 16.25

D1 13.90 14.00 14.10 Note 2

E 15.75 16.00 16.25

E1 13.90 14.00 14.10 Note 2

B 0.30 – 0.45

C 0.09 – 0.20

L 0.45 – 0.75

e 0.80 TYP

348

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64M1

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm,

64M1

5/25/06

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A 0.80 0.90 1.00

A1 – 0.02 0.05

b 0.180.25 0.30

D2 5.20 5.40 5.60

8.90 9.00 9.10

E2 5.20 5.40 5.60

e 0.50 BSC

L0.35 0.40 0.45

Note: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD.

2. Dimension and tolerance conform to ASMEY14.5M-1994.

TOP VIEW

SIDE VIEW

BOTTOM VIEW

Marked Pin# 1 ID

SEATING PLANE

0.08

K 1.25 1.40 1.55

Pin #1 Corner

Pin #1

Tr i angle

Pin #1

Chamfer

(C 0.30)

Option A

Option B

Pin #1

Notch

(0.20 R)

Option C

5.40 mm Exposed Pad, Micro Lead Frame Package (MLF)

349

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Errata

ATmega169 Rev E •Interrupts may be lost when writing the timer registers in the asynchronous timer

1. Interrupts may be lost when writing the timer registers in the asynchronous

timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock

is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/Workaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the

value 0xFF before writing the Timer2 Control Register, TCCR2 , or Outp ut C omp are

ATmega169 Rev D •Interrupts may be lost when writing the timer registers in the asynchronous timer

•High serial resistance in the glass can res ult in dim segments on the LCD

•IDCODE masks data from TDI input

3. Interrupts may be lost when writing the timer registers in the asynchronous

timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock

is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/Workaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the

value 0xFF before writing the Timer2 Control Register, TCCR2 , or Outp ut C omp are

2. High serial resistance in the glass can result in dim segments on the LCD

Some display types with high serial resistance (>20 kΩ) inside the glass can result

in dim segments on the LCD

Problem Fix/Workaround

Add a 1 nF (0.47 - 1.5 nF) capacitor between each common pin and ground.

1. IDCODE masks data from TDI input

The JTAG instruction IDCODE is not working correctly. Data to succeeding devices

are replaced by all-ones during Update-DR.

Problem Fix / Workaround

– If ATmega169 is the only device in the scan chain, the problem is not visible.

– Select the Device ID Register of the ATmega169 by issuing the IDCODE

instru ction or by entering th e Test-Logic- Reset state of the TAP contr oller to

read out the contents of its Device ID Register and possibly data from

succeeding devices of the scan chain. Issue the BYPASS instruction to the

ATmega169 while reading the Device ID Registers of preceding devices of

the boundary scan chain.

– If the Device IDs of all devices in the boundary scan chain must be captured

simultaneously, the ATmega169 must be the first device in the chain.

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ATmega169 Rev C •Interrupts may be lost when writing the timer registers in the asynchronous timer

•High Current Consumption In Power Down when JTAGEN is Programmed

•LCD Contrast Control

•Some Data Combinations Can Result in Dim Segments on the LCD

•LCD Current Consumption

•IDCODE masks data from TDI input

6. Interrupts may be lost when writing the timer registers in the asynchronous

timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock

is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/Workaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the

value 0xFF before writing the Timer2 Control Register, TCCR2 , or Outp ut C omp are

5. High Current Consump tion In Power Down when JTAGEN is Programmed

The input buffer on TDO (PF6) is always enabled and the pull-up is always disabled

when JTAG is programmed. This can leave the output floating.

Problem Fix/Workaround

Add external pu ll-u p to PF6.

Unprogram the JTAGEN Fuse before shipping out the end product.

4. LCD Contrast Control

The contrast control is not working pro perly when using synchronous clock (chip

clock) to obtain an LCD clock, and the chip clock is 125 kHz or faster.

Problem Fix/Workaround

Use a low chip clock frequency (32 kHz) or apply an external voltage to the LCD-

CAP pin.

3. Some Data Combinations Can Result in Dim Segments on the LCD

All segments connected to a common plane might be dimm ed (lower contrast ) when

a certain combination of data is displayed.

Problem Fix/Workaround

Default wavefo rm: If ther e are any unu sed segment pins, loading one o f these with a

1 nF capacitor and always writ e ‘0’ to this segment eliminates the pr oblem.

Low power waveform: Add a 1 nF capacitor to each common pin.

2. LCD Current Consumption

In an interval where VCC is within the range VLCD -0.2V to VLCD + 0.4V, the LCD

current consumption is up to three times higher than expected. This will only be an

issue in Power-save mode with the LCD running as the LCD current is negligible

compared to the overall power consumption in all other modes of operation.

Problem Fix/Workaround

No known workaround.

1. IDCODE masks data from TDI input

The JTAG instruction IDCODE is not working correctly. Data to succeeding devices

are replaced by all-ones during Update-DR.

351

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Problem Fix / Workaround

– If ATmega169 is the only device in the scan chain, the problem is not visible.

– Select the Device ID Register of the ATmega169 by issuing the IDCODE

instru ction or by entering th e Test-Logic- Reset state of the TAP contr oller to

read out the contents of its Device ID Register and possibly data from

succeeding devices of the scan chain. Issue the BYPASS instruction to the

ATmega169 while reading the Device ID Registers of preceding devices of

the boundary scan chain.

– If the Device IDs of all devices in the boundary scan chain must be captured

simultaneously, the ATmega169 must be the first device in the chain.

ATmega169 Rev B •Interrupts may be lost when writing the timer registers in the asynchronous timer

•Internal Oscillator Runs at 4 MHz

•LCD Contrast Voltage is not Correct

•External Oscillator is Non-functional

•USART

•ADC Measures with Lower Accuracy than Specified

•Serial Downloading

•IDCODE masks data from TDI input

8. Interrupts may be lost when writing the timer registers in the asynchronous

timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock

is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/Workaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the

value 0xFF before writing the Timer2 Control Register, TCCR2 , or Outp ut C omp are

7. Internal Oscillator Runs at 4 MHz

The Internal Oscillator runs at 4 MHz instead of the specified 8 MHz. Therefore, all

Flash/EEPROM programming times are twice as long as specified. This includes

Chip Erase, Byte programming, Page programming, Fuse programming, Lock bit

programming, EEPROM write from the CPU, and Flash Self-Programming.

For this reason, rev-B samples are shipped with the CKDIV8 Fuse unprogrammed.

Problem Fix/Workaround

If 8 MHz operation is required, apply an external clock (this will be fixed in rev. C).

6. LCD Contrast Voltage is not Correct

The LCD contrast voltage between 1.8V and 3.1V is incorrect. When the VCC is

between 1.8V and 3.1V, the LCD contrast voltage drops approx. 0.5V. The current

consumption in this interval is higher than expected.

Problem Fix/Workaround

Contrast will be wrong, but display will still be readable, can be partly compensated

for using the contrast control register (this will be fixed in rev. C).

5. External Os c illat or is Non-functiona l

The external oscillator does not run with the setup described in the datasheet.

Problem Fix/Workaround

Use other clock source (this will be fixed in rev. C).

352

ATmega169/V

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Alternative Problem Fix/Workaround

Adding a pull-down on XTAL1 will start the Oscillator.

4. USART

Writing TXEN to zero during transmission causes the transmission to sudd enly stop.

The datasheet description tells that the transmission should complete before stop-

ping the USART when TXEN is written to zero.

Problem Fix/Workaround

Ensure that the transmission is complete before writing TXEN to zero (this will be

fixed in rev. C).

3. ADC Measures with Lower Accuracy than Sp ecified

The ADC does not work as intended. There is a positive offset in the result.

Problem Fix/Workaround

This will be fixed in rev. C.

2. Serial downloading

When entering Serial Programming mode the second byte will not echo back as

described in the Serial Programming algorithm.

Problem Fix/Workaround

Check if the third byte echoes back to ensure that the device is in Programming

mode (this will be fixed in rev. C).

1. IDCODE masks data from TDI input

The JTAG instruction IDCODE is not working correctly. Data to succeeding devices

are replaced by all-ones during Update-DR.

Problem Fix / Workaround

– If ATmega169 is the only device in the scan chain, the problem is not visible.

– Select the Device ID Register of the ATmega169 by issuing the IDCODE

instru ction or by entering th e Test-Logic- Reset state of the TAP contr oller to

read out the contents of its Device ID Register and possibly data from

succeeding devices of the scan chain. Issue the BYPASS instruction to the

ATmega169 while reading the Device ID Registers of preceding devices of

the boundary scan chain.

– If the Device IDs of all devices in the boundary scan chain must be captured

simultaneously, the ATmega169 must be the first device in the chain.

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Datasheet Revision

History Please note that the referring page numbers in this section are referring to this docu-

ment. The referring revision in this section are referring to the document revision.

Changes from Rev.

2514O-03/06 to Rev.

2514P-07/06

Changes from Rev.

2514N-03/06 to Rev.

2514O-03/06

Changes from Rev.

2514M-05/05 to Rev.

2514N-03/06

Changes from Rev.

2514L-03/05 to Rev.

2514M-05/05

Changes from Rev.

2514K-04/04 to Rev.

2514L-03/05

1. Updated “Fast PWM Mode” on page 109.

2. Updated Features in “USI – Universal Serial Interf ace” on page 179.

3. Added “Clock speed considerations.” on page 185.

4. Updated “Bit 6 – ACBG: Analog Comparator Bandgap Select” on page

191.

5. Updated Table 49 on page 90, Table 51 on page 90, Table 56 on page 117,

Table 57 on page 118, Table 58 on page 119, Table 61 on page 135 and

Table 63 on page 136.

6. Updated “Prescaling and Conversion Timing” on page 196.

7. Updated Features in “LCD Controller” on page 210.

8. Updated “Errata” on page 349.

1. Updated number of General purpose I/O pins from 53 to 54.

2. Updated “Serial Peripheral Interface – SPI” on page 143.

1. Added Not recommended in new designs.

2. Removed the not ice: Thi s datashe et co ver s re vis ion A to E of ATmega169.

Revision F and onwards are now covered in ATmega169 datasheet,

“doc2597.pdf” found on www.atmel.com/avr.

3. Updated Table 17 on page 40.

1. This datasheet covers revisi on A to E of ATmega169.

Revision F and onwards are now covered in ATmega169 datasheet,

“doc2597.pdf” found on www.atmel.com/avr.

1. MLF-package alternative changed to “Quad Flat No-Lead/Micro Lead

Frame Package QFN/MLF”.

2. Updated Table 16 o n page 38, Table 56 on page 117, T able 57 on page 118 ,

Table 98 on page 223, Table 99 on page 223, Table 100 on page 224 and

Table 130 on page 284.

3. Added “Pin Change Interrupt Timing” on page 51.

4. Updated C Code Example in “USART Initialization” on page 157.

5. Added note to “Power Reduction Register - PRR” on page 34 and “LCD

Contrast Control Register – LCDCCR” on page 223.

6. Moved “No. of Words in a Page and No. of P ages in the Flash” a nd “No. of

Words in a Page and No. of Pages in the EEPROM” to “Page Size” on

page 269.

7. Updated “Serial Programming Algorithm” on page 282.

8. Updated “ATmega169 Typical Characteristics” on page 305.

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ATmega169/V

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Changes from Rev.

2514J-12/03 to Rev.

2514K-04/04

Changes from Rev.

2514I-09/03 to Rev.

2514J-12/03

Changes from Rev.

2514H-05/03 to Rev.

2514I-09/03

9. Renamed “Using the P o wer Reduction Register” to “Supply Current of I/O

modules” on page 310.

10. Updated “Register Summary” on page 339.

11. Updated “Ordering Information” on page 346.

12. Updated Figure 83 on page 194 , Figure 91 on page 201, and Figure 123 on

page 277.

1. Changed size from 0x60 to 0xFF in “Stack Pointer” on page 11.

2. Updated Table 17 on page 40, Ta ble 21 on page 44 and Tab le 115 on pag e

265.

3. Updated “Calibrated Internal RC Oscillator” on page 27.

4. Added new “Power Reduction Register” on page 34.

Examples found in “Supply Current of I/O modules” on page 310.

5. Fixed typo in port description for the “Analog to Digital Conver ter” on

page 193.

6. Removed old and added new “LCD Controller” on page 210.

7. Updated “Electrical Characteristics” on page 298.

8. Updated “ATmega169 Typical Characteristics” on page 305.

9. Updated “Ordering Information” on page 346.

ATmega169L replaced by ATmega169V and ATmega169.

1. Updated “Calibrated Internal RC Oscillator” on page 27

1. Removed “Advanc e Information” from the datasheet.

2. Removed AGND from Figure 2 on page 3 and added “System Clock

Prescaler” to Figure 11 on page 23.

3. Updated Table 16 on page 38, Table 17 on page 40, Table 19 on page 42

and Table 41 on page 72.

4. Renamed and updated “On-c hip Debug System” to “JTAG Interface and

On-chip Debug Syst em” on page 36.

5. Updated COM01:0 to COM0A1:0 in “Timer/Counter Control Register A –

TCCR0A” on page 89 and COM21:0 to COM2A1:0 in “Timer/Counter

Control Register A– TCCR2A” on page 135.

6. Updated “Test Access Port – TAP” on page 226 regarding JTAGEN.

7. Updated description for the JTD bit on page 235.

8. Added a note regarding JTAGEN fuse to Table 119 on page 268.

9. Updated Absolute Maximum Ratings* and DC Characteristics in

“Electri ca l Ch ara ct eri st ic s” o n pag e 29 8 .

10. Updated “Errata” on page 349 and add ed a pr o posal for solving pr ob l ems

regarding the JTAG instruction IDCODE.

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Changes from Rev.

2514G-04/03 to Rev.

2514H-05/03

1. Updated typo in Figure 148, Figure 168, and Figure 195.

Changes from Rev.

2514F-04/03 to Rev.

2514G-04/03

1. Updated “ATmega169 Typical Characteristics” on page 305.

2. Updated typo in “Ordering Information” on page 346.

3. Updated Figure 46 on page 109, Table 18 on page 40, and “Version” on page

233.

Changes from Rev.

2514E-02/03 to Rev.

2514F-04/03

1. Renamed ICP to ICP1 in whole document.

2. Removed note on “Crystal Oscillator Operating Modes” on page 25.

3. XTAL1/XTAL2 can be used as timer oscillator pins, described in chapter “Cal-

ibrated Internal RC Oscilla tor” on page 27 .

4. Switching between prescaler settings in “System Clock Prescaler” on page

29.

5. Updated DC and ACD Characteristics in chapter “Electrical Characteristics”

on page 298 are updated. Removed TBD’s from Table 16 on page 38, Table 19

on page 42, Table 134 on page 301.

6. Updated Figure 23 on page 56, Figure 26 on page 60 and Figure 110 on page

238 regarding WRITE PINx REGISTER.

7. Updated “Alternate Functions of Port F” on page 72 regarding JTAG.

8. Replaced Timer0 Overflow with Timer/Counter0 Compare Match in “USI – Uni-

versal Serial Interface” on page 179. Also updated “Start Condition Detector”

on page 185 and “USI Control Register – USICR” on page 187.

9. Updated Features for “Analog to Digital Converter” on page 193 and Table 88

on page 205.

10. Added notes on Figure 118 on page 259 and Table 118 on page 267.

Changes from Rev.

2514D-01/03 to Rev.

2514E-02/03

1. Updated the section “Features” on page 1 with information regarding

ATmega169 and ATmega169L.

2. Removed all references to the PG5 pin in Figure 1 on page 2, Figure 2 o n page

3, “Port G (PG4..PG0)” on page 6, “Alternate Functions of Port G” on page 74,

and “Register Description for I/O-Ports” on page 76.

3. Updated Table 118, “Extended Fuse Byte,” on page 267.

4. Added Errata for “Datasheet Rev ision His tory” on page 353 , in cluding “Signif-

icant Data Sh eet Changes”.

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ATmega169/V

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5. Updated the “Ordering Information” on page 346 to include the new speed

grade for ATmega169L and the new 16 MHz ATmega169.

Changes from Rev.

2514C-11/02 to Rev.

2514D-01/03

1. Added TCK frequency limit in “Programming via the JTAG Interface” on page

285.

2. Added Chip Erase as a fir st st ep in “Programming the Flash” on pag e 295 an d

“Programming the EEPROM” on page 296.

3. Added the section “Unconnected Pins” on page 60.

4. Added tips on how to disable the OCD system in “On-chip Debug System” on

page 35.

5. Corrected interrupt addresses. ADC and ANA_COMP had swapped places.

6. Improved the table in “SPI Timing Characteristics” on page 301 and removed

the table in “SPI Serial Programming Characteristics” on page 285.

7. Changed “will be ignored” to “must be written to zero” for unused Z-pointer

bits in “Performing a Page Write” on page 260.

8. Corrected “LCD Frame Complete” to “LCD Start of Frame” in the LCDCRA

9. Changed OUT to STS and IN to LDS in USI code examples, and corrected

fSCKmax. The USI I/O Registers are in the extended I/O space, so IN and OUT

cannot be used. LDS and STS take one more cycle when executed, so fSCKmax

had to be changed accordingly.

10. Removed TOSKON and TOSCK from Table 103 on page 239, and g10 and g20

from Figure 115 on page 241 and Table 105 on page 242, because these sig-

nals do not exist in boundary scan.

11. Changed fr om 4 to 16 MIPS and MHz in the device Features list.

12. Corrected Port A to Port F in “AVCC” on page 6 under “Pin Descriptions” on

page 5.

13. Corrected 230.4 Mbps to 230.4 kbps in “Examples of Baud Rate Setting” on

page 175.

14. Corrected placing of falling and rising XCK edges in Table 78, “UCPOL Bit

Settings,” on page 174.

15. Removed reference to Multipurpose Oscillator Application Note, which does

not exist.

16. Corrected Number of Calibrated RC Oscillator Cycles in Table 1 on page 19

from 8,448 to 67 ,584.

17. Various minor Timer1 corrections.

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ATmega169/V

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18. Added information about PWM symmetry for Timer0 and Timer2.

19. Corrected the contents of DIDR0 and DIDR1.

20. Made all bit names in the LCDDR Registers unique by adding the COM num-

ber digit in front of the two digits already there, e.g. SEG304.

21. Changed Extended Standby to ADC Noise Reduction mode under “Asynchro-

nous Operation of Timer/Counter2” on page 139.

22. Added note about Port B having better driving capabilities than the other

ports. As a conse quence the table, “DC Chara cterist ics” o n page 298 was c or-

rected as well.

23. Added note under “Filling the Temporary Buffer (Page Loading)” on page 260

about writing to the EEPROM during an SPM page load.

24. Removed ADHSM completely.

25. Updated “Packaging Information” on page 347.

Changes from Rev.

2514B-09/02 to Rev.

2514C-11/02

1. Added “Errata” on page 349.

2. Added Information for the 64-pad MLF Package in “Ordering Information” on

page 346 and “Packaging Information” on page 347.

3. Changed Temperature Range and Removed Industrial Ordering Codes in

“Packaging Information” on page 347.

Changes from Rev.

2514A-08/02 to Rev.

2514B-09/02

1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles.

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ATmega169/V

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Table of Contents Features................................................................................................ 1

Pin Configurations............................................................................... 2

Disclaimer....... ... ................... .... ................... ................... .... ................... ............... 2

Overview............................................................................................... 3

Block Diagram ............................. ................... ... .................... ................... ... ......... 3

Pin Descriptions.................................................................................................... 5

About Code Examples......................................................................... 6

AVR CPU Core ..................................................................................... 7

Introductio n..... ... ... .................... ................... ................... .................... .................. 7

Architectural Overview.......................................................................................... 7

ALU – Arithmetic Logic Unit.................................................................................. 8

Status Register..... ... .... ... ... .................... ................... ................................... ......... 9

General Purpose Register File ........................................................................... 10

Stack Pointer ...................................................................................................... 11

Instruction Exe cu tio n Tim in g . .... ................... ... .................... ................... ... .......... 12

Reset and Interrupt Handling.............................................................................. 12

AVR ATmega169 Memories .............................................................. 15

In-System Reprogrammable Flash Program Memory........................................ 15

SRAM Data Memor y.......... ... .................... ................... ................... .................... 16

EEPROM Data Memory...................................................................................... 17

I/O Memory..... ... ................... .................... ................... ................... .................... 22

System Clock and Clock Options .................................................... 23

Clock Systems and their Distribution.................................................................. 23

Clock Sources. ... ... ... .... ... ................... .................... ... ................... .................... ... 24

Default Clock Source.......................................................................................... 24

Crystal Oscillator ... ... .................... ... ... .................... ... ................... ... .... ................ 25

Low-frequency Crystal Oscillator........................................................................ 26

Calibrated Internal RC Oscillator........................................................................ 27

External Clock..................................................................................................... 28

Clock Output Buffer ............................................................................................ 29

Timer/Counter Oscillator.................... .... ............................................................. 29

System Clock Prescaler...................................................................................... 29

Power Management and Sleep Modes............................................. 32

Idle Mode............................................................................................................ 33

ADC Noise Reduction Mode............................................................................... 33

Power-down Mode.............................................................................................. 33

Power-save Mod e........... ... .................... ... ................... ................... .... ................ 33

Standby Mod e. ... ... ... .... ................... .................................... ................... ............. 34

Power Reduction Register.................................................................................. 34

ATmega169/V

2514P–AVR–07/06

Minimizing Power Consumption ......................................................................... 35

System Control and Reset................................................................ 37

Internal Voltage Reference................................................................................. 42

Watchdog Timer ................................................................................................. 43

Timed Sequences for Chan gin g th e Co nfigu ra tio n of the Wa tchdo g Timer ....... 45

Interrupts............................................................................................ 46

Interrupt Vec to rs in ATme g a169........ .... ... ... ................... .... ................... ............. 46

External Interrupts............................................................................. 51

Pin Change Interrupt Timing............................................................................... 51

I/O-Ports.............................................................................................. 55

Introduction......................................................................................................... 55

Ports as General Digital I/O................................................................................ 56

Alternate Port Functions..................................................................................... 60

8-bit Timer/Counter0 with PWM........................................................ 79

Overview............................................................................................................. 79

Timer/Counter Clo ck Sou rc es............ .... ... ... ................... .... ................... ... ... ....... 80

Counter Unit........................................................................................................ 80

Output Compare Unit.......................................................................................... 81

Compare Match Output Unit............................................................................... 83

Modes of Operation............................................................................................ 84

Timer/Counter Timing Diagrams......................................................................... 88

8-bit Timer/Counter Register Description ........................................................... 89

Timer/Counter0 and Timer/Counter1 Prescalers............................ 93

16-bit Timer/Counter1........................................................................ 95

Overview............................................................................................................. 95

Accessing 16-bit Registers................................................................................. 98

Timer/Counter Clo ck Sou rc es............ .... ... ... ................... .... ................... ... ... ..... 10 1

Counter Unit...................................................................................................... 101

Input Capture Unit............................................................................................. 102

Output Compare Units...................................................................................... 104

Compare Match Output Unit............................................................................. 106

Modes of Operation.......................................................................................... 107

Timer/Counter Timing Diagrams....................................................................... 115

16-bit Timer/Counter Register Description ....................................................... 117

8-bit Timer/Counter2 with PWM and Asynchronous Operation.. 124

Overview........................................................................................................... 124

Timer/Counter Clo ck Sou rc es............ .... ... ... ................... .... ................... ... ... ..... 12 5

iii

ATmega169/V

2514P–AVR–07/06

Counter Unit...................................................................................................... 125

Output Compare Unit........................................................................................ 126

Compare Match Output Unit............................................................................. 128

Modes of Operation.......................................................................................... 129

Timer/Counter Timing Diagrams....................................................................... 133

8-bit Timer/Counter Register Description ......................................................... 135

Asynchrono us op e ratio n of the Timer/Coun te r.. .... ... ... ................... .................. 138

Timer/Counter Pre scaler....... .... ... ... ................... .... ................... ... .................... . 142

Serial Peripheral Interface – SPI..................................................... 143

SS Pin Functionality . .... ... ... .................... ... ................... ................... .... .............. 148

Data Modes ...................................................................................................... 151

USART .............................................................................................. 152

Overview........................................................................................................... 152

Clock Generati on.. ... .... ... ... .................... ... ................... ................... .... .............. 153

Frame Forma ts......................... ................................... ................... .................. 156

USART Initialization.......................................................................................... 157

Data Transmission – The USART Transmitter................................................. 159

Data Reception – The USART Receiver .......................................................... 162

Asynchronous Data Reception......................................................................... 165

Multi-processor Communication Mode............................................................. 169

USART Register Description............................................................................ 170

Examples of Baud Rate Setting........................................................................ 175

USI – Universal Serial Interface...................................................... 179

Overview........................................................................................................... 179

Functional Descr ipt i on s ........ .... ... ... ... .... ................... ................... ... .................. 180

Alternative USI Usage ...................................................................................... 185

USI Register Descriptions................................................................................. 185

Analog Comparator ......................................................................... 190

Analog Comparator Multiplexed Input .............................................................. 192

Analog to Digital Converter ............................................................ 193

Features............................................................................................................ 193

Operation.......................................................................................................... 194

Starting a Conversion....................................................................................... 195

Prescaling and Conversion Timing................................................................... 196

Changing Channel or Reference Selection ...................................................... 199

ADC Noise Canceler......................................................................................... 200

ADC Conversion Result.................................................................................... 204

LCD Controller................................................................................. 210

Features............................................................................................................ 210

Overview........................................................................................................... 210

ATmega169/V

2514P–AVR–07/06

Mode of Operation............................................................................................ 212

LCD Usage....................................................................................................... 216

JTAG Interface and On-chip Debug System ................................. 226

Overview........................................................................................................... 226

Test Access Port – TAP.................................................................................... 226

TAP Controller.................................................................................................. 228

Using the Boundary-scan Chain....................................................................... 229

Using the On-chip Debug System .................................................................... 229

On-chip Debug Specific JTAG Instructions ...................................................... 230

On-chip Debug Related Register in I/O Memory.............................................. 231

Using the JTAG Programming Capabilities...................................................... 231

Bibliography...................................................................................................... 231

IEEE 1149.1 (JTAG) Boundary-scan .............................................. 232

Features............................................................................................................ 232

System Overvie w............ ................................... .................... ................... ........ 232

Data Registers.................................................................................................. 232

Boundary-scan Specific JTAG Instructions ...................................................... 234

Boundary-scan Related Register in I/O Memory.............................................. 235

Boundary-s ca n Cha in..... ... ... .... ... ................... .................... .............................. 236

ATmega169 Boundary-scan Order................................................................... 246

Boundary-scan Description Language Files..................................................... 251

Boot Loader Support – Read-While-Write Self-Programming..... 252

Boot Loader Features....................................................................................... 252

Application and Boot Loader Flash Sections.................................................... 252

Read-While-Write and No Read-While-Write Flash Sections........................... 252

Boot Loader Lock Bits....................................................................................... 255

Entering the Boot Lo ad e r P ro gram. .................................... ................... ........... 256

Addressing the Flash During Self-Programming .............................................. 258

Self-Programming the Flash............................................................................. 259

Memory Programming..................................................................... 266

Program And Data M em o ry Lo ck Bits ...... ... ... ... .... ................... ... .................... . 266

Fuse Bits...................... ... ................... .... ................... ................... ... .................. 267

Signature Bytes ................................................................................................ 269

Calibration Byte ................................................................................................ 269

Page Size ......................................................................................................... 269

Parallel Programming Parameters, Pin Mapping, and Commands.................. 269

Serial Programming Pin Mapping..................................................................... 272

Parallel Programm in g..... ... ... .... ... ................... ... .................... ................... ... ..... 27 3

Serial Downloading........................................................................................... 281

Programming via the JTAG Interface ............................................................... 285

Electrical Characteristics................................................................ 298

ATmega169/V

2514P–AVR–07/06

Absolute Maximu m Ra ting s*........... ... .... ... ... ................... .................... ... ........... 298

DC Characteristics............................................................................................ 298

External Clock Drive Waveforms...................................................................... 300

External Clock Drive......................................................................................... 300

Maximum Speed vs. VCC ........................................................................................................................ 300

SPI Timing Characteristics ............................................................................... 301

ADC Characteristics – Preliminary Data........................................................... 303

LCD Controller Char ac te rist ics – P re limin a ry Data......... .... ... ... ................... .... . 304

ATmega169 Typical Characteristics .............................................. 305

Active Supply Current....................................................................................... 305

Idle Supply Current........................................................................................... 308

Supply Current of I/O modules ......................................................................... 310

Power-down Supply Current............................................................................. 311

Power-save Supply Current.............................................................................. 312

Standby Supply Current.................................................................................... 313

Pin Pull-up ........................................................................................................ 317

Pin Driver Strength ........................................................................................... 320

Pin Thresholds and hysteresis.......................................................................... 326

BOD Thresholds and Ana l o g Comp ar a to r Off set ..... ... ... .................... ... ... ........ 329

Internal Oscillator Speed .................................................................................. 332

Current Consumption of Peripheral Units......................................................... 334

Current Consumption in Reset and Reset Pulsewidth...................................... 337

Instruction Set Summary ................................................................ 343

Ordering Information....................................................................... 346

Packaging Information.................................................................... 347

64A ................................................................................................................... 347

64M1................................................................................................................. 348

Errata ................................................................................................ 349

ATmega169 Rev E ........................................................................................... 349

ATmega169 Rev D........................................................................................... 349

ATmega169 Rev C........................................................................................... 350

ATmega169 Rev B ........................................................................................... 351

Datasheet Revision History ............................................................ 353

Changes from Rev. 2514O-03/06 to Rev. 2514P-07/06................................... 353

Changes from Rev. 2514N-03/06 to Rev. 2514O-03/06................................... 353

Changes from Rev. 2514M-05/05 to Rev. 2514N-03/06 .................................. 353

Changes from Rev. 2514L-03/05 to Rev. 2514M-05/05................................... 353

Changes from Rev. 2514K-04/04 to Rev. 2514L-03/05.................................... 353

ATmega169/V

2514P–AVR–07/06

Changes from Rev. 2514J-12/03 to Rev. 2514K-04/04.................................... 354

Changes from Rev. 2514I-09/03 to Rev. 2514J-12/03..................................... 354

Changes from Rev. 2514H-05/03 to Rev. 2514I-09/03 .................................... 354

Changes from Rev. 2514G-04/03 to Rev. 2514H-05/03................................... 355

Changes from Rev. 2514F-04/03 to Rev. 2514G-04/03................................... 355

Changes from Rev. 2514E-02/03 to Rev. 2514F-04/03 ................................... 355

Changes from Rev. 2514D-01/03 to Rev. 2514E-02/03................................... 355

Changes from Rev. 2514C-11/02 to Rev. 2514D-01/03................................... 356

Changes from Rev. 2514B-09/02 to Rev. 2514C-11/02................................... 357

Changes from Rev. 2514A-08/02 to Rev. 2514B-09/02................................... 357

Table of Contents ................................................................................. i

2514P–AVR–07/06

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