Rev.1.02, Feb.20.2020, page 1 of 13
R1LV1616HBG-I Series
Wide Temperature Range Version
16 M SRAM (1-Mword 16-bit)
REJ03C0263-0102
Rev. 1.02
Feb.20.2020
Description
The R1LV1616HBG-I Series is 16-Mbit static RAM organized 1-Mword 16-bit with embedded ECC.
R1LV1616HBG-I Series has realized higher density, higher performance and low power consumption by employing
CMOS process technology (6-transistor memory cell). It offers low power standby power dissipation; therefore, it is
suitable for battery backup systems. It is packaged in 48-ball plastic FBGA for high density surface mounting.
Features
Single 3.0 V supply: 2.7 V to 3.6 V
Fast access time: 45/55 ns (max)
Power dissipation:
Active: 9 mW/MHz (typ)
Standby: 1.5 W (typ)
Completely static memory.
No clock or timing strobe required
Equal access and cycle times
Common data input and output.
Three state output
Battery backup operation.
2 chip selection for battery backup
Temperature range: 40 to +85C
Embedded ECC (error checking and correction) for single-bit error correction
Ordering Information
Type No. Access time Package
R1LV1616HBG-4SI 45 ns 48-ball plastic FBGA with 0.75 mm ball pitch
R1LV1616HBG-5SI 55 ns PTBG0048HF (48FHJ)
R1LV1616HBG-I Series
Rev.1.02, Feb.20.2020, page 2 of 13
Pin Arrangement
Pin Description
Pin name Function
A0 to A19 Address input
I/O0 to I/O15 Data input/output
CS1# (CS1) Chip select 1
CS2 Chip select 2
WE# (WE) Write enable
OE# (OE) Output enable
LB# (LB) Lower byte select
UB# (UB) Upper byte select
VCC Power supply
VSS Ground
NU*1 Not used (test mode pin)
Note: 1. This pin should be connected to a ground (VSS), or not be connected (open).
(Top view)
48-ball FBGA
LB#
I/O8
I/O9
Vss
Vcc
I/O14
I/O15
A18
A
B
C
D
E
F
G
H
1 2 3 4 5 6
OE#
UB#
I/O10
I/O11
I/O12
I/O13
A19
A8
A0
A3
A5
A17
Vss
A14
A12
A9
A1
A4
A6
A7
A16
A15
A13
A10
A2
CS1#
I/O1
I/O3
I/O4
I/O5
WE#
A11
CS2
I/O0
I/O2
Vcc
Vss
I/O6
I/O7
NU
R1LV1616HBG-I Series
Rev.1.02, Feb.20.2020, page 3 of 13
Block Diagram
Memory matrix
A19
A8
A9
A10
A11
A12
A13
A14
A16
A15
A3
8,192 x 128 x 16
Row
decoder
・
Input
data
control
A0
A1A2A4A5A7
・
・
・
・
I
/
O0
I
/
O15
CS2
CS1#
OE#
VCC
VSS
Control logic
Column I
/
O
Column decoder
LB#
UB#
WE#
A6
LSB
MSB
A17
MSB
LS
ECC
encoder
・
・・
・
ECC
decoder
・
・
A18
・
・
・
・
R1LV1616HBG-I Series
Rev.1.02, Feb.20.2020, page 4 of 13
Operation Table
CS1# CS2 WE# OE# UB# LB# I/O0 to I/O7 I/O8 to I/O15 Operation
H High-Z High-Z Standby
L High-Z High-Z Standby
H H High-Z High-Z Standby
L H H L LLDout Dout Read
L H H L H L Dout High-Z Lower byte read
L H H L L H High-Z Dout Upper byte read
L H L L L Din Din Write
L H L H L Din High-Z Lower byte write
L H L L H High-Z Din Upper byte write
L H H H High-Z High-Z Output disable
Note: H: VIH, L: VIL, : VIH or VIL
Absolute Maximum Ratings
Parameter Symbol Value Unit
Power supply voltage relative to VSS V
CC 0.5 to +4.6 V
Terminal voltage on any pin relative to VSS V
T 0.5*1 to VCC + 0.3*2 V
Power dissipation PT 1.0 W
Storage temperature range Tstg 55 to +125 C
Storage temperature range under bias Tbias 40 to +85 C
Notes: 1. VT min: 2.0 V for pulse half-width 10 ns.
2. Maximum voltage is +4.6 V.
DC Operating Conditions
Parameter Symbol Min Typ Max Unit Note
Supply voltage VCC 2.7 3.0 3.6 V
V
SS 0 0 0 V
Input high voltage VIH 2.2  VCC + 0.3 V
Input low voltage VIL 0.3  0.6 V 1
Ambient temperature range Ta 40  +85 C
Note: 1. VIL min: 2.0 V for pulse half-width 10 ns.
R1LV1616HBG-I Series
Rev.1.02, Feb.20.2020, page 5 of 13
DC Characteristics
Parameter Symbol Min Typ Max Unit Test conditions
Input leakage current |ILI|   1 A Vin = VSS to VCC
Output leakage current |ILO|   1 A CS1# = VIH or CS2 = VIL or
OE# = VIH or WE# = VIL or
LB# = UB# = VIH, VI/O = VSS to VCC
Operating current ICC   20 mA
CS1# = VIL, CS2 = VIH,
Others = VIH/ VIL, II/O = 0 mA
Average operating current ICC1
(READ)
 22*1 35 mA
Min. cycle, duty = 100%,
II/O = 0 mA, CS1# = VIL, CS2 = VIH,
WE# = VIH, Others = VIH/VIL
I
CC1  30*1 50 mA
Min. cycle, duty = 100%,
II/O = 0 mA, CS1# = VIL, CS2 = VIH,
Others = VIH/VIL
ICC2
(READ)
 3*1 8 mA
Cycle time = 70 ns, duty = 100%,
II/O = 0 mA, CS1# = VIL, CS2 = VIH,
WE# = VIH, Others = VIH/VIL
Address increment scan or decrement
scan
I
CC2  20*1 30 mA
Cycle time = 70 ns, duty = 100%,
II/O = 0 mA, CS1# = VIL, CS2 = VIH,
Others = VIH/VIL
Address increment scan or decrement
scan
I
CC3  3*1 8 mA
Cycle time = 1 s, duty = 100%,
II/O = 0 mA, CS1# 0.2 V,
CS2 VCC 0.2 V
VIH VCC 0.2 V, VIL 0.2 V
Standby current ISB  0.1*1 0.5 mA CS2 = VIL
ISB1  0.5*1 8 A 0 V Vin
(1) 0 V CS2 0.2 V or
(2) CS1# VCC 0.2 V,
CS2 VCC 0.2 V or
(3) LB# = UB# VCC 0.2 V,
CS2 VCC 0.2 V,
CS1# 0.2 V
Average value
Output high voltage VOH 2.4   V IOH = 1 mA
V
OH V
CC
0.2
  V IOH = 100 A
Output low voltage VOL   0.4 V IOL = 2 mA
V
OL   0.2 V IOL = 100 A
Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25C and not guaranteed.
R1LV1616HBG-I Series
Rev.1.02, Feb.20.2020, page 6 of 13
Capacitance
(Ta = +25C, f = 1.0 MHz)
Parameter Symbol Min Typ Max Unit Test conditions Note
Input capacitance Cin   8 pF Vin = 0 V 1
Input/output capacitance CI/O   10 pF VI/O = 0 V 1
Note: 1. This parameter is sampled and not 100% tested.
AC Characteristics
(Ta = 40 to +85C, VCC = 2.7 V to 3.6 V)
Test Conditions
Input pulse levels: VIL = 0.4 V, VIH = 2.4 V
Input rise and fall time: 5 ns
Input and output timing reference levels: 1.4 V
Output load: See figures (Including scope and jig)
Dout
1
.
4
V
RL = 500Ω
50 pF
R1LV1616HBG-I Series
Rev.1.02, Feb.20.2020, page 7 of 13
Read Cycle
R1LV1616HBG-I
-4SI -5SI
Paramete
r
Symbol Min Max Min Max Unit Notes
Read cycle time tRC 45
 55  ns
Address access time tAA  45  55 ns
Chip select access time tACS1  45  55 ns
t
ACS2  45  55 ns
Output enable to output valid tOE  30  35 ns
Output hold from address change tOH 10
 10  ns
LB#, UB# access time tBA  45  55 ns
Chip select to output in low-Z tCLZ1 10
 10  ns 2, 3
t
CLZ2 10
 10  ns 2, 3
LB#, UB# enable to low-Z tBLZ 5
 5  ns 2, 3
Output enable to output in low-Z tOLZ 5
 5  ns 2, 3
Chip deselect to output in high-Z tCHZ1 0 20 0 20 ns 1, 2, 3
t
CHZ2 0 20 0 20 ns 1, 2, 3
LB#, UB# disable to high-Z tBHZ 0 15 0 20 ns 1, 2, 3
Output disable to output in high-Z tOHZ 0 15 0 20 ns 1, 2, 3
Write Cycle
R1LV1616HBG-I
-4SI -5SI
Parameter Symbol Min Max Min Max Unit Notes
Write cycle time tWC 45  55  ns
Address valid to end of write tAW 45  50  ns
Chip selection to end of write tCW 45  50  ns 5
Write pulse width tWP 35  40  ns 4
LB#, UB# valid to end of write tBW 45  50  ns
Address setup time tAS 0  0  ns 6
Write recovery time tWR 0  0  ns 7
Data to write time overlap tDW 25  25  ns
Data hold from write time tDH 0  0  ns
Output active from end of write tOW 5  5  ns 2
Output disable to output in high-Z tOHZ 0 15 0 20 ns 1, 2
Write to output in high-Z tWHZ 0 15 0 20 ns 1, 2
Notes: 1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and
are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from
device to device.
4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A
write begins at the latest transition among CS1# going low, CS2 going high, WE# going low and LB# going
low or UB# going low. A write ends at the earliest transition among CS1# going high, CS2 going low, WE#
going high and LB# going high or UB# going high. tWP is measured from the beginning of write to the end of
write.
5. tCW is measured from the later of CS1# going low or CS2 going high to the end of write.
6. tAS is measured from the address valid to the beginning of write.
7. tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle.
R1LV1616HBG-I Series
Rev.1.02, Feb.20.2020, page 8 of 13
Timing Waveform
Read Cycle
tAA tACS1
tACS2
tCLZ2
tCLZ1
tBLZ
tBA
tOH
tRC
Valid data
Valid address
High impedance
CS1#
CS2
LB#, UB#
OE#
tOLZ
tOE
tCHZ1
tCHZ2
tBHZ
tOHZ
Address*2
Dout*3
Notes: 1. BYTE# > VCC – 0.2 V or
BYTE# < 0.2 V
2. Word mode: A0 to A19
Byte mode: A-1 to A19
3. Word mode: I/O0 to I/O15
Byte mode: I/O0 to I/O7
R1LV1616HBG-I Series
Rev.1.02, Feb.20.2020, page 9 of 13
Write Cycle (1) (WE# Clock)
WE#
tWC
tAW
tWP
tWR
tCW
tCW
tBW
tAS
tOW
tWHZ
tDW tDH
Valid address
Valid data
CS1#
LB#, UB#
High impedance
CS2
Address*2
Dout*3
Din*3
Notes: 1. BYTE# > VCC – 0.2 V or
BYTE# < 0.2 V
2. Word mode: A0 to A19
Byte mode: A-1 to A19
3. Word mode: I/O0 to I/O15
Byte mode: I/O0 to I/O7
R1LV1616HBG-I Series
Rev.1.02, Feb.20.2020, page 10 of 13
Write Cycle (2) (CS1#, CS2 Clock, OE# = VIH)
Address*2
WE#
tWC
tAW
tWP
tWR
tCW
tCW
tBW
tAS
tDW tDH
Valid address
Valid data
LB#, UB#
Dout*3
Din*3
High impedance
CS2
CS1#
Notes: 1. BYTE# > VCC – 0.2 V or
BYTE# < 0.2 V
2. Word mode: A0 to A19
Byte mode: A-1 to A19
3. Word mode: I/O0 to I/O15
Byte mode: I/O0 to I/O7
tAS
R1LV1616HBG-I Series
Rev.1.02, Feb.20.2020, page 11 of 13
Write Cycle (3) (LB#, UB# Clock, OE# = VIH)
Address
WE#
tWC
tAW
tWP
tCW
tCW
tBW
tBW
tWR
tDW tDH
Valid address
UB# (LB#)
High impedance
CS2
CS1#
tAS
LB# (UB#)
Dout
Din-UB
(Din-LB)
Din-LB
(Din-UB)
Valid data
tDW tDH
Valid data
Note: 1. BYTE# > VCC – 0.2 V
R1LV1616HBG-I Series
Rev.1.02, Feb.20.2020, page 12 of 13
Low VCC Data Retention Characteristics
(Ta = 40 to +85C)
Parameter Symbol Min Typ Max Unit Test conditions*2
VCC for data retention VDR 1.5  3.6 V
Vin 0 V
(1) 0 V CS2 0.2 V or
(2) CS2 VCC 0.2 V,
CS1# VCC 0.2 V or
(3) LB# = UB# VCC 0.2 V,
CS2 VCC 0.2 V,
CS1# 0.2 V
Data retention current ICCDR  0.5*1 8 A VCC = 3.0 V, Vin 0 V
(1) 0 V CS2 0.2 V or
(2) CS2 VCC 0.2 V,
CS1# VCC 0.2 V or
(3) LB# = UB# VCC 0.2 V,
CS2 VCC 0.2 V,
CS1# 0.2 V
Average value
Chip deselect to data
retention time
tCDR 0   ns See retention waveforms
Operation recovery time tR 5   ms
Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25C and not guaranteed.
2. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer, LB#, UB# buffer and Din buffer. If CS2
controls data retention mode, Vin levels (address, WE#, OE#, CS1#, LB#, UB#, I/O) can be in the high
impedance state. If CS1# controls data retention mode, CS2 must be CS2 VCC 0.2 V or 0 V CS2 0.2
V. The other input levels (address, WE#, OE#, LB#, UB#, I/O) can be in the high impedance state.
R1LV1616HBG-I Series
Rev.1.02, Feb.20.2020, page 13 of 13
Low VCC Data Retention Timing Waveform (1) (CS1# Controlled)
CC
V
2.7 V
2.2 V
0 V
CS1#
t
CDR
t
R
CS1# V – 0.2 V
CC
DR
V
Data retention mode
Low VCC Data Retention Timing Waveform (2) (CS2 Controlled)
CC
V
2.7 V
0.6 V
0 V
CS2
CDR
t
R
0 V CS2 0.2 V
DR
V
Data retention modet
< <
Low VCC Data Retention Timing Waveform (3) (LB#, UB# Controlled)
CC
V
2.7 V
2.2 V
0 V
LB#, UB#
t
CDR
t
R
LB#, UB# V – 0.2 V
CC
DR
V
Data retention mode
All trademarks and registered trademarks are the property of their respective owners.
Revision History R1LV1616HBG-I Series Data Sheet
Rev. Date Contents of Modification
Page Description
0.01 Apr.29.2005 ― Initial issue
1.00 Sep.21.2005 ― Deletion of Preliminary
1.01 Feb.23.2017 p.1,p.3 Disclosed embedded ECC features
1.02 Feb.20.2020 Last page Updated the Notice to the latest version
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