PERFORMANCE MIN. TYP. MAX. UNITS
Int. Linearity @ +25°C
(ref. unadjusted)
End-point — ±2 ±2.6 LSB
Best-fi t Line — ±1.6 ±1.9 LSB
Int. Linearity Over Temp.
(ref. unadjusted)
End-point — ±2.3 ±2.6 LSB
Best-fi t Line — ±1.8 ±2.0 LSB
Zero-Scale Offset — ±1 ±2 LSB
(Code "0" to "1" transition)
Gain Error — ±1.5 ±3 LSB
Differential Gain ➂ — 2 — %
Differential Phase ➂ — 1.1 —
degrees
Aperture Delay — 8 — ns
Aperture Jitter — 50 — ps
Harmonic Distortion
(8MHz second order harm.) –40 –46 — dB
Ref. bandwidth
(See tech note 5) — 10 — MHz
Power Supply Rejection — ±0.02 ±0.05 %FSR/%Vs
No Missing Codes Over the operating temperature range
POWER REQUIREMENTS
Power Supply Range (+VDD) +3.0 +5.0 +5.5 Volts
Power Supply Current
+25°C — +45 +65 mA
+85°C — +40 +60 mA
–40°C — +50 +70 mA
+125°C — +40 +60 mA
–55°C — +50 +70 mA
Power Dissipation
+25°C — 225 325 mW
+85°C — 200 300 mW
–40°C — 250 350 mW
+125°C — 200 300 mW
–55°C — 250 350 mW
PHYSICAL/ENVIRONMENTAL
Operating Temp. Range, Case:
MC/LC Versions 0 — +70 °C
MC-C/LC-C Versions 0 — +70 °C
ME/LE Versions -40 — +85 °C
ME-C/LE-C Versions -40 — +85 °C
MM/LM/QL Versions –55 — +125 °C
MM-C/LM-C/QL-C Versions –55 — +125 °C
Storage Temp. Range –65 — +150 °C
Package Type
DIP 24-pin ceramic DIP
LCC 24-pin ceramic LCC
FUNCTIONAL SPECIFICATIONS
(Typical at +5V power, +25°C, 20MHz clock, +REFERENCE = +5V,
–REFERENCE = ground, unless noted)
ABSOLUTE MAXIMUM RATINGS
ANALOG INPUT MIN. TYP. MAX. UNITS
Single-Ended, Non-Isolated
Input Range DC - 20MHz 0 – +5.0 Volts
Analog Input Capacitance
(static - Pin 5 to 7) – 20 – pF
(dynamic - Pin 5 to 7) – 64 – pF
Reference Ladder Resistance – 500 – Ohms
Reference Input (Note 5) –0.5 – VDD +0.5 Volts
DIGITAL INPUTS
Logic Levels
Logic "1" 3.2 — — Volts
Logic "0" — — 0.8 Volts
Logic Loading
Logic Loading "1" — +1 +5 µA
Logic Loading "0" — +1 +5 µA
Clock Low Pulse Width 15 25 — nSec
DIGITAL OUTPUTS
Logic Levels
Logic "1" 2.4 4.5 5.0 Volts
Logic "0" — — 0.4 Volts
Logic Loading
Logic Loading "1" 4 — — mA
Logic Loading "0" 4 — — mA
Output Data Valid Delay From
Rising Clock Edge
99% probability 5 10 15 nSec
100% probability
+25°C 5 10 25 nSec
–55°C to +125°C — — 40 nSec
Data Output Resolution 8 — — Bits
Data Coding Straight binary
PERFORMANCE
Sampling Rate ➁ 15 20 — MSPS
Full Power Bandwidth 10 — — MHz
Diff. Linearity @ +25°C
(See tech note 7)
Code Transitions — ±0.5 ±1.0 LSB
Center of Codes — ±0.25 — LSB
Diff. Linearity Over Temp.
Code Transitions — ±0.5 ±1.0 LSB
Center of Codes — ±0.25 — LSB
Int. Linearity @ +25°C
(See tech note 4)(ref. adjusted)
End-point — — ±1/2 LSB
Best-fi t Line — — ±1/2 LSB
Int. Linearity Over Temp.
(ref. adjusted)
Best-fi t Line — ±1/2 ±1 LSB
Footnotes:
➀ Maximum input impedance is a function of clock frequency.
➁ At full-power input.
➂ For 10-step, 40 IRE NTSC ramp test.
PARAMETERS LIMITS UNITS
Power Supply Voltage (VDD Pin 1, 10, 19) –0.5 to +7 Volts
Digital Inputs –0.5 to +5.5 Volts
Analog Input –0.5 to (+VDD +0.5) Volts
Reference Inputs –0.5 to (+VDD +0.5) Volts
Digital Outputs –0.5 to +5.5 Volts
(short circuit protected to ground)
Lead Temperature (10 sec. max.) +300 max. °C
Storage Temperature –65 to +150 °C
09 Mar 2012 ADC-208A.B03 Page 2 of 4
ADC-208A
8-Bit, 20MSPS CMOS Flash A/D (ADC-208 Compatible)
®®
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