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1994
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD485506
LINE BUFFER
5K-WORD BY 16-BIT/10K-WORD BY 8-BIT
The mark <R> shows major revised points.
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.
Document No. M10060EJ8V0DS00 (8th edition)
Date Published March 2006 N CP(K)
Printed in Japan
Description
The
µ
PD485506 is a high speed FIFO (First In First Out) line buffer. Word organization can be changed either
5,048 words by 16 bits or 10,096 words by 8 bits. Its CMOS static circuitry provides high speed access and low power
consumption.
The
µ
PD485506 can be used for one line delay and time axis conversion in high speed facsimile machines and
digital copiers.
Moreover, the
µ
PD485506 can execute read and write operations independently on an asynchronous basis. Thus
the
µ
PD485506 is suitable as a buffer for data transfer between units with different transfer rates and as a buffer for
the synchronization of multiple input signals.
There are four versions, E, K, P, X and L. This data sheet can be applied to the version X and L. These versions
operate with different specifications. Each version is identified with its lot number (refer to 7. Example of Stamping).
Features
•5,048 words by 16 bits (Word mode) /10,096 words by 8 bits (Byte mode)
•Asynchronous read/write operations available
•Variable length delay bits; 21 to 5,048 bits or 10,096 bits (Cycle time: 25 ns)
15 to 5,048 bits or 10,096 bits (Cycle time: 35 ns)
•Power supply voltage VCC = 5.0 V ±0.5 V
•Suitable for sampling two lines of A3 size paper (16 dots/mm)
•All input/output TTL compatible
•3-state output
•Full static operation; data hold time = infinity
Ordering Information
Part Number R/W Cycle Time Package
µ
PD485506G5-25-7JF 25 ns 44-pin PLASTIC TSOP (II) (10.16 mm (400))
µ
PD485506G5-35-7JF 35 ns
µ
PD485506G5-25-7JF-A 25 ns
µ
PD485506G5-35-7JF-A 35 ns
Remark Products with -A at the end of the part number are lead-free products.
<R>
<R>
<R>
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
µ
PD485506
2Data Sheet M10060EJ8V0DS
Pin Configuration (Marking side)
44-pin PLASTIC TSOP (II) (10.16 mm (400))
[
µ
PD485506G5-7JF]
[
µ
PD485506G5-7JF-A]
DIN0 to DIN15 : Data Inputs
DOUT0 to DOUT15 : Data Outputs
WCK : Write Clock Input
RCK : Read Clock Input
WE : Write Enable Input
RE : Read Enable Input
OE : Output Enable Input
RSTW : Reset Write Input
RSTR : Reset Read Input
MD : Mode Set Input
VCC : +5.0 V Power Supply
GND : Ground
Remark Refer to Package Drawing for the 1-pin index mark.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
D
IN0
D
IN1
D
IN2
D
IN3
D
IN4
D
IN5
D
IN6
D
IN7
WE
MD
GND
RSTW
WCK
V
CC
D
IN8
D
IN9
D
IN10
D
IN11
D
IN12
D
IN13
D
IN14
D
IN15
D
OUT0
D
OUT1
D
OUT2
D
OUT3
D
OUT4
D
OUT5
D
OUT6
D
OUT7
RE
GND
RSTR
RCK
V
CC
D
OUT8
D
OUT9
D
OUT10
D
OUT11
D
OUT12
D
OUT13
D
OUT14
D
OUT15
OE
<R>
µ
PD485506
3
Data Sheet M10060EJ8V0DS
Block Diagram
WE
D
OUT0
D
OUT1
D
OUT2
D
OUT3
D
OUT4
D
OUT5
D
OUT6
D
OUT7
RSTR
RE
V
CC
GND
Write Address Pointer
Mode Controller
40,384 bits
(5,048 words by 8 bits)
Memory Cell Array
RSTW
WCK RCK
Output Buffer
Read Address Pointer
40,384 bits
(5,048 words by 8 bits)
Memory Cell Array
Input Buffer
Output Buffer
D
OUT8
D
OUT9
D
OUT10
D
OUT11
D
OUT12
D
OUT13
D
OUT14
D
OUT15
Output ControllerOutput Controller
OE
MD
D
IN0
D
IN1
D
IN2
D
IN3
D
IN4
D
IN5
D
IN6
D
IN7
D
IN8
D
IN9
D
IN10
D
IN11
D
IN12
D
IN13
D
IN14
D
IN15
Input Buffer
Input ControllerInput Controller
µ
PD485506
4Data Sheet M10060EJ8V0DS
1. Input/Output Pin Function
Pin
Pin Symbol Pin
Number Name
44 – 37, DIN0 Data
|Input
30 – 23 DIN15
1 – 8, DOUT0 Data
|Output
15 – 22 DOUT15
33 RSTW Reset
Write
Input
12 RSTR Reset
Read
Input
36 WE Write
Enable
Input
10 RE Read
Enable
Input
9OEOutput
Enable
Input
32 WCK Write
Clock
Input
13 RCK Read
Clock
Input
35 MD Mode
Set
Input
I/O Function
In Write data input pins.
The data inputs are strobed by the rising edge of WCK at the end of a cycle
and the setup and hold times (tDS, tDH) are defined at this point.
Out Read data output pins.
The access time is regulated from the rising edge of RCK at the beginning of a
cycle and defined by tAC.
In Reset input pin for the initialization of the write address pointer.
The state of RSTW is strobed by the rising edge of WCK at the beginning of a
cycle and the setup and hold times (tRS, tRH) are defined.
In Reset input pin for the initialization of the read address pointer.
The state of RSTR is strobed by the rising edge of RCK at the beginning of a
cycle and the setup and hold times (tRS, tRH) are defined.
In Write operation control signal input pin.
When WE is in the disable mode (“H” level), the internal write operation is
inhibited and the write address pointer stops at the current position.
In Read operation control signal input pin.
When RE is in the disable mode (“H” level), the internal read operation is
inhibited and the read address pointer stops at the current position. The data
outputs remain valid for that address.
In Output operation control signal input pin.
When OE is in the disable mode (“H” level), the data out is inhibited and the
output changes to high impedance. The internal read operation is executed at
that time and the read address pointer incremented in synchronization with the
read clock.
In Write clock input pin.
When WE is enabled (“L” level), the write operation is executed in
synchronization with the write clock. The write address pointer is incremented
simultaneously.
In Read clock input pin.
When RE is enabled (“L” level), the read operation is executed in synchroniza-
tion with the read clock. The read address pointer is incremented
simultaneously.
In Mode set input pin.
The level of MD gives the operation mode. When MD is in “L” level,
5,048 words by 16 bits configuration with DIN0 - DIN15, DOUT0 - DOUT15 is enabled.
When MD is in “H” level, 10,096 words by 8 bits configuration with DIN0 - DIN7,
DOUT0 - DOUT7 is enabled.
µ
PD485506
5
Data Sheet M10060EJ8V0DS
2. Operation Mode
µ
PD485506 is a synchronous memory. All signals are strobed at the rising edge of the clock (RCK, WCK).
For this reason, setup time and hold time are specified for the rising edge of the clock (RCK, WCK).
2.1 Mode Set Cycle (5,048 words by 16 bits or 10,096 words by 8 bits organization)
µ
PD485506 has a capability of selecting from two operation modes by judging the MD level when RSTW or
RSTR is enabled in the reset cycle.
MD Level Bit Configuration Data Inputs/Outputs Control Signal
“L” 5,048 words by 16 bits DIN0 - DIN15 WCK, WE, RSTW
DOUT0 - DOUT15 RCK, RE, RSTR
“H” 10,096 words by 8 bits DIN0 - DIN7 WCK, WE, RSTW
DOUT0 - DOUT7 RCK, RE, RSTR
Caution Don’t change the MD level during a reset cycle. (See Figure 4.6, 7, 8, 9 Mode Set Cycle Timing
Chart)
5,048 Words by 16 Bits FIFO
WCK WE RSTW
D
IN0
- D
IN15
D
OUT0
- D
OUT15
OERSTRRERCK
5,048 Words
by
16 Bits
10,096 Words by 8 Bits FIFO
OERSTRRERCK
D
IN0
- D
IN7
D
OUT0
- D
OUT7
WCK WE RSTW
10,096 Words by 8 Bits
Remark Fix DIN8 - DIN15 to “L” or “H” level in the 10,096 words by 8 bits mode.
µ
PD485506
6Data Sheet M10060EJ8V0DS
2.2 Write Cycle
When the WE input is enabled (“L” level), a write cycle is executed in synchronization with the WCK clock
input.
The data inputs are strobed by the rising edge of the clock at the end of a cycle so that read data after a one-
line (5,048 bits or 10,096 bits) delay and write data can be processed with the same clock. Refer to Write Cycle
Timing Chart.
When WE is disabled (“H” level) in a write cycle, the write operatoin is not performed during the cycle which
the WCK rising edge is in the WE = “H” level (tWEW). The WCK does not increment the write address pointer
at this time.
Unless inhibited by WE, the internal write address will automatically wrap around from 5,047 to 0 and begin
incrementing again.
2.3 Read Cycle
When the RE input is enabled (“L” level), a read cycle is executed in synchronization with the RCK clock input.
When the OE input is also enabled (“L” level) at that time, data is output after tAC. Refer to Read Cycle Timing
Chart.
When RE is disabled (“H” level) in a read cycle, the read operation is not performed during the cycle which
the RCK rising edge is in the RE = “H” level (tREW). The RCK does not increment the read address pointer at
this time.
2.4 Write Reset Cycle/Read Reset Cycle
After power up, the
µ
PD485506 requires the initialization of internal circuits because the read and write
address pointers are not defined at that time.
It is necessary to satisfy setup requirements and hold times as measured from the rising edge of WCK and
RCK, and then input the RSTW and RSTR signals to initialize the circuit.
Write and read reset cycles can be executed at any time and the address pointer returns zero. Refer to Write
Reset Cycle Timing Chart, Read Reset Cycle Timing Chart.
Remark Write and read reset cycles can be executed at any time and do not depend on the state of RE, WE or
OE.
µ
PD485506
7
Data Sheet M10060EJ8V0DS
Operation-related Restriction
Following restriction exists to read data written in a write cycle.
Read the written data after an elapse of 1/2 write cycle + tWAR since the write cycle ends (see Figure 2.1).
If tWAR is not satisfied, the output data may undefined.
Figure 2.1 Delay Bits Restriction Timing Chart
Remark This timing chart describes only the delay bits restriction, and does not defines the WE, RE, RSTW, RSTR
signals.
0123
WCK
012
RCK
1/2 write cycle
tWAR
DIN 0123
DOUT 0123
tAC
High impedance
High impedance
µ
PD485506
8Data Sheet M10060EJ8V0DS
3. Electrical Specifications
All voltages are referenced to GND.
Absolute Maximum Ratings
Parameter Symbol Condition Rating Unit
Voltage on any pin relative to GND VT–0.5Note to VCC + 0.5 V
Supply voltage VCC –0.5 to +7.0 V
Output current IO20 mA
Operating ambient temperature TA0 to 70 ˚C
Storage temperature Tstg –55 to +125 ˚C
Note –3.0 V MIN. (Pulse width = 10 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Symbol Condition MIN. TYP. MAX. Unit
Supply voltage VCC 4.5 5.0 5.5 V
High level input voltage VIH 2.4
VCC + 0.5
V
Low level input voltage VIL –0.3Note +0.8 V
Operating ambient temperature
TA070˚C
Note –3.0 V MIN. (Pulse width = 10 ns)
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter Symbol Test Condition MIN. TYP. MAX. Unit
Operating current ICC 140 mA
Input leakage current IIVI = 0 to VCC, Other Input 0 V –10 +10
µ
A
Output leakage current IOVO = 0 to VCC, DOUT: High impedance –10 +10
µ
A
High level output voltage VOH IOH = –1 mA 2.4 V
Low level output voltage VOL IOL = 2 mA 0.4 V
Capacitance (TA = 25 ˚C, f = 1 MHz)
Parameter Symbol Test Condition MIN. TYP. MAX. Unit
Input capacitance CI10 pF
Output capacitance CO10 pF
µ
PD485506
9
Data Sheet M10060EJ8V0DS
AC Characteristics (Recommended Operating Conditions unless otherwise noted)Notes 1, 2, 3
Parameter Symbol
µ
PD485506-25
µ
PD485506-35 Unit Notes
MIN. MAX. MIN. MAX.
Write clock cycle time tWCK 25 35 ns
Write clock pulse width tWCW 11 12 ns
Write clock precharge time tWCP 11 12 ns
Read clock cycle time tRCK 25 35 ns
Read clock pulse width tRCW 11 12 ns
Read clock precharge time tRCP 11 12 ns
Access time tAC 18 25 ns
Write data-read delay time tWAR 470 470 ns
Output hold time tOH 55ns
Output low-impedance time tLZ 518525ns4
Output high-impedance time tHZ 518525ns4
Input data setup time tDS 710ns
Input data hold time tDH 33ns
MD Set setup time tMS 20 20 ns
MD Set hold time tMH 10 10 ns
MD Set time tMD 00ns5
Output low-impedance time (Mode change) tLZM 518525ns4
Output high-impedance time (Mode change) tHZM 518525ns4
RSTW/RSTR Setup time tRS 710ns6
RSTW/RSTR Hold time tRH 33ns6
RSTW/RSTR Deselected time (1) tRN1 33ns7
RSTW/RSTR Deselected time (2) tRN2 710ns7
WE Setup time tWES 710ns8
WE Hold time tWEH 33ns8
WE Deselected time (1) tWEN1 33ns9
WE Deselected time (2) tWEN2 710ns9
RE Setup time tRES 710ns10
RE Hold time tREH 33ns10
RE Deselected time (1) tREN1 33ns11
RE Deselected time (2) tREN2 710ns11
OE Setup time tOES 710ns10
OE Hold time tOEH 33ns10
OE Deselected time (1) tOEN1 33ns11
OE Deselected time (2) tOEN2 710ns11
WE Disable time tWEW 00ms
RE Disable time tREW 00ms
OE Disable time tOEW 00ms
Write reset time tRSTW 00ms
Read reset time tRSTR 00ms
Transition time tT335335ns
µ
PD485506
10 Data Sheet M10060EJ8V0DS
Notes 1. AC measurements assume tT = 5 ns.
2. AC Characteristics test condition
Input Timing Specification
3.0 V
0 V
t
T
= 5 ns t
T
= 5 ns
1.5 V Test points
Output Timing Specification
Output Loads for Timing
1.1 kΩ
D
OUT
V
CC
5 pF
(t
LZ
,t
HZ
)
1.8 kΩ
1.1 kΩ
D
OUT
V
CC
30 pF
(t
AC
,t
OH
)
1.8 kΩ
3. Input timing reference levels = 1.5 V. Output timing reference levels; VOH = 2.0 V, VOL = 0.8 V.
4. tLZ, tHZ, tLZM and tHZM are measured at ±200 mV from the steady state voltage. Under any conditions,
tLZ ≥ tHZ and tLZM ≥ tHZM.
5. Mode set signal (MD) must be input synchronously with write reset signal (tRSTW period) or read reset signal
(tRSTR period). Under this condition, tRSTW = tMD (tRSTR = tMD).
6. If either tRS or tRH is less than the specified value, reset operations are not guaranteed.
7. If either tRN1 or tRN2 is less than the specified value, reset operations may extend to cycles preceding or
following the period of reset operations.
8. If either tWES or tWEH is less than the specified value, write disable operations are not guaranteed.
9. If either tWEN1 or tWEN2 is less than the specified value, internal write disable operations may extend to cycles
preceding or following the period of write disable operations.
10. If either tRES or tREH, tOES or tOEH is less than the specified value, read disable operations are not guaranteed.
11. If either tREN1 or tREN2, tOEN1 or tOEN2 is less than the specified value, internal read disable operations may
extend to cycles preceding or following the period of read disable operations.
0.8 V
2.0 V
High impedance High impedance
Test points
µ
PD485506
11
Data Sheet M10060EJ8V0DS
Write Cycle Timing Chart
Remark RSTW = “H” level
Read Cycle Timing Chart (RE Control)
Cycle n Cycle n+1 Cycle n+2 Disable Cycle Cycle n+3
t
WCW
t
WEN1
t
WES
t
WEW
t
WEH
t
WEN2
t
WCP
t
WCK
t
DS
t
DH
(n+1)
(n)
t
DS
t
DH
(n+2) (n+3)
WCK (Input)
WE (Input)
D
IN
(Input)
Remark OE = “L” level, RSTR = “H” level
Read Cycle Timing Chart (OE Control)
Cycle n Cycle n+1 Cycle n+2 Disable Cycle Cycle n+3
tRCW tREN1 tRES
tREW
tREH tREN2
tRCP
tRCK
(n+1)
tOH
(n+2) (n+3)
tOH
tAC
RCK (Input)
RE (Input)
DOUT (Output) (n)
tOH
tAC
Remark RE = “L” level, RSTR = “H” level
Cycle n Cycle n+1 Cycle n+2 Disable Cycle Cycle m
t
RCW
t
OEN1
t
OES
t
OEW
t
OEH
t
OEN2
t
RCP
t
RCK
(n+1)
(n)
t
AC
t
OH
(n+2) (m)
t
HZ
t
LZ
t
AC
t
LZ
High impedance
RCK (Input)
OE (Input)
D
OUT
(Output) High impedance
µ
PD485506
12 Data Sheet M10060EJ8V0DS
Write Reset Cycle Timing Chart (WE = Active)
Note In write reset cycle, reset operation is executed even without a reset cycle (tRSTW).
WCK can be input any number of times in a reset cycle.
Write Reset Cycle Timing Chart (WE = Inactive)
Note In write reset cycle, reset operation is executed even without a reset cycle (tRSTW).
WCK can be input any number of times in a reset cycle.
Cycle n Reset Cycle Cycle 0 Cycle 1
t
RN2
t
RH
t
RSTW Note
t
RS
t
RN1
“L” Level
t
DS
t
DH
t
DS
t
DH
(1)(0)(n)(n–1)
D
IN
(Input)
WE (Input)
RSTW (Input)
WCK (Input)
Cycle n Disable Cycle Cycle 0
t
RN2
t
RH
t
RSTW
Note
t
RS
t
RN1
t
DS
t
DH
t
DS
(0)(n)(n–1)
D
IN
(Input)
WE (Input)
RSTW (Input)
WCK (Input)
Reset Cycle
t
WEW
t
WEN1
t
WES
t
WEH
t
WEN2
µ
PD485506
13
Data Sheet M10060EJ8V0DS
Read Reset Cycle Timing Chart (RE = Active)
Note In read reset cycle, reset operation is executed even without a reset cycle (tRSTR).
RCK can be input any number of times in a reset cycle.
Remark OE = “L” level
Read Reset Cycle Timing Chart (RE = Inactive)
Cycle n Disable Cycle Cycle 0
tRN2tRHtRSTR Note
tRStRN1
tAC
tOH
tAC
tOH
(0)(n)(n–1)DOUT (Output)
RE (Input)
RSTR (Input)
RCK (Input)
tREH
tAC
Reset Cycle
tREN1 tRES
tREW
tREN2
Indefinite Data
Note In read reset cycle, reset operation is executed even without a reset cycle (tRSTR).
RCK can be input any number of times in a reset cycle.
Remark OE = “L” level
Cycle n Reset Cycle Cycle 0 Cycle 1
t
RN2
t
RH
t
RSTR Note
t
RS
t
RN1
“L” Level
t
AC
t
OH
t
AC
t
OH
(1)(0)(n)(n – 1)
D
OUT
(Output)
RE (Input)
RSTR (Input)
RCK (Input)
t
OH
t
AC
t
AC
(0)
µ
PD485506
14 Data Sheet M10060EJ8V0DS
4. Application
4.1 1 H Delay Line
µ
PD485506 easily allows a 1 H (5,048 bits/10,096 bits) delay line (see Figure 4.1).
Figure 4.1 1 H Delay Line Circuit
WCK
DIN
WE
RSTW
RCK
DOUT
RE
RSTR
40 MHz Clock Reset
Data Output
Data Input
8/16 8/16
Figure 4.2 1 H Delay Line Timing Chart
Note 5,048 cycles by 16 bits/10,096 cycles by 8 bits
Remark RE, WE, OE = “L” level
tWCK
tRCK
Cycle 0 Cycle 1 Cycle 2
1 H
(5,048/10,096 Cycles)
Cycle 5,047
Note
2 H
(5,048/10,096 Cycles)
tWCW
tRCW
tWCP
tRCP
tRS
tRH
tDH
tDS
(0) (1) (2)
(5,046) (5,047)
(0’) (1’)
tDS
tDH
tOHtAC
(0) (1)
(2’) (3’)
(2) (3)
WCK/RCK
(Input)
RSTW/
RSTR
(Input)
DIN
(Input)
DOUT
(Output)
Write
Read
Cycle 0’ Cycle 1’ Cycle 2’ Cycle 3’
Cycle 0 Cycle 1 Cycle 2 Cycle 3
(10,095)
(10,094)
(10,095)
µ
PD485506
15
Data Sheet M10060EJ8V0DS
4.2 n Bit Delay
It is possible to make delay read from the write data with the
µ
PD485506.
(1) Perform a reset operation in the cycle proportionate to the delay length (see Figure 4.3).
(2) Shift the input timing of write reset (RSTW) and read reset (RSTR) depending on the delay length (see Figure
4.4).
(3) Shift the address by disabling RE for the period proportionate to the delay length (see Figure 4.5).
n bit: Delay bits from write cycle to read cycle correspond to a same address cell.
Restrictions
Delay bits n can be set from minimum bits to maximum bits depending on the operating cycle time.
Refer to 2. Operation Mode Operation-related Restriction.
Cycle Time MIN.
MAX.
MD = “L” Level MD = “H” Level
25 ns 21 bits 5,048 bits 10,096 bits
35 ns 15 bits 5,048 bits 10,096 bits
Figure 4.3 n-Bit Delay Line Timing Chart (1)
Remark RE, WE, OE = “L” level
tWCK
tRCK
Cycle 0 Cycle 1 Cycle 2
1 H
(n Cycles)
Cycle (n–1)
2 H
(n Cycles)
tWCW
tRCW
tWCP
tRCP
tRS
tRH
tDH
tDS
(0) (1) (n–2) (n–1) (0’) (1’)
tDS
tDH
tOHtAC
(0) (1)
(2’) (3’)
(2) (3)
WCK/RCK
(Input)
RSTW/
RSTR
(Input)
DIN
(Input)
DOUT
(Output)
(2)
Write
Read
Cycle 0’ Cycle 1’ Cycle 2’ Cycle 3’
Cycle 0 Cycle 1 Cycle 2 Cycle 3
tWAR
tRH
tRS
µ
PD485506
16 Data Sheet M10060EJ8V0DS
Figure 4.4 n-Bit Delay Line Timing Chart (2)
Remark RE, WE, OE = “L” level
Figure 4.5 n-Bit Delay Line Timing Chart (3)
Remark WE, OE = “L” level
t
WCK
t
RCK
Cycle 0 Cycle 1 Cycle 2 Cycle n–1
t
WCW
t
RCW
t
WCP
t
RCP
t
RS
t
RH
t
DH
t
DS
(0) (1) (2) (n–2) (n–1) (n) (n+1)
t
DS
t
DH
t
OH
t
AC
(0) (1)
(n+2) (n+3)
(2) (3)
WCK/RCK
(Input)
RSTW/
RSTR
(Input)
D
IN
(Input)
D
OUT
(Output)
t
REH
n Cycles
RE
(Input)
t
REN2
t
WAR
Cycle n Cycle n+1 Cycle n+2 Cycle n+3
Cycle 0 Cycle 1 Cycle 2 Cycle 3
Write
Read
High impedance
tWCK
tRCK
Cycle 0 Cycle 1 Cycle 2 Cycle n–1
tWCW
tRCW
tWCP
tRCP
tRS
tRH
tDH
tDS
(0) (1) (2) (n–2) (n–1) (n) (n+1)
tDS
tDH
tOHtAC
(0) (1)
(n+2) (n+3)
(2) (3)
WCK/RCK
(Input)
RSTW
(Input)
DIN
(Input)
DOUT
(Output)
tRH
tRS
n Cycles
RSTR
(Input)
Write
Read
Cycle n Cycle n+1 Cycle n+2 Cycle n+3
Cycle 0 Cycle 1 Cycle 2 Cycle 3
tWAR
µ
PD485506
17
Data Sheet M10060EJ8V0DS
Figure 4.6 Mode Set Cycle Timing Chart (Write) (1)
Remark WE = “L” level
Figure 4.7 Mode Set Cycle Timing Chart (Write) (2)
Cycle n Reset Cycle Cycle 0 Cycle 1
tMHtMDtMS
tRStRN1 tRSTW tRH tRN2
tDS tDH
(0) (1)(n)
(n)
tDS tDH
tDS tDH tDS tDH
(n–1)
(n–1)
WCK
(Input)
RSTW
(Input)
MD
(Input)
DIN0 - DIN7
(Input)
DIN8 - DIN15
(Input)
tDS tDH
Remark WE = “L” level
Cycle n Reset Cycle Cycle 0 Cycle 1
tMHtMDtMS
tRStRN1 tRSTW tRH tRN2
tDS tDH
(0) (1)(n)
tDS tDH
(n–1)
WCK
(Input)
RSTW
(Input)
MD
(Input)
DIN0 - DIN7
(Input)
DIN8 - DIN15
(Input)
tDS tDH
tDS tDH
(0) (1)
µ
PD485506
18 Data Sheet M10060EJ8V0DS
Figure 4.8 Mode Set Cycle Timing Chart (Read) (1)
Remark RE, OE = “L” level
Figure 4.9 Mode Set Cycle Timing Chart (Read) (2)
Cycle n Reset Cycle Cycle 0 Cycle 1
tMS tMD tMH
tRN1 tRS tRSTR tRH tRN2
tAC
tOH
tAC
tOH
tAC
tOH
tAC
tOH tOH
(n–1) (n) (0) (0) (1)
tAC
tOH
tHZM
tOH
(n–1) (n) High impedance
MD
(Input)
RSTR
(Input)
RCK
(Input)
DOUT0 - DOUT7
(Output)
DOUT8 - DOUT15
(Output)
Remark RE, OE = “L” level
Cycle n Reset Cycle Cycle 0 Cycle 1
tMS tMD tMH
tRN1 tRS tRSTR tRH tRN2
tAC
tOH
tAC
tOH
tAC
tOH tOH
(n–1) (n) (0) (0) (1)
High impedance
MD
(Input)
RSTR
(Input)
RCK
(Input)
DOUT0 - DOUT7
(Output)
DOUT8 - DOUT15
(Output)
tAC
tOH
(0) (1)
tOH
(0)
tAC
tLZM
tAC
tOH
tAC
tOH
µ
PD485506
19
Data Sheet M10060EJ8V0DS
4.3 Double-speed Conversion
Figure 4.10 shows an example timing chart of double-speed and twice reading operation (fR = 2fW, 5,048 by
2 cycles or 10,096 by 2 cyclesNote) for a write operation (fW = 5,048 cycles or 10,096 cycles).
Caution The read operation collide with the write operation on the same line, last n bits output data
(5,048 –n to 5,048/10,096 –n to 10,096) in the first read operation will be undefined (see Figure 4.10
Double-speed Conversion Timing Chart).
Undefined bits mentioned above depend on the cycle time.
Read Cycle Time Undefined Bits
25 ns 21 bits
35 ns 15 bits
Note 5,048 cycles by 16 bits/10,096 cycles by 8 bits
µ
PD485506
20 Data Sheet M10060EJ8V0DS
Figure 4.10 Double-speed Conversion Timing Chart
Note 5,048 cycles by 16 bits/10,096 cycles by 8 bits
Remark RE, WE = “L” level
012 0’ 1’ 2’
5,047
(10,095)
5,046
Note
(10,094)
0”
5,047’
(10,095’)
5,046’
(10,094’)
1H
(5,048/10,096 Cycles
Note
)
2H
(5,048/10,096 Cycles)
WCK
(Input)
D
IN
(Input)
RSTW
(Input)
012
5,046
5,047
(10,094) (10,095)
Note
0’ 1’ 2’
5,047
’
(10,094’) (10,095’)
0”
5,046
’
1H
(5,048/10,096 Cycles
Note
)
First read cycle
1H
(5,048/10,096 Cycles)
Second read cycle
RCK
(Input)
D
OUT
(Output)
RSTR
(Input)
2H
(5,048/10,096 Cycles)
First read cycle
12
5,047
012
5,046
Note
(10,095)(10,094)
5,047
0’ 1’ 2’
(10,095)(10,094)
5,046 5,047’
0’ 1’
(10,095’)(10,094’)
5,046’
n bits output data will be undefined. n bits output data will be undefined.
t
AC
0
µ
PD485506
21
Data Sheet M10060EJ8V0DS
5. Package Drawing
44-PIN PLASTIC TSOP(II) (10.16 mm (400))
NOTE
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
C
18.63 MAX.
0.93 MAX.
0.1±0.05E
F
B
0.8 (T.P.)
1.2 MAX.
G0.97
H11.76±0.2
I10.16±0.1
J0.8±0.2
D0.32+0.08
−0.07
M0.13
N0.10
L0.5±0.1
K0.145+0.025
−0.015
P3°+7°
−3°
S44G5-80-7JF5-1
M
44 23
122
SN
S
K
L
F
E
P
J
G
DM
C
A
B
H
I
detail of lead end
µ
PD485506
22 Data Sheet M10060EJ8V0DS
6. Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the
µ
PD485506.
Type of Surface Mount Device
µ
PD485506G5-7JF : 44-pin PLASTIC TSOP (II) (10.16 mm (400))
µ
PD485506G5-7JF-A : 44-pin PLASTIC TSOP (II) (10.16 mm (400))
7. Example of Stamping
Letter E in the fifth character position in a lot number signifies version E, letter K, version K, letter P, version
P, letter X, version X, and letter L, version L.
JAPAN
D485506
Lot number
<R>
µ
PD485506
23
Data Sheet M10060EJ8V0DS
Revision History
Edition/ Page Type of Location Description
Data This Previous revision (Previous edition → This edition)
edition edition
8th edition/ p.1 p.1 Addition Ordering Information Lead-free products have been added
Mar. 2006 p.2 p.2 Addition Pin Configuration Lead-free products have been added
p.22 p.22 Addition Recommended Soldering Lead-free products have been added
Conditions
µ
PD485506
24 Data Sheet M10060EJ8V0DS
[MEMO]
µ
PD485506
25
Data Sheet M10060EJ8V0DS
[MEMO]
µ
PD485506
26 Data Sheet M10060EJ8V0DS
[MEMO]
µ
PD485506
27
Data Sheet M10060EJ8V0DS
1
2
3
4
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is
fixed, and also in the transition period when the input level passes through the area between VIL (MAX)
and VIH (MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or
GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins
must be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
NOTES FOR CMOS DEVICES
5
6
µ
PD485506
The information in this document is current as of March, 2006. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
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determine NEC Electronics' willingness to support a given application.
(Note)
•
•
•
•
•
•
M8E 02. 11-1
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audio
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Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
"Standard":
"Special":
"Specific":
