intel. 270011 PAGE-ADDRESSED 1M (8 x 16K x 8) EPROM @ Paged Organization mg Automatic Page Clear Reduced Physica! Address ~ Resets to Page 0 on Power-Up and Requirement . .On Demand with RST Signal m= Compatible with 28-Pin JEDEC EPROMs @ High-Performance . Single-Trace Modification for 200 ns Access Time Retrofitting 27128-Based Designs Low 30 mA Active Power m No-Hardware-Change Upgrades m Standard EPROM Features Drop-in 27513 Replacement . TTL Compatibility Two Line Control : gw Fast Programming Quick-Pulse Programming Algorithm puaigent identifier for Automated Programming Time as Fast as rogramming 15 Seconds m Smallest Megabit DIP Package 28-Pin DIP, Minimal Footprint without Address/Data Multipiexing The Intel 27C011 is a 5V-only, 1,048,576-bit Erasable Programmable Read Only Memory. It is organized as 8 pages of 16K 8-bit words. Its pin-compatibility with byte-wide JEDEC EPROMs allows retrofitting existing designs to the greater storage capacity afforded by the page-addressed organization. Its 16 K-byte physical address space requirement altows the 27C011 to be utilized in address-constrained system designs. When a 28-pin DIP socket is configured for 27C64 or 27C128 EPROMs, it is easily retrofitted to the 27C011. By adding a WRITE ENABLE signal to pin 27 (DIP) (unused on 27C64 and 27C128), the 27C011 can be used in an existing design. Thus, the 27C011 enables product enhancements via additional feature sets and firm- ware-intensive performance upgrades. . The page-addressed organization allows the use of 28-pin DIP packages, the smallest megabit EPROM footprint with applicability to all microprocessors. This provides very efficient circuit board layouts. The 27C011 is part of a multi-product megabit EPROM family. The other members are standard-addressed byte-wide and word-wide versions, the 27C010 and 27C210, respectively. The 27C010 is organized as 128K x 8 in a 32-pin DIP package which is pin-compatible with JEDEC-standard 28-pin 512K EPROMs. The 270210 is packaged in a 40-pin DIP with a 64K x 16 organization. , The 27C011 has an automatic page clear circuit for ease of use of its paged organization. The page-select latch is automatically cleared to the lowest order page upon system power-up. The 27C011 also contains many industry-standard features such as two-line output control for simple interfacing and the inteligent Identi- fier feature tor automated programming. It also can be programmed rapidly using Intels Quick-Pulse Program- ming Algorithm. October 1991 5-59 Order Number: 290232-003ntel. 27C011 - DATA. - {NPUTS/ DATA OUTPUTS OUTPUTS 03-0. Veet hob hp Yoo Om PAGE SELECT LoeK : - PROGRAM Pou OE AND CE Locic 1 AgnAy x AMORESS | Lf decover | peconer OUTPUT BUFFERS "(GATING 131,072 CELL MATRIX PAGE 0 PAGE 7 290232-1 Figure 1. Block Diagram 270513 270128 270011 27C128 27513 27513 27128A Ww 27128A 27513 RST Vpp Vpp/RS1 CY 1 28D Voc Voc Voc Ayo Aap 4,242 27D POM /WE PGM WE Ay A? 47s 26 A,; Aig Aig Ag Ag ag] 4 251 Ag Ag Ag As As 455 24 Ag Ag Ag Ay Ay a6 2D An Ay Any Ag Ag aQ7 22 OE GE OE/Vpp Ag Ag 42s 21F Ato Ato Ato Ay Ai Mole 2079) CE CE CE Ao Ag AoC} 10 199) 07 O7 07 Do/Oo Oo Dp/O9 411 1817 0g Os Og Dy/04 O1 D,/0,C4 12 17F Os Os Os Og Oo 02/0204 13 16F1% O4 O4 GND GND ono] 14 15 Os Og O3 290232-2 Figure 2. Pin Configuration 5-60intel. 270011 Pin Names Ag-Aig Addresses te Chip Enable - OE Output Enable . WE. Page-Select Write Enable O3~07 | Outputs Dy/Ox input/Outputs (X = 0, 1, or 2) Vpp/RST | Vpp/Page Reset NC No internal Connection D.U. Don't Use EXTENDED TEMPERATURE (EXPRESS) EPROMs The Intel EXPRESS EPROM family is a series of electrically programmable read only memories which have received additional processing to enhance product characteristics. EXPRESS processing is available for several densities of EPROM, allowing the choice of appropriate memory size to match sys- . tem applications. EXPRESS EPROM products are available with 168 +8 hour, 125C dynamic burn-in using Intels standard bias configuration. This pro- cess exceeds or meets most industry specifications of burn-in. The standard EXPRESS EPROM operat- ing temperature range is 0C to 70C. Extended op- erating temperature range (40G to +85C) EX- PRESS products are available. Like all Intel EPROMs, the EXPRESS EPROM family is inspected to 0.1% electrical AQL. This may allow the user to reduce or eliminate incoming inspection testing. EXPRESS EPROM PRODUCT FAMILY PRODUCT DEFINITIONS Burn-in Operating . - t 125C (hr) Type Temperature Q 0C to + 70C 168 +8 EXPRESS OPTIONS - 27011 VERSIONS Packaging Options. Speed Versions _ Cerdip -200V10 Q,T,L __ YT. Vpp/RST AiO Ayo 4, As Ao 43 A.C AQ fo qq Dp /0y w- 04/0) We D2/02 w- cnog Voc ) PGM/WE Py Ay3 Ag PJ Ag Ay 229 OE PIA: C1 CE TA 0 WW 05 ew O05 rw 04 PAN 05 27011 oan Ane WN = 7 _ = mex Ren 290232-3 Voc = +5V CE = GND Vpp = +5V0 A=1KN GND = ov 30us >| ao At3 290232-4 Binary Sequence. from Ag to Ay3 required for each page. Page changes during burn-in require, the following minimum timing parameter values (see Page-Select AC Characteristics): . twH = 500ns . "twp = 500 ns twr = 500 ns tog = 500 ns ton = 500 ns Burn-in Bias and Timing Diagrams 5-61intel. 270011 ABSOLUTE MAXIMUM RATINGS* . NOTICE: This is a production data sheet. The specifi- 0 ing T. Dur _ -{ cations are subject to change without notice. ad emperature During 0Cto +70C WARNING: Stressing the device beyond the Absolute vee e eee eeeee petett ees OPE Maximum Ratings may cause nent damage. Temperature Under Bias......... 10C to + 80C These are stress ratings only. Operation beyond the Storage Temperature .......... ~65C to + 125C Operating Conditions is not recommended and @x- . .tended exposure beyond the Operating Conditions All Input or Output Voltages with may affect device reliability. Respect to Ground............ 0:6V to + 6.5V Voltage on Ag with Respect to Ground........... 0.6V to + 13.0V Vpp Supply Voltage with Respect to Ground During Programming ....0.6V to +14V Vcc. Supply Voltage PES with Respect to Ground........ 0.6V to +7.0V READ OPERATION ... DC CHARACTERISTICS TTL and NMOS Inputs, 0C < Ta < +70C, Voc 10% Symbol Parameter. a Notes} .. Min | Typ(3)| Max | Units| Test Condition Iu Input Load Current 0.01 | . 1.0 BA | Vin = OV to 5.5V lLo Output Leakage Current |. +10 BA | Vout = OV to 5.5V ILAST Vpp/RST Load Current 9 500 vA |-Vpp = Voc Is ..., Veg Current Standby 1.0 mA | CE=Vin lec, Voc Current Active . 5 30 mA | CE= Vi ; : f = 5 MHz, loyt = OMA Ipp1 Vpp Current Read 7 10 pA | Vpp = Voc Vit Input Low Voltage (+ 10% Supply) 1 0.5 ' 08 Vv . View Input High Voltage (+ 10% Supply) 2.0 Voct+ 0.5} V VoL Output Low Voltage , 0.45 V_ | io. = 2.14mA Vou Output High Voltage 2.4 V-- | ton = ~400 pA VcLR Page Latch ClearVoc : 3.5 4.0 Vv los Output Short Circuit Current 6 100 mA Vpp Vpp Read Voltage . 8 Voc 0.7V Voc v NOTES: 1. Minimum DC input voltage is 0.5V. During transitions, the inputs may undershoot to 2.0V for periods less than 20 ns. Maximum DC voitage on output pins is Voc + 0.5V which may overshoot to Voc + 2V for periods less than 20 ns. 2. Operating temperature is for commercial product defined by this specification. Extended temperature options are available in EXPRESS and Automotive versions. 3. Typical limits are at Voc = 5V, Ta = +25C. 4. CE is Vec 0.2V. All other inputs can have any value within spec. 5. Maximum current value is with outputs Op to.O7 unloaded. aa 6. Output shorted for no more than one second. No more than one output shorted at a time. log is sampled but not 100% tested. : 7. Maximum active power usage is the sum of Ipp and lec. The maximum current value is with no loading on outputs Op to Or. . : 8. Vpp may be one diode voltage drop below Vcc. It may be connected directly toVoc. Also, Voc must be applied simulta- neously or before Vpp and removed simultaneously or after Vpp. : 9. Vpp/RST should be at a TTL Vin level except during programming or during page 0 reset.intel. 27011 READ OPERATION (Continued) ~ DC CHARACTERISTICS CMOS Inputs Symbol Parameter Notes| Min | Typ(3)| Max | Units Test Condition lu Input Load Current 0.01 1.0 pA | Vin = OV to 5.5V lo Output Leakage Current 10 BA | Vout = OV to 5.5V Ise Voc Current Standby 4 100 pA |CE = Voc lcci Vcc Current Active 5 30 mA |CE = Vit = 5 MHz, lovt = OMA Ippy Vpp Current Read 7 10. | pA |Vpp = Voc Vit Input Low Voltage . 0.5 0.8 Vv (+10% Supply) : Vin Input High Voltage 0.7 Voc Voct+0.5! V (+ 10% Supply) VoL Output Low Voltage 0.4 Vo flo, = 2.1mA Vou Output High Voltage Voc 0.8 Vito = 400 pA los Output Short Circuit Current} 6 100 mA NOTES: 1. Minimum DC input voltage is 0.5V. During transitions, the inputs may undershoot to 2.0V for periods less than 20 ns. Maximum DC voltage on output pins is Voc + 0.5V which may overshoot to Voc + 2V for periods fess than 20 ns. 2. Operating temperature is for commercial product defined by this specification. Extended temperature options are available in EXPRESS and Automotive versions. 3. Typical limits are at Voc = 5V, Ta = + 25C. 4, is Voc 0.2V. All other inputs can have any value within spec. 5. Maximum current value is with outputs Op to O7 unloaded. 6. Output shorted for no more than one second. No more than one output shorted at a time. log is sampled, not 100% tested. 7. Maximum active power usage.is the sum of Ipp and ioc. The maximum current value.is with no loading on outputs Op. to O;. AC CHARACTERISTICS()) orc < Ta < +70C Versions Veco + 10% 27C011-200V10 Units Symbol Characteristics Min Max | tacc Address to Output Delay 200 : ns toe CE to Output Delay 200 ns toe OE to Output Delay _ 70 ns tor (2) GE High to Output Float 0 60 ns ton(2) Output Hold from Addresses CE or OE, 0 ns Whichever Occurred First + aoe AC Waveforms for Read Operation for timing mea- AC CONDITIONS OF TEST > Sampled, not 100% tested. Input Rise and Fall Times (10% to 90%)...... 10ns Input Pulse Levels ................4. 0.45V to 2.4V Input Timing Reference Level ....... 0.8V and 2.0V Output Timing Reference Level ...... 0.8V and 2.0Vintel. 270011 PAGE-SELECT WRITE AND PAGE-RESET OPERATION. AC CHARACTERISTICS OC < Tas +70C | Symbol Parameter Limits Units : Test : : Min Max Conditions tow CE to End of Write 100 ns OE = Vin twe Write Pulse Width 100 ns | OF=Viy twa Write Recovery Time 20 ns tos Data Setup Time 50 ns OE = Vin ton Data Hold Time 200 | ns | OE =Vin tes TE to Write Setup Time 0 ns OE = Vin twH WE Low from OE High Delay Time 55 ns tast Reset Low Time 100 ns trav Reset to Address Valid 150 ns CAPACITANCE(! T, = +25C, f = 1 MHz Symbol Parameter Typ(1) | Max | Units | Conditions Cin Input Capacitance 4 8 pF | Vin = 0V Cout Output Capacitance 8 12 pF Vout = 0V ___ | Cvpp/fist | Vpp/RST Capacitance 18 25 pF | Vin = OV - 1. Sampied. Not 100% tested. AC TESTING INPUT/OUTPUT WAVEFORM _ AC TESTING LOAD CIRCUIT 13V 1N914 24 2.0 ig = 2.0 . Tc 3.3K0 ous moor X os => es POINTS <x os output pevice | our 290232-5 TEST 7 cu=100 pt AC Testing inputs are driven at 2.4V for a logic 1 and 0.45V for a of. "GL = 100 pF 2002926 ose tora lone measurements are made at 2.0V for a logic 1 and C; Includes Jig Capacitance 5-64intel. 27C011 AC WAVEFORMS FOR READ OPERATION vat | Va Vin ce vu Vow vie ADDRESSES : x : ed . . . 290232-7 AC WAVEFORMS FOR PAGE-SELECT WRITE OPERATION woonses POM/WE ADDRESS DON'T CARE Do/Op, 04/0;,D2/02 _ INPUT/OUTPUTS Ds-07 OUTPUTS two? 6) tell: TWR(2) o} Dm DATA IN STABLE aa | tw | r 4 HIGH Z 290232-8 5-65intel. 270011 AC WAVEFORMS FOR PAGE-RESET OPERATION ADDRESSES > ADDRESS DON'T CARE XX ADDRESS VALIO . test +++ tray +] Vpp/RST \ / NOTES: 1. Typical values are for Ta = + 25C and nominal supply voitages. 2. This parameter is only sampled and is not 100% tested. 3. OE may be delayed up to ice toe, after the falling edge of CE without impact on toe. 4. Write may be terminated by either CE or WE, providing that the minimum tow requirement is met before bringing WE high or that the minimum twp requirement is met before bringing CE high. 5. OE must be high during write cycle. 290232-9 DEVICE OPERATION The modes of operation of the 27C011 are listed in Table 1. A single 5V power supply is required in the read mode. All inputs are TTL levels except for Vpp and 12V on Ag for inteligent Identifier. Table 1. Operating Modes Pins | __ PGW | O input/ Mode CE | OE WE Ag | Ao | Vpp/RST | Voc | Outputs Outputs Read Vie} Vic] Vin x) | X Vin 5.0V Dout DoutT - Output Disable Vind Via] Vin xX x Vin 5.0V | HighZ High Z Standby Vin] X Xx x Xx Vin .0V High Z High Z Programming Vind} Vie) Vie X xX Vpp) | Voc(9) Din Din Verify , Viel Vic} Vin 4 x Vee) |-Vec8) | Dour Dout Program Inhibit Vin | X Vin x x Vpp3) | Vec(%) | High Z High Z Page-Select Write Vie} Vie] Vin X x Vin Voc) | (Note 7) | Page Din Page-Reset . X x xX x x ViL Voc | (Note 7) xX inteligent | Manufacturer |) Vic [| Vir | Vin : Vi) | Vib Vin 5.0V 89H 89H Identifier Device ye ta | vig | vue] vin) Vin 5.0V | 31H 31H NOTES: 1. X can be Vipy or Vic. 2. Addresses are dont care for page selection. See Table 2 for Diy values. 3. See Table 3 for Voc and Vpp. 4. AiAg, Aio-A13, = VIL. 5. Page 0 is automatically selected at power-up (Voc < 4.0V). 6. Vy = 12.0V +0.5%. 7. State of outputs depends on state of CE and OE. See Outputs State for Read, Output Disable, and Standby Modes. 5-66intel. 270014 Read Mode The 27C011 has three control functions, two of which must be logically active in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output En- able (OE) is the output controt and should be used to gate data from the output pins, independent of device selection. Assuming that addresses are sta- ble, the address access time (tacc) is equal to the delay from TE to output (tc). Data is available at the outputs after a delay of tog from the falling edge of OE, assuming that CE has been low and address- es have been stable for at least tacc-toe. WE is held high during read operations. , Standby Mode EPROMs can be placed in standby mode which re- duces the maximum current.of the device by apply- ing a TTL-high signal to the CE input. When in stand- by mode, the outputs are in a high impedance state, independent of the OE and WE inputs. Page-Select Write Mode The 27C011 is addressed by first selecting one of eight 16 K-byte pages. Individual bytes are thense- lected by normal random aceess within. the 16 K-byte page using the proper combination of Ao-A1g address inputs. By applying a TTL low sig- nal to the. WE input with CE low and OE high, the desired page is latched in according to the combina- tion of Do/Oo, D/O; and De/O. Address inputs are dont care during page selection. Care should be taken in organizing software pro- grams such that the number of page changes is min- imized. This allows maximum system performance. Atso, the processor's program counter status must be considered when page changes occur in the mid- die of an opcode sequence. After a page-select write, the program counter will be incremented to the next location (or further in pipelined systems) in the new page relative to that of the page-select write opcode in the previous page. Table 2. Page Selection Data Input/Output Page Selection | 22/02 | 91/01 | Do/Oo Select Page 0 Vit Vir VIL Select Page 1 Vit Vit Vin Select Page 2 Vit Vin Vit Select Page 3 Vit Vin Vin Select Page 4 Vin Vit Vit Select Page 5 Vin Vit Vin Select Page 6 Vin Vin Vir Select Page 7 Vin Vin Vie Page Reset The 270011 has an automatic page latch clear cir- cuit to ensure consistent page selection during sys- tem bootstrapping. The page latch is automatically cleared to page 0 upon power-up. As the Voc supply voltage ramps up, the page latch is cleared. After Voc exceeds the 4.0V maximum page latch clear voltage (Vc_RA), the latch clear circuit is disabled. . This ensures an adequate safety margin (500 mV of 5-67 system noise below the worst case 10% Vcc sup- ply condition) against spurious page latch clearing. The 27C011 also has a page reset pin: Vpp/FST. This pin should be tied: to an active fow reset line. These 27C01 1s will be reset to page 0 when this line is brought to TTL Low (V)). Two Line Control Because EPROMs are usually used in larger memo- ry arrays, Intel has provided 2 output controi lines which accommodate this multiple memory connec- tion. The two control lines for read operation allow for: oo : a) the lowest possible memory power dissipation, and , b) complete assurance that output bus contention will not occur. To use these two control lines most efficiently, CE should be decoded and used as the primary device selecting function, while OE. should be made a-com- mon connection to all devices in the array and con- nected to the READ line from the system control bus. This assures that all deselected memory devic- es are in their low power standby mode and that the output pins are active only when data is desired from a particular memory device. .. : Similarly, CE deselects other 27C011s or RAMs dur- ing page select write operation while WE is in com- mon with other devices in the array. WE is connect ed to the WRITE system control iine. SYSTEM CONSIDERATIONS The power switching characteristics of EPROMs re- quire careful decoupling of the devices. The supply current, Icc, has three segments that are of interest to the system designerthe standby current level, the active current level, and the transient current peaks that are produced by- the falling and rising edges of.Chip Enable. The magnitude of these tran- sient current peaks is dependent on the output ca- pacitive and inductive loading of the device. The as-ntel. 27G011 sociated transient voltage peaks can be suppressed by complying with Intels Two-Line Control and by properly selected decoupling capacitors. It is recom- mended that a 0.1 F ceramic capacitor be used on every device between Voc and GND. This should be a high frequency capacitor of low inherent induc- tance and should be placed as close to the device as possible. In addition, a 4.7 F bulk electrolytic capacitor should be used between Voc and GND for every eight devices. The bulk capacitor should be located near. where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage droop caused by the inductive effects of PC board traces. This inductive effect should be further minimized through special, layout considerations such as larger traces and gridding. In particular, the Vss (Ground) plane should be as sta- ble as possible. PROGRAMMING Caution: Exceeding 14.0V on Vpp will permanent- ly damage the 27C011. Initially, and after each erasure, all bits of the EPROM are in the 1 state. Data is introduced by selectively programming Os into the desired bit !o- cations. Although only Os will be programmed, both 1s and Os can be present in the data word. The only way to change a 0 to a 1 is by ultravio- let light erasure. The 270011 is in the programming mode when the Vpp input is at its. programming voltage and CE is at TTL-low. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. Program Inhibit Programming of multiple 27C01 1s in parallel with dif- ferent data is easily accomplished by. using the Pro- gram Inhibit mode. A high-level CE input inhibits the other 27C011s from being programmed. Except for CE, all inputs of the parallel 27C011s may be common. A TTL low-level pulse applied to the PGM/WE input with Vpp at its programming voltage will program the selected 270011. a Verify A verify (read) should be performed :on the pro- grammed bits to determine that they have been cor- rectly programmed. The verity is performed with OE and CE at Vi_ and Voc is at its programming voltage 5-68 Data should be verified tpy after the falling edge of CE. inteligent Identifier Mode The inteligent Identifier Mode.allows the reading out of a binary code fram an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically. matching the device to be pro- grammed with its corresponding programming algo- rithm. This mode is functional in the 25C +5C ambient temperature range that is required when programming the device. To activate this mode, the programming equipment must force 11.5V to 12.5V on address line AQ of the EPROM. Two identifier bytes may then be se- quenced. from the device outputs. by toggling ad- dress line AO from Vi, to- Vj. All other address lines must be held at Vj}. during the inteligent identifier Mode. . Byte 0 (AO = Vj.) represents the manufacturer code and byte 1 (AO = Vi) the device identifier code. These two identifier bytes are given in Table. 1. - ERASURE CHARACTERISTICS (FOR CERDIP EPROMs) The erasure characteristics are such that erasure begins to occur.upon exposure to light with wave- lengths shorter. than approximately 4000 Angstroms (A). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000-4000 A range. Data show that constant expo- sure to room level fluorescent lighting could. erase the EPROM in approximately 3 years, while it would take approximately. 1 week to cause erasure when exposed to direct sunlight. If the device is to be ex- posed to these types of lighting conditions for- ex- tended periods of time, opaque. tabels should be placed over the window to prevent unintentional era- sure. The recommended erasure procedure is exposure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV intensity x exposure time) for erasure should be a minimum of 15 Wsec/cm2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 1.W/cm2 power rat- ing. The EPROM should be placed within 1 inch of the lamp tubes during erasure. The maximum inte- grated dose an EPROM can be exposed to. without damage is 7258 Wsec/cm2 (1 week @ 12000 p.W/cmz2). Exposure of the device to high intensity UV light for long periods may cause permanent dam- age.27C011 START SELECT PAGE 0 SELECT ADORESS ALL BYTES SELECT LasT NEXT PAGE PAGE? YES DEVICE PASSED ADDR = FIRST LOCATION Voc = 6.25 Vep > 12.75V = FIRST LOCATION TO ORIGINAL DATA FOR CURRENT, PAGE FAN DEVICE DEVICE FAILED. 290232-10 Figure 4. 27C011 Quick-Pulse Programming Flowchart Quick Pulse Programming Algorithm Intel's 27C011 EPROM is programmed using the Quick-Pulse Programming algorithm, developed by Intel to substantially reduce the throughput time. in the production programming environment. This algo- rithm allows these devices to be programmed as fast as fourteen seconds, almost a hundred fold im- provement over previous algorithms. Actual pro- gramming time is a function of the PROM program- mer being used. The Quick-Pulse Programming algorithm uses initial pulses of 100 microseconds followed by a byte veri- 5-69 fication to determine when the address byte has been successfully programmed. Up to 25 100 ys pulses per byte are provided before a failure is rec- ognized. A flowchart of the Quick-Pulse Program- ming algorithm is shown in Figure 4. For the Quick-Pulse Programming algorithm, the en- tire sequence of programming pulses and byte verifi- cations is performed at Vcc = 6.25V and Vpp at 12.75V. When programming of the EPROM has been completed, all bytes should be compared to the original data with Voc = Vpp = 5.0V.intel. 270011 DC PROGRAMMING CHARACTERISTICS Ty, = 25C +5C Table 3 Limits Test Conditions Symbol Parameter Min Max Units (Note 1) lu Input Current (All Inputs) 1 pA Vin = Vitor Vin Vit Input Low Level (All Inputs) 0.1 0.8 Vv Vin Input High Level 2.4 6.5 Vv VoL Output Low Voltage During Verify 0.45 Vv lo. = 2.1 mA Vou ~ Output High Voltage During Verify 3.5 Vv lon = 2.5 pA Ioc23) Vcc Supply Current (Program and Verify) 40 mA Ipp2 Vpp Supply Current (Program) 50 mA CE = Vit Vio Ag inteligent Identifier Voltage 11.5 12.5 Vv Vpp Quick-Pulse Programming Algorithm 12.5 13.0 Vv Voc Quick-Pulse Programming Algorithm 6.0 6.5 Vv AC PROGRAMMING CHARACTERISTICS Ta = 25C +5C (See Table 3 for Voc and Vpp voltages.) Symbol Parameter Limits Conditions* Min | Typ | Max | Units (Note 1) tas Address Setup Time 2 ps toes OE Setup Time 2 ys tos Data Setup Time 2 ps taH Address Hold Time 0 ps tbH Data Hold Time 2 pS torP GE High to Output Float Delay | 0 130 ns (Note 2) tyes Vpp Setup Time 2 ps tvcs Voc Setup Time 2 pS tces CE Setup Time 2- ys tpw PGM Program Pulse Width 95 100 105 ps Quick-Puise Programming toe Data Valid from OE 150 ns *AC CONDITIONS OF TEST ee must be applied simultaneously or before Vpp and Input Rise and Fall Times (10% to 90%)... 20 ns Dihds Daremotsr ts orty aa nod 4 is not 100% tested. Input Pulse Levels ................65 0.45V to 2.4V Output Float is defined as the point where data is no long- input Timing Reference Level ....... 0.8V and 2.0V 3. lalla lh rade is with outputs Op-O7 un- Output Timing Reference Level ...... 0.8V and 2.0V loaded. 5-70intel. sco PROGRAMMING WAVEFORMS VERIFY , a Mi nut : tas . Yn ore q HIGH Z Z DATA DATA IN STABLE OATA OUT Vi Vin ye jo'2s] Lag. FH oy 12.754 " ___/| $.0 6.25V S| $0 ce * Vin wv : tees___, Yo vases ee von/we AT tow Lg toes i Vin er _ . _ OE Yu i, 290232~11 NOTES: 1. The Input Timing Reference Level is 0.8V for a Vi_ and 2.0V for a Vip. 2. toe and tprp are characteristics of the device but must be accommodated by the programmer. 3. The proper page to be programmed must be selected by a page-select write operation prior to programming each of the four 16 Kbyte pages. See Page Select Write AC and DC Characteristics for information on page selection operations. REVISION HISTORY Number Description 003 Removed Advance Information Classification Revised twp from 50 ns to 100 ns 5-71