IRF9540NSTRLHR - INTERNATIONAL RECTIFIER

IRF9540NS/L

HEXFET® Power MOSFET

lAdvanced Process Technology

lSurface Mount (IRF9540NS)

lLow-profile through-hole (IRF9540NL)

l175°C Operating Temperature

lFast Switching

lP-Channel

lFully Avalanche Rated

03/11/03

S

D

G

Absolute Maximum Ratings

Fifth Generation HEXFETs from International Rectifier utilize

advanced processing techniques to achieve extremely low

on-resistance per silicon area. This benefit, combined with

the fast switching speed and ruggedized device design that

HEXFET Power MOSFETs are well known for, provides the

designer with an extremely efficient and reliable device for

use in a wide variety of applications.

The D2Pak is a surface mount power package capable of

accommodating die sizes up to HEX-4. It provides the highest

power capability and the lowest possible on-resistance in

any existing surface mount package. The D2Pak is suitable

for high current applications because of its low internal

connection resistance and can dissipate up to 2.0W in a

typical surface mount application.

The through-hole version (IRF9540L) is available for low-

profile applications.

Description

VDSS = -100V

RDS(on) = 0.117Ω

ID = -23A

2

D Pak

TO-262

Parameter Typ. Max. Units

RθJC Junction-to-Case  1.1

RθJA Junction-to-Ambient ( PCB Mounted,steady-state)**  40

Thermal Resistance

°C/W

Parameter Max. Units

ID @ TC = 25°C Continuous Drain Current, VGS @ -10V-23

ID @ TC = 100°C Continuous Drain Current, VGS @ -10V-16 A

IDM Pulsed Drain Current  -76

PD @TA = 25°C Power Dissipation 3.8 W

PD @TC = 25°C Power Dissipation 140 W

Linear Derating Factor 0.91 W/°C

VGS Gate-to-Source Voltage ± 20 V

EAS Single Pulse Avalanche Energy 430 mJ

IAR Avalanche Current-11 A

EAR Repetitive Avalanche Energy14 mJ

dv/dt Peak Diode Recovery dv/dt  -5.0 V/ns

TJOperating Junction and -55 to + 175

TSTG Storage Temperature Range

Soldering Temperature, for 10 seconds 300 (1.6mm from case )

°C

PD - 91483E

IRF9540NS/L

 Starting TJ = 25°C, L = 7.1mH

RG = 25Ω, IAS = -11A. (See Figure 12)

 Repetitive rating; pulse width limited by

max. junction temperature. ( See fig. 11 )

Notes:

** When mounted on 1" square PCB (FR-4 or G-10 Material ).

For recommended footprint and soldering techniques refer to application note #AN-994.

ISD ≤ -11A, di/dt ≤ -470A/µs, VDD ≤ V(BR)DSS,

TJ ≤ 175°C

 Pulse width ≤ 300µs; duty cycle ≤ 2%.

 Uses IRF9540N data and test conditions

Source-Drain Ratings and Characteristics

Parameter Min. Typ. Max. Units Conditions

V(BR)DSS Drain-to-Source Breakdown Voltage -100   V VGS = 0V, ID = -250µA

∆V(BR)DSS/∆TJBreakdown Voltage Temp. Coefficient  -0.11  V/°C Reference to 25°C, ID = -1mA

RDS(on) Static Drain-to-Source On-Resistance   0.117 ΩVGS = -10V, ID = -11A 

VGS(th) Gate Threshold Voltage -2.0  -4.0 V VDS = VGS, ID = -250µA

gfs Forward Transconductance 5.3   S VDS = -50V, ID = -11A

  -25 µA VDS = -100V, VGS = 0V

  -250 VDS = -80V, VGS = 0V, TJ = 150°C

Gate-to-Source Forward Leakage   100 VGS = 20V

Gate-to-Source Reverse Leakage   -100 nA VGS = -20V

QgTotal Gate Charge   97 ID = -11A

Qgs Gate-to-Source Charge   15 nC VDS = -80V

Qgd Gate-to-Drain ("Miller") Charge   51 VGS = -10V, See Fig. 6 and 13 

td(on) Turn-On Delay Time  15  VDD = -50V

trRise Time  67  ID = -11A

td(off) Turn-Off Delay Time  51  RG = 5.1Ω

tfFall Time  51  RD = 4.2Ω, See Fig. 10 

Between lead,

  and center of die contact

Ciss Input Capacitance  1300  VGS = 0V

Coss Output Capacitance  400  pF VDS = -25V

Crss Reverse Transfer Capacitance  240   = 1.0MHz, See Fig. 5

Electrical Characteristics @ TJ = 25°C (unless otherwise specified)

IGSS

ns

IDSS Drain-to-Source Leakage Current

nH

7.5

LSInternal Source Inductance

Parameter Min. Typ. Max. Units Conditions

I

SContinuous Source Current MOSFET symbol

(Body Diode)   showing the

ISM Pulsed Source Current integral reverse

(Body Diode)   p-n junction diode.

VSD Diode Forward Voltage   -1.6 V TJ = 25°C, IS = -11A, VGS = 0V 

trr Reverse Recovery Time  150 220 ns TJ = 25°C, IF = -11A

Qrr Reverse Recovery Charge  830 1200 nC di/dt = -100A/µs 

ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

A

S

D

G

-23

-76

IRF9540NS/L

Fig 4. Normalized On-Resistance

Vs. Temperature

Fig 2. Typical Output Characteristics

Fig 1. Typical Output Characteristics

Fig 3. Typical Transfer Characteristics

1

10

100

0.1 1 10 100

D

DS

20µs PU LSE WIDTH

T = 25°C

c

A

-I , Drain-to-Source Current (A )

-V , Drain-to-Source Voltage (V)

VGS

TOP - 15V

- 1 0 V

- 8 .0 V

- 7 .0 V

- 6 .0 V

- 5 .5 V

- 5 .0 V

BOTTOM - 4.5V

-4.5V

1

10

100

0.1 1 10 100

D

DS

A

-I , Drain-to-Source Cu rrent (A)

-V , Drain-to-Source Voltage (V)

VGS

TOP - 15V

- 1 0 V

- 8 .0 V

- 7 .0 V

- 6 .0 V

- 5 .5 V

- 5 .0 V

BOTTOM - 4.5V

-4.5V

20µs PULS E WIDT H

T = 175°C

C

0.1

1

10

100

45678910

T = 25°C

J

GS

D

A

-I , Drain-to-Sou rce Current (A)

-V , Gate-to-Sour ce Vol tage (V)

V = -25V

20µs PULSE WIDTH

DS

T = 175° C

J

0.0

0.5

1.0

1.5

2.0

2.5

-60 -40 -20 0 20 40 60 80 100 120 140 160 180

J

T , Junction Temperature (°C)

R , Drain-to-Source On Resi stance

DS(on)

(Normalized)

A

V = -10V

GS

I = -19A

D

IRF9540NS/L

Fig 8. Maximum Safe Operating Area

Fig 6. Typical Gate Charge Vs.

Gate-to-Source Voltage

Fig 5. Typical Capacitance Vs.

Drain-to-Source Voltage

Fig 7. Typical Source-Drain Diode

Forward Voltage

0

500

1000

1500

2000

2500

3000

1 10 100

C , Capac it ance (pF)

A

DS

-V , Drain-to-Sou rce Vo ltag e (V)

V = 0V, f = 1MHz

C = C + C , C SHORTED

C = C

C = C + C

GS

iss gs gd ds

rss gd

oss ds gd

C

iss

C

oss

C

rss

0

4

8

12

16

20

0 20406080100

G

GS

A

-V , Gate-to-S ource Voltage (V)

Q , Total Gate Cha rge (nC)

V = -80V

V = -50 V

V = -20 V

DS

FOR TEST CIRCUIT

SEE FIGURE 13

I = - 1 1A

D

0.1

1

10

100

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

T = 25°C

J

V = 0V

GS

SD

A

-I , Re verse Dr ain Cu rrent (A)

-V , Source-to-Drain Voltag e (V)

T = 175° C

J

1

10

100

1000

1 10 100 1000

OPERATION IN THIS AREA LIMITED

BY R

DS(on)

10ms

A

-I , Drain Current (A )

-V , Drain-to-Source Voltage (V)

DS

D

100µs

1ms

T = 25°C

T = 175°C

Single Pulse

C

J

IRF9540NS/L

Fig 10a. Switching Time Test Circuit

Fig 10b. Switching Time Waveforms

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig 9. Maximum Drain Current Vs.

Case Temperature

VDS

-10V

Pulse Width ≤ 1 µs

Duty Factor ≤ 0.1 %

RD

VGS

VDD

RG

D.U.T.

+

-

V

DS

90%

10%

V

GS

t

d(on)

t

r

t

d(off)

t

f

25 50 75 100 125 150 175

0

5

10

15

20

25

T , Case Temperature ( C)

I , Drain Current (A)

°

C

D

0.01

0.1

1

10

0.00001 0.0001 0.001 0.01 0.1 1

Notes:

1. D u ty fa c to r D = t / t

2. Peak T =P x Z + T

1 2

JDM thJC C

P

t

DM

1

2

t , R ectangular Pulse Dura t ion (sec)

Thermal Response (Z )

1

thJC

0.01

0.02

0.05

0.10

0.20

D = 0.50

SINGLE PULSE

(THERMAL RESPONSE)

IRF9540NS/L

Fig 13b. Gate Charge Test Circuit

Fig 13a. Basic Gate Charge Waveform

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

QG

QGS QGD

VG

Charge

-10V

D.U.T. VDS

ID

IG

-3mA

VGS

.3µF

50KΩ

.2µF

12V

Current Regulator

Same Type as D.U.T.

Current Sampling Resistors

+

-

Fig 12b. Unclamped Inductive Waveforms

Fig 12a. Unclamped Inductive Test Circuit

tpV

(

BR

)

DSS

I

AS

R

G

I

AS

0.01

Ω

t

p

D.U.T

L

V

DS

V

DD

DRIVER

A

15V

-20V

0

200

400

600

800

1000

1200

25 50 75 100 125 150 175

J

E , Single Puls e Avalanche Energy (mJ)

AS

A

Starting T , Junction Temperature (°C)

I

TOP -4.7A

-8.1A

BOTTOM -11A

D

IRF9540NS/L

Peak Diode Recovery dv/dt Test Circuit

P.W. Period

di/dt

Diode Recovery

dv/dt

Ripple ≤5%

Body Diode Forward Drop

Re-Applied

Voltage

Reverse

Recovery

Current Body Diode Forward

Current

V

GS

=10V

V

DD

I

SD

Driver Gate Drive

D.U.T. I

SD

Waveform

D.U.T. V

DS

Waveform

Inductor Curent

D = P.W.

Period

+

-

+

-







RG

VDD

• dv/dt controlled by RG

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

D.U.T*Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer



* Reverse Polarity of D.U.T for P-Channel

VGS

[ ]

*** VGS = 5.0V for Logic Level and 3V Drive Devices

[ ] ***

Fig 14. For P-Channel HEXFETS

IRF9540NS/L

D2Pak Package Outline

D2Pak Part Marking Information

F530S

THIS IS A

N IRF530S WITH

LO

T C

ODE 8024

A

SSEM

BLED O

N WW

02, 2000

IN THE A

SSEMBLY LINE "L"

A

SSEM

BLY

LO

T C

ODE

INTERNA

TIO

NA

L

REC

TIFIER

LO

G

O

PA

RT NUM

BER

DA

TE C

O

DE

YEA

R 0 = 2000

W

EEK 02

LINE L

IRF9540NS/L

TO-262 Part Marking Information

TO-262 Package Outline

EXA

M

PLE:THIS IS A

N IRL3103L

LOT C

O

DE 1789

A

SSEM

BLY

PA

RT NUMBER

DA

TE C

ODE

W

EEK 19

LINE C

LO

T C

ODE

YEA

R 7 = 1997

A

SSEM

BLED O

N WW

19, 1997

IN THE A

SSEM

BLY LINE "C

"LOG

O

REC

TIFIER

INTERNA

TIONA

L

IRF9540NS/L

D2Pak Tape & Reel Information

3

4

TRR

FEE D DIRECTION

1.85 (.073)

1.65 (.065)

1.60 (.063)

1.50 (.059)

4.10 (.161)

3.90 (.153)

TRL

FEE D DIRECTION

10. 90 ( .429)

10. 70 ( .421) 16.10 (.634)

15.90 (.626)

1.75 (.069)

1.25 (.049)

11.60 (.457)

11.40 (.449) 15.42 (.609)

15.22 (.601)

4.72 (.136)

4.52 (.178)

24.30 (.957)

23.90 (.941)

0.368 (.0145)

0.342 (.0135)

1.60 (. 063 )

1.50 (. 059 )

13.50 (.532)

12.80 (.504)

330.00

(14.173)

MAX.

27.40 (1.079)

23.90 (.941)

60.00 ( 2.3 62)

MIN.

30.40 (1.197)

MAX.

26.4 0 (1 .0 39 )

24.40 (.961)

NOTES :

1. COMFORMS TO EIA-418.

2. CONTROLLING DIMENS IO N: MILLIMET ER .

3. DIMENSION MEASURED @ HUB.

4. INCLUDES FLANGE D ISTOR TION @ OUTER EDGE.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.03/03

Note: For the most current drawings please refer to the IR website at:

http://www.irf.com/package/