M29W640FB70N6E - STMicroelectronics

Rev3

December 2005 1/72

M29W640FT

M29W640FB

64 Mbit (8Mb x8 or 4Mb x16, Page, Boot Block)

3V Supply Flash Memory

Features summary

Supply Voltage

–VCC =2.7V to 3.6V for Program, Erase,

Read

–VPP =12V for Fast Program (optional)

Asynchronous Random/Page Read

–Page Width: 4 Words

–Page Access: 25ns

–Random Access: 60ns, 70ns

Programming Time

–10 µs per Byte/Word typical

–4 Words/8 Bytes Program

135 memory blocks

–1 Boot Block and 7 Parameter Blocks,

8KBytes each (Top or Bottom Location)

–127 Main Blocks, 64 KBytes each

Program/Erase Controller

–Embedded Byte/Word Program algorithms

Program/Erase Suspend and Resume

–Read from any Block during Program

Suspend

–Read and Program another Block during

Erase Suspend

Unlock Bypass Program command

–Faster Production/Batch Programming

VPP/WP pin for Fast Program and Write Protect

Temporary Block Unprotection mode

Common Flash Interface

–64-bit Security Code

Extended Memory Block

–Extra block used as security block or to

store additional information

Low power consumption

–Standby and Automatic Standby

100,000 Program/Erase cycles per block

Figure 1.Packages

Electronic Signature

–Manufacturer Code: 0020h

Table 1.Device Codes

ECOPACK® packages

Root Part NumberDevice Code

M29W640FT22EDh

M29W640FB22FDh

FBGA

TSOP48 (N)

12 x 20mm

TFBGA48 (ZA)

6x8mm

www.st.com

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Contents

1Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1Address Inputs (A0-A21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2Data Inputs/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3Data Inputs/Outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.4Data Input/Output or Address Input (DQ15A–1) . . . . . . . . . . . . . . . . . . . . . . 11

2.5Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.6Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.7Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.8V

PP/Write Protect (VPP/WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.9Reset/Block Temporary Unprotect (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.10Ready/Busy Output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.11Byte/Word Organization Select (BYTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.12V

CC Supply Voltage (2.7V to 3.6V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.13V

SS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.4Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.5Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.6Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.6.1Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.6.2Block Protect and Chip Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.1Standard commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.1.1Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.1.2Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.1.3Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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4.1.4Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1.5Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1.6Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.1.7Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.1.8Program Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.1.9Program Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.1.10Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.2Fast Program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.2.1Double Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.2.2Quadruple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.2.3Octuple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2.4Double Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2.5Quadruple Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2.6Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2.7Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2.8Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.3Block Protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.3.1Enter Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.3.2Exit Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.3.3Block Protect and Chip Unprotect commands . . . . . . . . . . . . . . . . . . . . . . . . 27

5Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.1Data Polling Bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.2Toggle Bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.3Error Bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.4Erase Timer Bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.5Alternative Toggle Bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

9Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Appendix ABlock addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

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Appendix BCommon Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Appendix CExtended Memory Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

C.1Factory Locked Extended Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

C.2Customer Lockable Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Appendix DBlock Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

D.1Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

D.2In-System Technique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

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List of tables

Table 1.Device Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 1.Signal Names. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 2.Hardware Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 3.Bus Operations, BYTE = VIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 4.Bus Operations, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 5.Commands, 16-bit mode, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 6.Commands, 8-bit mode, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 7.Program, Erase Times and Program, Erase Endurance Cycles. . . . . . . . . . . . . . . . . . . . . 29

Table 8.Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 9.Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 10.Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 11.Device Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 12.DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 13.Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 14.Write AC Characteristics, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 15.Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 16.Reset/Block Temporary Unprotect AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 17.TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data. . . 44

Table 18.TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, Package Mechanical Data. . . . . . 45

Table 19.Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 20.Top Boot Block Addresses, M29W640FT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 21.Bottom Boot Block Addresses, M29W640FB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 22.Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 23.CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 24.CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 25. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 26.Primary Algorithm-Specific Extended Query Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 27.Security Code Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 28.Extended Block Address and Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 29.Programmer Technique Bus Operations, BYTE = VIH or VIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Table 30.Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

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List of figures

Figure 1.Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1.Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 2.TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 3.TFBGA48 Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4.Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 5.Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 6.AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 7.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 8.Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 9.Page Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 10.Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 11.Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 12.Reset/Block Temporary Unprotect AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 13.Accelerated Program Timing Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 14.TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . . . 44

Figure 15.TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, Package Outline . . . . . . . . . . . . . 45

Figure 16.Programmer Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 17.Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 18.In-System Equipment Group Protect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 19.In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

M29W640FT, M29W640FB 1 Summary description

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1 Summary description

The M29W640F is a 64 Mbit (8Mb x8 or 4Mb x16) non-volatile memory that can be read,

erased and reprogrammed. These operations can be performed using a single low voltage (2.7

to 3.6V) supply. On power-up the memory defaults to its Read mode.

The memory is divided into blocks that can be erased independently so it is possible to

preserve valid data while old data is erased. Blocks can be protected in units of 256 KByte

(generally groups of four 64 KByte blocks), to prevent accidental Program or Erase commands

from modifying the memory. Program and Erase commands are written to the Command

Interface of the memory. An on-chip Program/Erase Controller simplifies the process of

programming or erasing the memory by taking care of all of the special operations that are

required to update the memory contents. The end of a program or erase operation can be

detected and any error conditions identified. The command set required to control the memory

is consistent with JEDEC standards.

The device features an asymmetrical blocked architecture. The device has an array of 135

blocks:

8 Parameters Blocks of 8 KBytes each (or 4KWords each)

127 Main Blocks of 64 KBytes each (or 32KWords each)

M29W640FT has the Parameter Blocks at the top of the memory address space while the

M29W640FB locates the Parameter Blocks starting from the bottom.

The M29W640F has an extra block, the Extended Block, of 128 Words in x16 mode or of 256

Byte in x8 mode that can be accessed using a dedicated command. The Extended Block can

be protected and so is useful for storing security information. However the protection is not

reversible, once protected the protection cannot be undone.

Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory.

They allow simple connection to most microprocessors, often without additional logic.

The VPP/WP signal is used to enable faster programming of the device, enabling multiple word/

byte programming. If this signal is held at VSS, the boot block, and its adjacent parameter block,

are protected from program and erase operations.

The device supports Asynchronous Random Read and Page Read from all blocks of the

memory array.

The memories are offered in TSOP48 (12x 20mm) and TFBGA48 (6x8mm, 0.8mm pitch)

packages.

In order to meet environmental requirements, ST offers the M29W640FT and the M29W640FB

in ECOPACK® packages. ECOPACK packages are Lead-free. The category of second Level

Interconnect is marked on the package and on the inner box label, in compliance with JEDEC

Standard JESD97. The maximum ratings related to soldering conditions are also marked on

the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at:

www.st.com.

The memory is delivered with all the bits erased (set to 1).

1 Summary description M29W640FT, M29W640FB

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Figure 1.Logic Diagram

Table 1.Signal Names

A0-A21Address Inputs

DQ0-DQ7Data Inputs/Outputs

DQ8-DQ14Data Inputs/Outputs

DQ15A–1 (or DQ15)Data Input/Output or Address Input (or Data Input/Output)

EChip Enable

GOutput Enable

WWrite Enable

RP Reset/Block Temporary Unprotect

RB Ready/Busy Output

BYTE Byte/Word Organization Select

VCC Supply Voltage

VPP/WP Supply Voltage for Fast Program (optional) or Write Protect

VSS Ground

NCNot Connected Internally

AI11250

A0-A21

DQ0-DQ14

VCC

M29W640FT

M29W640FB

VSS

DQ15A–1

BYTE

VPP/WP

M29W640FT, M29W640FB 1 Summary description

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Figure 2.TSOP Connections

DQ3

DQ9

DQ2

A6 DQ0

DQ6

A9 DQ13

A17

A10DQ14

DQ12

DQ10

DQ15A–1

VCC

DQ4

DQ5

DQ7

VPP/WP

A21

M29W640FT

M29W640FB

2425

DQ8

A20

A19

A18

DQ1

DQ11

A12

A13

A16

A11

BYTE

A15

A14 VSS

VSS

AI11251

1 Summary description M29W640FT, M29W640FB

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Figure 3.TFBGA48 Connections (Top view through package)

654321

VSS

A15

A14

A12

A13

DQ3

DQ11

DQ10

A18

VPP

DQ1

DQ9

DQ8

DQ0

A17

DQ2

DQ6

DQ13

DQ14

A10

DQ4

VCC

DQ12

DQ5

A19

A21

A11

DQ7

VSS

A5A20

A16

BYTE

DQ15

A–1

AI11554

M29W640FT, M29W640FB 2 Signal descriptions

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2 Signal descriptions

See Figure1: Logic Diagram, and Table1: Signal Names, for a brief overview of the signals

connected to this device.

2.1 Address Inputs (A0-A21)

The Address Inputs select the cells in the memory array to access during Bus Read operations.

During Bus Write operations they control the commands sent to the Command Interface of the

Program/Erase Controller.

2.2 Data Inputs/Outputs (DQ0-DQ7)

The Data I/O outputs the data stored at the selected address during a Bus Read operation.

During Bus Write operations they represent the commands sent to the Command Interface of

the Program/Erase Controller.

2.3 Data Inputs/Outputs (DQ8-DQ14)

The Data I/O outputs the data stored at the selected address during a Bus Read operation

when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high

impedance. During Bus Write operations the Command Register does not use these bits.

When reading the Status Register these bits should be ignored.

2.4 Data Input/Output or Address Input (DQ15A–1)

When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When

BYTE is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the LSB of the

addressed Word, DQ15A–1 High will select the MSB. Throughout the text consider references

to the Data Input/Output to include this pin when BYTE is High and references to the Address

Inputs to include this pin when BYTE is Low except when stated explicitly otherwise.

2.5 Chip Enable (E)

The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be

performed. When Chip Enable is High, VIH, all other pins are ignored.

2.6 Output Enable (G)

The Output Enable, G, controls the Bus Read operation of the memory.

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2.7 Write Enable (W)

The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface.

2.8 V

PP/Write Protect (VPP/WP)

The VPP/Write Protectpin provides two functions. The VPP function allows the memory to use

an external high voltage power supply to reduce the time required for Unlock Bypass Program

operations. The Write Protect function provides a hardware method of protecting the two

outermost boot blocks. The VPP/Write Protect pin must not be left floating or unconnected.

When VPP/Write Protect is Low, VIL, the memory protects the two outermost boot blocks;

Program and Erase operations in this block are ignored while VPP/Write Protect is Low, even

when RP is at VID.

When VPP/Write Protectis High, VIH, the memory reverts to the previous protection status of

the two outermost boot blocks. Program and Erase operations can now modify the data in the

two outermost boot blocks unless the block is protected using Block Protection.

Applying VPPH to the VPP/WP pin will temporarily unprotect any block previously protected

(including the two outermost parameter blocks) using a High Voltage Block Protection

technique (In-System or Programmer technique). See Table2: Hardware Protection for details.

When VPP/Write Protect is raised to VPP the memory automatically enters the Unlock Bypass

mode. When VPP/Write Protect returns to VIH or VIL normal operation resumes. During Unlock

Bypass Program operations the memory draws IPP from the pin to supply the programming

circuits. See the description of the Unlock Bypass command in the Command Interface section.

The transitions from VIH to VPP and from VPP to VIH must be slower than tVHVPP

, see Figure13:

Accelerated Program Timing Waveforms.

Never raise VPP/Write Protect to VPP from any mode except Read mode, otherwise the

memory may be left in an indeterminate state.

A 0.1µF capacitor should be connected between the VPP/Write Protect pin and the VSS Ground

pin to decouple the current surges from the power supply. The PCB track widths must be

sufficient to carry the currents required during Unlock Bypass Program, IPP

Table 2.Hardware Protection

VPP/WP RP Function

VIL

VIH 2 outermost parameter blocks protected from

Program/Erase operations

VID All blocks temporarily unprotected except the 2

outermost blocks

VIH or VID VID All blocks temporarily unprotected

VPPH VIH or VID All blocks temporarily unprotected

M29W640FT, M29W640FB 2 Signal descriptions

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2.9 Reset/Block Temporary Unprotect (RP)

The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the

memory or to temporarily unprotect all Blocks that have been protected.

Note that if VPP/WP is at VIL, then the two outermost boot blocks will remain protected even if

RP is at VID.

A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, VIL, for at

least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready

for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See the

Ready/Busy Output section, Table16: Reset/Block Temporary Unprotect AC Characteristics

and Figure12: Reset/Block Temporary Unprotect AC Waveforms, for more details.

Holding RP at VID will temporarily unprotect the protected Blocks in the memory. Program and

Erase operations on all blocks will be possible. The transition from VIH to VID must be slower

than tPHPHH.

2.10 Ready/Busy Output (RB)

The Ready/Busy pin is an open-drain output that can be used to identify when the device is

performing a Program or Erase operation. During Program or Erase operations Ready/Busy is

Low, VOL. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase

Suspend mode.

After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy

becomes high-impedance. See Table16: Reset/Block Temporary Unprotect AC Characteristics

and Figure12: Reset/Block Temporary Unprotect AC Waveforms, for more details.

The use of an open-drain output allows the Ready/Busy pins from several memories to be

connected to a single pull-up resistor. A Low will then indicate that one, or more, of the

memories is busy.

2.11 Byte/Word Organization Select (BYTE)

The Byte/Word Organization Select pin is used to switch between the x8 and x16 Bus modes of

the memory. When Byte/Word Organization Select is Low, VIL, the memory is in x8 mode, when

it is High, VIH, the memory is in x16 mode.

2.12 V

CC Supply Voltage (2.7V to 3.6V)

VCC provides the power supply for all operations (Read, Program and Erase).

The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout

Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during

power up, power down and power surges. If the Program/Erase Controller is programming or

erasing during this time then the operation aborts and the memory contents being altered will

be invalid.

A 0.1µF capacitor should be connected between the VCC Supply Voltage pin and the VSS

Ground pin to decouple the current surges from the power supply. The PCB track widths must

be sufficient to carry the currents required during Program and Erase operations, ICC3.

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2.13 V

SS Ground

VSS is the reference for all voltage measurements. The device features two VSS pins which

must be both connected to the system ground.

M29W640FT, M29W640FB 3 Bus operations

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3 Bus operations

There are five standard bus operations that control the device. These are Bus Read, Bus Write,

Output Disable, Standby and Automatic Standby. See Table3: Bus Operations, BYTE = VIL

and Table4: Bus Operations, BYTE = VIH, for a summary. Typically glitches of less than 5ns on

Chip Enable or Write Enable are ignored by the memory and do not affect bus operations.

3.1 Bus Read

Bus Read operations read from the memory cells, or specific registers in the Command

Interface. A valid Bus Read operation involves setting the desired address on the Address

Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable

High, VIH. The Data Inputs/Outputs will output the value, see Figure8: Read Mode AC

Waveforms, and Table13: Read AC Characteristics, for details of when the output becomes

valid.

3.2 Bus Write

Bus Write operations write to the Command Interface. To speed up the read operation the

memory array can be read in Page mode where data is internally read and stored in a page

buffer. The Page has a size of 4 Words and is addressed by the address inputs A0-A1.

A valid Bus Write operation begins by setting the desired address on the Address Inputs. The

Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or

Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command

Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output

Enable must remain High, VIH, during the whole Bus Write operation. See Figure10: Write AC

Waveforms, Write Enable Controlled,Figure11: Write AC Waveforms, Chip Enable Controlled,

and Table14: Write AC Characteristics, Write Enable Controlled and Table15: Write AC

Characteristics, Chip Enable Controlled, for details of the timing requirements.

3.3 Output Disable

The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH.

3.4 Standby

When Chip Enable is High, VIH, the memory enters Standby mode and the Data Inputs/Outputs

pins are placed in the high-impedance state. To reduce the Supply Current to the Standby

Supply Current, ICC2, Chip Enable should be held within VCC ± 0.2V. For the Standby current

level see Table12: DC Characteristics.

During program or erase operations the memory will continue to use the Program/Erase Supply

Current, ICC3, for Program or Erase operations until the operation completes.

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3.5 Automatic Standby

If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 300ns or more

the memory enters Automatic Standby where the internal Supply Current is reduced to the

Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus Read

operation is in progress.

3.6 Special Bus Operations

Additional bus operations can be performed to read the Electronic Signature and also to apply

and remove Block Protection. These bus operations are intended for use by programming

equipment and are not usually used in applications. They require VID to be applied to some

pins.

3.6.1 Electronic Signature

The memory has two codes, the manufacturer code and the device code, that can be read to

identify the memory. These codes can be read by applying the signals listed in Table3: Bus

Operations, BYTE = VIL and Table4: Bus Operations, BYTE = VIH.

3.6.2 Block Protect andChip Unprotect

Groups of blocks can be protected against accidental Program or Erase. The Protection

Groups are shown in Appendix A: Block addressesTable20 and Table21. The whole chip can

be unprotected to allow the data inside the blocks to be changed.

The VPP/Write Protectpin can be used to protect the two outermost boot blocks. When VPP/

Write Protectis at VIL the two outermost boot blocks are protected and remain protected

regardless of the Block Protection Status or the Reset/Block Temporary Unprotect pin status.

Block Protect and Chip Unprotect operations are described in Appendix D: Block Protection.

M29W640FT, M29W640FB 3 Bus operations

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Table 3.Bus Operations, BYTE = VIL

1.X = VIL or VIH.

OperationEGW Address Inputs

DQ15A–1, A0-A21

Data Inputs/Outputs

DQ14-DQ8DQ7-DQ0

Bus Read VIL VIL VIH Cell AddressHi-ZData Output

Bus Write VIL VIH VIL Command AddressHi-ZData Input

Output DisableX

IH VIH XHi-ZHi-Z

Standby VIH XXXHi-ZHi-Z

Read Manufacturer

Code VIL VIL VIH A0-A3 = VIL, A6 = VIL,

A9 = VID, Others VIL or VIH Hi-Z20h

Read Device Code VIL VIL VIH

A0 = VIH, A1-A3= VIL,

A6 = VIL, A9 = VID,

Others VIL or VIH

Hi-Z EDh (M29W640FT)

FDh (M29W640FB)

Read Extended

Memory Block Verify

Code VIL VIL VIH

A0 -A1 = VIH, A2-A3= VIL,

A6 = VIL, A9 = VID,

Others VIL or VIH

Hi-Z 80h (factory locked)

00h (Customer

Lockable)

Read Block

Protection Status VIL VIL VIH

A0,A2,A3, A6= VIL,

A1= VIH, A9 = VID,

A12-A21 = Block Address,

Others VIL or VIH

Hi-Z 01h (protected)

00h (unprotected)

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Table 4.Bus Operations, BYTE = VIH

1.X = VIL or VIH.

OperationEGW Address Inputs

A0-A21 Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

Bus Read VIL VIL VIH Cell AddressData Output

Bus Write VIL VIH VIL Command AddressData Input

Output DisableX

IH VIH XHi-Z

Standby VIH XXXHi-Z

Read Manufacturer

Code VIL VIL VIH A0-A3 = VIL, A6 = VIL,

A9 = VID, Others VIL or VIH 0020h

Read Device Code VIL VIL VIH A0 = VIH, A1-A3= VIL, A6 = VIL,

A9 = VID, Others VIL or VIH

22EDh (M29W640FT)

22FDh (M29W640FB)

Read Extended

Memory Block Verify

Code VIL VIL VIH

A0 -A1 = VIH, A2-A3= VIL,

A6 = VIL, A9 = VID,

Others VIL or VIH

80h (factory locked)

00h (Customer Lockable)

Read Block

Protection Status VIL VIL VIH

A0,A2,A3, A6= VIL,

A1 = VIH, A9 = VID,

A12-A21 = Block Address,

Others VIL or VIH

0001h (protected)

0000h (unprotected)

M29W640FT, M29W640FB 4 Command Interface

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4 Command Interface

All Bus Write operations to the memory are interpreted by the Command Interface. Commands

consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of

Bus Write operations will result in the memory returning to Read mode. The long command

sequences are imposed to maximize data security.

The address used for the commands changes depending on whether the memory is in 16-bit or

8-bit mode. See either Table5, or Table6, depending on the configuration that is being used,

for a summary of the commands.

4.1 Standard commands

4.1.1 Read/Reset command

The Read/Reset command returns the memory to its Read mode. It also resets the errors in

the Status Register. Either one or three Bus Write operations can be used to issue the Read/

Reset command.

The Read/Reset command can be issued, between Bus Write cycles before the start of a

program or erase operation, to return the device to read mode. If the Read/Reset command is

issued during the timeout of a Block Erase operation then the memory will take up to 10µs to

abort. During the abort period no valid data can be read from the memory. The Read/Reset

command will not abort an Erase operation when issued while in Erase Suspend.

4.1.2 Auto Select command

The Auto Select command is used to read the Manufacturer Code, the Device Code, the Block

Protection Status and the Extended Memory Block Verify Code. Three consecutive Bus Write

operations are required to issue the Auto Select command. Once the Auto Select command is

issued the memory remains in Auto Select mode until a Read/Reset command is issued. Read

CFI Query and Read/Reset commands are accepted in Auto Select mode, all other commands

are ignored.

In Auto Select mode, the Manufacturer Code and the Device Code can be read by using a Bus

Read operation with addresses and control signals set as shown in Table3: Bus Operations,

BYTE = VIL and Table4: Bus Operations, BYTE = VIH, except for A9 that is ‘Don’t Care’.

The Block Protection Status of each block can be read using a Bus Read operation with

addresses and control signals set as shown in Table3: Bus Operations, BYTE = VIL and

Table4: Bus Operations, BYTE = VIH, except for A9 that is ‘Don’t Care’. If the addressed block

is protected then 01h is output on Data Inputs/Outputs DQ0-DQ7, otherwise 00h is output (in

8-bit mode).

The protection status of the Extended Memory block, or Extended Memory Block Verify code,

can be read using a Bus Read operation with addresses and control signals set as shown in

Table3: Bus Operations, BYTE = VIL and Table4: Bus Operations, BYTE = VIH, except for A9

that is ‘Don’t Care’. If the Extended Block is "Factory Locked" then 80h is output on Data Input/

Outputs DQ0-DQ7, otherwise 00h is output (8-bit mode).

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4.1.3 Read CFI Query command

The Read CFI Query Command is used to read data from the Common Flash Interface (CFI)

Memory Area. This command is valid when the device is in the Read Array mode, or when the

device is in Autoselected mode.

One Bus Write cycle is required to issue the Read CFI Query Command. Once the command is

issued subsequent Bus Read operations read from the Common Flash Interface Memory Area.

The Read/Reset command must be issued to return the device to the previous mode (the Read

Array mode or Autoselected mode). A second Read/Reset command would be needed if the

device is to be put in the Read Array mode from Autoselected mode.

See Appendix B: Common Flash Interface (CFI), Tables 22,23,24,25,26 and 27 for details on

the information contained in the Common Flash Interface (CFI) memory area.

4.1.4 Chip Erase command

The Chip Erase command can be used to erase the entire chip. Six Bus Write operations are

required to issue the Chip Erase Command and start the Program/Erase Controller.

If any blocks are protected then these are ignored and all the other blocks are erased. If all of

the blocks are protected the Chip Erase operation appears to start but will terminate within

about 100µs, leaving the data unchanged. No error condition is given when protected blocks

are ignored.

During the erase operation the memory will ignore all commands, including the Erase Suspend

command. It is not possible to issue any command to abort the operation. Typical chip erase

times are given in Table7: Program, Erase Times and Program, Erase Endurance Cycles. All

Bus Read operations during the Chip Erase operation will output the Status Register on the

Data Inputs/Outputs. See the section on the Status Register for more details.

After the Chip Erase operation has completed the memory will return to the Read Mode, unless

an error has occurred. When an error occurs the memory will continue to output the Status

Read Mode.

The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All

previous data is lost.

4.1.5 Block Erase command

The Block Erase command can be used to erase a list of one or more blocks. Six Bus Write

operations are required to select the first block in the list. Each additional block in the list can be

selected by repeating the sixth Bus Write operation using the address of the additional block.

The Block Erase operation starts the Program/Erase Controller about 50µs after the last Bus

Write operation. Once the Program/Erase Controller starts it is not possible to select any more

blocks. Each additional block must therefore be selected within 50µs of the last block. The 50µs

timer restarts when an additional block is selected. The Status Register can be read after the

sixth Bus Write operation. See the Status Register section for details on how to identify if the

Program/Erase Controller has started the Block Erase operation.

If any selected blocks are protected then these are ignored and all the other selected blocks are

erased. If all of the selected blocks are protected the Block Erase operation appears to start but

will terminate within about 100µs, leaving the data unchanged. No error condition is given when

protected blocks are ignored.

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During the Block Erase operation the memory will ignore all commands except the Erase

Suspend command. Typical block erase times are given in Table7: Program, Erase Times and

Program, Erase Endurance Cycles. All Bus Read operations during the Block Erase operation

will output the Status Register on the Data Inputs/Outputs. See the section on the Status

After the Block Erase operation has completed the memory will return to the Read Mode,

unless an error has occurred. When an error occurs the memory will continue to output the

Status Register. A Read/Reset command must be issued to reset the error condition and return

to Read mode.

The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All

previous data in the selected blocks is lost.

4.1.6 Erase Suspend command

The Erase Suspend Command may be used to temporarily suspend a Block Erase operation

and return the memory to Read mode. The command requires one Bus Write operation.

The Program/Erase Controller will suspend within the Erase Suspend Latency time of the

Erase Suspend Command being issued. Once the Program/Erase Controller has stopped the

memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend

command is issued during the period when the memory is waiting for an additional block

(before the Program/Erase Controller starts) then the Erase is suspended immediately and will

start immediately when the Erase Resume Command is issued. It is not possible to select any

further blocks to erase after the Erase Resume.

During Erase Suspend it is possible to Read and Program cells in blocks that are not being

erased; both Read and Program operations behave as normal on these blocks. If any attempt is

made to program in a protected block or in the suspended block then the Program command is

ignored and the data remains unchanged. The Status Register is not read and no error

condition is given. Reading from blocks that are being erased will output the Status Register.

It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands

during an Erase Suspend. The Read/Reset command must be issued to return the device to

Read Array mode before the Resume command will be accepted.

4.1.7 Erase Resume command

The Erase Resume command must be used to restart the Program/Erase Controller after an

Erase Suspend. The device must be in Read Array mode before the Resume command will be

accepted. An erase can be suspended and resumed more than once.

4.1.8 Program Suspend command

The Program Suspend command allows the system to interrupt a program operation so that

data can be read from any block. When the Program Suspend command is issued during a

program operation, the device suspends the program operation within the Program Suspend

Latency time (see Table7: Program, Erase Times and Program, Erase Endurance Cycles for

value) and updates the Status Register bits.

After the program operation has been suspended, the system can read array data from any

address. However, data read from Program-Suspended addresses is not valid.

The Program Suspend command may also be issued during a program operation while an

erase is suspended. In this case, data may be read from any addresses not in Erase Suspend

4 Command Interface M29W640FT, M29W640FB

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or Program Suspend. If a read is needed from the Extended Block area (One-time Program

area), the user must use the proper command sequences to enter and exit this region.

The system may also issue the Auto Select command sequence when the device is in the

Program Suspend mode. The system can read as many Auto Select codes as required. When

the device exits the Auto Select mode, the device reverts to the Program Suspend mode, and is

ready for another valid operation. See Auto Select command sequence for more information.

4.1.9 Program Resume command

After the Program Resume command is issued, the device reverts to programming. The

controller can determine the status of the program operation using the DQ7 or DQ6 status bits,

just as in the standard program operation. See Write Operation Status for more information.

The system must write the Program Resume command, to exit the Program Suspend mode

and to continue the programming operation.

Further issuing of the Resume command is ignored. Another Program Suspend command can

be written after the device has resumed programming.

4.1.10 Program command

The Program command can be used to program a value to one address in the memory array at

a time. The command requires four Bus Write operations, the final write operation latches the

address and data, and starts the Program/Erase Controller.

Programming can be suspended and then resumed by issuing a Program Suspend command

and a Program Resume command, respectively (see Section4.1.8: Program Suspend

command and Section4.1.9: Program Resume command).

If the address falls in a protected block then the Program command is ignored, the data remains

unchanged. The Status Register is never read and no error condition is given.

During the program operation the memory will ignore all commands. It is not possible to issue

any command to abort or pause the operation. Typical program times are given in Table7:

Program, Erase Times and Program, Erase Endurance Cycles. Bus Read operations during

the program operation will output the Status Register on the Data Inputs/Outputs. See the

section on the Status Register for more details.

After the program operation has completed the memory will return to the Read mode, unless an

error has occurred. When an error occurs the memory will continue to output the Status

Read mode.

Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase

Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.

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4.2 Fast Program commands

There are four Fast Program commands available to improve the programming throughput, by

writing several adjacent words or bytes in parallel. The Double, Quadruple and Octuple Byte

Program commands are available for x8 operations, while the Double Quadruple Word Program

command are available for x16 operations.

Fast Program commands can be suspended and then resumed by issuing a Program Suspend

command and a Program Resume command, respectively (see Section4.1.8: Program

Suspend command and Section4.1.9: Program Resume command).

When VPPH is applied to the VPP/Write Protect pin the memory automatically enters the Fast

Program mode. The user can then choose to issue any of the Fast Program commands. Care

must be taken because applying a VPPH to the VPP/WP pin will temporarily unprotect any

protected block.

4.2.1 Double Byte Program command

The Double Byte Program command is used to write a page of two adjacent Bytes in parallel.

The two bytes must differ only in DQ15A-1. Three bus write cycles are necessary to issue the

Double Byte Program command.

1.The first bus cycle sets up the Double Byte Program Command.

2. The second bus cycle latches the Address and the Data of the first byte to be written.

3. The third bus cycle latches the Address and the Data of the second byte to be written.

4.2.2 Quadruple Byte Program command

The Quadruple Byte Program command is used to write a page of four adjacent Bytes in

parallel. The four bytes must differ only for addresses A0, DQ15A-1. Five bus write cycles are

necessary to issue the Quadruple Byte Program command.

1.The first bus cycle sets up the Quadruple Byte Program Command.

2. The second bus cycle latches the Address and the Data of the first byte to be written.

3. The third bus cycle latches the Address and the Data of the second byte to be written.

4. The fourth bus cycle latches the Address and the Data of the third byte to be written.

5. The fifth bus cycle latches the Address and the Data of the fourth byte to be written and

starts the Program/Erase Controller.

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4.2.3 Octuple Byte Program command

This is used to write eight adjacent Bytes, in x8 mode, simultaneously. The addresses of the

eight Bytes must differ only in A1, A0 and DQ15A-1.

Nine bus write cycles are necessary to issue the command:

1.The first bus cycle sets up the command.

2. The second bus cycle latches the Address and the Data of the first Byte to be written.

3. The third bus cycle latches the Address and the Data of the second Byte to be written.

4. The fourth bus cycle latches the Address and the Data of the third Byte to be written.

5. The fifth bus cycle latches the Address and the Data of the fourth Byte to be written.

6. The sixth bus cycle latches the Address and the Data of the fifth Byte to be written.

7. The seventh bus cycle latches the Address and the Data of the sixth Byte to be written.

8. The eighth bus cycle latches the Address and the Data of the seventh Byte to be written.

9. The ninth bus cycle latches the Address and the Data of the eighth Byte to be written and

starts the Program/Erase Controller.

4.2.4 Double Word Program command

The Double Word Program command is used to write a page of two adjacent Words in parallel.

The two Words must differ only for the address A0.

Three bus write cycles are necessary to issue the Double Word Program command.

The first bus cycle sets up the Quadruple Word Program Command.

The second bus cycle latches the Address and the Data of the first Word to be written.

The third bus cycle latches the Address and the Data of the second Word to be written and

starts the Program/Erase Controller.

After the program operation has completed the memory will return to the Read mode, unless an

error has occurred. When an error occurs Bus Read operations will continue to output the

Status Register. A Read/Reset command must be issued to reset the error condition and return

to Read mode.

Note that the Fast Program commands cannot change a bit set at ’0’ back to ’1’. One of the

Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to

’1’.

Typical Program times are given in Table7: Program, Erase Times and Program, Erase

Endurance Cycles.

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4.2.5 Quadruple Word Program command

This is used to write a page of four adjacent Words (or 8 adjacent Bytes), in x16 mode,

simultaneously. The addresses of the four Words must differ only in A1 and A0.

Five bus write cycles are necessary to issue the command:

The first bus cycle sets up the command.

The second bus cycle latches the Address and the Data of the first Word to be written.

The third bus cycle latches the Address and the Data of the second Word to be written.

The fourth bus cycle latches the Address and the Data of the third Word to be written.

The fifth bus cycle latches the Address and the Data of the fourth Word to be written and

starts the Program/Erase Controller.

4.2.6 Unlock Bypass command

The Unlock Bypass command is used in conjunction with the Unlock Bypass Program

command to program the memory faster than with the standard program commands. When the

cycle time to the device is long, considerable time saving can be made by using these

commands. Three Bus Write operations are required to issue the Unlock Bypass command.

Once the Unlock Bypass command has been issued the memory will only accept the Unlock

Bypass Program command and the Unlock Bypass Reset command. The memory can be read

as if in Read mode.

When VPP is applied to the VPP/Write Protect pin the memory automatically enters the Unlock

Bypass mode and the Unlock Bypass Program command can be issued immediately.

4.2.7 Unlock Bypass Program command

The Unlock Bypass command is used in conjunction with the Unlock Bypass Program

command to program the memory. When the cycle time to the device is long, considerable time

saving can be made by using these commands. Three Bus Write operations are required to

issue the Unlock Bypass command.

Once the Unlock Bypass command has been issued the memory will only accept the Unlock

Bypass Program command and the Unlock Bypass Reset command. The memory can be read

as if in Read mode.

The memory offers accelerated program operations through the VPP/Write Protect pin. When

the system asserts VPP on the VPP/Write Protect pin, the memory automatically enters the

Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program

command sequence. The memory uses the higher voltage on the VPP/Write Protect pin, to

accelerate the Unlock Bypass Program operation.

Never raise VPP/Write Protect to VPP from any mode except Read mode, otherwise the

memory may be left in an indeterminate state.

4.2.8 Unlock Bypass Reset command

The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock

Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset

command. Read/Reset command does not exit from Unlock Bypass Mode.

4 Command Interface M29W640FT, M29W640FB

26/72

4.3 Block Protection commands

4.3.1 Enter Extended Block command

The device has an extra 256 Byte block (Extended Block) that can only be accessed using the

Enter Extended Block command. Three Bus write cycles are required to issue the Extended

Block command. Once the command has been issued the device enters Extended Block mode

where all Bus Read or Write operations to the Boot Block addresses access the Extended

Block. The Extended Block (with the same address as the Boot Blocks) cannot be erased, and

can be treated as one-time programmable (OTP) memory. In Extended Block mode the Boot

Blocks are not accessible.

To exit from the Extended Block mode the Exit Extended Block command must be issued.

The Extended Block can be protected, however once protected the protection cannot be

undone.

4.3.2 Exit Extended Block command

The Exit Extended Block command is used to exit from the Extended Block mode and return

the device to Read mode. Four Bus Write operations are required to issue the command.

M29W640FT, M29W640FB 4 Command Interface

27/72

4.3.3 Block Protect andChip Unprotect commands

Groups of blocks can be protected against accidental Program or Erase. The Protection

Groups are shown in Appendix A: Block addresses,Table20: Top Boot Block Addresses,

M29W640FT and Table21: Bottom Boot Block Addresses, M29W640FB. The whole chip can

be unprotected to allow the data inside the blocks to be changed.

Block Protect and Chip Unprotect operations are described in Appendix D: Block Protection.

Table 5.Commands, 16-bit mode, BYTE = VIH

1.X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in

hexadecimal.

The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15

are Don’t Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.

Command

Length

Bus Write Operations

1st2nd3rd4th5th6th

AddrDataAddrDataAddrDataAddrDataAddrDataAddrData

Read/Reset 1XF0

3555AA2AA55XF0

Auto Select3555AA2AA5555590

Program4555AA2AA55555A0PAPD

Double Word Program355550PA0PD0PA1PD1

Quadruple Word

Program 555556PA0PD0PA1PD1PA2PD2PA3PD3

Unlock Bypass3555AA2AA5555520

Unlock Bypass

Program 2XA0PAPD

Unlock Bypass Reset2X90X00

Chip Erase6555AA2AA5555580555AA2AA5555510

Block Erase6+555AA2AA5555580555AA2AA55BA30

Program/Erase

Suspend 1XB0

Program/Erase

Resume 1X30

Read CFI Query15598

Enter Extended Block3555AA2AA5555588

Exit Extended Block4555AA2AA5555590X00

4 Command Interface M29W640FT, M29W640FB

28/72

Table 6.Commands, 8-bit mode, BYTE = VIL

1.X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in

hexadecimal.

The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15

are Don’t Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.

Command

Length

Bus Write Operations

1st2nd3rd4th5th6th7th8th9th

AddDataAddDataAddDataAddDataAddDataAddDataAddDataAddDataAddData

Read/Reset 1XF0

3AAAAA55555XF0

Auto Select3AAAAA55555AAA90

Program4AAAAA55555AAAA0PAPD

Double Byte

Program 3AAA50PA0PD0PA1PD1PA2PD2

Quadruple

Byte Program 5AAA56PA0PD0PA1PD1PA2PD2PA3PD3

Octuple Byte

Program 9AAA8BPA0PD0PA1PD1PA2PD2PA3PD3PA4PD4PA5PD5PA6PD6PA7PD7

Unlock

Bypass 3AAAAA55555AAA20

Unlock

Bypass

Program 2XA0PAPD

Unlock

Bypass Reset 2X90X00

Chip Erase6AAAAA55555AAA80AAAAA55555AAA10

Block Erase 6

+AAAAA55555AAA80AAAAA55555BA30

Program/

Erase

Suspend 1XB0

Program/

Erase

Resume 1X30

Read CFI

Query 1AA98

Enter

Extended

Block 3AAAAA55555AAA88

Exit Extended

Block 4AAAAA55555AAA90X00

M29W640FT, M29W640FB 4 Command Interface

29/72

Table 7.Program, Erase Times and Program, Erase Endurance Cycles

ParameterMin Typ(1) (2)

1.Typical values measured at room temperature and nominal voltages.

2.Sampled, but not 100% tested.

Max(2) Unit

Chip Erase80 400(3)

3.Maximum value measured at worst case conditions for both temperature and VCC after 100,00 program/erase cycles.

Block Erase (64 KBytes)0.8 6(4) s

Erase Suspend Latency Time 50(4)

4.Maximum value measured at worst case conditions for both temperature and VCC.

µs

Program (Byte or Word)10 200(3) µs

Double Byte10 200(3) µs

Double Word /Quadruple Byte Program10 200(3) µs

Quadruple Word / Octuple Byte Program10 200(3) µs

Chip Program (Byte by Byte)80 400(3) s

Chip Program (Word by Word)40 200(3) s

Chip Program (Double Word/Quadruple Byte Program)20 100(3) s

Chip Program (Quadruple Word/Octuple Byte Program)10 50(3) s

Program Suspend Latency Time4µs

Program/Erase Cycles (per Block)100,000cycles

Data Retention20years

5 Status Register M29W640FT, M29W640FB

30/72

5 Status Register

Bus Read operations from any address always read the Status Register during Program and

Erase operations. It is also read during Erase Suspend when an address within a block being

erased is accessed.

The bits in the Status Register are summarized in Table8: Status Register Bits.

5.1 Data Polling Bit (DQ7)

The Data Polling Bit can be used to identify whether the Program/Erase Controller has

successfully completed its operation or if it has responded to an Erase Suspend. The Data

Polling Bit is output on DQ7 when the Status Register is read.

During Program operations the Data Polling Bit outputs the complement of the bit being

programmed to DQ7. After successful completion of the Program operation the memory returns

to Read mode and Bus Read operations from the address just programmed output DQ7, not its

complement.

During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state of

DQ7. After successful completion of the Erase operation the memory returns to Read Mode.

In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation within

a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the Program/

Erase Controller has suspended the Erase operation.

Figure4: Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid

Address is the address being programmed or an address within the block being erased.

5.2 Toggle Bit (DQ6)

The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully

completed its operation or if it has responded to an Erase Suspend. The Toggle Bit is output on

DQ6 when the Status Register is read.

During Program and Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with

successive Bus Read operations at any address. After successful completion of the operation

the memory returns to Read mode.

During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block

being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has

suspended the Erase operation.

Figure5: Data Toggle Flowchart, gives an example of how to use the Data Toggle Bit.

M29W640FT, M29W640FB 5 Status Register

31/72

5.3 Error Bit (DQ5)

The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error

Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the correct

data to the memory. If the Error Bit is set a Read/Reset command must be issued before other

commands are issued. The Error bit is output on DQ5 when the Status Register is read.

Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to do

so will set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’. One of

the Erase commands must be used to set all the bits in a block or in the whole memory from ’0’

to ’1’.

5.4 Erase Timer Bit (DQ3)

The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation

during a Block Erase command. Once the Program/Erase Controller starts erasing the Erase

Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Bit is set to ’0’

and additional blocks to be erased may be written to the Command Interface. The Erase Timer

Bit is output on DQ3 when the Status Register is read.

5.5 Alternative Toggle Bit (DQ2)

The Alternative Toggle Bit can be used to monitor the Program/Erase controller during Erase

operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is read.

During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc.,

with successive Bus Read operations from addresses within the blocks being erased. A

protected block is treated the same as a block not being erased. Once the operation completes

the memory returns to Read mode.

During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with

successive Bus Read operations from addresses within the blocks being erased. Bus Read

operations to addresses within blocks not being erased will output the memory cell data as if in

Read mode.

After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be

used to identify which block or blocks have caused the error. The Alternative Toggle Bit

changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses within

blocks that have not erased correctly. The Alternative Toggle Bit does not change if the

addressed block has erased correctly.

5 Status Register M29W640FT, M29W640FB

32/72

Table 8.Status Register Bits

1.Unspecified data bits should be ignored.

Figure 4.Data Polling Flowchart

OperationAddressDQ7DQ6DQ5DQ3DQ2RB

ProgramAny AddressDQ7Toggle0 ––0

Program During Erase

Suspend Any AddressDQ7Toggle0 ––0

Program ErrorAny AddressDQ7Toggle1 ––Hi-Z

Chip EraseAny Address0Toggle01ToggleHi-Z

Block Erase before

timeout Erasing Block0Toggle00Toggle0

Non-Erasing Block0Toggle00No Toggle0

Block Erase Erasing Block0Toggle01ToggleHi-Z

Non-Erasing Block0Toggle01No Toggle0

Erase Suspend Erasing Block1No Toggle0 –ToggleHi-Z

Non-Erasing BlockData read as normalHi-Z

Erase Error Good Block Address0Toggle11No Toggle0

Faulty Block Address0Toggle11Toggle0

READ DQ5 & DQ7

at VALID ADDRESS

START

READ DQ7

at VALID ADDRESS

FAILPASS

AI90194

DQ7

DATA YES

YES

DQ5

= 1

DQ7

DATA YES

M29W640FT, M29W640FB 5 Status Register

33/72

Figure 5.Data Toggle Flowchart

READ DQ6

START

READ DQ6

TWICE

FAILPASS

AI90195B

DQ6

TOGGLE NO

YES

DQ5

= 1

YES

DQ6

TOGGLE

READ

DQ5 & DQ6

6 Maximum rating M29W640FT, M29W640FB

34/72

6 Maximum rating

Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause

permanent damage to the device. Exposure to Absolute Maximum Rating conditions for

extended periods may affect device reliability. These are stress ratings only and operation of

the device at these or any other conditions above those indicated in the Operating sections of

this specification is not implied. Refer also to the STMicroelectronics SURE Program and other

relevant quality documents.

Table 9.Absolute Maximum Ratings

SymbolParameterMinMaxUnit

TBIAS Temperature Under Bias –50125 °C

TSTG Storage Temperature –65150 °C

VIO Input or Output Voltage(1)(2)

1.Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions.

2.Maximum voltage may overshoot to VCC +2V during transition and for less than 20ns during transitions.

–0.6 VCC +0.6 V

VCC Supply Voltage –0.64V

ID Identification Voltage –0.613.5V

PP(3)

3.V

PP must not remain at 12V for more than a total of 80hrs.

Program Voltage –0.613.5V

M29W640FT, M29W640FB 7 DC and AC parameters

35/72

7 DC and AC parameters

This section summarizes the operating and measurement conditions, and the DC and AC

characteristics of the device. The parameters in the DC and AC Characteristic tables that follow

are derived from tests performed under the Measurement Conditions summarized in the

relevant tables. Designers should check that the operating conditions in their circuit match the

measurement conditions when relying on the quoted parameters.

Table 10.Operating and AC Measurement Conditions

Figure 6.AC Measurement I/O Waveform

Figure 7.AC Measurement Load Circuit

Parameter M29W640FT, M29W640FBUnit

MinMax

VCC Supply Voltage 2.73.6V

Ambient Operating Temperature –4085 °C

Load Capacitance (CL)30pF

Input Rise and Fall Times10ns

Input Pulse Voltages 0 to VCC V

Input and Output Timing Ref. Voltages VCC/2 V

AI05557

VCC

VCC/2

AI05558

CL includes JIG capacitance

DEVICE

UNDER

TEST

25k

VCC

25k

VCC

0.1µF

VPP

0.1µF

7 DC and AC parameters M29W640FT, M29W640FB

36/72

Table 11.Device Capacitance

1.Sampled only, not 100% tested.

Table 12.DC Characteristics

SymbolParameterTest ConditionMinMaxUnit

CIN Input Capacitance VIN = 0V 6pF

COUT Output Capacitance VOUT = 0V 12pF

SymbolParameterTest ConditionMinMaxUnit

ILI Input Leakage Current 0V VIN VCC ±1µA

ILO Output Leakage Current 0V VOUT VCC ±1µA

ICC1 Supply Current (Read) E = VIL, G = VIH,

f = 6MHz 10mA

ICC2 Supply Current (Standby) E = VCC ±0.2V,

RP = VCC ±0.2V 100 µA

ICC3 Supply Current (Program/

Erase) Program/Erase

Controller active

VPP/WP =

VIL orV

IH 20mA

VPP/WP = VPP 20mA

VIL Input Low Voltage –0.50.8V

IH Input High Voltage 0.7VCC VCC +0.3 V

VPP Voltage for VPP/WP Program

Acceleration VCC = 2.7V ±10% 11.512.5V

PP Current for VPP/WP Program

Acceleration VCC = 2.7V ±10% 15mA

VOL Output Low Voltage IOL = 1.8mA 0.45V

OH Output High Voltage IOH = –100µAV

CC –0.4 V

VID Identification Voltage11.512.5V

LKO(1)

1.Sampled only, not 100% tested.

Program/Erase Lockout

Supply Voltage 1.82.3V

M29W640FT, M29W640FB 7 DC and AC parameters

37/72

Figure 8.Read Mode AC Waveforms

Figure 9.Page Read AC Waveforms

AI05559

tAVAV

tAVQVtAXQX

tELQXtEHQZ

tGLQV

tGLQXtGHQX

VALID

A0-A20/

A–1

DQ0-DQ7/

DQ8-DQ15

tELQV tEHQX

tGHQZ

VALID

tBHQV

tELBL/tELBHtBLQZ

BYTE

AI11553

A2-A21

A0-A1 VALID

DQ0-DQ15

VALIDVALIDVALID

VALID ADDRESS

VALID DATA

VALID

DATA VALID DATAVALID DATA

tAVQV1tGLQV

tAVQV

tELQV tEHQX

tEHQZ

tGHQX

tGHQZ

7 DC and AC parameters M29W640FT, M29W640FB

38/72

Table 13.Read AC Characteristics

SymbolAltParameterTest Condition

M29W640FT,

M29W640FB Unit

6070

tAVAV tRC Address Valid to Next Address Valid E = VIL,

G = VIL Min6070ns

tAVQV tACC Address Valid to Output Valid E = VIL,

G = VIL Max6070ns

tAVQV1 tPAGE Address Valid to Output Valid (Page) E = VIL,

G = VIL Max2525ns

tELQX(1)

1.Sampled only, not 100% tested.

tLZ Chip Enable Low to Output Transition G = VIL Min00ns

tELQV tCE Chip Enable Low to Output Valid G = VIL Max6070ns

tGLQX(1) tOLZ Output Enable Low to Output Transition E = VIL Min00ns

tGLQV tOE Output Enable Low to Output Valid E = VIL Max2525ns

tEHQZ(1) tHZ Chip Enable High to Output Hi-Z G = VIL Max2525ns

tGHQZ(1) tDF Output Enable High to Output Hi-Z E = VIL Max2525ns

tEHQX

tGHQX

tAXQX

tOH Chip Enable, Output Enable or Address

Transition to Output Transition Min00ns

tELBL

tELBH

tELFL

tELFH Chip Enable to BYTE Low or HighMax55ns

tBLQZ tFLQZ BYTE Low to Output Hi-ZMax2525ns

tBHQV tFHQV BYTE High to Output ValidMax3030ns

M29W640FT, M29W640FB 7 DC and AC parameters

39/72

Figure 10.Write AC Waveforms, Write Enable Controlled

AI05560

A0-A20/

A–1

DQ0-DQ7/

DQ8-DQ15

VALID

VCC

tVCHEL

tWHEH

tWHWL

tELWL

tAVWL

tWHGL

tWLAX

tWHDX

tAVAV

tDVWH

tWLWHtGHWL

tWHRL

7 DC and AC parameters M29W640FT, M29W640FB

40/72

Table 14.Write AC Characteristics, Write Enable Controlled

SymbolAltParameter

M29W640FT,

M29W640FB Unit

6070

tAVAV tWC Address Valid to Next Address ValidMin6070ns

tELWL tCS Chip Enable Low to Write Enable LowMin00ns

tWLWH tWP Write Enable Low to Write Enable HighMin4545ns

tDVWH tDS Input Valid to Write Enable HighMin4545ns

tWHDX tDH Write Enable High to Input TransitionMin00ns

tWHEH tCH Write Enable High to Chip Enable HighMin00ns

tWHWL tWPH Write Enable High to Write Enable LowMin3030ns

tAVWL tAS Address Valid to Write Enable LowMin00ns

tWLAX tAH Write Enable Low to Address TransitionMin4545ns

tGHWL Output Enable High to Write Enable LowMin00ns

tWHGL tOEH Write Enable High to Output Enable LowMin00ns

tWHRL(1)

1.Sampled only, not 100% tested.

tBUSY Program/Erase Valid to RB LowMax3030ns

tVCHEL tVCS VCC High to Chip Enable Low Min5050 µs

M29W640FT, M29W640FB 7 DC and AC parameters

41/72

Figure 11.Write AC Waveforms, Chip Enable Controlled

AI05561

A0-A20/

A–1

DQ0-DQ7/

DQ8-DQ15

VALID

VCC

tVCHWL

tEHWH

tEHEL

tWLEL

tAVEL

tEHGL

tELAX

tEHDX

tAVAV

tDVEH

tELEHtGHEL

tEHRL

7 DC and AC parameters M29W640FT, M29W640FB

42/72

Table 15.Write AC Characteristics, Chip Enable Controlled

SymbolAltParameter M29W640FT, M29W640FB Unit

6070

tAVAV tWC Address Valid to Next Address ValidMin6070ns

tWLEL tWS Write Enable Low to Chip Enable LowMin00ns

tELEH tCP Chip Enable Low to Chip Enable HighMin4545ns

tDVEH tDS Input Valid to Chip Enable HighMin4545ns

tEHDX tDH Chip Enable High to Input TransitionMin00ns

tEHWH tWH Chip Enable High to Write Enable HighMin00ns

tEHEL tCPH Chip Enable High to Chip Enable LowMin3030ns

tAVEL tAS Address Valid to Chip Enable LowMin00ns

tELAX tAH Chip Enable Low to Address TransitionMin4545ns

tGHEL Output Enable High Chip Enable LowMin00ns

tEHGL tOEH Chip Enable High to Output Enable LowMin00ns

tEHRL(1)

1.Sampled only, not 100% tested.

tBUSY Program/Erase Valid to RB LowMax3030ns

tVCHWL tVCS VCC High to Write Enable Low Min5050 µs

M29W640FT, M29W640FB 7 DC and AC parameters

43/72

Figure 12.Reset/Block Temporary Unprotect AC Waveforms

Figure 13.Accelerated Program Timing Waveforms

Table 16.Reset/Block Temporary Unprotect AC Characteristics

SymbolAltParameter M29W640FT,

M29W640FB Unit

tPHWL(1)

tPHEL

tPHGL(1)

1.Sampled only, not 100% tested.

tRH RP High to Write Enable Low, Chip Enable Low,

Output Enable Low Min50ns

tRHWL(1)

tRHEL(1)

tRHGL(1)

tRB RB High to Write Enable Low, Chip Enable Low,

Output Enable Low Min0ns

tPLPX tRP RP Pulse WidthMin500ns

tPLYH tREADY RP Low to Read ModeMax50 µs

tPHPHH(1) tVIDR RP Rise Time to VID Min500ns

tVHVPP(1) VPP Rise and Fall Time Min250ns

AI02931B

RP tPLPX

tPHWL, tPHEL, tPHGL

tPLYH

tPHPHH

E, G

tRHWL, tRHEL, tRHGL

AI05563

VPP/WP

VPP

VIL or VIH tVHVPP tVHVPP

8 Package mechanical M29W640FT, M29W640FB

44/72

8 Package mechanical

Figure 14.TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline

1.Drawing is not to scale.

Table 17.TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data

Symbol millimetersinches

TypMinMaxTypMinMax

A1.2000.0472

A10.1000.0500.1500.00390.00200.0059

A21.0000.9501.0500.03940.03740.0413

B0.2200.1700.2700.00870.00670.0106

C0.1000.2100.00390.0083

CP0.1000.0039

D112.00011.90012.1000.47240.46850.4764

E20.00019.80020.2000.78740.77950.7953

E118.40018.30018.5000.72440.72050.7283

e0.500 ––0.0197 ––

L0.6000.5000.7000.02360.01970.0276

L10.8000.0315

a305305

TSOP-G

DIE

LA1

M29W640FT, M29W640FB 8 Package mechanical

45/72

Figure 15.TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, Package Outline

1.Drawing is not to scale.

Table 18.TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, Package Mechanical Data

Symbol millimetersinches

TypMinMaxTypMinMax

A1.2000.0472

A10.2600.0102

A20.9000.0354

b0.3500.4500.01380.0177

D6.0005.9006.1000.23620.23230.2402

D14.000 ––0.1575 ––

ddd0.1000.0039

E8.0007.9008.1000.31500.31100.3189

E15.600 ––0.2205 ––

e0.800 ––0.0315 ––

FD1.000 ––0.0394 ––

FE1.200 ––0.0472 ––

SD0.400 ––0.0157 ––

SE0.400 ––0.0157 ––

E1E

BGA-Z32

ddd

FE SD

BALL "A1"

9 Part Numbering M29W640FT, M29W640FB

46/72

9 Part Numbering

Table 19.Ordering Information Scheme

Note: This product is also available with the Extended Block factory locked. For further details

and ordering information contact your nearest ST sales office.

Devices are shipped from the factory with the memory content bits erased to 1. For a list of

available options (Speed, Package, etc.) or for further information on any aspect of this device,

please contact your nearest ST Sales Office.

Example: M29W640FB70N6F

Device Type

M29

Operating Voltage

W = VCC = 2.7 to 3.6V

Device Function

640F = 64 Mbit (x8/x16), Boot Block

Array Matrix

T = Top Boot

B = Bottom Boot

Speed

60 = 60ns

70 = 70ns

Package

N = TSOP48: 12 x 20 mm

ZA = TFBGA48: 6x8mm, 0.80 mm pitch

Temperature Range

6 = 40 to 85 °C

Option

E = ECOPACK Package, Standard Packing

F = ECOPACK Package, Tape & Reel Packing

M29W640FT, M29W640FB 9 Part Numbering

47/72

Appendix A Block addresses

Table 20.Top Boot Block Addresses, M29W640FT

Block KBytes/

KWords Protection Block

Group (x8)(x16)

064/32

Protection Group

000000h–00FFFFh(1) 000000h–007FFFh(1)

164/32010000h–01FFFFh008000h–00FFFFh

264/32020000h–02FFFFh010000h–017FFFh

364/32030000h–03FFFFh018000h–01FFFFh

464/32

Protection Group

040000h–04FFFFh020000h–027FFFh

564/32050000h–05FFFFh028000h–02FFFFh

664/32060000h–06FFFFh030000h–037FFFh

764/32070000h–07FFFFh038000h–03FFFFh

864/32

Protection Group

080000h–08FFFFh040000h–047FFFh

964/32090000h–09FFFFh048000h–04FFFFh

1064/320A0000h–0AFFFFh050000h–057FFFh

1164/320B0000h–0BFFFFh058000h–05FFFFh

1264/32

Protection Group

0C0000h–0CFFFFh060000h–067FFFh

1364/320D0000h–0DFFFFh068000h–06FFFFh

1464/320E0000h–0EFFFFh070000h–077FFFh

1564/320F0000h–0FFFFFh078000h–07FFFFh

1664/32

Protection Group

100000h–10FFFFh080000h–087FFFh

1764/32110000h–11FFFFh088000h–08FFFFh

1864/32120000h–12FFFFh090000h–097FFFh

1964/32130000h–13FFFFh098000h–09FFFFh

2064/32

Protection Group

140000h–14FFFFh0A0000h–0A7FFFh

2164/32150000h–15FFFFh0A8000h–0AFFFFh

2264/32160000h–16FFFFh0B0000h–0B7FFFh

2364/32170000h–17FFFFh0B8000h–0BFFFFh

2464/32

Protection Group

180000h–18FFFFh0C0000h–0C7FFFh

2564/32190000h–19FFFFh0C8000h–0CFFFFh

2664/321A0000h–1AFFFFh0D0000h–0D7FFFh

2764/321B0000h–1BFFFFh0D8000h–0DFFFFh

9 Part Numbering M29W640FT, M29W640FB

48/72

2864/32

Protection Group

1C0000h–1CFFFFh0E0000h–0E7FFFh

2964/321D0000h–1DFFFFh0E8000h–0EFFFFh

3064/321E0000h–1EFFFFh0F0000h–0F7FFFh

3164/321F0000h–1FFFFFh0F8000h–0FFFFFh

3264/32

Protection Group

200000h–20FFFFh100000h–107FFFh

3364/32210000h–21FFFFh108000h–10FFFFh

3464/32220000h–22FFFFh110000h–117FFFh

3564/32230000h–23FFFFh118000h–11FFFFh

3664/32

Protection Group

240000h–24FFFFh120000h–127FFFh

3764/32250000h–25FFFFh128000h–12FFFFh

3864/32260000h–26FFFFh130000h–137FFFh

3964/32270000h–27FFFFh138000h–13FFFFh

4064/32

Protection Group

280000h–28FFFFh140000h–147FFFh

4164/32290000h–29FFFFh148000h–14FFFFh

4264/322A0000h–2AFFFFh150000h–157FFFh

4364/322B0000h–2BFFFFh158000h–15FFFFh

4464/32

Protection Group

2C0000h–2CFFFFh160000h–167FFFh

4564/322D0000h–2DFFFFh168000h–16FFFFh

4664/322E0000h–2EFFFFh170000h–177FFFh

4764/322F0000h–2FFFFFh178000h–17FFFFh

4864/32

Protection Group

300000h–30FFFFh180000h–187FFFh

4964/32310000h–31FFFFh188000h–18FFFFh

5064/32320000h–32FFFFh190000h–197FFFh

5164/32330000h–33FFFFh198000h–19FFFFh

5264/32

Protection Group

340000h–34FFFFh1A0000h–1A7FFFh

5364/32350000h–35FFFFh1A8000h–1AFFFFh

5464/32360000h–36FFFFh1B0000h–1B7FFFh

5564/32370000h–37FFFFh1B8000h–1BFFFFh

5664/32

Protection Group

380000h–38FFFFh1C0000h–1C7FFFh

5764/32390000h–39FFFFh1C8000h–1CFFFFh

5864/323A0000h–3AFFFFh1D0000h–1D7FFFh

5964/323B0000h–3BFFFFh1D8000h–1DFFFFh

Block KBytes/

KWords Protection Block

Group (x8)(x16)

M29W640FT, M29W640FB 9 Part Numbering

49/72

6064/32

Protection Group

3C0000h–3CFFFFh1E0000h–1E7FFFh

6164/323D0000h–3DFFFFh1E8000h–1EFFFFh

6264/323E0000h–3EFFFFh1F0000h–1F7FFFh

6364/323F0000h–3FFFFFh1F8000h–1FFFFFh

6464/32

Protection Group

400000h–40FFFFh200000h–207FFFh

6564/32410000h–41FFFFh208000h–20FFFFh

6664/32420000h–42FFFFh210000h–217FFFh

6764/32430000h–43FFFFh218000h–21FFFFh

6864/32

Protection Group

440000h–44FFFFh220000h–227FFFh

6964/32450000h–45FFFFh228000h–22FFFFh

7064/32460000h–46FFFFh230000h–237FFFh

7164/32470000h–47FFFFh238000h–23FFFFh

7264/32

Protection Group

480000h–48FFFFh240000h–247FFFh

7364/32490000h–49FFFFh248000h–24FFFFh

7464/324A0000h–4AFFFFh250000h–257FFFh

7564/324B0000h–4BFFFFh258000h–25FFFFh

7664/32

Protection Group

4C0000h–4CFFFFh260000h–267FFFh

7764/324D0000h–4DFFFFh268000h–26FFFFh

7864/324E0000h–4EFFFFh270000h–277FFFh

7964/324F0000h–4FFFFFh278000h–27FFFFh

8064/32

Protection Group

500000h–50FFFFh280000h–287FFFh

8164/32510000h–51FFFFh288000h–28FFFFh

8264/32520000h–52FFFFh290000h–297FFFh

8364/32530000h–53FFFFh298000h–29FFFFh

8464/32

Protection Group

540000h–54FFFFh2A0000h–2A7FFFh

8564/32550000h–55FFFFh2A8000h–2AFFFFh

8664/32560000h–56FFFFh2B0000h–2B7FFFh

8764/32570000h–57FFFFh2B8000h–2BFFFFh

8864/32

Protection Group

580000h–58FFFFh2C0000h–2C7FFFh

8964/32590000h–59FFFFh2C8000h–2CFFFFh

9064/325A0000h–5AFFFFh2D0000h–2D7FFFh

9164/325B0000h–5BFFFFh2D8000h–2DFFFFh

Block KBytes/

KWords Protection Block

Group (x8)(x16)

9 Part Numbering M29W640FT, M29W640FB

50/72

9264/32

Protection Group

5C0000h–5CFFFFh2E0000h–2E7FFFh

9364/325D0000h–5DFFFFh2E8000h–2EFFFFh

9464/325E0000h–5EFFFFh2F0000h–2F7FFFh

9564/325F0000h–5FFFFFh2F8000h–2FFFFFh

9664/32

Protection Group

600000h–60FFFFh300000h–307FFFh

9764/32610000h–61FFFFh308000h–30FFFFh

9864/32620000h–62FFFFh310000h–317FFFh

9964/32630000h–63FFFFh318000h–31FFFFh

10064/32

Protection Group

640000h–64FFFFh320000h–327FFFh

10164/32650000h–65FFFFh328000h–32FFFFh

10264/32660000h–66FFFFh330000h–337FFFh

10364/32670000h–67FFFFh338000h–33FFFFh

10464/32

Protection Group

680000h–68FFFFh340000h–347FFFh

10564/32690000h–69FFFFh348000h–34FFFFh

10664/326A0000h–6AFFFFh350000h–357FFFh

10764/326B0000h–6BFFFFh358000h–35FFFFh

10864/32

Protection Group

6C0000h–6CFFFFh360000h–367FFFh

10964/326D0000h–6DFFFFh368000h–36FFFFh

11064/326E0000h–6EFFFFh370000h–377FFFh

11164/326F0000h–6FFFFFh378000h–37FFFFh

11264/32

Protection Group

700000h–70FFFFh380000h–387FFFh

11364/32710000h–71FFFFh388000h–38FFFFh

11464/32720000h–72FFFFh390000h–397FFFh

11564/32730000h–73FFFFh398000h–39FFFFh

11664/32

Protection Group

740000h–74FFFFh3A0000h–3A7FFFh

11764/32750000h–75FFFFh3A8000h–3AFFFFh

11864/32760000h–76FFFFh3B0000h–3B7FFFh

11964/32770000h–77FFFFh3B8000h–3BFFFFh

12064/32

Protection Group

780000h–78FFFFh3C0000h–3C7FFFh

12164/32790000h–79FFFFh3C8000h–3CFFFFh

12264/327A0000h–7AFFFFh3D0000h–3D7FFFh

12364/327B0000h–7BFFFFh3D8000h–3DFFFFh

Block KBytes/

KWords Protection Block

Group (x8)(x16)

M29W640FT, M29W640FB 9 Part Numbering

51/72

12464/32

Protection Group

7C0000h–7CFFFFh3E0000h–3E7FFFh

12564/327D0000h–7DFFFFh3E8000h–3EFFFFh

12664/327E0000h–7EFFFFh3F0000h–3F7FFFh

1278/4 7F0000h–7F1FFFh3F8000h–3F8FFFh

1288/4 7F2000h–7F3FFFh3F9000h–3F9FFFh

1298/4 7F4000h–7F5FFFh3FA000h–3FAFFFh

1308/4 7F6000h–7F7FFFh3FB000h–3FBFFFh

1318/4 7F8000h–7F9FFFh3FC000h–3FCFFFh

1328/4 7FA000h–7FBFFFh3FD000h–3FDFFFh

1338/4 7FC000h–7FDFFFh3FE000h–3FEFFFh

1348/4 7FE000h–7FFFFFh3FF000h–3FFFFFh

1.Used as the Extended Block Addresses in Extended Block mode.

Block KBytes/

KWords Protection Block

Group (x8)(x16)

9 Part Numbering M29W640FT, M29W640FB

52/72

Table 21.Bottom Boot Block Addresses, M29W640FB

Block KBytes/

KWords Protection Block

Group (x8)(x16)

08/4

Protection Group

000000h-001FFFh(1) 000000h–000FFFh(1)

18/4 002000h-003FFFh001000h–001FFFh

28/4 004000h-005FFFh002000h–002FFFh

38/4 006000h-007FFFh003000h–003FFFh

48/4 008000h-009FFFh004000h–004FFFh

58/4 00A000h-00BFFFh005000h–005FFFh

68/4 00C000h-00DFFFh006000h–006FFFh

78/4 00E000h-00FFFFh007000h–007FFFh

864/32010000h-01FFFFh008000h–00FFFFh

964/32020000h-02FFFFh010000h–017FFFh

1064/32030000h-03FFFFh018000h–01FFFFh

1164/32

Protection Group

040000h-04FFFFh020000h–027FFFh

1264/32050000h-05FFFFh028000h–02FFFFh

1364/32060000h-06FFFFh030000h–037FFFh

1464/32070000h-07FFFFh038000h–03FFFFh

1564/32

Protection Group

080000h-08FFFFh040000h–047FFFh

1664/32090000h-09FFFFh048000h–04FFFFh

1764/320A0000h-0AFFFFh050000h–057FFFh

1864/320B0000h-0BFFFFh058000h–05FFFFh

1964/32

Protection Group

0C0000h-0CFFFFh060000h–067FFFh

2064/320D0000h-0DFFFFh068000h–06FFFFh

2164/320E0000h-0EFFFFh070000h–077FFFh

2264/320F0000h-0FFFFFh078000h–07FFFFh

2364/32

Protection Group

100000h-10FFFFh080000h–087FFFh

2464/32110000h-11FFFFh088000h–08FFFFh

2564/32120000h-12FFFFh090000h–097FFFh

2664/32130000h-13FFFFh098000h–09FFFFh

2764/32

Protection Group

140000h-14FFFFh0A0000h–0A7FFFh

2864/32150000h-15FFFFh0A8000h–0AFFFFh

2964/32160000h-16FFFFh0B0000h–0B7FFFh

3064/32170000h-17FFFFh0B8000h–0BFFFFh

M29W640FT, M29W640FB 9 Part Numbering

53/72

3164/32

Protection Group

180000h-18FFFFh0C0000h–0C7FFFh

3264/32190000h-19FFFFh0C8000h–0CFFFFh

3364/321A0000h-1AFFFFh0D0000h–0D7FFFh

3464/321B0000h-1BFFFFh0D8000h–0DFFFFh

3564/32

Protection Group

1C0000h-1CFFFFh0E0000h–0E7FFFh

3664/321D0000h-1DFFFFh0E8000h–0EFFFFh

3764/321E0000h-1EFFFFh0F0000h–0F7FFFh

3864/321F0000h-1FFFFFh0F8000h–0FFFFFh

3964/32

Protection Group

200000h-20FFFFh100000h–107FFFh

4064/32210000h-21FFFFh108000h–10FFFFh

4164/32220000h-22FFFFh110000h–117FFFh

4264/32230000h-23FFFFh118000h–11FFFFh

4364/32

Protection Group

240000h-24FFFFh120000h–127FFFh

4464/32250000h-25FFFFh128000h–12FFFFh

4564/32260000h-26FFFFh130000h–137FFFh

4664/32270000h-27FFFFh138000h–13FFFFh

4764/32

Protection Group

280000h-28FFFFh140000h–147FFFh

4864/32290000h-29FFFFh148000h–14FFFFh

4964/322A0000h-2AFFFFh150000h–157FFFh

5064/322B0000h-2BFFFFh158000h–15FFFFh

5164/32

Protection Group

2C0000h-2CFFFFh160000h–167FFFh

5264/322D0000h-2DFFFFh168000h–16FFFFh

5364/322E0000h-2EFFFFh170000h–177FFFh

5464/322F0000h-2FFFFFh178000h–17FFFFh

5564/32

Protection Group

300000h-30FFFFh180000h–187FFFh

5664/32310000h-31FFFFh188000h–18FFFFh

5764/32320000h-32FFFFh190000h–197FFFh

5864/32330000h-33FFFFh198000h–19FFFFh

5964/32

Protection Group

340000h-34FFFFh1A0000h–1A7FFFh

6064/32350000h-35FFFFh1A8000h–1AFFFFh

6164/32360000h-36FFFFh1B0000h–1B7FFFh

6264/32370000h-37FFFFh1B8000h–1BFFFFh

Block KBytes/

KWords Protection Block

Group (x8)(x16)

9 Part Numbering M29W640FT, M29W640FB

54/72

6364/32

Protection Group

380000h-38FFFFh1C0000h–1C7FFFh

6464/32390000h-39FFFFh1C8000h–1CFFFFh

6564/323A0000h-3AFFFFh1D0000h–1D7FFFh

6664/323B0000h-3BFFFFh1D8000h–1DFFFFh

6764/32

Protection Group

3C0000h-3CFFFFh1E0000h–1E7FFFh

6864/323D0000h-3DFFFFh1E8000h–1EFFFFh

6964/323E0000h-3EFFFFh1F0000h–1F7FFFh

7064/323F0000h-3FFFFFh1F8000h–1FFFFFh

7164/32

Protection Group

400000h-40FFFFh200000h–207FFFh

7264/32410000h-41FFFFh208000h–20FFFFh

7364/32420000h-42FFFFh210000h–217FFFh

7464/32430000h-43FFFFh218000h–21FFFFh

7564/32

Protection Group

440000h-44FFFFh220000h–227FFFh

7664/32450000h-45FFFFh228000h–22FFFFh

7764/32460000h-46FFFFh230000h–237FFFh

7864/32470000h-47FFFFh238000h–23FFFFh

7964/32

Protection Group

480000h-48FFFFh240000h–247FFFh

8064/32490000h-49FFFFh248000h–24FFFFh

8164/324A0000h-4AFFFFh250000h–257FFFh

8264/324B0000h-4BFFFFh258000h–25FFFFh

8364/32

Protection Group

4C0000h-4CFFFFh260000h–267FFFh

8464/324D0000h-4DFFFFh268000h–26FFFFh

8564/324E0000h-4EFFFFh270000h–277FFFh

8664/324F0000h-4FFFFFh278000h–27FFFFh

8764/32

Protection Group

500000h-50FFFFh280000h–287FFFh

8864/32510000h-51FFFFh288000h–28FFFFh

8964/32520000h-52FFFFh290000h–297FFFh

9064/32530000h-53FFFFh298000h–29FFFFh

9164/32

Protection Group

540000h-54FFFFh2A0000h–2A7FFFh

9264/32550000h-55FFFFh2A8000h–2AFFFFh

9364/32560000h-56FFFFh2B0000h–2B7FFFh

9464/32570000h-57FFFFh2B8000h–2BFFFFh

Block KBytes/

KWords Protection Block

Group (x8)(x16)

M29W640FT, M29W640FB 9 Part Numbering

55/72

9564/32

Protection Group

580000h-58FFFFh2C0000h–2C7FFFh

9664/32590000h-59FFFFh2C8000h–2CFFFFh

9764/325A0000h-5AFFFFh2D0000h–2D7FFFh

9864/325B0000h-5BFFFFh2D8000h–2DFFFFh

9964/32

Protection Group

5C0000h-5CFFFFh2E0000h–2E7FFFh

10064/325D0000h-5DFFFFh2E8000h–2EFFFFh

10164/325E0000h-5EFFFFh2F0000h–2F7FFFh

10264/325F0000h-5FFFFFh2F8000h–2FFFFFh

10364/32

Protection Group

600000h-60FFFFh300000h–307FFFh

10464/32610000h-61FFFFh308000h–30FFFFh

10564/32620000h-62FFFFh310000h–317FFFh

10664/32630000h-63FFFFh318000h–31FFFFh

10764/32

Protection Group

640000h-64FFFFh320000h–327FFFh

10864/32650000h-65FFFFh328000h–32FFFFh

10964/32660000h-66FFFFh330000h–337FFFh

11064/32670000h-67FFFFh338000h–33FFFFh

11164/32

Protection Group

680000h-68FFFFh340000h–347FFFh

11264/32690000h-69FFFFh348000h–34FFFFh

11364/326A0000h-6AFFFFh350000h–357FFFh

11464/326B0000h-6BFFFFh358000h–35FFFFh

11564/32

Protection Group

6C0000h-6CFFFFh360000h–367FFFh

11664/326D0000h-6DFFFFh368000h–36FFFFh

11764/326E0000h-6EFFFFh370000h–377FFFh

11864/326F0000h-6FFFFFh378000h–37FFFFh

11964/32

Protection Group

700000h-70FFFFh380000h–387FFFh

12064/32710000h-71FFFFh388000h–38FFFFh

12164/32720000h-72FFFFh390000h–397FFFh

12264/32730000h-73FFFFh398000h–39FFFFh

12364/32

Protection Group

740000h-74FFFFh3A0000h–3A7FFFh

12464/32750000h-75FFFFh3A8000h–3AFFFFh

12564/32760000h-76FFFFh3B0000h–3B7FFFh

12664/32770000h-77FFFFh3B8000h–3BFFFFh

Block KBytes/

KWords Protection Block

Group (x8)(x16)

9 Part Numbering M29W640FT, M29W640FB

56/72

12764/32

Protection Group

780000h-78FFFFh3C0000h–3C7FFFh

12864/32790000h-79FFFFh3C8000h–3CFFFFh

12964/327A0000h-7AFFFFh3D0000h–3D7FFFh

13064/327B0000h-7BFFFFh3D8000h–3DFFFFh

13164/32

Protection Group

7C0000h-7CFFFFh3E0000h–3E7FFFh

13264/327D0000h-7DFFFFh3E8000h–3EFFFFh

13364/327E0000h-7EFFFFh3F0000h–3F7FFFh

13464/327F0000h-7FFFFFh3F8000h–3FFFFFh

1.Used as the Extended Block Addresses in Extended Block mode.

Block KBytes/

KWords Protection Block

Group (x8)(x16)

M29W640FT, M29W640FB 9 Part Numbering

57/72

Appendix B Common Flash Interface (CFI)

The Common Flash Interface is a JEDEC approved, standardized data structure that can be

read from the Flash memory device. It allows a system software to query the device to

determine various electrical and timing parameters, density information and functions

supported by the memory. The system can interface easily with the device, enabling the

software to upgrade itself when necessary.

When the CFI Query Command is issued the device enters CFI Query mode and the data

structure is read from the memory. Tables 22,23,24,25,26, and 27, show the addresses used

to retrieve the data.

The CFI data structure also contains a security area where a 64 bit unique security number is

written (see Table27: Security Code Area). This area can be accessed only in Read mode by

the final user. It is impossible to change the security number after it has been written by ST.

Table 22.Query Structure Overview

1.Query data are always presented on the lowest order data outputs.

Address Sub-section NameDescription

x16x8

10h20hCFI Query Identification StringCommand set ID and algorithm data offset

1Bh36hSystem Interface InformationDevice timing & voltage information

27h4EhDevice Geometry DefinitionFlash device layout

40h80h Primary Algorithm-specific Extended

Query table Additional information specific to the Primary

Algorithm (optional)

61hC2hSecurity Code Area64 bit unique device number

9 Part Numbering M29W640FT, M29W640FB

58/72

Table 23.CFI Query Identification String

1.Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

Table 24.CFI Query System Interface Information

Address DataDescriptionValue

x16x8

10h20h0051h “Q”

11h22h0052hQuery Unique ASCII String "QRY""R"

12h24h0059h "Y"

13h26h0002h Primary Algorithm Command Set and Control Interface ID code 16 bit

ID code defining a specific algorithm AMD

Compatible

14h28h0000h

15h2Ah0040h Address for Primary Algorithm extended Query table (see Table26)P = 40h

16h2Ch0000h

17h2Eh0000h Alternate Vendor Command Set and Control Interface ID Code

second vendor - specified algorithm supported NA

18h30h0000h

19h32h0000h Address for Alternate Algorithm extended Query tableNA

1Ah34h0000h

Address DataDescriptionValue

x16x8

1Bh36h0027h VCC Logic Supply Minimum Program/Erase voltage

bit 7 to 4BCD value in volts

bit 3 to 0BCD value in 100 mV 2.7V

1Ch38h0036h VCC Logic Supply Maximum Program/Erase voltage

bit 7 to 4BCD value in volts

bit 3 to 0BCD value in 100 mV 3.6V

1Dh3Ah00B5h VPP [Programming] Supply Minimum Program/Erase voltage

bit 7 to 4HEX value in volts

bit 3 to 0BCD value in 100 mV 11.5V

1Eh3Ch00C5h VPP [Programming] Supply Maximum Program/Erase voltage

bit 7 to 4HEX value in volts

bit 3 to 0BCD value in 100 mV 12.5V

1Fh3Eh0004h Typical timeout per single byte/word program = 2n µs16µs

20h40h0000h Typical timeout for minimum size write buffer program = 2n µsNA

21h42h000Ah Typical timeout per individual Block Erase = 2n ms 1s

22h44h0000h Typical timeout for full Chip Erase = 2n ms NA

23h46h0004h Maximum timeout for byte/word program = 2n times typical 256 µs

24h48h0000h Maximum timeout for write buffer program = 2n times typical NA

M29W640FT, M29W640FB 9 Part Numbering

59/72

25h4Ah0003h Maximum timeout per individual Block Erase = 2n times typical 8s

26h4Ch0000h Maximum timeout for Chip Erase = 2n times typical NA

Address DataDescriptionValue

x16x8

9 Part Numbering M29W640FT, M29W640FB

60/72

Table 25. Device Geometry Definition

1.For Bottom Boot devices, Erase Block Region 1 is located from address 000000h to 007FFFh and Erase Block Region 2

from address 008000h to 3FFFFFh.

For Top Boot devices, Erase Block Region 1 is located from address 000000h to 3F7FFFh and Erase Block Region 2 from

address 3F8000h to 3FFFFFh.

Address DataDescriptionValue

x16x8

27h4Eh0017h Device Size = 2n in number of bytes 8 MByte

28h

29h 50h

52h 0002h

0000h Flash Device Interface Code description x8, x16

Async.

2Ah

2Bh 54h

56h 0004h

0000h Maximum number of bytes in multi-byte program or page = 2n16 Bytes

2Ch58h0002h Number of Erase Block Regions. It specifies the number of

regions containing contiguous Erase Blocks of the same size. 2

2Dh

2Eh 5Ah

5Ch 0007h

0000h Region 1 Information

Number of Erase Blocks of identical size = 0007h+1 8

2Fh

30h 5Eh

60h 0020h

0000h Region 1 Information

Block size in Region 1 = 0020h * 256 byte 8Kbyte

31h

32h 62h

64h 007Eh

0000h Region 2 Information

Number of Erase Blocks of identical size= 007Eh+1 127

33h

34h 66h

68h 0000h

0001h Region 2 Information

Block size in Region 2 = 0100h * 256 byte 64Kbyte

35h

36h

37h

38h

6Ah

6Ch

6Eh

70h

0000h

Region 3 Information

Number of Erase Blocks of identical size=007Fh+1

Region 3 Information

Block size in Region 3 = 0000h * 256 byte

39h

3Ah

3Bh

3Ch

72h

74h

76h

78h

0000h

Region 4 Information

Number of Erase Blocks of Identical size=007Fh+1

Region 4 Information

Block size in Region 4 = 0000h * 256 byte

M29W640FT, M29W640FB 9 Part Numbering

61/72

Table 26.Primary Algorithm-Specific Extended Query Table

Address DataDescriptionValue

x16x8

40h80h0050h

Primary Algorithm extended Query table unique ASCII string “PRI”

"P"

41h82h0052h "R"

42h84h0049h "I"

43h86h0031hMajor version number, ASCII “1”

44h88h0033hMinor version number, ASCII"3"

45h8Ah0000h Address Sensitive Unlock (bits 1 to 0)

00h = required, 01h = not required

Silicon Revision Number (bits 7 to 2) Yes

46h8Ch0002h Erase Suspend

00h = not supported, 01h = Read only, 02 = Read and Write 2

47h8Eh0004h Block Protection

00h = not supported, x = number of blocks per protection group 4

48h90h0001h Temporary Block Unprotect

00h = not supported, 01h = supported Yes

49h92h0004h Block Protect /Unprotect

04 = M29W640F 04

4Ah94h0000hSimultaneous Operations, 00h = not supportedNo

4Bh96h0000hBurst Mode: 00h = not supported, 01h = supportedNo

4Ch98h0001h Page Mode: 00h = not supported, 01h = 4 page word, 02h = 8

page word Yes

4Dh9Ah00B5h VPP Supply Minimum Program/Erase voltage

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV 11.5V

4Eh9Ch00C5h VPP Supply Maximum Program/Erase voltage

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV 12.5V

4Fh9Eh0002h

0003h

Top/Bottom Boot Block Flag

02h = Bottom Boot device

03h = Top Boot device

–

50hA0h0001h Program Suspend

00h = Not Supported

01h = Supported Supported

9 Part Numbering M29W640FT, M29W640FB

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Table 27.Security Code Area

Address DataDescription

x16x8

61hC3h, C2hXXXX

64 bit: unique device number

62hC5h, C4hXXXX

63hC7h, C6hXXXX

64hC9h, C8hXXXX

M29W640FT, M29W640FB 9 Part Numbering

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Appendix C Extended Memory Block

The M29W640F has an extra block, the Extended Block, that can be accessed using a

dedicated command.

This Extended Block is 128 Words in x16 mode and 256 Bytes in x8 mode. It is used as a

security block to provide a permanent security identification number) or to store additional

information.

The Extended Block is either Factory Locked or Customer Lockable, its status is indicated by bit

DQ7. This bit is permanently set to either ‘1’ or ‘0’ at the factory and cannot be changed. When

set to ‘1’, it indicates that the device is factory locked and the Extended Block is protected.

When set to ‘0’, it indicates that the device is customer lockable and the Extended Block is

unprotected. Bit DQ7 being permanently locked to either ‘1’ or ‘0’ is another security feature

which ensures that a customer lockable device cannot be used instead of a factory locked one.

Bit DQ7 is the most significant bit in the Extended Block Verify Code and a specific procedure

must be followed to read it. See “Extended Memory Block Verify Code” in Table3: Bus

Operations, BYTE = VIL and Table4: Bus Operations, BYTE = VIH, for details of how to read bit

DQ7.

The Extended Block can only be accessed when the device is in Extended Block mode. For

details of how the Extended Block mode is entered and exited, refer to the Section4.3.1: Enter

Extended Block command and Section4.3.2: Exit Extended Block command, and to Table5

and Table6: Commands, 8-bit mode, BYTE = VIL.

C.1 Factory Locked Extended Block

In devices where the Extended Block is factory locked, the Security Identification Number is

written to the Extended Block address space (see Table28: Extended Block Address and Data)

in the factory. The DQ7 bit is set to ‘1’ and the Extended Block cannot be unprotected.

C.2 Customer Lockable Extended Block

A device where the Extended Block is customer lockable is delivered with the DQ7 bit set to ‘0’

and the Extended Block unprotected. It is up to the customer to program and protect the

Extended Block but care must be taken because the protection of the Extended Block is not

reversible.

There are two ways of protecting the Extended Block:

Issue the Enter Extended Block command to place the device in Extended Block mode,

then use the In-System Technique with RP either at VIH or at VID (refer to Appendix D,

SectionD.2: In-System Technique and to the corresponding flowcharts, Figure18 and

Figure19, for a detailed explanation of the technique).

Issue the Enter Extended Block command to place the device in Extended Block mode,

then use the Programmer Technique (refer to Appendix D,SectionD.1: Programmer

Technique and to the corresponding flowcharts, Figure16 and Figure17, for a detailed

explanation of the technique).

Once the Extended Block is programmed and protected, the Exit Extended Block command

must be issued to exit the Extended Block mode and return the device to Read mode.

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Table 28.Extended Block Address and Data

Address Data

x8x16Factory LockedCustomer Lockable

000000h-00020Fh000000h-00000FhSecurity Identification Number Determined by Customer

000021h-0000FFh000010h-00007FhUnavailable

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Appendix D Block Protection

Block protection can be used to prevent any operation from modifying the data stored in the

memory. The blocks are protected in groups, refer to Appendix A: Block addresses,Table20

and Table21 for details of the Protection Groups. Once protected, Program and Erase

operations within the protected group fail to change the data.

There are three techniques that can be used to control Block Protection, these are the

Programmer technique, the In-System technique and Temporary Unprotection. Temporary

Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP; this is described

in the Signal Descriptions section.

D.1 Programmer Technique

The Programmer technique uses high (VID) voltage levels on some of the bus pins. These

cannot be achieved using a standard microprocessor bus, therefore the technique is

recommended only for use in Programming Equipment.

To protect a group of blocks follow the flowchart in Figure16: Programmer Equipment Group

Protect Flowchart. To unprotect the whole chip it is necessary to protect all of the groups first,

then all groups can be unprotected at the same time. To unprotect the chip follow Figure17:

Programmer Equipment Chip Unprotect Flowchart.Table29: Programmer Technique Bus

Operations, BYTE = VIH or VIL, gives a summary of each operation.

The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is

specified, it is followed as closely as possible. Do not abort the procedure before reaching the

end. Chip Unprotect can take several seconds and a user message should be provided to show

that the operation is progressing.

D.2 In-System Technique

The In-System technique requires a high voltage level on the Reset/Blocks Temporary

Unprotect pin, RP(1). This can be achieved without violating the maximum ratings of the

components on the microprocessor bus, therefore this technique is suitable for use after the

memory has been fitted to the system.

To protect a group of blocks follow the flowchart in Figure18: In-System Equipment Group

Protect Flowchart. To unprotect the whole chip it is necessary to protect all of the groups first,

then all the groups can be unprotected at the same time. To unprotect the chip follow Figure19:

In-System Equipment Chip Unprotect Flowchart.

The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is

specified, it is followed as closely as possible. Do not allow the microprocessor to service

interrupts that will upset the timing and do not abort the procedure before reaching the end.

Chip Unprotect can take several seconds and a user message should be provided to show that

the operation is progressing.

Note:RP can be either at VIH or at VID when using the In-System Technique to protect the Extended

Block.

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Table 29.Programmer Technique Bus Operations, BYTE = VIH or VIL

OperationEGW Address Inputs

A0-A21 Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

Block (Group)

Protect(1)

1.Block Protection Groups are shown in Appendix A, Tables 20 and 21.

VIL VID VIL Pulse A9 = VID, A12-A21= BlockAddress

Others=X X

Chip Unprotect VID VID VIL Pulse A9 = VID, A12=V

IH, A15=V

Others=X X

Block (Group)

Protection Verify VIL VIL VIH

A0, A2, A3 = VIL, A1=V

IH, A6=V

IL,

A9 = VID, A12-A21= BlockAddress

Others=X

Pass=XX01h

Retry = XX00h

Block (Group)

Unprotection Verify VIL VIL VIH

A0, A2, A3 = VIL, A1=V

IH, A6=V

IH,

A9 = VID, A12-A21= BlockAddress

Others=X

Retry=XX01h

Pass = XX00h

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Figure 16.Programmer Equipment Group Protect Flowchart

1.Block Protection Groups are shown in Appendix A, Tables 20 and 21.

ADDRESS = GROUP ADDRESS

AI11555

G, A9 = VID,

E = VIL

n = 0

Wait 4µs

Wait 100µs

W = VIL

W = VIH

E, G = VIH,

A0, A2, A3 = VIL, A1 =VIH,

A6 =VIL, A9 = VID, Others = X

A9 = VIH

E, G = VIH

++n

= 25

START

FAIL

PASS

YES

DATA

01hYES

W = VIH

E = VIL

Wait 4µs

G = VIL

Wait 60ns

Read DATA

Verify Protect Set-upEnd

A9 = VIH

E, G = VIH

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Figure 17.Programmer Equipment Chip Unprotect Flowchart

1.Block Protection Groups are shown in Appendix A, Tables 20 and 21.

PROTECT ALL GROUPS

AI11556

A6, A12, A15 = VIH(1)

E, G, A9 = VID

DATA

W = VIH

E, G = VIH

ADDRESS = CURRENT GROUP ADDRESS

A0, A2, A3 = VIL, A1 =VIH,

A6 =VIL, A9 = VID, Others = X

Wait 10ms

00h

INCREMENT

CURRENT GROUP

n = 0

CURRENT GROUP = 0

Wait 4µs

W = VIL

++n

= 1000

START

YES

YESNO

NO LAST

GROUP

YES

E = VIL

Wait 4µs

G = VIL

Wait 60ns

Read DATA

FAIL PASS

Verify Unprotect Set-upEnd

A9 = VIH

E, G = VIH A9 = VIH

E, G = VIH

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Figure 18.In-System Equipment Group Protect Flowchart

2.Block Protection Groups are shown in Appendix A, Tables 20 and 21.

3.RP can be either at VIH or at VID when using the In-System Technique to protect the Extended Block.

AI11563

WRITE 60h

ADDRESS = GROUP ADDRESS

A0, A2, A3, A6 = VIL, A1 = VIH

n = 0

Wait 100µs

WRITE 40h

ADDRESS = GROUP ADDRESS

A0, A2, A3, A6 = VIL, A1 = VIH

RP = VIH ++n

= 25

START

FAIL

PASS

YES

DATA

01hYES

RP = VIH

Wait 4µs

Verify Protect Set-upEnd

READ DATA

ADDRESS = GROUP ADDRESS

A0, A2, A3, A6 = VIL, A1 = VIH

RP = VID

ISSUE READ/RESET

COMMAND

ISSUE READ/RESET

COMMAND

WRITE 60h

ADDRESS = GROUP ADDRESS

A0, A2, A3, A6 = VIL, A1 = VIH

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Figure 19.In-System Equipment Chip Unprotect Flowchart

1.Block Protection Groups are shown in Appendix A, Tables 20 and 21.

AI11564

WRITE 60h

ANY ADDRESS WITH

A0, A2, A3 = VIL, A1, A6 = VIH

n = 0

CURRENT GROUP = 0

Wait 10ms

WRITE 40h

ADDRESS = CURRENT GROUP ADDRESS

A0, A2, A3 = VIL, A1, A6 = VIH

RP = VIH

++n

= 1000

START

FAIL PASS

YES

DATA

00h

YESNO

RP = VIH

Wait 4µs

READ DATA

ADDRESS = CURRENT GROUP ADDRESS

A0, A2, A3 = VIL, A1, A6 = VIH

RP = VID

ISSUE READ/RESET

COMMAND

ISSUE READ/RESET

COMMAND

PROTECT ALL GROUPS

INCREMENT

CURRENT GROUP

LAST

GROUP

YES

WRITE 60h

ANY ADDRESS WITH

A0, A2, A3, A6 = VIL, A1 = VIH

M29W640FT, M29W640FB 10 Revision History

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10 Revision History

Table 30.Document Revision History

DateVersionRevision Details

01-Mar-20050.1First Issue.

17-May-20050.2 Asynchronous Page mode added.

70ns speed class added.

07-Oct-20051.0

Device codes modified.

TFBGA63 replaced by TFBGA48 6x8 package. ECOPACK text updated

Page size changed to 4 Word.

90ns speed class removed.

Quadruple Word/Octuple Byte Program command added.

Table3: Bus Operations, BYTE = VIL and Table4: Bus Operations, BYTE = VIH: A0-

A21 addresses for reading the Device Code, the Manufacturer Code, the Extended

Memory Block Verify Code, and the Block Protection Status, have been updated.

Appendix D: Block Protection:Table29: Programmer Technique Bus Operations, BYTE

= VIH or VIL: A0-A21 addresses updated for Block Protection/Unprotection Verify using

the Programmer technique.

02-Dec-20052

Datasheet status changed to “Full Datasheet”.

60ns speed class added.

Program Suspend and Resume added.

Section2.8: VPP/Write Protect (VPP/WP) and Section4.2: Fast Program commands.

Section4: Command Interface restructured.

Table28: Extended Block Address and Data updated.

15-Dec-20053Double Byte Program commands added in Section4: Command Interface.

Table3: Bus Operations, BYTE = VIL and Table4: Bus Operations, BYTE = VIH.: A6

changed from VIH to VIL for Read Block Protection Status operation.

M29W640FT, M29W640FB

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