©
2007 Microchip Technology Inc. DS22070A-page 1
MCP1824/MCP1824S
Features
• 300 mA Output Current Capability
• Input Operating Voltage Range: 2.1V to 6.0V
• Adjustable Output Voltage Range: 0.8V to 5.0V
(MCP1824 only)
• Standard Fixed Output Voltages:
- 0.8V, 1.2V, 1.8V, 2.5V, 3.0V, 3.3V, 5.0V
• Other Fixed Output Voltage Options Available
Upon Request
• Low Dropout Voltage: 200 mV Typical at 300 mA
• Typical Output Voltage Tolerance: 0.4%
• Stabl e with 1.0 µF Ceramic Output Capacitor
• Fast Response to Load Transients
• Low Supply Current: 120 µA (typical)
• Low Shutdown Supply Current: 0.1 µA (typical)
(MCP1824 only)
• Fixed Delay on Power Good Output
(MCP1824 only)
• Short Circuit Current Limiting and
Overtemperature Protecti on
• 5-Lead Plastic SOT-223, SOT-23 Package
Options (MCP1824)
• 3-Lead Plastic SOT-223 Package Option
(MCP1824S)
Applications
• High-Speed Driver Chipset Power
• Networking Backplane Cards
• Notebook Computers
• Network Interface Cards
• Palmt op Com pute rs
• 2.5V to 1.XV Regulators
Description
The MCP1824/MCP1824S is a 300 mA Low Dropout
(LDO) linear regulator that provides high current and
low outp ut volt age s. The MCP1 824 comes in a fi xed or
adjustable output voltage version, with an output
voltage range of 0.8V to 5.0V. The 300 mA output
current cap ability , combin ed with the low output voltage
capability, make the MCP1824 a good choice for new
sub-1.8V output voltage LDO applications that have
high curre nt demands . The MCP1824S i s a 3-pin fixed
voltage version.
The MCP1824/MCP1824S is stable using ceramic
output capacitors that inherently provide lower output
noise and reduce the size and cost of the entire
regulator solution. Only 1 µF of output capacitance is
needed to stabilize the LDO.
Using CMOS construction, the quiescent current
consumed by the MCP1824/MCP1824S is typically
less than 120 µA over the entire input voltage range,
making it a ttra cti ve for p ort able co mp uti ng app lic ati on s
that demand high output current. The MCP1824
versions have a Shutdown (SHDN) pin. When shut
down, the quiescent current is reduced to less than
0.1 µA.
On the MCP1824 fixed output versions, the scaled-
down output voltage is internally monitored and a
power good (PWRGD) output is provided when the
output is within 92% of regulation (typical). The
PWRGD delay is internally fixed at 110 µs (typical).
The overtemperature and short circuit current-limiting
provi de additional protection for the LDO during s ystem
fault conditions.
300 mA, Low Voltage, Low Quiescent Current LDO Regulator
MCP1824/MCP1824S
DS22070A-page 2
©
2007 Microchip Technology Inc.
Package Types
MCP1824
12345
6
SOT-223-5
SOT-223 SOT-23
Pin Fixed Adjustable Fixed Adjustable
1SHDN SHDN VIN VIN
2V
IN VIN GND (TAB) GND (TAB)
3 GND (TAB) GND (TAB) SHDN SHDN
4V
OUT VOUT PWR G D ADJ
5 PWRGD ADJ V
OUT VOUT
6 GND (TAB) GND (TAB) — —
123
SOT-223-3
4
MCP1824S
Pin SOT-223
1V
IN
2 GND (TAB)
3V
OUT
4 GND (TAB)
Fixed/Adjustable
SOT-23-5
123
54
©
2007 Microchip Technology Inc. DS22070A-page 3
MCP1824/MCP1824S
Typical Applications
MCP1824 Ad justable Output Vol tage
MCP1824 Fixed Output Voltage
VOUT = 1.8V @ 300 mA
VIN = 2.3V to 2.8V
On
Off
1µF
100 kΩ
4.7 µF
C1C2
R1
SHDN
VIN
GND
VOUT
PWRGD
20 kΩ
R2
VOUT = 1.2 V @ 300 mA
VIN = 2.1V to 2.8V
On
Off
1µF
40 kΩ
4.7 µF
C1C2
R1
SHDN
VIN
GND
VOUT
VADJ
1
1
MCP1824/MCP1824S
DS22070A-page 4
©
2007 Microchip Technology Inc.
Functional Block Diagram - Adjustable Output (MCP1824)
EA +
–
VOUT
PMOS
Rf
Cf
ISNS
Overtemperature
VREF
Comp
92% of VREF
TDELAY
VIN
Driver w/limit
and SHDN
GND
Soft-Start
ADJ/SENSE
Undervoltage
Lock Out
VIN Reference
SHDN
SHDN
SHDN
Sensing
(UVLO)
©
2007 Microchip Technology Inc. DS22070A-page 5
MCP1824/MCP1824S
Functional Block Diagram - Fixed Output (MCP1824S)
EA +
–
VOUT
PMOS
Rf
Cf
ISNS
Overtemperature
VREF
Comp
92% of VREF
TDELAY
VIN
Driver w/limit
and SHDN
GND
Soft-Start
Sense
Undervoltage
Lock Out
VIN Reference
SHDN
SHDN
SHDN
Sensing
(UVLO)
MCP1824/MCP1824S
DS22070A-page 6
©
2007 Microchip Technology Inc.
Functional Block Diagram - Fixed Output (MCP1824)
EA +
–
VOUT
PMOS
Rf
Cf
ISNS
Overtemperature
VREF
Comp
92% of VREF
TDELAY
VIN
Driver w/limit
and SHDN
GND
Soft-Start
Sense
Undervoltage
Lock Out
VIN Reference
SHDN
SHDN
SHDN
Sensing
(UVLO)
PWRGD
©
2007 Microchip Technology Inc. DS22070A-page 7
MCP1824/MCP1824S
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
Input Voltage, VIN.............................................................6.5V
Maximum Voltage on Any Pin... (GND – 0.3V) to (VIN + 0.3)V
Maximum Power Dissipation......... Internally-Limited (Note 6)
Output Short Circuit Duration................................Continuous
Storage temperature ............... .. .. .. .. ..... .... .. .. .-65°C to +150°C
Maximum Junction Temperature, TJ...........................+150°C
Operating Junction Tempe rature, TJ.............-40°C to +125°C
EESD protection on all pins........... ≥ 4kV HBM; ≥ 300V MM
† Notice: Stresses above those listed under “M aximum Rat-
ings” may cause permanent damage to the devic e. This is a
stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied. Expo-
sure to max imum rati ng conditions for extended periods may
affect device reliability.
AC/DC CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX), Note 1, VR = 1.8V for Adjustable Output,
IOUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C.
Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C
Parameters Sym Min Typ Max Units Conditions
Input Operating Voltage VIN 2.1 —6.0 V
Output Voltage Range VOUT 0.8 — 5.0 V
Input Quiescent Current Iq— 120 220 µA IL = 0 mA, VOUT = 0.8V to
5.0V
Input Quiescent Current for
SHDN Mode ISHDN —0.13µA SHDN = GND
Maximum Continuous Output
Current IOUT 300 ——mAV
IN = 2.1V to 6.0V
VR = 0.8V to 5.0V
Line Regulation ΔVOUT/
(VOUT x ΔVIN)— ±0.05 ±0.17 %/V (Note 1) ≤ VIN ≤ 6V
Load Regulation ΔVOUT/VOUT -1.0 ±0.5 1.0 %I
OUT = 1 mA to 300 mA ,
(Note 4)
Output Short Circuit Current IOUT_SC — 720 — mA RLOAD <0.1Ω, Peak Current
Dropout Voltage VDROPOUT — 200 320 mV Note 5, IOUT = 300 mA,
VIN(MIN) =2.1V
Pulsed Applications
Maximum Pu lsed Output
Current IPULSE — 500 — mA VIN = 2.1V to 6.0V
VR = 0.8V to 5.0V,
Duty Cycle ≤ 60%,
Period < 10 ms
Note 1: The minimum VIN must meet two conditions: VIN ≥ 2.1V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX).
2: VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output
voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1.
3: TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the
temperature range. VOUT-LOW is the lowest voltage measured over the temperature range.
4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is
tested over a load range from 1 m A to the maximum specified output current.
5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its
nominal value that was measured with an input voltage of VIN = VOUT(MAX) + VDROPOUT(MAX).
6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction to air. (i.e., T A, TJ, θJA). Exceeding the maximum allowable power
dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained
junction temperatures above 150°C can impact device reliability.
7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the
desired junction temperature. The test time is small enough such that the rise in the junction temperature over the
ambient temperature is not significant.
MCP1824/MCP1824S
DS22070A-page 8
©
2007 Microchip Technology Inc.
Maximum Pulsed Output Duty
Cycle IPULSE_DUTY ——60%V
IN = 2.1V to 6.0V,
VR = 0.8V to 5.0V,
IOUT = 500 mA,
Period < 10 ms
Maximum Pulsed Output Period IPULSE_PERIOD ——10msV
IN = 2.1V to 6.0V
VR = 0.8V to 5.0V,
IOUT = 500 mA
Adjust Pin Characteristics (Adjustable Output Only)
Adjustable Output Voltage
Range VOUT_ADJ 0.8 — 5.5 V
Adjust Pin Reference Voltage VADJ 0.402 0.410 0.418 VV
IN = 2.1V to VIN =6.0V,
IOUT = 1 mA
Adjust Pin Leakage Current IADJ -10 ±0.01 +10 nA VIN = 6.0V, VADJ =0Vto6V
Adjust Temperature Coefficient TCVOUT — 40 — ppm/°C Note 3
Fixed-Output Characteristics (Fixed Outpu t Only)
Voltage Regulation VOUT VR - 2.5% VR ±0.5% VR + 2.5% VNote 2
Power Good Characteristics
PWRGD Input Volt age Operat-
ing Range VPWRGD_VIN 1.0 — 6.0 V TA = +25°C
1.2 —6.0 TA = -40°C to +125°C
For VIN < 2.1V, ISINK = 100 µA
PWRGD Threshold Voltage
(Referenced to VOUT)VPWRGD_TH %VOUT Falling Edge
89 92 95 VOUT < 2.5V Fixed,
VOUT = Adj.
90 92 94 VOUT >= 2.5V Fixed
PWRGD Threshold Hysteresis VPWRGD_HYS 1.0 2.0 3.0 %VOUT
PWRGD Output Voltage Low VPWRGD_L —0.050.4 VI
PWRGD SINK = 1.2 mA,
ADJ = 0V
PWRGD Output Current Sink
Capability IPWRGD 1.2 6.0 — mA VPWRGD = 0.200V
PWRGD Leakage PWRGD_LK —1—nAV
PWRGD = VIN = 6.0V
PWRGD Time Delay TPG — 110 — µs Rising Edge
RPULLUP = 10 kΩ
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX), Note 1, VR = 1.8V for Adjustable Output,
IOUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C.
Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C
Parameters Sym Min Typ Max Units Conditions
Note 1: The minimum VIN must meet two conditions: VIN ≥ 2.1V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX).
2: VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output
voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1.
3: TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemp erature). VOUT-HIGH is the highest voltage measured over the
temperature range. VOUT-LOW is the lowest voltage measured over the temperature range.
4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is
tested over a load range from 1 m A to the maximum specified output current.
5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its
nominal value that was measured with an input voltage of VIN = VOUT(MAX) + VDROPOUT(MAX).
6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction to air. (i.e., TA, TJ, θJA). Exceeding the maximum allowable power
dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained
junction temperatures above 150°C can impact device reliability.
7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the
desired junction temperature. The test time is small enough such that the rise in the junction temperature over the
ambient temperature is not significant.
©
2007 Microchip Technology Inc. DS22070A-page 9
MCP1824/MCP1824S
Detect Threshold to PWRGD
Active Time Delay TVDET-PWRGD — 200 — µs VOUT = VPWRGD_TH + 50 mV
to VPWRGD_TH - 50 mV
Shutdown Input
Logic High Input VSHDN-HIGH 45 ——%V
IN VIN = 2.1V to 6.0V
Logic Low Input VSHDN-LOW ——15 %VIN VIN = 2.1V to 6.0V
SHDN Input Leakage Current SHDNILK -0.1 ±0.001 +0.1 µA VIN =6V, SHDN =VIN,
SHDN = GND
AC Performance
Output Delay From SHDN TOR — 100 — µs SHDN = GND to VIN,
VOUT = GND to 95% VR
Output Noise eN—2.0—µV/√Hz IOUT = 200 mA, f = 1 kHz,
COUT = 10 µF (X7R Ceramic),
VOUT = 2.5V
Power Supply Ripple Rejection
Ratio PSRR — 55 — dB f = 100 Hz,
IOUT = 10 mA,
VINAC = 200 mV pk-pk,
CIN = 0 µ F
Thermal Shutdown Temperature TSD — 150 — °C IOUT = 100 µA, VOUT = 1.8V,
VIN = 2.8V
Thermal Shutdown Hysteresis ΔTSD —10—°CI
OUT = 100 µA, VOUT = 1.8V,
VIN = 2.8V
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX), Note 1, VR = 1.8V for Adjustable Output,
IOUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C.
Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C
Parameters Sym Min Typ Max Units Conditions
Note 1: The minimum VIN must meet two conditions: VIN ≥ 2.1V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX).
2: VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output
voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1.
3: TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the
temperature range. VOUT-LOW is the lowest voltage measured over the temperature range.
4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is
tested over a load range from 1 m A to the maximum specified output current.
5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its
nominal value that was measured with an input voltage of VIN = VOUT(MAX) + VDROPOUT(MAX).
6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction to air. (i.e., T A, TJ, θJA). Exceeding the maximum allowable power
dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained
junction temperatures above 150°C can impact device reliability.
7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the
desired junction temperature. The test time is small enough such that the rise in the junction temperature over the
ambient temperature is not significant.
MCP1824/MCP1824S
DS22070A-page 10
©
2007 Microchip Technology Inc.
TEMPERATURE SPECIFICATIONS
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Operati ng Junction Temperature Range TJ-40 — +125 °C Steady State
Maximum Junction Temper ature TJ— — +150 °C Transient
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 3LD SOT-223 θJA — 62 — °C/W EIA/JEDEC JESD51-751-7
4 Lay er Board
θJC —15—
Thermal Resistance, 5LD SOT-23 θJA — 256 — °C/W EIA/JE DEC JESD51-75 1-7
4 Lay er Board
θJC —81—
Thermal Resistance, 5LD SOT-223 θJA — 62 — °C/W EIA/JE DEC JESD51-751-7
4 Lay er Board
θJC —15—
©
2007 Microchip Technology Inc. DS22070A-page 11
MCP1824/MCP1824S
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA,
Temperature = +25°C, VIN = VOUT + 0.5V, Fixed output, SHDN = 10 kΩ pullup to VIN.
FIGURE 2-1: Quiescent Current vs. Input
Voltage (Adjustable Version).
FIGURE 2-2: Ground Current vs. Load
Current (Adjus table Version).
FIGURE 2-3: Quiescent Current vs.
Junction Temperature (Adjustable Version).
FIGURE 2-4: Line Regulation vs.
Temperature (Adjustable Version).
FIGURE 2-5: Load Regulation vs.
Temperature (Adjustable Version).
FIGURE 2-6: Adjust Pin Voltage vs.
Temperature (Adjustable Version).
Note: The g r ap hs and t ables prov id ed fol low i ng thi s n ote are a statis tic al s umm ar y based on a l im ite d n um ber of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
90
100
110
120
130
140
23456
Input Voltage (V)
Quiescent Current (
μ
A)
130°C
-45°C
25°
C
90°
C
VOUT = 1.2V Adj
IOUT = 0 mA
0°C
100
110
120
130
140
150
160
170
180
0 50 100 150 200 250 300
Load Current (mA)
Ground Current (
μ
A)
VIN=3.3V
VOUT = 1. 2V Adj
VIN=5.0V
VIN=2.5V
90
100
110
120
130
140
150
160
170
-45 -20 5 30 55 80 105 130
Temperature (°C)
Quiescent Current (
μ
A)
VIN=6.0V
VIN=3.0V
VIN=4.0V
VOUT = 0.8V Adj
IOUT = 0 mA
VIN=5.0V
VIN=2.1V
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
-45 -20 5 30 55 80 105 130
Temperature (°C)
Line Regulation (%/V)
VOUT = 1.2V adj
VIN
= 2.1V to 6.0V
IOUT = 1 mA
IOUT=300 mA
IOUT = 50 mA
IOUT=100 mA
IOUT=200 mA
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
-45 -20 5 30 55 80 105 130
Temperature (°C)
Load Regulation (%)
IOUT = 1.0 mA to 30 0 mA
VOUT = 5.0V
VOUT = 3.3V VOUT = 0.8V
VOUT = 1.8V
0.407
0.408
0.409
0.410
0.411
0.412
0.413
-45 -20 5 30 55 80 105 130
Temperature (°C)
Adjust Pin Voltage (V)
VOUT = 1.2V
IOUT = 1.0 mA
VIN = 2.1V
VIN = 6.0V
VIN = 4.0V
MCP1824/MCP1824S
DS22070A-page 12
©
2007 Microchip Technology Inc.
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA,
Temperature = +25°C, VIN = VOUT + 0.5V, Fixed output, SHDN = 10 kΩ pullup to VIN.
FIGURE 2-7: Dropout Voltage vs. Load
Current (Adjus table Version).
FIGURE 2-8: Dropout V oltage vs.
Temperature (Adjustable Version).
FIGURE 2-9: Power Good (PWRGD)
Time Delay vs. Temperature.
FIGURE 2-10: Quiescent Current vs. Input
Voltage.
FIGURE 2-11: Quiescent Current vs. Input
Voltage.
FIGURE 2-12: Ground Current vs. Load
Current.
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0 50 100 150 200 250 300
Load Current (mA)
Dropout Voltage (V)
VOUT = 2.5V Ad j
VOUT = 5.0V Ad j
0.14
0.15
0.16
0.17
0.18
0.19
0.20
0.21
0.22
0.23
0.24
-45 -20 5 30 55 80 105 130
Temperature (°C)
Dropout Voltage (V)
VOUT = 3.3V Adj
VOUT = 5.0V Ad j
VOUT = 2.5V Ad j
IOUT = 300 mA
50
60
70
80
90
100
110
-45 -20 5 30 55 80 105 130
Temperature (°C)
Power Good Time Delay (µS)
VOUT = 0.8V Fixed
IOUT = 0 mA
VIN = 2.1V
VIN = 5.0V
VIN = 3.3V
90
100
110
120
130
140
150
160
23456
Input Voltage (V)
Quiescent Current (
μ
A)
-45°C
+130°C
+90°C
+25°C
VOUT = 0.8V
IOUT = 0 mA
0°C
90
100
110
120
130
140
150
3.0 3.5 4.0 4.5 5.0 5.5 6.0
Input Voltage (V)
Quiescent Curre nt (
μ
A)
VOUT = 2.5V
IOUT = 0 mA
+130°C
-45°C
+25°C
+90°C
+0°C
0
50
100
150
200
250
0 50 100 150 200 250 300
Load Current (mA)
Ground Current (
μ
A)
VIN = 2.1V for V R
=0.8V
VIN = 3.5V for VR
=3.0V
VOUT=0.8V
VOUT=3.0V
©
2007 Microchip Technology Inc. DS22070A-page 13
MCP1824/MCP1824S
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA,
Temperature = +25°C, VIN = VOUT + 0.5V, Fixed output, SHDN = 10 kΩ pullup to VIN.
FIGURE 2-13: Quiescent Current vs.
Temperature.
FIGURE 2-14: ISHDN vs. Temperature.
FIGURE 2-15: Line Regulation vs.
Temperature.
FIGURE 2-16: Line Regulation vs.
Temperature.
FIGURE 2-17: Load Regulation vs.
Temperature.
FIGURE 2-18: Load Regulation vs.
Temperature.
90
95
100
105
110
115
120
125
130
-45 -20 5 30 55 80 105 130
Temperature (°C)
Quiescent Current (
μ
A)
VOUT = 0.8V
VOUT = 2.5V
IOUT = 0 mA
c
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
-45 -20 5 30 55 80 105 130
Temperature (°C)
Ishdn (
μ
A)
VIN = 2.3V
VIN = 3.3V
VR = 0.8V
VIN = 6.0V
0.00
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
-45 -20 5 30 55 80 105 130
Temperature (°C)
Line Regulation (%/V)
VOUT = 0.8V
VIN = 2.1V to 6.0V
IOUT = 100 mA
IOUT = 300 mA
IOUT = 50 mA
IOUT = 200 mA
IOUT = 1 mA
0.010
0.014
0.018
0.022
0.026
0.030
0.034
0.038
0.042
-45-205 305580105130
Temperature (°C)
Line Regulation (%/V)
IOUT = 100 mA
IOUT = 1 mA
IOUT = 50 mA
IOUT = 200 mA IOUT = 300 mA
VR = 2.5V
VIN = 3.0V to 6.0V
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
-45-205 305580105130
Temperature (°C)
Load Regulation (%)
VOUT = 0.8V
IOUT = 1 mA to 300 mA
VIN = 2.1V
VIN
= 4.0V
V
IN
= 5.0V
VIN
= 6.0V
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
-45-205 305580105130
Temperature (°C)
Load Regulation (%)
VOUT = 2.5V
VOUT = 5.0V
IOUT = 1 mA to 300 mA
VOUT = 0.8V
MCP1824/MCP1824S
DS22070A-page 14
©
2007 Microchip Technology Inc.
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µ F Ceramic (X7R), IOUT = 1 mA,
Temperature = +25°C, VIN = VOUT + 0.5V, Fixed output, SHDN = 10 kΩ pullup to VIN.
FIGURE 2-19: Dropout Voltage vs. Load
Current.
FIGURE 2-20: Dropout Voltage vs.
Temperature.
FIGURE 2-21: Short Circuit Current vs.
Input Voltage.
FIGURE 2-22: Output Noise Voltage
Density vs. Frequency.
FIGURE 2-23: Power Supply Ripple
Rejection (PSRR) vs. Frequency (Adj.).
FIGURE 2-24: Power Supply Ripple
Rejection (PSRR) vs. Frequency.
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
0 50 100 150 200 250 300
Load Current (mA)
Dropout Voltage (V)
VOUT = 5.0V
VOUT = 2.5V
0.12
0.14
0.16
0.18
0.20
0.22
0.24
-45 -20 5 30 55 80 105 130
Temperature (°C)
Dropout Voltage (V)
IOUT = 300 mA
VOUT = 2.5V
VOUT = 5.0V
0.00
100.00
200.00
300.00
400.00
500.00
600.00
0123456
Input Voltage (V)
Short Circuit Current (mA)
VOUT = 0.8V
0.010
0.100
1.000
10.000
0.01 0.1 1 10 100 1000
Frequency (kHz)
Noise (mV/√Hz)
VR=0.8 V, VIN=2.1V
VR=3.0 V, VIN=3.8V COUT
μ
CIN
=4.7
μ
F cer
IOUT=200 mA
-80.0
-70.0
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
0.01 0.1 1 10 100 1000
Frequency (kHz)
PSRR (dB)
VR=1.2V Adj
VIN=2.5V
VINAC = 200 mV p-p
CIN=0
μ
F
IOUT=10 mA
-90.0
-80.0
-70.0
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
0.01 0.1 1 10 100 1000
Frequency (kHz)
PSRR (d B)
VR=3.0V (Fixed)
VIN=3.5V
VINAC=200 mV p-p
CIN=0
μ
F
IOUT=10 mA
©
2007 Microchip Technology Inc. DS22070A-page 15
MCP1824/MCP1824S
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µ F Ceramic (X7R), IOUT = 1 mA,
Temperature = +25°C, VIN = VOUT + 0.5V, Fixed output, SHDN = 10 kΩ pullup to VIN.
FIGURE 2-25: Startup from VIN
(Adjustable Version).
FIGURE 2-26: Startup from Shutdown
(Adjustable Version).
FIGURE 2-27: Power Good (PWRGD)
Timing.
FIGURE 2-28: Power Good (PWRGD)
Timing.
FIGURE 2-29: Dynamic Line Response.
FIGURE 2-30: Dynamic Line Response.
MCP1824/MCP1824S
DS22070A-page 16
©
2007 Microchip Technology Inc.
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µ F Ceramic (X7R), IOUT = 1 mA,
Temperature = +25°C, VIN = VOUT + 0.5V, Fixed output, SHDN = 10 kΩ pullup to VIN.
FIGURE 2-31: Dynamic Load Response.
FIGURE 2-32: Dynamic Load Response.
FIGURE 2-33: Power Good Pulldown
Voltage Vs Load.
FIGURE 2-34: Startup Current.
0
100
200
300
400
500
600
700
800
900
0 2 4 6 8 10 12 14 16 18 20
PWRG D Sin k Cu rr e n t (mA)
PWRGD Voltage (m V)
VR = 0.8V
VR = 3.0V
VR = 5.0V
©
2007 Microchip Technology Inc. DS22070A-page 17
MCP1824/MCP1824S
3.0 PIN DESCRIPTION
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Shutdown Control Input (SHDN)
The SHDN input is used to turn t he LDO outpu t voltag e
on and off. When the SHDN input is at a logic-high
level, the LDO output voltage is enabled. When the
SHDN input is pulled to a logic-low level, the LDO
output voltage is disabled. When the SHDN input is
pulled low, the PWRGD output also goes low and the
LDO enters a low quiescent current shutdown state
where the typical quiescent current is 0.1 µA.
3.2 Input Voltage Supply (VIN)
Connect the unregulated or regulated input voltage
source to VIN. If the input voltage source is located
several inc he s a way from the L DO, o r the i npu t so urc e
is a battery, it is recommended that an input capacitor
be used. A typical input capacitance value of 1 µF to
10 µF should be sufficient for most applications. The
type of capacitor used can be ceramic, tantalum, or
aluminum electrolytic. The low ESR characteristics of
the ceramic capacitor will yield better noise and PSRR
performance at high frequency.
3.3 Ground (GND)
For the optimal Noise and Power Supply Rejection
Ratio (PSRR) performance, the GND pin of the LDO
should be tied to an electrically quiet circuit ground.
This w ill hel p the LDO pow e r sup pl y rej ec tio n ratio and
noise performance. The ground pin of the LDO only
conducts the ground current of the LDO, so a heavy
trace is not required. For applications that have
switching or noisy inputs, tie the GND pin to the return
of the output capacitor. Ground planes help lower
induct a nce an d volt age spik es cau sed b y fast t rans ient
load currents and are recommended for applications
that are subjected to fast load transients.
3.4 Regulated Output Voltage (V OUT)
The VOUT pin is the regulated output voltage of the
LDO. A minimum output capacitance of 1.0 µF is
required for LDO st ability. The MCP1 824/MCP1824 S is
stable with ceramic, tantalum, and aluminum-
electrolytic capacitors. See Section 4.3 “Output
Capacitor” for output capacitor selection guidance.
3.5 Power Good Output (PWRGD)
For fixed applications, the PWRGD output is an open-
drain output used to indicate when the LDO output
voltage is within 92% (typically) of its nominal
regulation value. The PWRGD threshold has a typical
hystere sis v alue of 2%. The PWRGD output i s dela yed
by 110 µs (typical) from the time the LDO output is
within 92% + 3% (maximum hysteresis) of the
regulated output value on power-up. This delay time is
internal ly fix ed.
3.6 Output Voltage Adjust Input (ADJ)
For adjustable applications, the output voltage is
connected to the ADJ input through a resistor divider
that sets the output voltage regulation value. This
provides the users the capability to set the output
volt age to an y va lue th ey de sire within the 0.8V to 5.0V
range of the devic e.
3.7 Exposed Pad (EP)
The SOT-223 package has an exposed metal pad on
the bottom of the package. The exposed metal pad
gives the device better thermal characteristics by
providing a good thermal path to either the PCB or
heat sink to rem ove hea t from the d evice. Th e expose d
pad of the package is at ground potential.
SOT-223 SOT-23
Name Description
3-Pin
Fixed 5-Pin
Fixed 5-Pin
Adj 5-Pin
Fixed 5-Pin
Adj
—1 1 3 3 SHDN Shutdown Control Input (active-low)
12211V
IN Input Voltage Supply
23322GNDGround
34455V
OUT Regulated Output Voltage
—5—4—PWRGD Power Good Output
——5—4 ADJ Output Voltage Adjust/Sense Input
Exposed
Pad Exposed
Pad Exposed
Pad —— EP Exposed Pad of the Package (ground potential)
MCP1824/MCP1824S
DS22070A-page 18
©
2007 Microchip Technology Inc.
4.0 DEVICE OVERVIEW
The MCP18 24/MCP1824 S is a 30 0 mA output curren t,
Low Dropout (LDO) voltage regulator. The low dropout
voltage of 200 mV typical at 300 mA of current makes
it ideal for battery-powered applications. The input
voltage range is 2.1V to 6.0V. Unlike other high output
current LDOs, the MCP1824/MCP1824S only draws a
maximum of 220 µA of quiescent current. The
MCP1824 adds a shutdown control input pin and a
power goo d outp ut pin . The two output volta ge opt ion s
are fixed or adjustable. The adjustable option is
available on the MCP1824 devices . The adjust able out-
put voltage is set using two external resistors.
4.1 LDO Output Voltage
The MCP1824 LDO is available with either a fixed
output voltage or an adjustable output voltage. The
output voltage range is 0.8V to 5.0V for either version.
The MCP1824S LDO is available as a fixed voltage
device.
4.1.1 ADJUST INPUT
The adjustable version of the MCP1824 uses the ADJ
pin to get the output voltage feedback for output voltage
regulation. This allows the user to set the output volt-
age of the devi ce with tw o ext ernal res istors . The nom -
inal voltage for ADJ is 0.41V.
Figure 4-1 shows the adjustable version of the
MCP1824. Resistors R1 and R2 form the resistor
divider network necessary to set the output voltage.
With this configuration, Equation 4-1 represents the
equation for setting VOUT.
EQUATION 4-1: CALCULATING VOUT
FIGURE 4-1: Typical Adj us table Ou tput
Voltage Application Circuit.
The allowable resistance value range for resistor R2 is
from 10 kΩ to 200 kΩ. Solving Equation 4-1 for R1
yields Equation 4-2.
EQUATION 4-2: CALCULATING ADJ PIN
RESISTOR VALUES
4.2 Output Current and Current
Limiting
The MCP1824/MCP1824S LDO is tested and ensured
to supp ly a mi nimu m of 300 mA of outp ut cu rren t. The
MCP1824/M CP1824S has no min imum outpu t load, s o
the output load current can go to 0 mA and the LDO will
continue to regulate the output voltage to within
tolerance.
The MC P1824/ MCP1824 S also inco rporat es an o utput
current limit. If the output voltage falls below 0.7V due
to an ov erlo ad cond ition ( usual ly rep resents a short ed
load c on d it ion ) , the ou t put cu rr e nt is lim it e d t o 72 0 mA
(typical). If the overload condition is a soft overload, the
MCP1824/MCP1824S will supply higher load currents
of up to 900 mA. The MCP1824/MCP1824S should not
be operated in this condition continuously as it may
result in failure of the device. However, this does allow
for device usage in applications that have higher
pulsed load currents having an average output current
value of 300 mA or less.
Output overload conditions may also result in an over-
temperature shutdown of the device. If the junction
temperature rises above 150°C (typical), the LDO will
shut down the output voltage. See Section 4.8 “Over-
temperature Protection” for more information on
overtemperature shutdown.
VOUT VADJ R1R2
+
R2
------------------
⎝⎠
⎛⎞
=
Where:
VOUT = LDO Output Voltage
VADJ =ADJ Pin Voltage
(typically 0.41V)
SHDN
GND
ADJ
21µF
VOUT
4.7 µF
VIN
On
Off R1
R2
C1
C2
MCP1824-ADJ
134 5
R1R2VOUT
VADJ
------------- 1–
⎝⎠
⎛⎞
=
Where:
VOUT = L D O Ou tput Voltage
VADJ =ADJ Pin Voltage
(typically 0.41V)
©
2007 Microchip Technology Inc. DS22070A-page 19
MCP1824/MCP1824S
4.3 Output Capacitor
The MCP1824/MCP1824S requires a minimum output
capacitance of 1 µF for output voltage stability . Ceramic
capacitors are recommended because of their size,
cost, and environmental robustness qualities.
Aluminum-electrolytic and tantalum capacitors can be
used o n the L DO output as wel l. The Equiva lent Se ries
Resistance (ESR) of the electrolytic output capacitor
must be no greater than 1 ohm. The output capacitor
should be located as close to the LDO output as is
practical. Ceramic materials X7R and X5R have low
temperature coefficients and are well within the
acceptable ESR range required. A typical 1 µF X7R
0805 capaci tor has an ESR of 50 milli -ohms.
Larger LDO output capacitors can be used with the
MCP1824/MCP1824S to improve dynamic
performance and power supply ripple rejection
performance. A maximum of 22 µF is recommended.
Aluminum-electrolytic capacitors are not recom-
mended for low temperature applications of < -25°C.
4.4 I nput Capacitor
Low input source impedance is necessary for the LDO
output to operate properly. When operating from
batteries, or in applications with long lead length
(> 10 inches) between the input source and the LDO,
some input capacitance is recommended. A minimum
of 1.0 µF to 4.7 µF is recommended for most
applications.
For applications that have output step load
requirem ents, th e inp ut ca p ac itance of the LDO is ve ry
important. The input capacitance provides the LDO
with a good local low-impedance source to pull the
transient currents from, in order to respond quickly to
the output load step. For good step response
performance, the input capacitor should be of
equi valent (or hi gher) value t han the output capacit or.
The capacitor shoul d b e pl ac ed as cl os e to the in put of
the LDO as is practical. Larger input capacitors will also
help reduce any hi gh -freq uen cy noi se on the i np ut an d
output of the LDO and reduce the effects of any
inductance that exists between the input source
voltage and the input capacitance of the LDO.
4.5 Power Good Output (PWRGD)
The PWRGD output is used to indicate when the output
voltage of the LDO is within 92% (typical value, see
Section 1.0 “Electrical Characteristics” for Minimu m
and Maximum specifications) of its nominal regulation
value.
As the output voltage of the LDO rises, the PWRGD
output will be held low until the output voltage has
exceeded the power good thresh old plus the hysteresis
value. Once this threshold has been exceeded, the
power good time delay is started (shown as TPG in the
Electrical Characteristics table). The power good time
delay is fixed at 110 µs (typical). After the time delay
period, the PWRGD output will go high, indicating that
the outpu t v oltage is stabl e a nd wi thin regul ati on l im it s .
If the output voltage of the LDO falls below the power
good threshold, the power good output will transition
low. The power good circui try has a 200 µs delay whe n
detecting a falling output voltage, which helps to
increase noise immunity of the power good output and
avoid false triggering of the power good output during
fast output transients. See Figure 4-2 for power good
timing cha r ac teri sti cs .
When the LDO is put into Shutdown mode using the
SHDN input, the power good output is pulled low
immediately, indicating that the output voltage will be
out of regulation. The timing diagram for the power
good out put when usi ng the shut down inpu t is shown i n
Figure 4-3.
The power good output is an open-drain output that can
be pulled up to a ny vol t ag e that is e qua l to or le ss tha n
the LDO input voltage. This output is capable of sinking
1.2 mA minimum (VPWRGD < 0.4V maximum).
FIGURE 4-2: Power Good Timing.
FIGURE 4-3: Power Good Timing from
Shutdown.
TPG
TVDET_PWRGD
VPWRGD_TH
VOUT
PWRGD
VOL
VOH
VIN
SHDN
VOUT
30 µs 70 µs
TOR
PWRGD
TPG
MCP1824/MCP1824S
DS22070A-page 20
©
2007 Microchip Technology Inc.
4.6 Shut down Input (SHDN)
The SHDN inp ut is an ac ti ve-l ow inp ut s ig nal th at turn s
the LDO on and off. The SHDN threshold is a
percentage of the input voltage. The typical value of
this shutdown threshold is 30% of VIN, with minimum
and maximum limits over the entire operating
temperature range of 45% and 15%, respectively.
The SHDN input will ignore low-going pulses (pulses
meant to shut down the LDO) that are up to 400 ns in
pulse w idth. If the shut down input is pul led low for more
than 400 ns, the LDO will enter Shutdown mode. This
small bit of filtering helps to reject any system noise
spikes on the shutdown input signal.
On the rising edge of the SHDN input, the shutdown
circuitry has a 30 µs delay before allowing the LDO
output to turn on. This delay helps to reject any false
turn-on s ignals or noise on t he SHDN i nput signal. Af ter
the 30 µs delay, the LDO output enters its soft-start
period as it rises from 0V to its final regulation value. If
the SHDN input signal is pulled low during the 30 µs
delay period, the timer will be reset and the delay time
will start over again on the next rising edge of the
SHDN input. The total time from the SHDN input going
high (turn-on) to the LDO output being in regulation is
typica lly 10 0 µs. See Figure 4-4 for a t iming diagra m of
the SHDN input.
FIGURE 4-4: Shutdown Input Timing
Diagram.
4.7 Dropout V olt age and Undervoltage
Lockout
Dropout voltage is defined as the input-to-output
voltage differential at which the output voltage drops
2% below the nominal value that was measured with a
VR + 0.5V differential applied. The MCP1824/
MCP1824S LDO has a very low dropout voltage
specification of 210 mV (typical) at 300 mA of output
current. Se e Section 1.0 “Electrical Charac teristics”
for maximum dropout voltage specifications.
The MCP1824/MCP1824S LDO operates across an
input voltage range of 2.1V to 6.0V and incorporates
input Undervoltage Lockout (UVLO) circui try that keep s
the LDO output voltage off until the input voltage
reaches a minimum of 2.00V (typical) on the rising
edge of the input v olt age. As the inpu t volt a ge fall s, the
LDO output will remain on until the input voltage level
reaches 1.82V (typical).
Since the MCP1824/MCP1824S LDO undervoltage
lockou t activates a t 1.82V as the i nput volta ge is fall ing,
the dropout voltage specification does not apply for
output voltages that are les s tha n 1.8V.
For high-c urre nt ap pli ca tio ns , vo lt age drop s ac ros s the
PCB traces must be taken into account. The trace
resistances can cause significant voltage drops
between the input voltage source and the LDO. For
applications with input voltages near 2.1V, these PCB
trace voltage drops can sometimes lower the input
voltage enough to trigger a shutdown due to
undervol tage lo ckout.
4.8 Overtemperature Protection
The MCP1824/MCP1824S LDO has temperature-
sensing circuitry to prevent the junction temperature
from exceeding approximately 150°C. If the LDO
junction temperature does reach 150°C, the LDO
output will be turned off until the junction temperature
cools to approximately 140°C, at which point the LDO
output will automatically resume normal operation. If
the internal power dissipation continues to be
excessive, the device will again shut off. The junction
temperature of the die is a function of power
dissipation, ambient temperature and p ackage thermal
resistance. See Section 5.0 “Application Circuits/
Issues” for more information on LDO power
dissipation and junction temperature.
SHDN
VOUT
30 µs 70 µs
TOR 400 ns (typ)
©
2007 Microchip Technology Inc. DS22070A-page 21
MCP1824/MCP1824S
5.0 APPLICATION CIRCUITS/
ISSUES
5.1 Typical Applicat ion
The MCP1 824/MCP182 4S is used for ap plications th at
require high LDO output current and a power good
output.
FIGURE 5-1: Typical App li ca tio n Circui t.
5.1.1 APPLICATION CONDITIONS
5.2 Power Calculation s
5.2.1 POW ER D ISS IPATIO N
The internal power dissipation within the MCP1824/
MCP1824S is a function of input voltage, output
voltage, output current and quiescent current.
Equation 5-1 can be used to calculate the internal
power dissipatio n for the LDO.
EQUATION 5- 1:
In addition to the LDO pass element power dissipation,
there is power dissipation within the MCP1824/
MCP1824S as a result of quiescent or ground current.
The power dissipation as a result of the ground current
can be calculated using the following equation:
EQUATION 5-2:
The total power dissipated within the MCP1824/
MCP1824S is the sum of the power dissipated in the
LDO p ass devi ce and th e P(IGND) term. Because of the
CMOS cons tructi on, the ty pical IGND for the MCP182 4/
MCP1824S is 120 µ A. Operating at a maximum VIN of
3.465 V results in a power d issipat ion of 0.12 milli-W att s
for a 2.5V output. For most applications, this is small
compared to the LDO pass device power dissipation
and can be neglected.
The maximum continuous operating junction
temperature specified for the MCP1824/MCP1824S is
+125°C. To estimate the internal junction temperature
of the MCP1824/MCP1824S, the total internal power
dissipation is multiplied by the thermal resistance from
junction to ambient (RθJA) of the device. The thermal
resistance from junction to ambient for the SOT-223-5
package is estimated at 62° C/W.
EQUATION 5-3:
Package Type = SOT-223-5
Input Voltage Range = 3.3V ± 5%
VIN maximum = 3.465V
VIN minimum = 3.135V
VDROPOUT (max) = 0.350V
VOUT (typical) = 2. 5V
IOUT = 300 mA maximum
PDISS (typical) = 0.240W
Temperature Rise = 14.88°C
10 µF
VOUT = 2.5V @ 300 mA
R1C2
10 kΩ
PWRGD
SHDN
GND
2
4.7 µF
On
Off
C1
MCP1824-2.5
134 5
3.3V VIN
PLDO VIN MAX)()
VOUT MIN()
–()IOUT MAX)()
×=
Where:
PLDO = LDO Pass device internal
power dissipation
VIN(MAX) = Maximum input voltage
VOUT(MIN) = LDO minimum outp ut voltage
PIGND()
VIN MAX()
IVIN
×=
Where:
PI(GND = Power dissipation due to the
quiescent current of the LDO
VIN(MAX) = Maximum input voltage
IVIN = Current flow ing in the V IN pin
with no LDO output current
(LDO quiescent current)
TJMAX()
PTOTAL RθJA
×TAMAX
+=
TJ(MAX) = Maximum continuous junction
temperature
PTOTAL = Total device power dissipation
RθJA = Thermal resistance from junction to
ambient
TAMAX = Maximum ambient temperature
MCP1824/MCP1824S
DS22070A-page 22
©
2007 Microchip Technology Inc.
The maximum power dissipation capability for a
package can be calculated given the junction-to-
ambient thermal resistance and the maximum ambient
temperature for the application. Equation 5-4 can be
used to determine the package maximum internal
power dissipation.
EQUATION 5- 4:
EQUATION 5- 5:
EQUATION 5- 6:
5.3 Typical Applicat ion
Internal power dissipation, junction temperature rise,
junction temperature, and maximum power dissipation
is calculated in the following example. The power
dissipation as a result of ground current is small
enough to be neglected.
5.3.1 POWER DISSIPATION EXAMPLE
5.3.1.1 Device Ju nct ion Temp eratur e Ris e
The internal junction temperature rise is a function of
internal power dissipation and the thermal resistance
from junction-to-ambient for the application. The
thermal resistance from junction-to-ambient (RθJA) is
derived from EIA/JEDEC standards for measuring
thermal resistance. The EIA/JEDEC specification is
JESD51. The standard describes the test method and
board specifications for measuring the thermal
resist ance fro m junct ion to ambi ent. The a ctual the rmal
resistance for a particular application can vary
depending on many factors such as copper area and
thickness. Refer to AN792, “A Method to Determine
How Much Power a SOT23 Can Dissipate in an
Application” (DS00792), for more information regarding
this subject.
PDMAX()
TJMAX()
TAMAX()
–()
RθJA
---------------------------------------------------
=
PD(MAX) = Maximum device power dissipation
TJ(MAX) = maximum continuous junction
temperature
TA(MAX) = maximum ambient temperature
RθJA = Thermal resistance from junction-to-
ambient
TJRISE()
PDMAX()
RθJA
×=
TJ(RISE) = Rise in device junction temperature
over the ambient temperature
PD(MAX) = Maximum devic e pow er dis si p a tion
RθJA = Thermal resistance from junction-to-
ambient
TJTJRISE()
TA
+=
TJ= Junction temperature
TJ(RISE) = Rise in device junction temperature
over the ambient temperature
TA= Ambient temperature
Package
Package Type = SOT-223-5
Input Voltage
VIN =3.3V ± 5%
LDO Output Voltage and Current
VOUT =2.5V
IOUT =300mA
Maximum Ambient Temperature
TA(MAX) =60°C
Internal Power Dissipation
PLDO(MAX) =(V
IN(MAX) – VOUT(MIN)) x IOUT(MAX)
PLDO = ((3.3V x 1.05) – (2.5V x 0.975))
x 300 mA
PLDO = 0.308 Watts
TJ(RISE) =P
TOTAL x RθJA
TJRISE = 0.308 W x 62° C/W
TJRISE =19.1°C
©
2007 Microchip Technology Inc. DS22070A-page 23
MCP1824/MCP1824S
5.3.1.2 Junction Temperature Estimate
To estimate the internal junction temperature, the
calculated temperature rise is added to the ambient or
offset temperature. For this example, the worst-case
junction temperature is estimated below:
5.3.1.3 Maximum Package Power
Dissipation at 60°C Ambient
Temperature
From this table, yo u can see the difference in maxi mum
allowable power dissipation between the SOT-223-5
pac kag e and the SOT-23-5 packag e.
TJ =T
JRISE + TA(MAX)
TJ = 19.1°C + 60.0°C
TJ =79.1°C
SOT-223-5 (62°C/W RθJA):
PD(MAX) = (125°C – 60°C) / 62°C/W
PD(MAX) = 1.048W
SOT-23-5 (256°C/Watt RθJA):
PD(MAX) = (125°C – 60°C)/ 256°C/W
PD(MAX) = 0.254W
MCP1824/MCP1824S
DS22070A-page 24
©
2007 Microchip Technology Inc.
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Al phanume ric trac ea bil ity code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb- free. The Pb-free JEDEC designa tor ( )
can be found on the outer packaging for this package.
Note: In the event the fu ll Mic rochip part nu mber ca nnot be m arked o n one lin e, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
3-Lead SOT-223 (MCP1824S)
XXXXXXX
XXXYYWW
NNN
Example:
1824S08
EDB0710
256
Part Number Marking
Code
MCP1824ST-0802E/DB 1824S08
MCP1824ST-1202E/DB 1824S12
MCP1824ST-1802E/DB 1824S18
MCP1824ST-2502E/DB 1824S25
MCP1824ST-3002E/DB 1824S30
MCP1824ST-3302E/DB 1824S33
MCP1824ST-5002E/DB 1824S50
©
2007 Microchip Technology Inc. DS22070A-page 25
MCP1824/MCP1824S
Package Marking Information (Continued)
5-Lead SOT-223 (MCP1824)
XXXXXXX
XXXYYWW
NNN
Example:
1824082
EDC0710
256
5-Lead SOT-23 Example:
1
XXNN
1
UL25
Part Number Marking
Code
MCP1824T-0802E/DC 1824082
MCP1824T-1202E/DC 1824122
MCP1824T-1802E/DC 1824182
MCP1824T-2502E/DC 1824252
MCP1824T-3002E/DC 1824302
MCP1824T-3302E/DC 1824332
MCP1824T-5002E/DC 1824502
MCP1824T-ADJE/DC 1824ADJ
Part Number Marking
Code
MCP1824T-0802E/OT ULNN
MCP1824T-1202E/OT UMNN
MCP1824T-1802E/OT UPNN
MCP1824T-2502E/OT UQNN
MCP1824T-3002E/OT URNN
MCP1824T-3302E/OT USNN
MCP1824T-5002E/OT UTNN
MCP1824T-ADJE/OT UKNN
MCP1824/MCP1824S
DS22070A-page 26
©
2007 Microchip Technology Inc.
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0ROGHG3DFNDJH+HLJKW $   
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2YHUDOO/HQJWK '   
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2007 Microchip Technology Inc. DS22070A-page 27
MCP1824/MCP1824S
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2YHUDOO+HLJKW $ ± ± 
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0ROGHG3DFNDJH+HLJKW $   
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0ROGHG3DFNDJH:LGWK (   
2YHUDOO/HQJWK '   
/HDG7KLFNQHVV F   
/HDG:LGWK E   
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DS22070A-page 28
©
2007 Microchip Technology Inc.
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©
2007 Microchip Technology Inc. DS22070A-page 29
MCP1824/MCP1824S
APPENDIX A: REVISION HISTORY
Revision A (November 2007)
• Original Release of this Document.
MCP1824/MCP1824S
DS22070A-page 30
©
2007 Microchip Technology Inc.
NOTES:
©
2007 Microchip Technology Inc. DS22070A-page 31
MCP1824/MCP1824S
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP1824 : 30 0 mA Low Dropou t Regul a tor
MCP1824 T: 30 0 mA Low Dro pou t Regul a tor
Tape and Reel
MCP1824 S : 300 m A Low Dro pou t Reg ula tor
MCP1824 S T: 30 0 mA Low Dro pou t Regulator
Tape and Reel
Output Voltage *: 08 = 0.8V “Standard”
12 = 1.2V “Standard”
18 = 1.8V “Standard”
25 = 2.5V “Standard”
30 = 3.0V “Standard”
33 = 3.3V “Standard”
50 = 5.0V “Standard”
ADJ = Adjustable Output Voltage ** (MCP1824 Only)
*Contact factory for other output voltage options
** When ADJ is used, the “extra feature code” and
“toler ance” columns do not apply. Refer to examples.
Extra Feature Code : 0 = Fixed
Tolerance: 2 = 2.5% (Standard)
Temperature: E = -40°C to +125°C
Package Type: DB = Plastic Small Transistor Outline, SOT- 223, 3-lead
DC = Plastic Small Transistor Outline, SOT-223, 5-lead
OT = Plastic Small T ransistor Outline, SOT-23, 5-lead
Note: ADJ (Adjustable) only available in 5-lead version.
PART NO. XXX
Output Feature
Code
Device Voltage
X
Tolerance
X/
Temp.
XX
Package
Examples:
a) MCP1824-0802E/XX: 0.8V LDO Regulator
b) MCP1824-1002E/XX: 1.0V LDO Regulator
c) MCP1824-1202E/XX: 1.2V LDO Regulator
d) MCP1824-1802E/XX: 1.8V LDO Regulator
e) MCP1824-2502E/XX: 2.5V LDO Regulator
f) MCP1824-3002E/XX: 3.0V LDO Regulator
g) MCP1824-3302E/XX: 3.3V LDO Regulator
h) MCP1824-5002E/XX: 5.0V LDO Regulator
i) MCP1824-ADJE/XX: ADJ LDO Regulator
a) MCP1824S-0802E/XX:0.8V LDO Regulat or
b) MCP1824S-1002E/XX:1.0V LDO Regulat or
c) MCP1824S-1202E/X X:1.2V LDO Regulator
d) MCP1824S-1802E/XX:1.8V LDO Regulat or
e) MCP1824S-2502E/XX:2.5V LDO Regulat or
f) MCP1824S-2502E/XX:3.0V LDO Regulator
g) MCP1824S-3302E/XX:3.3V LDO Regulat or
h) MCP1824S-5002E/XX:5.0V LDO Regulat or
XX = DB for 3LD SOT-223 package
= DC for 5LD SOT-223 package
= OT for 5LD SOT-23 package
MCP1824/MCP1824S
DS22070A-page 32
©
2007 Microchip Technology Inc.
NOTES:
©
2007 Microchip Technology Inc. DS22070A-page 33
Information contained in this publication regarding device
applications a nd t he lik e is provided only f or your con ve nience
and may be su perseded by u pda t es . It is y our responsibili ty to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
PICmicro, PICST ART, PRO MA TE, rfPIC and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Linear Active Thermistor, Migratable
Memory, M XDEV, MXLAB, SEEVAL, SmartSensor and The
Embedded Control Solutions Company are registered
trademarks of Microchip Technology Incorporated in the
U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,
WiperLock and ZENA are trademarks of Microchip
Technolo gy Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporat ed, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that it s family of products is one of the most secure families of it s kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’ s code protection f eature may be a violati on of t he Digit al Millennium Copyright Act. If such act s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, micro peripherals, nonvolat ile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS22070A-page 34
©
2007 Microchip Technology Inc.
AMERICAS
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Tel: 480-792-7200
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Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhage n
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-14 4-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08 -91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
WORLDWIDE SALES AND SERVICE
10/05/07