CY2213ZC-1T - Cypress Semiconductor

High-Frequency Programmable PEC

Clock Generat

CY221

Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600

Document #: 38-07263 Rev. *E Revised May 23, 2003

1CY2213

Features Benefits

• Jitter peak-peak (TYPICAL) = 35 ps High-accuracy clock generation

• LVPECL output One pair of differential ou tput drivers

• Default Select option Phase-locked loop (PLL) multiplier select

• Serially-configurable multiply ratios Eight-bit feedback counter and six-bit reference counter for high accuracy

• Output edge-rate control Minimize electromagnetic interference (EMI)

• 16-pin TSSOP Industry-standard, low-cost package saves on board space

• High frequency 125- to 400-MHz (-1) or to 500-MHz (-2) extended output range for high-speed

applications

• 3.3V operation Enables application compatibility

Block Diagram

CLKB

CLK

SER CLK

XIN

XOUT

PLL

Xtal

Oscillator

CLK

VDD

SER DATA

VSS

CLKB

VSS

VDD

XIN

VSS

VDDX

SER CLK

VDD

XOUT

VSSX

SER DATA

16-pin TSSOP

Pin Configuration

CY2213

CY221

Document #: 38-07263 Rev. *E Page 2 of 10

CY2213 Two-Wire Serial Interface

Introduction

The CY2 213 has a two-w ire seri al inte rfac e de si gne d for da t a

transfe r operat ions, and is used for programm ing the P and Q

values for frequency generation. Sclk is the serial clock line

contr olle d by the mast er devic e. Sdata is a serial bidirectional

dat a line. The CY221 3 is a slave dev ice and can eit her read or

write information on the dataline upon request from the master

device.

Figure 1 shows the basic bus connections between master

and slave device. The buses are shared by a number of

devices and are pulled high by a pull-up resistor.

Serial Interface Specificat ions

Figure 2 shows the basic transmission specification. To begin

and end a transmission, the master device generates a start

signal (S) and a stop signal (P). Start (S) is defined as

switching the Sdata from HIGH to LOW while the Sclk is at

HIGH. Si milarly, stop (P) is d efined as switchi ng the Sdata from

LOW to HIGH while holding th e Sclk HIGH. Between these two

signals, data on Sdata is synchronous with the clock on the Sclk.

Data is allowed to change only at LOW period of clock, and

must be stable at the HIGH period of clock. To acknowledge,

drive the Sdata LOW before the Sclk rising edge and hold it

LOW until the Sclk falling edge.

Serial Interfa ce For ma t

Each slave carries an addres s. The data transfer is initiated by

a start signal (S). Each transfer segment is 1 byte in length.

The sl ave addre ss and the read/wri te bit are first sent from t he

master device after the start signal. The addressed slave

device must acknowledge (Ack) the master device. Depending

on the Read/Write bit, the master device will either write data

into (log ic 0) or rea d data (l ogic 1) from the slav e device. Eac h

time a byte of data is successfully transferred, the receiving

device must acknowledge. At the end of the transfer, the

master device will generate a stop signal (P).

Serial Interfa ce Transfer Format

Figure 2 shows the serial interface transfer format used with

the CY2213. T wo dummy bytes must be transferred before the

first dat a by te. The CY221 3 has only three by tes of lat ches to

store information, an d the third byte of dat a is res erv ed. Ex tra

data will be ignored.

Pin Description

Pin Name Pin Number Pin Description

VDDX 13.3V Power Supply for Crystal Driver

VSSX 2Ground for Crystal Driver

XOUT 3Reference Crystal Feedback

XIN 4Reference Crystal Input

VDD 53.3 V Power Supply (all VDD pins must be tied directly on board)

OE 6Output Enable, 0 = output disable, 1 = output enable (no internal pull-up)

VSS 7Ground

SER CLK 8Serial Interfa ce C lock

SER DATA 9Serial Interfa ce D ata

VDD 10 3.3V Power Supply (all VDD pins must be tied directly on board)

VSS 11 Ground

CLKB 12 LVPECL Output Clock (complement)

CLK 13 LVPECL Output Clock

VSS 14 Ground

VDD 15 3.3V Power Supply (all VDD pins must be tied directly on board)

S16 PLL Multiplier Select Input, Pull-up Resistor Internal

Frequency Table

S M (PLL Multiplier) Example Input Crystal Frequency CLK,CLKB

0 x16 25 MHz 400 MHz

31.25 MHz 500 MH z

1 x8 15.625 MHz 125 MHz

CY221

Document #: 38-07263 Rev. *E Page 3 of 10

To program the CY2213 usin g the two-wire serial i nterface, set

the SELPQ bit HIGH. The default setting of this bit is LOW . The

P and Q values are determined by the following formulas:

Pfinal = (P7..0 + 3) * 2

Qfinal = Q5..0 + 2.

If the QCNTBYP b it is set HIGH, then Qfinal defaults to a value

of 1. The default setting of this bit is LOW.

If the SELPQ bit is set LOW, the PLL multipliers will be set

using the values in the Select Function Table.

CyberClocks™ has been developed to generate P and Q

values for stable PLL operation. This software is downloadable

from www.cypress.com.

Figure 1. Device Connections

Figure 2. Serial Interface Specifications

Figure 3. CY2213 Transfer Format

Seria l Int erface Address for the CY2213

A6 A5 A4 A3 A2 A1 A0 R/W

11001010

Serial Interface Programming for the CY2213

b7 b6 b5 b4 b3 b2 b1 b0

Data0 QCNTBYP SELPQ Q<5> Q<4> Q<3> Q<2> Q<1> Q<0>

Data1 P<7> P<6> P<5> P<4> P<3> P<2> P<1> P<0>

Data2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

Sclk

Sdata

Sclk_C

Sclk_in

Sdata_C

Sdata_in

M a ste r Device

Sclk_in

Sdata_C

Sdata_in

Slave D evice

VDD

Fig. 2 S eria l Interfa ce Sp ecifi catio ns

St a rt (S ) St o p (P )

Sclk

data

valid data Acknowledge

Ack

1 bit8 bits

Data 1 P

Slave Address AckSDummy Byte 0

R/W Dummy Byte 1 Ack

1 bit 1 bit

Ack

1 bit7 bits 8 bits1 bit

Data 0 Ack

1 bit8 bits1 bit8 bits

CY221

Document #: 38-07263 Rev. *E Page 4 of 10

PLL Frequency = Reference x P/Q = Output

Absolute Maximum Conditions

The following table reflects stress ratings only, and functional

operation at the maximums are not guaranteed.

Crystal Requirements

Requi rement s to use pa rallel mod e fundamen tal xt al. Extern al

capacitors are required in the crystal oscillator circuit. Please

refer to the application note entitled Crystal Oscillator Topics

for details.

DC Electrical Spec ifica t ions

AC Electrical Specifications

Reference

PLL

VCO

Output

Figure 4. PLL Block Diagram

Parameter Description Min. Max. Unit

VDD,ABS Max. voltage on VDD, or VDDX with respect to ground –0 .5 4.0 V

VI, ABS Max. voltage on any pin with respect to ground –0.5 VDD+0.5 V

Parameter Description Min. Max. Unit

XFFrequency 10 31.25 MHz

Parameter Description Min. Max. Unit

VDD Supply voltage 3.00 3.60 V

TAAmbient o perating t emperature 0 70 °C

VIL Input signal low voltage at pin S 0.35 VDD

VIH Input signal high voltage at pin S 0.65 VDD

RPUP Internal pull-up resistance 10 100 kΩ

tPU Power-up time for all VDDs to reach minimum specified voltage

(power ramps must be monotonic) 0.05 500 ms

Parameter Description Min. Max. Unit

fIN Input frequency with driven reference 1 133 MHz

fXTAL,IN Input frequency with crystal input 10 31.25 MHz

CIN,CMOS Input capacitance at S pin[1] 10 pF

3.3V DC Device Characteristics (Driving load, Figure 5)

Parameter Description Min. Typ. Max. Unit

VOH Output high voltage, referenced to VDD –1.02 –0.95 –0.88 V

VOL Output low voltage, referenced to VDD –1.81 –1.70 –1.62 V

3.3V DC Device Characteristics (Driving load, Figure 6)

Parameter Description Min. Typ. Max. Unit

VOH Output high voltage 1.1 1.2 1.3 V

VOL Output low voltage 0 0 0 V

Note:

1. Capacitance measured at freq. = 1 MHz, DC Bias = 0.9V, and VAC < 100 mV.

CY221

Document #: 38-07263 Rev. *E Page 5 of 10

State Transition Characteristics

Specifies the maximum settling time of the CLK and CLKB

outputs from device power-up. For VDD and VDDX any

sequences are allowed to power-up and power-down the

CY22 13.

From To Transition Latency Description

VDD/VDDX On CLK/CLKB Normal 3 ms Time from VDD/VDDX is applied and settled to CLK/CLKB outputs settled.

AC Device Characteristics

Parameter Description Min. Max. Unit

tCYCLE Clock cycle time 2.50 (400 MHz) 8.00 (125 MHz) ns

tJCRMS Cycle-to-cycle RMS jitter 0.25% % tCYCLE

At 125-MHz frequency 20 ps

At 400-/500-MHz frequency 6.25/5 ps

tJCPK Cycle-to-cycle jitter (pk-pk) 1.75% % tCYCLE

At 125-MHz frequency 140 ps

At 200-MHz frequency, XF = 25 MHz 55 ps

At 400-/500-MHz frequency 43.75/35 ps

tJPRMS Period jitter RMS 0.25% % tCYCLE

At 125-MHz frequency 20 ps

At 400-/500-MHz frequency 6.25/5 ps

tJPPK Period jitter (pk-pk) 2.0% % tCYCLE

At 125-MHz frequency 160 ps

At 200-MHz frequency, XF = 25 MHz 65 ps

At 400-/500-MHz frequency 50/40 ps

tJLT Long term RMS Jitter (P < 20) 1.75% % tCYCLE

At 125-MHz frequency 140 ps

At 400-/500-MHz frequency 43.75/35 ps

tJLT Lo ng term RMS Jitter (20 < P < 40) 2.5% % tCYCLE

At 125-MHz frequency 200 ps

At 400-/500-MHz frequency 62.5/50 ps

tJLT Long-term RMS Jitter (40 < P < 60) 3.5% % tCYCLE

At 125-MHz frequency 280 ps

At 400-/500-MHz frequency 87.5/70 ps

Phase Noise Phase Noise at 10 kHz (x8 mode) @ 125 MHz –107 –92 dBc

DC Long-term average output duty cycle 45 55 %

tDC,ERR Cycle-cycle duty cycle error at x8 with

15.625-MHz input 70 ps

tCR, tCF Output rise and fall times (measured at 20% –

80% of VOHmin and VOLmax)100 400 ps

BWLOOP PLL Loop Bandwidth 50 kHz (–3 dB) 8 MHz (–20 dB)

CY221

Document #: 38-07263 Rev. *E Page 6 of 10

Functional Specifications

Crystal Input

The CY2213 receives its reference from an external crystal.

Pin XIN is the reference crystal input, and pin XOUT is the

refere nce cryst al feedbac k. The para meters for the crys tal are

given on page 5 of this data sheet. The oscillator circuit

requires external capacitors. Please refer to the application

note entitled Crystal Oscillator Topics for details.

Select Input

There is only one select input, pin S. This pin selects the

frequency multiplier in the PLL, and is a standard LVCMOS

input. The S pin has an internal pull -up res is tor. The multiplier

selection is given on page 2 of this data sheet.

PECL Clock Output Driver

Figure 5 and Figure 6 sh ow the clock output driver.

An alternative termination scheme can be used to drive a

standard PECL fanout buffer

82Ω

PECL

Differential

Driver

82Ω

130Ω130Ω

130Ω

130Ω50Ω

50Ω

VDD

Measurement Point

Figure 5. Output Driving Load (-1)

PECL

Differential

Driver

62Ω45Ω

45Ω

62Ω45Ω

45Ω

Measurement Point

Figure 6. Output Driving Load (-2)

135Ω

PECL

Differential

Driver

135Ω

79Ω79Ω

79Ω

79Ω50Ω

50Ω

VDD

Measurement Point

Figure 7. Output Driving Load(-3)

CY221

Document #: 38-07263 Rev. *E Page 7 of 10

The PECL differential driver is designed for low-voltage,

high-fre quency ope ration. It sig nificantl y reduces the tran sient

switching noise and power dissipation when compared to

conve ntional CMOS d rivers. Th e nominal v alue of the ch annel

impedance is 50Ω. The pull-up and pull-down resistors provide

matching channel termination. The combination of the differ-

ential driver and the output network determines the voltage

swing on the channel. The output clock is specified at the

measurement point indicated in Figure 5 and Figure 6.

Signal Waveforms

A physical signal that appears at the pins of the device is

deemed valid or invalid depending on its voltage and timing

relations with other signals. This section defines the voltage

and timing waveforms for the input and output pins of the

CY2213. The Device Characteristics tables list the specifica-

tions for the device parameters that are defined here.

Input and Output voltage waveforms are defined as shown in

Figure 8. Rise and fall ti me s are defin ed as the 20% and 80%

measurement points of VOHmin – VOLmax.

The device paramete rs are d efined i n Table 1. Figure 9 sho ws

the de fin iti on o f lon g-term duty c yc le , wh ich is simply th e CLK

waveform high-time divided by the cycle time (defined at the

crossing point). Long-term duty cycle is the average over

many (> 10,000) cycles. DC is defined as the output clock

long-term duty cycle.

Jitter

This section defines the specifications that relate to timing

uncertainty (or jitter) of the input and output waveforms.

Figure 10 shows the definition of period jitter with respect to

the f alling edge of the CLK signal. Peri od jitter is th e differenc e

between the minimum and maximum cycle times over many

cycles (typically 12800 cycles at 400 MHz). Equal require-

ments apply for rising edges of the CLK signal. tJP is defined

as the output peri od jitt er.

Figure 11 shows the definition of cycle-to-cycle jitter with

respect to the falling edge of the CLK signal. Cycle-to-cycle

jitt er is the di ffere nce bet ween cyc le time s of adj acent cycles

over ma ny cyc les ( typ ical ly 1280 0 cyc les at 400 MHz). Equal

requirements apply for rising edges of the CLK signal. tJC is

defined as the clock output cycle-to-cycle jitter.

Table 1. Definition of Device Parameters

Parameter Definition

VOH, VOL Clock output high and low voltages

VIH, VIL VDD LVC M OS input high and low voltages

tCR, tCF Clock output rise and fall times

tCR

tCF

V(t)

VOHmin

80%

20% VOLmax

Figure 8. Voltage Waveforms

tPW+

tCYCLE

CLK

CLKB

DC = tPW+/tCYCLE

Figure 9. Duty CycleJitter

CY221

Document #: 38-07263 Rev. *E Page 8 of 10

Figure 12 shows the definition of cycle-to-cycle duty cycle

error. Cycle-to-cycle duty cycle error is defined as the

difference between high-times of adjacent cycles over many

cycles (typically 12800 cycles at 400 MHz). Equal require-

ments ap ply to t he lo w-t imes . t DC,ERR is defined as the clock

output cycle-to-cycle duty cycle error.

Figure 13 shows the definition of long-term jitter error.

Long-term jitter is defined as the accumulated timing error over

many c y cl es (typ ic ally 12800 cycles at 400 MHz ) . It ap pli es to

both rising and falling edges. tJLT is defin ed as t he lo ng-ter m

jitter.

tCYCLE

tJP = tCYCLE,max – tCYCLE, min. over many cycles

CLK

CLKB

Figure 10. Period Jitt er

tCYCLE,i

tJC = tCYLCE,i – tCYCLE,i+1 over many consecutive cycles

CLK

CLKB

tCYCLE, i+1

Figure 11. C ycl e-to-c ycl e Jitter

tPW+,i

tDC,ERR = tPW+,i – tPW+,i+1 over many consecutive cycles

CLK

CLKB

tPW+,i+1

tCYCLE,i+1 tCYCLE, i+1

Cycle i Cycle i+1

Figure 12. Cycle-to-cycle Duty Cycle Error

tJLT = tmax – tmin over many cycles

CLK

CLKB

tmin

tmax

Figure 13. Long-term Jitter

CY221

Document #: 38-07263 Rev. *E Page 9 of 10

of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semiconductor pr oduct. Nor does it convey or imply any licen se under p atent or other rights. C ypress Semicond uctor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Ordering Information

Package Drawing and Dimensions

CyberCl ocks is a trade mark of C ypress Semicond uctor . All pr oduct and comp any n ames me ntioned in this doc ument ma y be th e

trademarks of their respective holders.

Ordering Code Package Type Operating Range Operating Vo ltage

CY2213ZC-1 16-lead TSSOP Commercial, to 400 MHz 3.3V

CY2213ZC-1T 16-lead TSSOP – Tape and Reel Commercial, to 400 MHz 3.3V

CY2213ZC-2 16-lead TSSOP Commercial, to 500 MHz 3.3V

CY2213ZC-2T 16-lead TSSOP – Tape and Reel Commercial, to 500 MHz 3.3V

16-Lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16

51-85091-**

CY221

Document #: 38-07263 Rev. *E Page 10 of 10

Document History Page

Document Title: CY2213 High-Frequency Programmable PECL Clock Generator

Document Number: 38-07263

REV. ECN NO. Issue Date Orig. of

Change Description of Change

** 113090 02/06/02 DSG Change from Spec number: 38-01100 to 38-07263

*A 113512 05/24/02 CKN Added PLL Block Diagram (Figure 4) and PLL frequency equation

*B 121882 1 2/1 4/02 RBI Power-up r equ irem en t s add ed to Ope rati ng C ond iti ons

*C 123215 12/19/02 LJN Previous revision was released with incorrect *A numbering in footer; *A should have

been *B (and was changed accordingly)

*D 124012 03/05/03 CKN Added -2 to data sheet; edited line 3 of Benefits

*E 126557 05/27/03 RGL Added 200-MHz Jitter Spec.

Added optional output termination