900MHz Balanced Mixer with High Side LO Buffer, and RF Balun ADL5367 Preliminary Technical Data FEATURES Power Conversion Loss of 7.0dB RF Frequency 500MHz to 1500MHz IF Frequency DC to 450 MHz SSB Noise Figure with 10dBm Blocker of 17dB Input IP3 of 37dBm Input P1dB of 25 dBm Typical LO Drive of 0 dBm Single-ended, 50 RF and LO Input Ports High Isolation SPDT LO Input Switch Single Supply Operation: 3.3 to 5 V Exposed Paddle 5 x 5 mm, 20 Lead LFCSP Package 2000V HBM / 500V FICDM ESD Performance APPLICATIONS Cellular Base Station Receivers Transmit Observation Receivers Radio Link Downconverters Figure 1. Functional Block Diagram GENERAL DESCRIPTION The ADL5367 utilizes a highly linear doubly balanced passive mixer core along with integrated RF and LO balancing circuitry to allow for single-ended operation. The ADL5367 incorporates an RF balun allowing for optimal performance over a 700 to 1000 MHz RF input frequency range using high-side LO injection. (Pin compatible parts for low side injection are also available). The balanced passive mixer arrangement provides good LO to RF leakage, typically better than -20dBm, and excellent intermodulation performance. The balanced mixer core also provides extremely high input linearity allowing the device to be used in demanding cellular applications where inband blocking signals may otherwise result in the degradation of dynamic performance. For low voltage applications, the ADL5367 is capable of operation at voltages down to 3V with substantially reduced current. Two digital logic inputs allowed the user to control an internal resistor string D/A converter to optimize the intermodulation or noise performance of the application. LO current can be externally set using a resistor to minimize DC current commensurate with the desired level of performance. An additional logic pin is provided to power down (<100uA) the circuit when desired. The ADL5367 is fabricated using a BiCMOS high performance IC process. The device is available in a 5mm x 5mm 20-lead LFCSP package and operates over a -40C to +85C temperature range. An evaluation board is also available. RF Frequency Single Mixer Single Mixer + IF Amp Dual Mixer + IF Amp 500MHz to 1500MHz ADL5367 ADL5357 ADL5358 1500MHz to 2500MHz ADL5365 ADL5355 ADL5356 REV. PrB Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.326.8703 (c) 2009 Analog Devices, Inc. All rights reserved. ADL5367 Preliminary Technical Data ADL5367--Specifications Table 1. VS = 5 V, TA = 25C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, Zo = 50, unless otherwise noted Parameter Conditions Min Typ Max Unit RF INPUT INTERFACE Return Loss Tunable to >20dB over a limited bandwidth Input Impedance Differential impedance, f = 200 MHz 50 1500 LO INTERFACE LO Power Return Loss -3 0 10 50 Input Impedance High Side LO MHz 50 DC IF Frequency Range LO Frequency Range dB 500 RF Frequency Range OUTPUT INTERFACE Output Impedance 16 700 450 MHz +10 dBm dB 1700 MHz DYNAMIC PERFORMANCE Power Conversion Gain Including 1:1 IF port transformer and PCB loss -7.0 dB Voltage Conversion Gain ZSOURCE = 50, Differential ZLOAD = 50 Differential -7.0 dB 7.4 dB 10dBm Blocker present +/-5MHz from wanted RF input, LO source filtered 17 dB Input Third Order Intercept fRF1 = 900 MHz, fRF2 = 901 MHz, fLO = 1103 MHz, each RF tone at 0 dBm 37 dBm Input Second Order Intercept fRF1 = 900 MHz, fRF2 = 950 MHz, fLO = 1103 MHz, each RF tone at 0 dBm 63 dBm 25 dBm -13 dBm LO to RF Input Leakage -28 dBm RF to IF Output Isolation 42 dB SSB Noise Figure SSB Noise Figure Under-Blocking Input 1 dB Compression Point LO to IF Output Leakage Unfiltered IF Output IF/2 Spurious 0 dBm Input Power -66 dBc IF/3 Spurious 0dBm Input Power -72 dBc POWER INTERFACE Supply Voltage Quiescent Current 3 Resistor Programmable REV. PrB | Page 2 of 9 5 100 5.5 V mA Preliminary Technical Data ADL5367 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage, VPOS PWDN, LOSW, VGS0, VGS1 RF Input Power RFIN Internal Power Dissipation JA (Exposed Paddle Soldered Down) JC (At Exposed Paddle) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating 5.5 V TBD TBD TBD TBD TBD TBD -40C to +85C -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION REV. PrB | Page 3 of 9 ADL5367 Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 2 3 4, 5, 16 6, 8 7 9 10 11, 15 12, 13 14 17 18, 19 20 Mnemonic VPMX RFIN RFCT COMM VLO3, VLO2 LGM3 LOSW NC LOI1, LOI2 VGS0, VGS1 VPSW PWDN IFON, IFOP VCMI Function Positive Supply Voltage for the mixer: 5.00 V. RF Input. Must be ac-coupled. RF Balun Center Tap (AC Ground). Device Common (DC Ground). Positive Supply Voltage for LO Amplifier. LO Amplifier Bias Control. LO Switch. No Connect. LO Input. Must be ac-coupled. Mixer Gate Bias Control. Ground for nominal operation. Positive Supply Voltage for LO Switch. Connect to Ground for Normal Operation. Connect pin to 3.3V for disable mode. Differential IF Output. No Connect. REV. PrB | Page 4 of 9 Preliminary Technical Data ADL5367 TYPICAL PERFORMANCE CHARACTERISTICS 0 15 -1 14 -2 13 -3 12 Noise Figure ( dB) Conversion Gain (dB) VS = 5 V, TA = 25C, as measured using typical circuit schematic with high-side LO unless otherwise noted. -4 -5 -6 -7 10 9 8 7 -8 6 -9 -10 500 11 600 700 800 900 1000 1100 1200 1300 1400 5 500 1500 600 700 800 900 1000 1100 1200 1300 1400 1500 1400 1500 RF Frequency (MHz) RF Frequency (MHz) Figure 3. Conversion Gain versus RF Frequency Figure 6. Single-Sideband NF versus RF Frequency 40 0 -5 LO to RF Leakage (dBm) 35 Input IP3 (dBm) 30 25 20 -10 -15 -20 -25 -30 15 -35 10 500 600 700 800 900 1000 1100 1200 1300 1400 1500 RF Frequency (MHz) Input P1dB (dBm) 25 20 15 10 5 700 800 900 1000 1100 700 800 900 1000 1100 1200 1300 Figure 8. LO to RF Leakage versus LO Frequency 30 600 600 RF Frequency (MHz) Figure 4. IIP3 versus RF Frequency 0 500 -40 500 1200 1300 1400 1500 RF Frequency (MHz) Figure 5. IP1dB versus RF Frequency REV. PrB | Page 5 of 9 ADL5367 Preliminary Technical Data 40 35 0 30 Input IP3 (dBm) Conversion Gain (dB) -2 -4 -6 -8 25 20 15 10 -10 5 -12 0 500 600 700 800 900 1000 1100 1200 1300 RF Frequency (MHz) -14 500 600 700 800 900 1000 1100 1200 1300 1400 1500 RF Frequency Figure 9. Up Conversion: Input IP3 vs. RF Frequency Figure 8. Up Conversion: Conversion Gain vs. RF frequency REV. PrB | Page 6 of 9 1400 1500 Preliminary Technical Data ADL5367 EVALUATION BOARD An evaluation board is available for the family of double balanced mixers, including ADL5365 and ADL5367. The standard evaluation board schematic is presented in Figure 10. The evaluation board is fabricated on a multilayer Rogers board. Table 4 details the various configuration options of the evaluation board. Figure 10. Evaluation Board Schematic. Table 4. Eval Board Configuration Components C2, C6, C8, C20, C21 C1, C4, C5 T1, R1, R24, R25 Function Power Supply Decoupling. Nominal supply decoupling consists a 10F capacitor to ground in parallel with 10pF capacitors to ground positioned as close to the device as possible. RF Input Interface. The input channels is ac-coupled through C1. C4 and C5 provide bypassing for the center taps of the RF input baluns. IF Output Interface. T1is a 1:1 impedance transformer used to provide a single ended IF output interface. R1 should be removed for balanced output operation. REV. PrB | Page 7 of 9 Default Conditions C2 = 10 F (size 0603) C6, C8, C20, C21 = 10 pF (size 0402) C1 = 22 pF (size 0402) C4 = 10 pF (size 0402) C5 = 0.01 F (size 0402) T1 = TC1-1-13M+ (MiniCircuits) R1 = 0 (size 0402) R24, R25 = 560 pF (size 0402) ADL5367 C10, C12, R4 R21 C22, L3, R9, R14, R22, R23, VGS0, VGS1 Preliminary Technical Data LO Interface. C10 and C12 provide ac-coupling for the LO1_IN and LO2_IN local oscillator inputs. LOSEL selects the appropriate LO input for both mixer cores. R4 provides a pull-down to ensure LO1_IN is enabled when the LOSEL test point has logic low. LO2_IN is enabled when LOSEL is pulled to logic high. PWDN Interface. R21 pulls the PWDN logic low and enables the device. PWR_UP test point allows PWDN interface to be excercised using external logic generator. It is permissible to ground the PWDN pin for nominal operation. Bias Control. R22 and R23 form a voltage divider to provide a 3V for logic control, bypassed to ground through C22. VGS0 and VGS1 jumpers provide programmability at pin VGS0 and VGS1. It is recommeded to pull these two pins to ground for nominal operation. R9 sets the bias point for the internal LO buffers. R14 is essentially no connect. REV. PrB | Page 8 of 9 C10, C12 = 22pF (size 0402) R4 = 10k (size 0402) R21 = 10k (size 0402) C22 = 1 nF (size 0402) L3 = 0 (size 0603) R9 = 1.1 k (size 0402) R14 = OPEN R22 = 10k (size 0402) R23 = 15k (size 0402) VGS0 = VGS1 = 3-pin shunt Preliminary Technical Data ADL5367 OUTLINE DIMENSIONS Figure 11. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm x 5 mm Body, Very Thin Quad (CP-20-5) Dimensions shown in millimeters ORDERING GUIDE Models ADL5367XCPZ-R71 ADL5367-EVALZ 1 Temperature Range -40C to +85C Package Description 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Package Option CP-20-5 Branding TBD Transport Media Quantity TBD, Reel 1 Z = Pb-free part. REV. PrB | Page 9 of 9 PR08083-0-2/09(PrB)