1 www.semtech.com
SC1404
Mobile Multi-Output PWM Controller
with Virtual Current SenseTM
POWER MANAGEMENT
Description Features
Applications
Typical Application Circuit
The SC1404 is a multiple-output power supply controller designed
for battery operated systems. The SC1404 provides synchronous
rectified buck converter control for two power supplies. An effi-
ciency of 95% can be achieved. The SC1404 uses Semtech’s
proprietary Virtual Current SenseTM technology along with external
error amplifier compensation to achieve enhanced stability and
DC accuracy over a wide range of output filter components while
maintaining fixed frequency operation. The SC1404 also pro-
vides two linear regulators for system housekeeping. The 5V lin-
ear regulator takes its input from the battery; for efficiency, the
output is switched to the 5V output when available. The 12V lin-
ear regulator output is generated from a coupled inductor off the
5V switching regulator.
Control functions include: power up sequencing, soft start, power-
good signaling, and frequency synchronization. Line and load
regulation is to +/-1% of the output voltage. The internal oscilla-
tor can be adjusted to 200 kHz or 300 kHz or synchronized to an
external clock. The mosfet drivers provide >1A peak drive current
for fast mosfet switching.
The SC1404 includes a PSAVE# input to select pulse skipping
mode for high efficiency at light load, or fixed frequency mode for
low noise operation.
6 to 30V input range (operation possible below 6V)
3.3V and 5V dual synchronous outputs
Fixed-frequency or PSAVE for maximum efficiency over
wide load current range
5V/50mA linear regulator
12V/200mA linear regulator
Virtual Current Sense TM for enhanced stability
Accurate low-loss current limiting
Out-of-phase switching reduces input capacitance
External compensation supports wide range of
output filter components for reduced cost
Programmable power-up sequence
Power Good output
Output overvoltage & overcurrent protection with output
undervoltage shutdown
4μA typical shutdown current
6mW typical quiescent power
Notebook and Subnotebook Computers
Automotive Electronics
Desktop DC-DC Converters
Revision: June 08, 2005
2© 2005 Semtech Corp. www.semtech.com
SC1404
PRELIMINARYPOWER MANAGEMENT
Electrical Characteristics
Absolute Maximum Ratings
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Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = 0V, VL load = 0mA, REF load = 0mA, PSAVE# = 0V, TA =-40 to 85°C.
Typical values are at TA = +25°C. Circuit = Typical Application Circuit
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Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters
specified in the Electrical Characteristics section is not implied.
3© 2005 Semtech Corp. www.semtech.com
SC1404
POWER MANAGEMENT
Electrical Characteristics Cont.
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Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = 0V, VL load = 0mA, REF load = 0mA, PSAVE# = 0V, TA =-40 to 85°C.
Typical values are at TA = +25°C. Circuit = Typical Application Circuit
4© 2005 Semtech Corp. www.semtech.com
SC1404
PRELIMINARYPOWER MANAGEMENT
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Electrical Characteristics Cont.
Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = 0V, VL load = 0mA, REF load = 0mA, PSAVE# = 0V, TA =-40 to 85°C.
Typical values are at TA = +25°C. Circuit = Typical Application Circuit
5© 2005 Semtech Corp. www.semtech.com
SC1404
POWER MANAGEMENT
Electrical Characteristics Cont.
Notes:
(1) This device is ESD sensitive. Use of standard ESD handling procedures required.
(2) Applicable from 0 to +85°C.
Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = 0V, VL load = 0mA, REF load = 0mA, PSAVE# = 0V, TA =-40 to 85°C.
Typical values are at TA = +25°C. Circuit = Typical Application Circuit
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6© 2005 Semtech Corp. www.semtech.com
SC1404
PRELIMINARYPOWER MANAGEMENT
Pin Descriptions
Note: All logic level inputs and outputs are open collector TTL compatible.
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7© 2005 Semtech Corp. www.semtech.com
SC1404
POWER MANAGEMENT
Block Diagram
8© 2005 Semtech Corp. www.semtech.com
SC1404
PRELIMINARYPOWER MANAGEMENT
Pin Configuration Ordering Information
ECIVEDEGAKCAPT(.PMET
BMA
)
RTSTI4041CS82-POSST
)1(
C°58+-04-
TRTSTI4041CS82-POSST
)2()1(
noitpOeerf-daeL
RTSSI4041CS82-POSS
)1(
TRTSSI4041CS82-POSS
)2()1(
noitpOeerf-daeL
Block Diagram
TSSOP-28/SSOP-28
Top View
3HSC3NO
3LSC3HD
3PMOC3ESAHP
TUO213TSB
DDV3LD
CNYS#NDHS
5NO+V
DNGLV
FERDNGP
#EVASP5LD
#TESER5TSB
5PMOC5ESAHP
5LSC5HD
5HSCQES
SC1404
1
2
3
4
5
6
7
8
9
11
12
13
14
10
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Note:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices for TSSOP and 1000 devices
for SSOP.
(2) Lead-free product. This product is fully WEEE and
RoHS compliant.
9© 2005 Semtech Corp. www.semtech.com
SC1404
POWER MANAGEMENT
Detailed Description
The SC1404 is a versatile multiple-output power supply controller
for battery operated systems. The SC1404 provides synchronous
rectified buck control in fixed frequency forced-continuous (PWM)
mode and hysteretic PSAVE mode, for two switching power supplies
over a wide load range. Out of phase switching reduces input
noise and RMS current, which reduces the input filter inductors
and capacitors. The two switchers have on-chip preset output
voltages of 5.0V and 3.3V.
The control circuitry for each PWM controller includes digital
softstart, voltage error amplifier with built-in slope compensation,
pulse width modulator, power save, overcurrent, overvoltage and
undervoltage fault protection. Two linear regulators and a precision
reference voltage are also provided. The 5V/30mA linear regulator
(VL) uses battery power to feed the gate drivers. For improved
efficiency, VL automatically switches over the +5V converter output
if available. The 12V linear regulator supplies up to 200mA.
Semtech’s proprietary Virtual Current SenseTM provides greater
advantages in the aspect of stability and signal-to-noise ratio than
the conventional current sense method.
PWM Control
There are two separate PWM control blocks for each switcher.
They are switched out-of-phase with each other. This interleaved
topology reduces input filter requirements by reducing current
drawn from the filter capacitors. To avoid both switchers switching
at the same instance, there is a built-in delay between the turn-on
of the 3.3V switcher and 5V switcher, the amount of which depends
on the input voltage (see Out-of-Phase Switching).
The PWM provides two modes of control over the entire load range.
The SC1404 operates in forced continuous conduction mode as
a fixed frequency peak current mode controller with falling edge
modulation. Current sense is done differently than in conventional
peak current mode control. Semtech’s proprietary Virtual Current
SenseTM emulates the necessary inductor current information for
proper functioning of the IC. In order to accommodate a wide
range of output filters, a COMP pin is also available for
compensating the error amplifier externally. A nominal error
amplifier gain of 18 improves the system loop gain and the output
transient behavior.
When operating in continuous conduction mode, the high-side
mosfet is turned on at the start of each switching cycle. It is turned
off when the desired duty cycle is reached. Active shoot-through
protection will delay the lower mosfet turn-on until the phase node
drops below 1V. The low-side mosfet remains on until the beginning
of the next switching cycle. Again, active shoot-through protection
ensures that the low-side mosfet gate voltage drops low before
the high-side mosfet turns on.
Under light load conditions when the PSAVE# pin is low, the
SC1404 operates hysteretically in the discontinuous conduction
mode to reduce its switching frequency and switching bias current.
The switching of the output mosfet does not depend on a given
oscillator frequency, but on the hysteretic voltage set around the
nominal output voltage. When entering PSAVE# mode (from heavy
to light load), if the minimum (valley) inductor current measured
at CSHx-CSLx is below the Zero Cross threshold (typically 5 mV) for
four switching cycles, the virtual current sense circuitry will shut off
and the mode changes to hysteretic mode. As the load current
increases, if the minimum (valley) inductor current is above the
threshold for four switching cycles, the converter stops psave mode
and enters PWM operation. The change in frequency between
hysteretic psave and PWM mode provides hysteresis to inhibit
chattering between the two modes of operation.
Gate Drive / Control
The gate drivers on the SC1404 are designed to switch large
mosfets. The high-side gate driver must drive the gate of high-side
mosfet above the V+ input. The supply for the gate drivers is
generated by charging a boostrap capacitor from the VL supply
when the low-side driver is on. In continuous conduction mode,
the low-side driver output that controls the synchronous rectifier
in the power stage is on when the high-side driver is off. Under light
load conditions when PSAVE# pin is low, the inductor ripple current
will approach the point where it reverses polarity. This is detected
by the low-side driver control and the synchronous rectifier is turned
off before the current reverses, preventing energy drain from the
output. The low-side driver operation is also affected by various
fault conditions as described in the Fault Protection section.
Internal Bias Supply
The VL linear regulator is a 5V output that powers the gate drivers,
2.5V reference and internal controls of the SC1404. The regulator
is capable of supplying up to 30mA (including mosfet gate charge
current). The VL pin should be bypassed to GND with 4.7uF to
supply the large gate drive current pulses.
The regulator receives input power from the V+ battery input. Effi-
ciency is improved by providing a bootstrap for the VL output.
When the 5V SMPS output voltage reaches 5V, internal circuitry
turns on a PMOS device between CSL5 and VL. The internal VL
regulator is then disabled, and VL bias is provided by the high
efficiency 5V switcher.
The REF output is accurate to +/- 2% over temperature. It is capable
of delivering 5mA max and should be bypassed with 1uF minimum
capacitor. Loading the REF pin will reduce the REF voltage slightly
as seen in the following table.
10© 2005 Semtech Corp. www.semtech.com
SC1404
PRELIMINARYPOWER MANAGEMENT
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Current Sense (CSH, CSL)
Output current of each supply is sensed at the CSH and CSL pins.
Overcurrent is reached when the current sense voltage exceeds
55mV typical. On a cycle-by-cycle basis, a positive overcurrent
turns off the high-side driver and a negative overcurrent turns off
the low-side driver.
Oscillator
When the SYNC pin is high the oscillator runs at 300kHz; when
SYNC is low the frequency is 200kHz. The oscillator will synchronize
to the falling edge of a clock on the SYNC pin with a frequency
between 240kHz and 350kHz. In general, 200kHz operation
provides highest efficiency, while 300kHz allows for smaller output
ripple and/or smaller filter components.
Fault Protection
In addition to cycle-by-cycle current limit, the SC1404 provides
overtemperature, output overvoltage, and undervoltage
protection. Overtemperature protection will shut the device down
if die temperature exceeds 150°C, with 10°C hysteresis.
If either SMPS output is more than 10% above its nominal value,
both SMPS are latched off and the low side mosfets are latched
on. To prevent the output from ringing below ground in a fault
condition, a 1A Schottky diode should be placed across each output.
Two different levels of undervoltage (UV) are detected. If the output
falls 9% below its nominal value, the RESET# output is pulled low.
If the output falls 25% below its nominal value, both SMPS are
latched off.
Both of the latched faults (OVP and UV) persist until SHDN or ON3
is toggled, or the V+ input is brought below 1V.
Shutdown and Operating Modes
Holding the SHDN pin low disables the SC1404, reducing the V+
input current to less than 10uA. When SHDN is high, the part
enters standby mode where the VL regulator and VREF are enabled.
Turning on either SMPS will put the SC1404 in run mode.
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Power up Controls and Soft Start
The user controls the SC1404 RESET# through the SEQ, ON3 and
ON5 pins, as shown in the Startup Sequence Chart. At startup,
RESET# is held low for 32K switching cycles, and then RESET# is
determined by the output voltages and the SEQ pin.
To prevent surge currents at startup, each SMPS has a counter
and DAC to incrementally raise the current limit (CSH-CSL voltage).
The current limit follows discrete steps of typically 25%, 40%, 60%,
80%, and 100%, each step lasting 128 clock cycles. To charge up
the output capacitors, inductor current at startup must exceed
load current. When the output voltage reaches it’s nominal value
the SMPS will reduce duty cycle, but the excess LI2 energy of the
inductor must flow into the load and output capacitors. If the
output capacitor is relatively small, the peak output voltage can
approach the overvoltage trip point. To prevent nuisance OVP at
startup, the inductance and capacitance must meet the following
criteria:
59.1
2
2
_
_⋅≤
OCMAX
NOMO
MIN
MAX
IL
V
C
L
ILMAX_OC is the maximum inductor current set by the current-limit
components, and VO_NOM is the nominal output voltage.
12OUT Supply
The 12OUT linear regulator is capable of supplying 200mA. The
input voltage to the 12OUT regulator is generated by a secondary
winding on the 5V SMPS inductor.
A heavy load on the 12OUT regulator when the 5V SMPS operates
in PSAVE mode will cause VDD to sag, causing 12OUT to drop. If
12OUT output drops 0.8% from its nominal value, the 5V SMPS is
forced out of PSAVE mode and into PWM mode for several cycles.
This recharges the bulk input capacitor on VDD.
The 12OUT linear regulator has internal protection to prevent
damage under short circuit conditions. Overvoltage protection is
provided on the VDD input. If VDD rises above 19V, a 10mA shunt
load is applied to VDD to reduce the voltage. The overvoltage
threshold has 0.5V hysteresis.
11© 2005 Semtech Corp. www.semtech.com
SC1404
POWER MANAGEMENT
Reference Circuit Design
The schematic for the reference circuit is shown on page 20. The
reference circuit is configured as follows:
Switching Regulator 1 Vout1 = 3.3V @ 6A
Switching Regulator 2 Vout2 = 5.0V @ 6A
VL Regulator Vout3 = 5.0V @ 30mA
12V regulator Vout4 = 12.0V @ 200mA
Input voltage Vin = 7 to 21V
Designing the Output Filter
Before calculating the filter inductance and capacitance, an
acceptable inductor ripple current is determined. Ripple current
is usually set at 10% to 20% of the maximum load. However,
increasing the ripple current allows for a smaller inductor and will
also quicken the output transient response. In this example, we
set the ripple current to be 25% of maximum load.
AAIO5.16%25 =×=Δ
The inductance is found from ripple current, frequency, input
voltage, and output voltage. Minimum required inductance is
found at maximum Vin, where ripple current is the greatest.
uH
IoF
VinVo
VominL 18.6
)/1( =
Δ×
−
×=
For the reference design, the Coiltronics DR127-6R8 is used. This
is acceptable for the 3V output, which uses a simple inductor. The
5V inductor must have a 12V winding with a turns ratio of 2.2:1.
For the 5V inductor, the TTI-8215 from Transpower Technologies
is used, which has 5V inductance of 6.4uH.
To specify the output capacitance, the allowable output ripple
voltage must be determined. Output ripple is often specified at
1% of the output voltage. For the 3.3V output, we selected a
maximum ripple voltage of 33mVp-p. The maximum allowable
ESR would then be:
Ω==ΔΔ= mAmVIVESR OOMAX 225.1/33/
Panasonic SP Polymer Aluminum capacitors are a good choice.
For this design, use one 180uF, 4V device, with ESR of 15mΩ.
The output capacitor must support the inductor RMS ripple current.
To check the actual ripple versus the capacitor’s RMS rating:
A
AI
IO
actualRMS 43.0
12
5.1
12
_==
Δ
=
This is much less than the capacitor’s ripple rating of 3.3A.
Choosing the Main Switching mosfet
The IRF7143 is used in the reference design. Before choosing the
main (high-side) mosfet, we need to check three parameters: volt-
age, power, and current rating.
The maximum drain to source voltage of the mosfet is mainly
determined by the switcher topology. With a buck topology,
V21VV MAX_INMAX_DS ==
The IRF7413 is a 30V device, which allows for 70% derating at
21V operation.
The mosfet power dissipation has three components: conduction
losses, switching losses, and gate drive losses. The conduction
loss is determined using the RMS mosfet current; the equation is
QES3NO5NOTESERNOITPIRCSED
FERWOLWOL.SPMSV3.3swolloF .ffosSPMShtoB.edomlortnoctratstnadnepednI
FERWOLHGIH.woL.FFOSPM
SV3.3,NOSPMSV5
FERHGIHWOL.SPMSV3.3swolloF.FFOSPMSV5,NOSPMSV3.3
FERHGIHHGIH.SPMSV3.3swolloF.nosSPMShtoB
DNGWOLX .woL.f
fosSPMShtoB
DNGHGIHWOL/HGIHerastuptuohtobretfahgiH
.noitalugerni
,HGIH=5NOfI.hgihseog3NOnehwstratsV5
.ffosiV
3,WOL=5NOfI.nosiV3
LVWOLX .woL.ffosSPMShtoB
LVHGIHWOL/HGIHerastuptuohtobretfahgiH
.noitalugerni
,HGIH=5NOfI.hgihs
eog3NOnehwstratsV3
.ffosiV5,WOL=5NOfI.nosiV5
Startup Sequence Chart
Applications Information
12© 2005 Semtech Corp. www.semtech.com
SC1404
PRELIMINARYPOWER MANAGEMENT
shown below. The mosfet current is a trapezoid waveform with
values equal to:
2
ΔI
II L
LOADMIN −= 2
ΔI
II L
LOADMAX +=
Lfs
D)(1Vo
ΔIL⋅
−⋅
=Vin
Vo
D=
(
)
22 MAXMAXMINMINRMS IIIIDI +⋅+⋅=
As input voltage decreases, the duty cycle increases and the ripple
current decrease, and overall the RMS mosfet current will increase.
The conduction losses are then given by the formula below, where
Rds(on) is 18m-ohm for the IRF7413 at room temperature. Note
that Rds(on) increases with temperature.
2
RMSds(on)CONDUCTION IRP ⋅=
The mosfet switching loss is estimated according to:
G
OUTS
2
INRSS
SWITCHING
I
IfVC
P⋅⋅⋅
=
Crss is the mosfet’s reverse transfer capacitance, 240pF for
IRF7413. Ig is the gate driver current, which is 1A for SC1403.
The mosfet gate drive loss is estimated from:
S
2
GGATE fVgfsC
2
1
P⋅⋅⋅=
Cg is the effective gate capacitance, equal to the Total Gate Charge
divided by VGS, from the vendor datasheet, and is 7.9nF for the
IRF7413. Vgfs is the final gate-source voltage, 5V in this case.
The total mosfet loss is the sum of the three loss components.
GATESWITCHINGCONDUCTIONTOTAL_DISS PPPP ++=
The mosfet dissipation under conditions of 15V input, 6A load,
and ambient temperature of 25C, can be determined as:
DNOM = 0.22 ΔIL = 1.26A
IMIN = 5.37A IMAX = 6.63A IRMS = 4.88A
Rds(on) (100C) = 18 mohm
PCONDUCTION = 429mW
PSWITCHING = 97mW PGATE = 30mW
PTOTAL_DISS = 429 + 97 + 30 = 556 mW
The junction temperature rise resulting from the power dissipa-
tion is calculated as:
JATJ θPΔT⋅=
PT is the total device dissipation, and θJA is the package thermal
resistance, which is 50°C/W for the IRf7413. The junction tem-
perature rise is then:
ΔTJ = 0.556W . 50°C/W = 27.8°
This is an acceptable temperature rise, so no special heat sinking
is required.
Designing the Loop
A good loop design is a combination of the power train and com-
pensation design. In the SC1404, the control-to-output/power train
response is dominated by the load impedance, the inductor, out-
put capacitance, and the ESR of the output caps. The low fre-
quency gain is dominated by the output load impedance and the
effective current sense resistor. Inherent to Virtual Current SenseTM,
there is one additional low frequency pole sitting between 100Hz
and 1kHz and a zero between 15kHz and 25kHz. he output of
error amplifier COMP pin is available for external compensation. A
traditional pole-zero-pole compensation is not necessary in the
design using SC1404, a simple high frequency pole is usually
sufficient.
Single-Pole Compensation Method
Given parameters:
Vin = 19V, Vout = 3.3V @ 2.2A,
Output impedance, Ro = 3.3V/2.2A = 1.5 Ω,
Panasonic SP cap, Co = 180uF, Resr = 15 Ωm,
Output inductor, Lo = 4.7uH
Switching frequency, Fs = 300kHz
Simulated Control-to-Output gain & phase response (up to
100kHz) is plotted below.
-50
-40
-30
-20
-10
0
10
20
30
40
50
1.00E+02 1.00E+03 1.00E+04 1.00E+05
f (Hz)
Gain (dB)
13© 2005 Semtech Corp. www.semtech.com
SC1404
POWER MANAGEMENT
Applications Information
Applications Information
-200
-150
-100
-50
0
50
100
150
200
1.00E+02 1.00E+03 1.00E+04 1.00E+05
f (Hz)
Phase (deg)
Measured Control-to-Output gain & phase response (up to 100kHz)
is plotted below.
-50
-40
-30
-20
-10
0
10
20
30
40
50
1.00E+02 1.00E+03 1.00E+04 1.00E+05
f (Hz)
Gain (d
B
-200
-150
-100
-50
0
50
100
150
200
1.00E+02 1.00E+03 1.00E+04 1.00E+05
f (Hz)
Phase (deg)
Single-pole compensation is achieved using a 100pF capacitor
from the COMP pin to ground. The simulated feedback gain &
phase response (up to 100kHz) is plotted below.
-15
-10
-5
0
5
10
15
20
25
1.00E+02 1.00E+03 1.00E+04 1.00E+05
f (Hz)
Gain (dB)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
1.00E+02 1.00E+03 1.00E+04 1.00E+05
f (Hz)
Phase (deg)
Measured feedback gain & phase responses (up to 100kHz) is
plotted below.
14© 2005 Semtech Corp. www.semtech.com
SC1404
PRELIMINARYPOWER MANAGEMENT
Applications Information
.
-15
-10
-5
0
5
10
15
20
25
1.00E+02 1.00E+03 1.00E+04 1.00E+05
f (Hz)
Gain (dB)
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
20
1.00E+02 1.00E+03 1.00E+04 1.00E+05
Frequency (Hz)
Phase (deg)
Simulated overall gain & phase responses (up to 100kHz) is plot-
ted below.
-80
-60
-40
-20
0
20
40
60
80
1.00E+02 1.00E+03 1.00E+04 1.00E+05
f (Hz)
Gain (dB)
-20
0
20
40
60
80
100
120
140
160
180
1.00E+02 1.00E+03 1.00E+04 1.00E+05
f (Hz)
Phase (deg)
Measured overall gain & phase response of the single-pole com-
pensation using SC1404 is plotted below.
-20
0
20
40
60
80
100
120
140
160
180
1.00E+02 1.00E+03 1.00E+04 1.00E+05
f (Hz)
Phase (deg)
paCtuptuOnoitasnepmoCdednemmoceR
eulaVpaC
Fμ081=<Fp001
Fμ0001<&Fμ081>Fp002
Fμ0001>Fp033
15© 2005 Semtech Corp. www.semtech.com
SC1404
POWER MANAGEMENT
Applications Information
Input Capacitor Selection and Out-of-phase Switching
The SC1404 uses out-of-phase switching between the two
converters to reduce input ripple current, allowing smaller cheaper
input capacitors compared to in-phase switching.
The figure below shows in-phase switching. I3in is the input current
for the 3V converter, I5in is the input current for the 5V converter.
The two converters start each switching cycle simultaneously,
causing a significant amount of overlap and a high peak current.
The total input current the third waveform, which shows how the
two currents add together. The fourth waveform is current in and
out of the input capacitors.
I3in
I5in
Iin average
Icap
0
0
D3
D5
The next figure shows out-of-phase switching. The 3V and 5V
pulses are spaced apart, so there is no overlap. This gives two
benefits; the peak current is reduced, and the effective switch
frequency is raised. Both of these make filtering easier. The third
waveform is the total input current, and the fourth waveform shows
the current flowing in and out of the input capacitors. The rms
value of the capacitor current is significantly lower than the in-
phase case, which allows for smaller capacitors.
I3in
I5in
Icap
Iin
average
0
0
D3
D5
As the input voltage is reduced, the duty cycle of both converters
increases. At input voltages less than 8.3V, it is impossible to
prevent overlap regardless of the phase between the converters.
Overlap is seen in the following figure.
I5in
Iin
0
average
Icap
0
period
phase lead
D3
D5
From an input filter standpoint it is desirable to minimize the
overlap; but it is also desirable to keep the turn-on and turn-off
transitions of the two converters separated in time, to minimize
interaction between the two converters. The SC1404 keeps the
turn-on and turn-off transitions separated in time by changing the
phase between the converters depending on the input voltage.
The following table shows the phase relationship between 3V and
5V turn-on, based on input voltage.
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egatlovegatlov egatlov egatlovegatlov
V5otV3morfdaelesahPV5otV3morfdaelesahP V5otV3mo
rfdaelesahP V5otV3morfdaelesahPV5otV3morfdaelesahP
V6.9>niVdoirepgnihctiwsfo%14
V5dnaV3.3neewtebpalrevooN
n
iV>V6.9
V7.6>
doirepgnihctiwsfo%95
suoenatlumistneverpotpalrevollamS
gnihctiwsV5/V3
niV>7.6doirepgnihctiwsf
o%46
suoenatlumistneverpotpalrevollamS
gnihctiwsV5/V3
16© 2005 Semtech Corp. www.semtech.com
SC1404
PRELIMINARYPOWER MANAGEMENT
Typical Characteristics
Input ripple current can be calculated from the following equations.
cycleduty 3V 3.3V/VD3 IN ==
cycleduty 5V 5V/VD5 IN ==
current load DC3V I3 =
current load DC5V I5 =
DOVL = overlapping duty cycle of the 3V and 5V pulses
(varies according to input voltage)
INOVL V9.6V for 0D ≤=
9.6V V6.7V for 0.41) - (D5D INOVL <≤=
6.7 Vfor 0.36) - (D5D INOVL <=
current input DC AverageIIN =
5533 DIDIIIN ⋅+⋅=
INSW_RMS Vfrom drawn current RMSI =
I5I3D2I5D5I3D3I OVL
22
SW_RMS
2⋅⋅⋅+⋅+⋅=
22 IN_AVESW_RMSRMS_CAP III +=
The worst-case ripple current varies by application. For the case
6A load on both outputs, the worst-case ripple occurs at Vin =
7.5V, and the rms capacitor current is 4.2A. The reference design
uses 4 paralleled ceramic capacitors, (Murata GRM32NF51E106Z,
10 uF 25V, size 1210). Each capacitor is rated at 2.2A.
Choosing Synchronous mosfet and Schottky Diode
Since this is a buck topology, the voltage and current ratings of the
synchronous mosfet are the same as the main switching mosfet.
It makes sense cost- and volume-wise to use the same mosfet for
the main switch as for the synchronous mosfet. Therefore, IRF7413
is used again in the design for synchronous mosfet.
To improve overall efficiency, an external Schottky diode is used in
parallel with the low side mosfet. The freewheeling current enters
the Schottky diode instead of the inefficient body diode of the
synchronous mosfet. It is really important when laying out the
board to place the synchronous mosfet and Schottky diode close
to each other to reduce the current ramp-up and ramp-down time
due to parasitic inductance between the channel of the mosfet
and the Schottky diode. The current rating of the Schottky diode
can be determined by the following equation:
0.2A
TS
100n
LOAD
IIF_AVG =⋅=
where 100nsec is the estimated time between the mosfet turn-
off and the Schottky diode turn-on and Ts = 3.33uS.A Schottky
diode with a forward current of 0.5A is sufficient for this design.
Operation below 6V input
The SC1404 will operate below 6V input voltage with careful
design, but there are limitations. The first limitation is the
maximum available duty cycle from the SC1404, which limits
the obtainable output voltage. The design should minimize all
circuit losses through the system in order to deliver maximum
power to the output.
A second limitation with operation below 6V is transient
response. When load current increases rapidly, the output
voltage drops slightly; the feedback loop normally increases duty
cycle briefly to bring the output voltage back up. If duty cycle is
already near the maximum limit, the duty cycle cannot increase
enough to meet the demand, and the output voltage sags more
than normal. This problem can not be solved by changing the
feedback compensation, it is a function of the input voltage,
duty cycle, and inductor and capacitor values.
If an application requires 5V output from an input voltage below
6V, the following guidelines should be used:
1 - Set the switching frequency to 200 kHz (Tie SYNC to
ground). This increases the maximum duty cycle
compared to 300 kHz operation.
2 - Minimize the resistance in the power train. Select
mosfets, inductor, and current sense resistor to provide
the lowest resistance as is practical.
3 - Minimize the pcb resistance for all traces carrying
high current. This includes traces to the input
capacitors, mosfetS and diodes, inductor, current sense
resistor, and output capacitor.
4 - Minimize the resistance between the SC1404
circuit and the power source (battery, battery charger,
AC adaptor).
5 - Use low ESR capacitors on the input to prevent the
input voltage dropping during on-time.
6 - If large load transients are expected, high
capacitance and low ESR capacitors should be used on
both the input and output.
17© 2005 Semtech Corp. www.semtech.com
SC1404
POWER MANAGEMENT
5V Start-up with slow Vin ramp.
Proper startup of the 5V output can be hampered by slow dV/dt on
the input. The SC1404 will power up and attempt to generate an
output when the input voltage exceeds 4.5 volts. If the input has
a slow dV/dt, the input voltage will not rise significantly during the
start-up sequence, leading to two conditions. First, the VL supply
can be hundreds of mV below 5V, since the input may not yet be
above 5V. Second, the duty cycle will be at maximum, leading to
very small off-times. These two conditions tend to reduce the
boost voltage; if continued indefinitely, the boost capacitor may
be unable to recharge fully, and eventually the high-side driver
loses its boost bias.
To avoid this the following steps should be taken:
1. If possible the dV/dt of the input supply should exceed .02V/
usec. This dV/dt condition only applies when the input passes
between 4 and 6 volts, the point at which the SC1404 begins a
startup sequence. An alternative is to make sure the input voltage
reaches 6 volts within 100 usec of SC1404 startup at
approximately 4.2 volts. This is sufficiently fast to allow VL and
duty cycle to achieve normal levels and prevents the boost voltage
from falling.
2. If the input dV/dt cannot meet condition 1, the startup of the
SC1404 should be delayed until the input voltage reaches 6V.
This can be done using either the SHDN# or ON5 pin. If the dV/dt
is moderate (slews from 4 to 6 volts in several msecs), an RC
delay on either the SHDN# or ON5 pin should be enough to delay
turn-on until the input reaches 6V.
3. For slow dV/dt on the input (10’s of msec), the SC1404 should
be held off until the input reaches 6V. This can be done using a
comparator or external logic to hold the SHDN# or ON5 pin low
until the input reaches 6V.
12V Load Limitations
The 12V regulator derives input power from a secondary winding
on the 5V inductor. During the 5V off-time, the inductor transfers
energy from the 5V winding to the secondary winding, thereby
providing a crudely regulated 15V that feeds the 12V regulator.
Note that duty cycle increases at low input voltages, and therefore
the on-time decreases. At low input voltages, the duty cycle
increases to maintain the 5V output. The off-time consequently
decreases, which has two detrimental effects. It allows less time
to recharge the raw 15V capacitor, and it also raises the peak 15V
current required to maintain the average 12V load. The 15V
winding needs higher peak current, delivered in less time. But the
stray (leakage) inductance of the inductor resists rapid changes in
winding current, and ultimately limits how much current can be
drawn from 15V before the voltage falls.
The following guidelines for 12V loading apply to the typical circuit,
page 22.
egnarniVegnarniV egnarniV egnarniVegnarniVsnoitidnocdaolV21snoitidnocdaolV21 snoitidnocdaolV21 snoitidnocdaolV21snoitidnocdaolV21
>V01daolV21< daolV5*2/1
xamAm002=daolV21
V01-V7daolV21< daolV5*2/1
:daolV21etaredylraeniL
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V7taAm001
V7-V6daolV21< daolV5*2/1
:daolV21etaredylraeniL
V01taAm001
V7taAm52
18© 2005 Semtech Corp. www.semtech.com
SC1404
PRELIMINARYPOWER MANAGEMENT
Overvoltage Test
Measuring the overvoltage trip point can be problematic. Any
buck converter with synchronous mosfets can act as a boost con-
verter, sending energy from output to input. In some cases the
energy sent to the input is enough to drive the input voltage be-
yond normal levels, causing input overvoltage. To prevent this,
enable the SC1404 PSAVE# feature, which effectively disables
the low side mosfet drive so that little energy, if any, is transferred
back to the input.
Semtech recommends the following circuit for measuring the ov-
ervoltage trip point. D1 prevents the output voltage from damag-
ing lab supply 1. R1 limits the amount of energy that can be cycled
from the output to the input. R2 absorbs the energy that might
flow from output to input, and D2 protects lab supply from pos-
sible damage. The ON5 signal is monitored to indicate when
overvoltage occurs.
Initial conditions:
Both lab supplies set to zero volts
No load connected to 3V or 5V
PSAVE# enabled (PSAVE# tied to GND)
ON5 enabled
ON3 enabled
DVMs monitoring ON5 and the output under test.
Oscilloscope probe connected to Phase Node
of the output under test (not strictly required).
Set Lab Supply 2 to provide 10V at the SC1404 input. The phase
node of the output being tested should show some switching ac-
tivity. The ON5 pin should be above 4V.
Slowly increase Lab Supply 1 until the output under test rises
slightly above it’s normal DC level. As Lab Supply 1 increases,
switching activity at the phase node will cease. The ON5 pin should
remain above 4V.
Increase Lab Supply 1 in very small increments, monitoring both
ON5 and the output under test. The overvoltage trip point is the
highest voltage seen at the output before ON5 pulls low (approxi-
mately 0.3V). Do not record the voltage seen at the output after
ON5 has pulled low; when ON5 pulls low, the current flowing in D1
changes, corrupting the voltage seen at the output.
1K
D1
e.g. 1N4004
R2 75
to DVM
D1
e.g. 1N4004
Vin
Supply
R1
470
2
SC1404
Evaluation
Board
Lab
Output
test
under
1
Supply
Lab
to DVM
1/2W
ON5
VL
1/2W
3.3V Efficiency
50
60
70
80
90
100
0.01 0.1 1 10
Load C urren t (A)
Effici ency (%)
6V 10V 19V
5V Efficienc
y
80
85
90
95
100
0.01 0.1 1 10
Load Current (A)
Efficiency (%
)
6V 10V 19V
Typical Characteristics
19© 2005 Semtech Corp. www.semtech.com
SC1404
POWER MANAGEMENT
As with any high frequency switching regulator design, a good PCB
layout is essential to optimize performance of the converter. Be-
fore starting pcb layout, a careful layout strategy is strongly recom-
mended. See the pcb layout in the SC1404 Evaluation Kit manual
for example. In most applications, FR4 board material with 4 or
more layers and at least 2-ounce copper is recommended(for
output current up to 6A). Use at least one inner layer for ground
connection. It is good practice to tie signal ground and power ground
together at one single point so that the signal ground is not easily
contaminated. Also be sure that high current paths have low in-
ductance and resistance by making trace widths as wide as pos-
sible and lengths as short as possible. Use low-impedance by-
passing for lines that pull large amounts of current in short periods
of time. The following step by step layout strategy is recommended.
Step #1. Power train components placement.
a. Power train arrangement.
Place power train components first. The figure below shows the
recommended power train arrangement. Q1 is the main switching
mosfet, Q2 is the low side mosfet, D1 is the Schottky diode and
L1 is the output inductor.
Q2
D1
Q1
L1
The phase node is generally the largest source of noise in the
converter circuit since it switches at very high rate of speed. The
phase node connections should be kept to a minimum size con-
sistent with its connectivity and current carrying requirements.
Place the Schottky diode as close to the phase node as possible
to minimize the trace inductance between it and the low side
mosfet, to reduce the efficiency loss due to the current ramp-up
and down time. This is important when the converter needs to
handle high di/dt requirements.
Layout Guidelines
b. Current Sense.
Minimize the length of current sense signal traces. Keep them
less than 15mm. Kelvin connections should be used; try to keep
the traces parallel to each other and route them close to each
other as much as possible. Even though SC1404 implements
Virtual Current Sense scheme, the current sense signal is sampled
by the SC1404 to determine the PSAVE threshold. See the follow-
ing figure for a Kelvin connection of the current sense signal.
c. Gate Drive.
SC1404 has built-in gate drivers capable of sinking/sourcing 1A
peaks. Upper gate drive signals are noisier than the lower ones.
Therefore, place them away from sensitive analog circuitries. Make
sure the lower gate traces are as close as possible to the IC pins
and both upper and lower gate traces as wide as possible.
Step #2: PWM controller placement (pins) and signal ground is-
land.
Connect all analog grounds to a separate solid copper island
plane, which connects to the SC1404’s GND pin. This includes
REF, COMP3, COMP5, SYNC, ON3, ON5, PSV# and RESET#.
Step #3: Ground plane arrangement.
There are several ways to tie the different grounds together. Since
this is a buck topology converter, the output ground is relatively
quieter than the input ground. Therefore connect analog ground
to power ground at the output side. Often it is useful to use a
separate ground symbol for the two grounds, and tie the two
grounds together at a single point through a 0Ω resistor. The
power ground for the input side and the power ground for the
output side is the same ground and they can be tied together
using internal planes.
CSH
CSL
SC1404
Rcs
L1
20© 2005 Semtech Corp. www.semtech.com
SC1404
PRELIMINARYPOWER MANAGEMENT
Evaluation Board Schematic
3_3V
SEQ
R22
0 Ohm
DH3
CSH5
R23
0 ohm
S1
DIP_SW5_PTH
1
2
3
4
5
10
9
8
7
6
ON3
D6
MBRS1100T3
C13
100pF
C14
100pF
R12 2M
1 2
R14 2M
1 2
R15 2M
1 2
R17 2M
1 2
SHDN#
BST3
COMP3
RESET#
COMP5
COMP3 COMP5
T-ON5
BST5R
REF
C25
1uF/16V
D4
30BQ015
A C
J2
GND
1
J3
GND
1
D2
30BQ015
A C
J4
GND
1
C18
NO_POP
J15
SHDN#
1
J5
GND
1
J12
RESET#
1
V+
R7
0.005
C9
4.7uF/35V
C19
150uF/6.3V
D1
BAT54A
BST5
L1
6.8uH
1 2
R6
0.005
VL
T/L2
TTI8215
1
5
7
4
10
6
VIN
JP4
1 2
LX3
DH5
J27
V+
1
PSV#
J1
B_JACK_PAIR
POS 1
NEG
2
DL3
U1 SC1404ITS
CSH3
1
CSL3
2
COMP3
3
12OU T
4
VDD
5
SYNC
6
TIME/ON5
7
GND
8
REF
9
PSAVE
10
RESET
11
COMP5
12
CSL5
13
CSH5
14 SEQ 15
DH5 16
PHASE5 17
BST5 18
DL5 19
PGN D 20
VL 21
V+ 22
SHDN 23
DL3 24
BST3 25
PHASE3 26
DH3 27
RUN/ON3 28
LX5
R4
0
12
R5
0
12
JP1
1 2
JP2
1 2
JP3
1 2
VDD
J13T- ON5
1
J11ON3
1
CSH3
VIN
DL5
SY NC
C43
NO_POP
C40
0.1uF
VLC35
0.1uF
C36
0.1uF C34
0.1uF
C33
0.1uF
SC1404 EVB Schematic
C1
10uF/25V
1
2
R18
NO_POP
C12
0.1uF
C10
0.1uF
R21
NO_POP
R1
10
12
C3
0.22uF
R20
NO_POP
R19
NO_POP
J16
3_3V
1
J17
CSL3
1
J18
5V
1
J19
CSH5
1
J20
CSL5
1
J21
CSH3
1
C11
4.7uF/16V
C4
0.22uF
D3
140T3
A C
C26
0.1uF
R16
1k
12
J6
B_JACK_PAIR
POS 1
NEG
2
J7
B_JACK_PAIR
POS
1
NEG
2
R13
2M
1 2
C20
NO_POP
C15
0.22uF C16
0.22uF
D5
140T3
A C
C29
NO_POP
C28
NO_POP
J22
LX3
1J23
LX5
1
C38
1uF
C39
1uF
C22
4.7uF/16V
C2
10uF/25V
1
2
D
Q1
IRF7413
4
1
2
3
5
6
7
8
BST3R
C42
4.7uF/25V
J9
SYNC
1
J24
VIN
1
VDD
J14
VL
1
J10 PS V #
1
C5
10uF/25V
1
2
C6
10uF/25V
1
2
J8
REF
1
D
Q2
IRF7413
4
1
2
3
5
6
7
8
D
Q3
IR F 7413
4
1
2
3
5
6
7
8
3_3V
5V
VL
VIN
REF
VL
+12V
RESET#
D
Q4
IRF7413
4
1
2
3
5
6
7
8
C41
NO_POP
VIN
C37
0.01uF
C17
180uF/4V
J25
+12V
1
J26
GND
1
5V
C27
0.01uF
21© 2005 Semtech Corp. www.semtech.com
SC1404
POWER MANAGEMENT
Evaluation Board Bill of Materials
METIYTQNOITANGISEDREBMUNTRAPNOITPIRCSEDRERUTCAFUNAMMROF
ROTCAF
14 6C,5C,2C,1C520Z601V5Y032MRGV52,Fu01ataruM0121
21 61C,5
1C,4C,3C,V05,Fu22.0
V5Y
cinosanaP508
39CV53,Fu7.4esac_B
4-3C,43C,33C,62C,21C,01C
04C,63C,5
R7X,V05,Fu1.0cinosanaP30
60
522C,11CN052M574YV61,Fu7.4pacavoN2181
631C,41CK101H1CV1JCEV05,Fp001cinosanaP3060
771CR181G0EU-FEEV4,Fu081cinosanaP34
37_esaC_D
891CR151J0EU-FEEV3.6,Fu051cinosanaP3437_esaC_D
952C501C1BF3JCEV61,Fu1cinosanaP6021
0172C,73CK401C1BV1JCEV05
,Fu10.0cinosanaP3060
1183C,93CFu13060
2124CV52,Fu7.4
3111DA45TAB,am002,V03
edonA_Claud
xeteZ32-TOS
412 4D,2D510QB03.R.ICMS
512 5D
,3D3T041SRBMA1,V04
ykttohcS
alorotoMBMS
6116D3T0011SRBMalorotoMBMS
22© 2005 Semtech Corp. www.semtech.com
SC1404
PRELIMINARYPOWER MANAGEMENT
METIYTQNOITANGISEDREBMUNTRAPNOITPIRCSEDRERUTCAFUNAMMROF
ROTCAF
714 4PJ,3PJ,2PJ,1PJgreBniP2
rotcennoC
greB
813 7J,6J,1Jkc
aJananaB
riaP
914272J-8J,5J-2JstnioPtseT
0211L8R6-721RDrotcudnITMS
Hu8.6
scinortlioC
124 4Q,3Q,2Q,1Q3147FRIlennahc-NV03
TEFSOM
lanoitanretnI
reifitceR
8OS
2211RynAmho01ynA3060
324 32R,22R,5R,4RynAmho0ynA3060
422 7R,6R34BF500R2152LSWmhom5elaDyahsi
V2152
525 71R,51R,41R,31R,21RynAmhogeM2ynA3060
62161RynAmhoK1ynA3060
7211WSnoitisop-5
hctiwspiD
ynA
82
1
2L/T5128-ITTrewopsnarT
seigolonhceT
9211USTI4041CShcetmeS
Evaluation Board Bill of Materials Cont.
23© 2005 Semtech Corp. www.semtech.com
SC1404
POWER MANAGEMENT
Evaluation Board Gerber Plots
TT
TT
Topop
opop
op
Inner1Inner1
Inner1Inner1
Inner1 BottomBottom
BottomBottom
Bottom
Inner2Inner2
Inner2Inner2
Inner2
24© 2005 Semtech Corp. www.semtech.com
SC1404
PRELIMINARYPOWER MANAGEMENT
Outline Drawing - TSSOP-28
Land Pattern - TSSOP-28
25© 2005 Semtech Corp. www.semtech.com
SC1404
POWER MANAGEMENT
hcnarBnawiaT 0833-8472-2-688:leT
Fxa0933-8472-2-688:
HbmGdnalreztiwShcetmeS hcnarBnapaJ 0590-8046-3-18:leT
15
90-8046-3-18:xaF
hcnarBaeroK Tle7734-725-2-28:
F6734-725-2-28:xa
).K.U(detimiLhcetmeS 006-725-4971-44:leT
106-
725-4971-44:xaF
eciffOiahgnahS T0380-1936-12-68:le
1380-1936-12-68:xaF
LRASecnarFhcetmeS 00-22-82-961)0(-33
:leT
89-21-82-961)0(-33:xaF
foyraidisbusdenwo-yllohwasiGAlanoitanretnIhcetmeS
.A.S.Uehtnisretrauqdaehstisahhcihw,noitaroproChcetmeS
HbmGynamreGhcetmeS 321-041-1618)0(-94:leT
421-041-1618)0(-94:xaF
Contact Information for Semtech International AG
Outline Drawing - SSOP-28
.281 (7.15)
Z
G
Y
P
(C) 5.50.216
0.65.026
0.43.017
1.65.065
8.80.346
X
INCHES
DIMENSIONS
Z
P
Y
X
DIM
C
G
MILLIMETERS
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
NOTES:
1.
Land Pattern - SSOP-28
