SC1404 Mobile Multi-Output PWM Controller with Virtual Current SenseTM POWER MANAGEMENT Description Features 6 to 30V input range (operation possible below 6V) 3.3V and 5V dual synchronous outputs Fixed-frequency or PSAVE for maximum efficiency over wide load current range 5V/50mA linear regulator 12V/200mA linear regulator TM Virtual Current Sense for enhanced stability Accurate low-loss current limiting Out-of-phase switching reduces input capacitance External compensation supports wide range of output filter components for reduced cost Programmable power-up sequence Power Good output Output overvoltage & overcurrent protection with output undervoltage shutdown 4A typical shutdown current 6mW typical quiescent power The SC1404 is a multiple-output power supply controller designed for battery operated systems. The SC1404 provides synchronous rectified buck converter control for two power supplies. An efficiency of 95% can be achieved. The SC1404 uses Semtech's proprietary Virtual Current SenseTM technology along with external error amplifier compensation to achieve enhanced stability and DC accuracy over a wide range of output filter components while maintaining fixed frequency operation. The SC1404 also provides two linear regulators for system housekeeping. The 5V linear regulator takes its input from the battery; for efficiency, the output is switched to the 5V output when available. The 12V linear regulator output is generated from a coupled inductor off the 5V switching regulator. Control functions include: power up sequencing, soft start, powergood signaling, and frequency synchronization. Line and load regulation is to +/-1% of the output voltage. The internal oscillator can be adjusted to 200 kHz or 300 kHz or synchronized to an external clock. The mosfet drivers provide >1A peak drive current for fast mosfet switching. Applications Notebook and Subnotebook Computers Automotive Electronics Desktop DC-DC Converters The SC1404 includes a PSAVE# input to select pulse skipping mode for high efficiency at light load, or fixed frequency mode for low noise operation. Typical Application Circuit Revision: June 08, 2005 1 www.semtech.com SC1404 POWER MANAGEMENT Absolute Maximum Ratings PRELIMINARY Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. PAR AMETER D ESC R IPTION MAXIMU M U N ITS Supply and Phase Voltages -0.3 to +30 V PHASE3, PHASE5 to GND Phase Voltages -2.0 (transi ent - 100 nsec) V BST3, BST5, D H3, D H5 to GND Boost voltages -0.3 to +36 V Power Ground to Si gnal Ground 0.3 V Logi c Supply -0.3 to +6 V Hi gh-si de Gate D ri ve Supply -0.3 to +6 V Hi gh-si de Gate D ri ve Outputs -0.3 to (+BSTx + 0.3) V Low-si de Gate D ri ve Outputs and C urrent Sense i nputs -0.3 to +(VL + 0.3) V Logi c i nputs/outputs -0.3 to +(VL + 0.3) V ON3, SHD N# to GND -0.3 to +(V+ + 0.3V) V VL, REF Short to GND C onti nuous VD D , V+, PHASE3, PHASE5 to GND PGND to GND VL to GND BST3 to PHASE3; D H3 to PHASE3; BST5 to PHASE5; D H5 to PHASE5 D L3, D L5 to GND C SL5, C SH5, C SL3, C SH3 to GND REF, SYNC , SEQ, PSAVE#, ON5, RESET#, VL, FB3, FB5, C OMP3, C OMP5 to GND REF C urrent +5 mA VL C urrent +50 mA -0.3 to (+VD D + 0.3) V 12OUT to GND 12OUT Short to GND C onti nuous 12V output current +200 mA Juncti on Temperature Range +150 C juncti on to ambi ent 76 C /Watt TS Storage Temperature Range -65 to +200 C TL Lead Temperature +300 C , 10 second max. C 12OUT C urrent TJ Package Thermal Resi stance Electrical Characteristics Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = 0V, VL load = 0mA, REF load = 0mA, PSAVE# = 0V, TA =-40 to 85C. Typical values are at TA = +25C. Circuit = Typical Application Circuit PAR AMETER CONDITIONS MI N T YP MAX UNITS 30.0 V MAIN SMPS CONTR OLLER S Input Voltage Range 6 3V Output Voltage V+ = 6.0 to 30V, 3V load = 0A to current limit 3.23 3.3 3.37 V 5V Output Voltage V+ = 6.0 to 30V, 5V load = 0A to current limit 4.9 5.0 5.1 V Load Regulation Either SMPS, 0A to current limit, PSAVE# = VL -0.4 % Line Regulation Either SMPS, 6.0 < V+ < 30V, PSAVE# = VL 0.05 %/V (c) 2005 Semtech Corp. 2 www.semtech.com SC1404 POWER MANAGEMENT Electrical Characteristics Cont. Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = 0V, VL load = 0mA, REF load = 0mA, PSAVE# = 0V, TA =-40 to 85C. Typical values are at TA = +25C. Circuit = Typical Application Circuit PAR AMETER Current-Limit Thresholds (N ote 2) CONDITIONS MI N T YP MAX UNITS CSHX - CSLX (p ositive current) 40 55 70 mV CSHX - CSLX (negative current) -50 Zero Crossing Threshold CSHX - CSLX PSAVE# = 0V, not tested 5 mV Soft-Star t Ramp Time From enable to 95% full current limit, with resp ect to fOSC 512 clks Oscillator Frequency SYN C = VL SYN C = 0V 220 170 300 200 Maximum Duty Factor SYN C = VL SYN C = 0V 92 94 94 96 % SYN C Inp ut High Pulse N ot tested 300 ns SYN C Inp ut Low Pulse Width N ot tested 300 SYN C Rise/Fall Time N ot tested 200 SYN C Inp ut Frequency Range Current-Sense Inp ut Leakage Current 380 230 240 350 CSH3 = 3.3V, CSH5 = 5.0V 3 kHz kHz 10 A ER R OR AMP DC Loop Gain From internal feedback node to COMP3/COMP5 Gain Bandwidth Product Outp ut Resistance COMP3, COMP5 18 V/V 8 MHz 25 Kohms INTER NAL R EGULATOR AND R EFER ENCE VL Outp ut Voltage VL Undervoltage Lockout Fault Threshold VL Switchover Lockout REF Outp ut Voltage REF Load Regulation (c) 2005 Semtech Corp. SHDN # = V+; 6V < V+ <30V, 0mA <I LOAD< 30mA, ON 3 = ON 5 = 0V 4.6 Falling edge, hysteresis = 0.7V 3.5 Switchover at star tup - rising edge N o external load 5.25 3.7 4.1 4.5 2.45 2.5 2.55 0A < ILOAD < 50A 12.5 0mA < ILOAD < 5mA 50 3 V mV www.semtech.com SC1404 POWER MANAGEMENT Electrical Characteristics Cont. PRELIMINARY Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = 0V, VL load = 0mA, REF load = 0mA, PSAVE# = 0V, TA =-40 to 85C. Typical values are at TA = +25C. Circuit = Typical Application Circuit PARAMETER REF Sink Current REF Fault Lockout Voltage V+ Operating Supply Current V+ Standby Supply Current V+ Shutdown Supply Current Quiescent Power Consumption CONDITIONS MI N 10mV rise in REF voltage T YP MAX 10 Falling edge 1.8 VL switched over to VOUT5, 5V SMPS on, ILOAD5 = ILOAD3 = 0A, PSAVE# = 0V 10 V+ = 6V to 30V, both SMPS off, PSAVE# = 0V; includes current into SHDN# 300 V+ = 6V to 30V, SHDN# = 0V -1 SMPS enabled, No Load on SMPS 3 UNITS A 2.2 V 50 A 15 6 mW FAULT DETECTION Overvoltage Trip Threshold Overvoltage Fault Propagation Delay With respect to unloaded output voltage Output driven 2% above overvoltage trip V 7 10 15 1.5 TH % s Output Undervoltage Threshold With respect to unloaded output voltage 65 75 85 % Output Undervoltage Lockout Time From each SMPS enabled, with respect to f OSC 5000 6144 7000 clks Thermal Shutdown Threshold Typical hysteresis = 10C +150 C RESET# RESET# Trip Threshold RESET# Propagation Delay RESET# Delay Time With respect to unloaded output voltage, falling edge; typical hysteresis = 1% -12 Falling edge, output driven 2% below RESET# trip threshold With respect to fOSC -9 -5 1.5 27,000 32,000 % s 37,000 clks 0.6 V INPUTS AND OUTPUTS Logic Input Low Voltage ON3, PSAVE#, ON5, SHDN#, SYNC (SEQ = REF) Logic Input High Voltage ON3, PSAVE#, ON5, SHDN#, SYNC (SEQ = REF) (c) 2005 Semtech Corp. 4 2.4 V www.semtech.com SC1404 POWER MANAGEMENT Electrical Characteristics Cont. Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = 0V, VL load = 0mA, REF load = 0mA, PSAVE# = 0V, TA =-40 to 85C. Typical values are at TA = +25C. Circuit = Typical Application Circuit PAR AMETER CONDITIONS MI N Inp ut Leakage Current PSAVE#, ON 5, SYN C SEQ = REF Inp ut Leakage Current ON 3 Inp ut Leakage Current SHDN # T YP MAX UNITS -1 +1 A ON 3 = 15V -2 +2 A SHDN # = 15V -1 +10 A 0.4 V 3 Logic Outp ut Low Voltage RESET#, ISIN K = 4mA Logic Outp ut High Current RESET# = 3.5V 1 mA ON 5 Pull-down Resistance ON 5, ON 3 = 0V, SEQ = REF 100 ohms DL3, DH3, DL5, DH5, forced to 2.5V 1 A BST3 to DH3, DH3 to PHASE3, BST5 to DH5, DH5 to PHASE5, VL to DL3, DL3 to PGN D, VL to DL5, DL5 to PGN D 1.5 PHASE3, PHASE5, to GN D 1.0 Gate Driver Sink/Source Current Gate Driver On-Resistance N on-Overlap Threshold Shoot-through (N on-Overlap ) Delay DHx falling edge to DLx rising edge DLx falling edge to DHx rising edge (1V threshold on DHx and DLx, no external cap acitance on DLx or DHx) 10 35 17 75 7 ohms V 25 115 nsec 21 V 30 mA 30 A 12.75 V 12V LINEAR R EGULATOR VDD Shunt Threshold VDD Shunt Current Rising edge, hysteresis = 5% 17 VDD = 20V 5 VDD Leakage Current VDD = 5V, Standby mode 12OUT Outp ut Voltage 0mA < Load < 200mA 11.55 12OUT forced to 11V, VDD = 13V 200 12OUT Current Limit 12OUT Regulation Threshold Quiescent VDD Current 10 12.1 mA Falling edge 11.9 VDD = 18V, run mode, no 12OUT load 80 V 100 A Notes: (1) This device is ESD sensitive. Use of standard ESD handling procedures required. (2) Applicable from 0 to +85C. (c) 2005 Semtech Corp. 5 www.semtech.com SC1404 POWER MANAGEMENT Pin Descriptions Pin # Pin Name PRELIMINARY Pin Functio n Connect to the inductor side of a current sense resistor. 1 CSH3 Current limit sense inp ut for 3V SMPS. 2 CSL3 Outp ut voltage sense inp ut for 3V SMPS. Connect to the outp ut side of a current sense resistor. 3 COMP3 Comp ensation p in and outp ut of the 3.3V SMPS error amp lifier. 4 12OUT 12V internal linear regulator outp ut. 5 VDD Sup p ly voltage inp ut for the 12OUT linear regulator. Also connects internally to a 19V overvoltage shunt regulator clamp . 6 SYN C Oscillator Synchronization and Frequency Select. Tie to VL for 300 kHz op eration; tie to GN D for 200 kHz. Drive externally to synchronize to an external oscillator between 240 kHz and 350 kHz. 7 ON 5 5V ON /OFF Control Inp ut. Connect a 1K-10K ohm resistor in series with ON 5 to allow 5V shutdown on OVP/UV. 8 GN D Low noise Analog Ground and Feedback reference p oint. 9 REF 2.5 V Reference Voltage outp ut. Byp ass to GN D with 1 F minimum. 10 PSAVE# Logic inp ut that disables PSAVE Mode when high. Connect to GN D for normal use. 11 RESET# Active-low timed Reset outp ut. RESET# swings from GN D to VL. RESET# goes high after a fixed 32,000 clock cycle delay following a successful p ower up . 12 COMP5 Comp ensation p in and outp ut of the 5V SMPS error amp lifier. 13 CSL5 Outp ut voltage sense inp ut for 5V SMPS. Connect to the outp ut side of a current sense resistor. 14 CSH5 Current limit sense inp ut for 5V SMPS. Connect to the inductor side of a current sense resistor. 15 SEQ Inp ut that selects SMPS p ower-up sequence and selects monitor voltage(s) used by RESET#. 16 DH5 Gate Drive Outp ut for the 5V, high-side N -Channel switch. 17 PHASE5 18 BST5 19 DL5 20 PGN D 21 VL 5 V internal linear regulator outp ut. For imp roved efficiency, VL is switched to the 5V SMPS outp ut when 5V SMPS is enabled. 22 V+ Battery Voltage inp ut. 23 SHDN # 24 DL3 25 BST3 26 PHASE3 27 DH3 28 ON 3 5V switching node (inductor) connection. Boost cap acitor connection for 5V high-side gate drive. Gate drive outp ut for the 5V low-side synchronous rectifier MOSFET Power Ground. Shutdown control inp ut, active low. Gate drive outp ut for the 3V low-side synchronous rectifier MOSFET. Boost cap acitor connection for 3V high-side gate drive. 3V switching node (inductor) connection. Gate drive outp ut for the 3V high-side N -Channel switch. 3V ON /OFF Control Inp ut. Note: All logic level inputs and outputs are open collector TTL compatible. (c) 2005 Semtech Corp. 6 www.semtech.com SC1404 POWER MANAGEMENT Block Diagram (c) 2005 Semtech Corp. 7 www.semtech.com SC1404 POWER MANAGEMENT Pin Configuration PRELIMINARY Ordering Information Top View C S L3 C OMP3 12OU T VD D SYN C ON 5 GN D 9 10 11 R EF PSAVE# R E S E T# 12 13 14 C OMP5 C S L5 C SH 5 SC1404 1 2 3 4 5 6 7 8 C SH 3 28 27 26 25 24 23 SH D N # 22 V+ 21 20 19 18 17 ON 3 DEVICE PACKAGE SC1404ITSTR TSSOP-28 (1) SC1404ITSTRT TSSOP-28 (1)(2) TEMP. (TAMB) DH3 PH ASE3 Lead-free Option B S T3 D L3 SC1404ISSTR SC1404ISSTRT VL -40 - +85C SSOP-28(1) SSOP-28(1)(2) Lead-free Option PGN D D L5 Note: (1) Only available in tape and reel packaging. A reel contains 2500 devices for TSSOP and 1000 devices for SSOP. (2) Lead-free product. This product is fully WEEE and RoHS compliant. B S T5 PH ASE5 16 DH5 15 SEQ TSSOP-28/SSOP-28 Block Diagram (c) 2005 Semtech Corp. 8 www.semtech.com SC1404 POWER MANAGEMENT Detailed Description Under light load conditions when the PSAVE# pin is low, the SC1404 operates hysteretically in the discontinuous conduction mode to reduce its switching frequency and switching bias current. The switching of the output mosfet does not depend on a given oscillator frequency, but on the hysteretic voltage set around the nominal output voltage. When entering PSAVE# mode (from heavy to light load), if the minimum (valley) inductor current measured at CSHx-CSLx is below the Zero Cross threshold (typically 5 mV) for four switching cycles, the virtual current sense circuitry will shut off and the mode changes to hysteretic mode. As the load current increases, if the minimum (valley) inductor current is above the threshold for four switching cycles, the converter stops psave mode and enters PWM operation. The change in frequency between hysteretic psave and PWM mode provides hysteresis to inhibit chattering between the two modes of operation. The SC1404 is a versatile multiple-output power supply controller for battery operated systems. The SC1404 provides synchronous rectified buck control in fixed frequency forced-continuous (PWM) mode and hysteretic PSAVE mode, for two switching power supplies over a wide load range. Out of phase switching reduces input noise and RMS current, which reduces the input filter inductors and capacitors. The two switchers have on-chip preset output voltages of 5.0V and 3.3V. The control circuitry for each PWM controller includes digital softstart, voltage error amplifier with built-in slope compensation, pulse width modulator, power save, overcurrent, overvoltage and undervoltage fault protection. Two linear regulators and a precision reference voltage are also provided. The 5V/30mA linear regulator (VL) uses battery power to feed the gate drivers. For improved efficiency, VL automatically switches over the +5V converter output if available. The 12V linear regulator supplies up to 200mA. Semtech's proprietary Virtual Current SenseTM provides greater advantages in the aspect of stability and signal-to-noise ratio than the conventional current sense method. Gate Drive / Control The gate drivers on the SC1404 are designed to switch large mosfets. The high-side gate driver must drive the gate of high-side mosfet above the V+ input. The supply for the gate drivers is generated by charging a boostrap capacitor from the VL supply when the low-side driver is on. In continuous conduction mode, the low-side driver output that controls the synchronous rectifier in the power stage is on when the high-side driver is off. Under light load conditions when PSAVE# pin is low, the inductor ripple current will approach the point where it reverses polarity. This is detected by the low-side driver control and the synchronous rectifier is turned off before the current reverses, preventing energy drain from the output. The low-side driver operation is also affected by various fault conditions as described in the Fault Protection section. PWM Control There are two separate PWM control blocks for each switcher. They are switched out-of-phase with each other. This interleaved topology reduces input filter requirements by reducing current drawn from the filter capacitors. To avoid both switchers switching at the same instance, there is a built-in delay between the turn-on of the 3.3V switcher and 5V switcher, the amount of which depends on the input voltage (see Out-of-Phase Switching). Internal Bias Supply The PWM provides two modes of control over the entire load range. The SC1404 operates in forced continuous conduction mode as a fixed frequency peak current mode controller with falling edge modulation. Current sense is done differently than in conventional peak current mode control. Semtech's proprietary Virtual Current SenseTM emulates the necessary inductor current information for proper functioning of the IC. In order to accommodate a wide range of output filters, a COMP pin is also available for compensating the error amplifier externally. A nominal error amplifier gain of 18 improves the system loop gain and the output transient behavior. The VL linear regulator is a 5V output that powers the gate drivers, 2.5V reference and internal controls of the SC1404. The regulator is capable of supplying up to 30mA (including mosfet gate charge current). The VL pin should be bypassed to GND with 4.7uF to supply the large gate drive current pulses. The regulator receives input power from the V+ battery input. Efficiency is improved by providing a bootstrap for the VL output. When the 5V SMPS output voltage reaches 5V, internal circuitry turns on a PMOS device between CSL5 and VL. The internal VL regulator is then disabled, and VL bias is provided by the high efficiency 5V switcher. When operating in continuous conduction mode, the high-side mosfet is turned on at the start of each switching cycle. It is turned off when the desired duty cycle is reached. Active shoot-through protection will delay the lower mosfet turn-on until the phase node drops below 1V. The low-side mosfet remains on until the beginning of the next switching cycle. Again, active shoot-through protection ensures that the low-side mosfet gate voltage drops low before the high-side mosfet turns on. (c) 2005 Semtech Corp. The REF output is accurate to +/- 2% over temperature. It is capable of delivering 5mA max and should be bypassed with 1uF minimum capacitor. Loading the REF pin will reduce the REF voltage slightly as seen in the following table. 9 www.semtech.com SC1404 POWER MANAGEMENT Loadi ng Resi stance (ohm) 511 Vref D evi ati on 8.3mV 2.67K 3.1mV PRELIMINARY 49.9K 0.5mV 255K 0.3mV 1Meg SH D N ON3 ON5 MODE DESCRIPTION Low X X Shutdown Minimum bias current High Low Low Standby VREF and VL regulator enable High High High Run Mode Both SMPS Running 0mV Current Sense (CSH, CSL) Output current of each supply is sensed at the CSH and CSL pins. Overcurrent is reached when the current sense voltage exceeds 55mV typical. On a cycle-by-cycle basis, a positive overcurrent turns off the high-side driver and a negative overcurrent turns off the low-side driver. Power up Controls and Soft Start The user controls the SC1404 RESET# through the SEQ, ON3 and ON5 pins, as shown in the Startup Sequence Chart. At startup, RESET# is held low for 32K switching cycles, and then RESET# is determined by the output voltages and the SEQ pin. Oscillator When the SYNC pin is high the oscillator runs at 300kHz; when SYNC is low the frequency is 200kHz. The oscillator will synchronize to the falling edge of a clock on the SYNC pin with a frequency between 240kHz and 350kHz. In general, 200kHz operation provides highest efficiency, while 300kHz allows for smaller output ripple and/or smaller filter components. To prevent surge currents at startup, each SMPS has a counter and DAC to incrementally raise the current limit (CSH-CSL voltage). The current limit follows discrete steps of typically 25%, 40%, 60%, 80%, and 100%, each step lasting 128 clock cycles. To charge up the output capacitors, inductor current at startup must exceed load current. When the output voltage reaches it's nominal value the SMPS will reduce duty cycle, but the excess LI2 energy of the inductor must flow into the load and output capacitors. If the output capacitor is relatively small, the peak output voltage can approach the overvoltage trip point. To prevent nuisance OVP at startup, the inductance and capacitance must meet the following criteria: Fault Protection In addition to cycle-by-cycle current limit, the SC1404 provides overtemperature, output overvoltage, and undervoltage protection. Overtemperature protection will shut the device down if die temperature exceeds 150C, with 10C hysteresis. If either SMPS output is more than 10% above its nominal value, both SMPS are latched off and the low side mosfets are latched on. To prevent the output from ringing below ground in a fault condition, a 1A Schottky diode should be placed across each output. L MAX V O _ NOM 2 1 . 59 C MIN IL MAX _ OC 2 ILMAX_OC is the maximum inductor current set by the current-limit components, and VO_NOM is the nominal output voltage. Two different levels of undervoltage (UV) are detected. If the output falls 9% below its nominal value, the RESET# output is pulled low. If the output falls 25% below its nominal value, both SMPS are latched off. 12OUT Supply The 12OUT linear regulator is capable of supplying 200mA. The input voltage to the 12OUT regulator is generated by a secondary winding on the 5V SMPS inductor. Both of the latched faults (OVP and UV) persist until SHDN or ON3 is toggled, or the V+ input is brought below 1V. A heavy load on the 12OUT regulator when the 5V SMPS operates in PSAVE mode will cause VDD to sag, causing 12OUT to drop. If 12OUT output drops 0.8% from its nominal value, the 5V SMPS is forced out of PSAVE mode and into PWM mode for several cycles. This recharges the bulk input capacitor on VDD. Shutdown and Operating Modes Holding the SHDN pin low disables the SC1404, reducing the V+ input current to less than 10uA. When SHDN is high, the part enters standby mode where the VL regulator and VREF are enabled. Turning on either SMPS will put the SC1404 in run mode. (c) 2005 Semtech Corp. The 12OUT linear regulator has internal protection to prevent damage under short circuit conditions. Overvoltage protection is provided on the VDD input. If VDD rises above 19V, a 10mA shunt load is applied to VDD to reduce the voltage. The overvoltage threshold has 0.5V hysteresis. 10 www.semtech.com SC1404 POWER MANAGEMENT Startup Sequence Chart SEQ ON3 ON5 R ESET DESCRIPTION REF LOW LOW Follows 3.3V SMPS. Independant start control mode. Both SMPSs off. REF LOW HIGH Low. 5V SMPS ON, 3.3V SMPS OFF. REF HIGH LOW Follows 3.3V SMPS. 3.3V SMPS ON, 5V SMPS OFF. REF HIGH HIGH Follows 3.3V SMPS. Both SMPSs on. GND LOW X Low. Both SMPSs off. GND HIGH HIGH/LOW High after both outputs are in regulation. 5V starts when ON3 goes high. If ON5 = HIGH, 3V is on. If ON5 = LOW, 3V is off. VL LOW X Low. Both SMPSs off. VL HIGH HIGH/LOW High after both outputs are in regulation. 3V starts when ON3 goes high. If ON5 = HIGH, 5V is on. If ON5 = LOW, 5V is off. Applications Information To specify the output capacitance, the allowable output ripple voltage must be determined. Output ripple is often specified at 1% of the output voltage. For the 3.3V output, we selected a maximum ripple voltage of 33mVp-p. The maximum allowable ESR would then be: Reference Circuit Design The schematic for the reference circuit is shown on page 20. The reference circuit is configured as follows: Switching Regulator 1 Switching Regulator 2 VL Regulator 12V regulator Input voltage ESR MAX = V O / IO = 33mV / 1.5 A = 22m Vout1 = 3.3V @ 6A Vout2 = 5.0V @ 6A Vout3 = 5.0V @ 30mA Vout4 = 12.0V @ 200mA Vin = 7 to 21V Panasonic SP Polymer Aluminum capacitors are a good choice. For this design, use one 180uF, 4V device, with ESR of 15m. The output capacitor must support the inductor RMS ripple current. To check the actual ripple versus the capacitor's RMS rating: Designing the Output Filter IRMS_ actual= Before calculating the filter inductance and capacitance, an acceptable inductor ripple current is determined. Ripple current is usually set at 10% to 20% of the maximum load. However, increasing the ripple current allows for a smaller inductor and will also quicken the output transient response. In this example, we set the ripple current to be 25% of maximum load. I O = 25 % x 6 A = 1 . 5 A The inductance is found from ripple current, frequency, input voltage, and output voltage. Minimum required inductance is found at maximum Vin, where ripple current is the greatest. L min = Vo x This is much less than the capacitor's ripple rating of 3.3A. Choosing the Main Switching mosfet The IRF7143 is used in the reference design. Before choosing the main (high-side) mosfet, we need to check three parameters: voltage, power, and current rating. The maximum drain to source voltage of the mosfet is mainly determined by the switcher topology. With a buck topology, (1 - Vo / Vin ) = 6 . 18 uH F x Io VDS _ MAX = VIN _ MAX = 21 V For the reference design, the Coiltronics DR127-6R8 is used. This is acceptable for the 3V output, which uses a simple inductor. The 5V inductor must have a 12V winding with a turns ratio of 2.2:1. For the 5V inductor, the TTI-8215 from Transpower Technologies is used, which has 5V inductance of 6.4uH. (c) 2005 Semtech Corp. IO 1.5A = = 0.43A 12 12 The IRF7413 is a 30V device, which allows for 70% derating at 21V operation. The mosfet power dissipation has three components: conduction losses, switching losses, and gate drive losses. The conduction loss is determined using the RMS mosfet current; the equation is 11 www.semtech.com SC1404 POWER MANAGEMENT PRELIMINARY TJ = 0.556W 50C/W = 27.8 . shown below. The mosfet current is a trapezoid waveform with values equal to: I L - 2 I MIN = I LOAD I MAX = I LOAD Vo (1- D) IL = fs L Designing the Loop Vo D = Vin D (I MIN I RMS = This is an acceptable temperature rise, so no special heat sinking is required. I L + 2 2 + I MIN I MAX + I MAX 2 A good loop design is a combination of the power train and compensation design. In the SC1404, the control-to-output/power train response is dominated by the load impedance, the inductor, output capacitance, and the ESR of the output caps. The low frequency gain is dominated by the output load impedance and the effective current sense resistor. Inherent to Virtual Current SenseTM, there is one additional low frequency pole sitting between 100Hz and 1kHz and a zero between 15kHz and 25kHz. he output of error amplifier COMP pin is available for external compensation. A traditional pole-zero-pole compensation is not necessary in the design using SC1404, a simple high frequency pole is usually sufficient. ) As input voltage decreases, the duty cycle increases and the ripple current decrease, and overall the RMS mosfet current will increase. The conduction losses are then given by the formula below, where Rds(on) is 18m-ohm for the IRF7413 at room temperature. Note that Rds(on) increases with temperature. PCONDUCTION = Rds(on) IRMS 2 The mosfet switching loss is estimated according to: P SWITCHING = C RSS V IN 2 f S I OUT Single-Pole Compensation Method IG Given parameters: Vin = 19V, Vout = 3.3V @ 2.2A, Output impedance, Ro = 3.3V/2.2A = 1.5 , Panasonic SP cap, Co = 180uF, Resr = 15 m , Output inductor, Lo = 4.7uH Switching frequency, Fs = 300kHz Crss is the mosfet's reverse transfer capacitance, 240pF for IRF7413. Ig is the gate driver current, which is 1A for SC1403. The mosfet gate drive loss is estimated from: PGATE = 1 2 2 CG Vgfs fS Cg is the effective gate capacitance, equal to the Total Gate Charge divided by VGS, from the vendor datasheet, and is 7.9nF for the IRF7413. Vgfs is the final gate-source voltage, 5V in this case. Simulated Control-to-Output gain & phase response (up to 100kHz) is plotted below. The total mosfet loss is the sum of the three loss components. PTOTAL_DISS = PCONDUCTION + PSWITCHING + PGATE 50 40 30 The mosfet dissipation under conditions of 15V input, 6A load, and ambient temperature of 25C, can be determined as: IL = 1.26A IMAX = 6.63A 10 Gain (dB) DNOM = 0.22 IMIN = 5.37A 20 0 -10 IRMS = 4.88A -20 -30 Rds(on) (100C) = 18 mohm PCONDUCTION = 429mW PSWITCHING = 97mW -40 -50 1.00E+02 1.00E+03 1.00E+04 1.00E+05 f (Hz) PGATE = 30mW PTOTAL_DISS = 429 + 97 + 30 = 556 mW The junction temperature rise resulting from the power dissipation is calculated as: T J = PT JA PT is the total device dissipation, and JA is the package thermal resistance, which is 50C/W for the IRf7413. The junction temperature rise is then: (c) 2005 Semtech Corp. 12 www.semtech.com SC1404 POWER MANAGEMENT Applications Information Information Applications 200 200 150 150 100 100 Phase (deg) 50 Phase (deg) 50 0 -50 -50 -100 -100 -150 -150 -200 1.00E+02 -200 1.00E+02 0 1.00E+03 1.00E+04 1.00E+03 1.00E+04 1.00E+05 f (Hz) 1.00E+05 f (Hz) Single-pole compensation is achieved using a 100pF capacitor from the COMP pin to ground. The simulated feedback gain & phase response (up to 100kHz) is plotted below. Measured Control-to-Output gain & phase response (up to 100kHz) is plotted below. 50 25 40 20 30 15 10 10 Gain (dB) Gain (dB 20 0 -10 5 0 -20 -5 -30 -10 -40 -15 -50 1.00E+02 1.00E+03 1.00E+04 1.00E+02 1.00E+05 1.00E+03 1.00E+04 1.00E+05 f (Hz) f (Hz) 0 -10 -20 Phase (deg) -30 -40 -50 -60 -70 -80 -90 -100 1.00E+02 1.00E+03 1.00E+04 1.00E+05 f (Hz) Measured feedback gain & phase responses (up to 100kHz) is plotted below. (c) 2005 Semtech Corp. 13 www.semtech.com SC1404 POWER MANAGEMENT Applications Information PRELIMINARY . 180 160 25 140 20 120 Phase (deg) 15 Gain (dB) 10 5 100 80 60 40 0 20 -5 0 -10 -20 -15 1.00E+02 1.00E+02 1.00E+03 1.00E+04 1.00E+03 1.00E+05 1.00E+04 1.00E+05 f (Hz) f (Hz) Measured overall gain & phase response of the single-pole compensation using SC1404 is plotted below. 20 180 -40 160 -60 140 -80 120 -100 Phase (deg) Phase (deg) 0 -20 -120 -140 -160 -180 1.00E+02 100 80 60 40 1.00E+03 1.00E+04 1.00E+05 20 Frequency (Hz) 0 Simulated overall gain & phase responses (up to 100kHz) is plotted below. -20 1.00E+02 1.00E+03 1.00E+04 1.00E+05 f (Hz) 80 60 40 Output C ap Recommended C ompensati on C ap Value < = 180F 100pF > 180F & <1000F 200pF >1000F 330pF Gain (dB) 20 0 -20 -40 -60 -80 1.00E+02 1.00E+03 1.00E+04 1.00E+05 f (Hz) (c) 2005 Semtech Corp. 14 www.semtech.com SC1404 POWER MANAGEMENT Applications Information As the input voltage is reduced, the duty cycle of both converters increases. At input voltages less than 8.3V, it is impossible to prevent overlap regardless of the phase between the converters. Overlap is seen in the following figure. Input Capacitor Selection and Out-of-phase Switching The SC1404 uses out-of-phase switching between the two converters to reduce input ripple current, allowing smaller cheaper input capacitors compared to in-phase switching. period The figure below shows in-phase switching. I3in is the input current for the 3V converter, I5in is the input current for the 5V converter. The two converters start each switching cycle simultaneously, causing a significant amount of overlap and a high peak current. The total input current the third waveform, which shows how the two currents add together. The fourth waveform is current in and out of the input capacitors. phase lead D3 I5in D5 Iin D3 D5 average I3in 0 I5in 0 Iin Icap average 0 From an input filter standpoint it is desirable to minimize the overlap; but it is also desirable to keep the turn-on and turn-off transitions of the two converters separated in time, to minimize interaction between the two converters. The SC1404 keeps the turn-on and turn-off transitions separated in time by changing the phase between the converters depending on the input voltage. The following table shows the phase relationship between 3V and 5V turn-on, based on input voltage. 0 Icap The next figure shows out-of-phase switching. The 3V and 5V pulses are spaced apart, so there is no overlap. This gives two benefits; the peak current is reduced, and the effective switch frequency is raised. Both of these make filtering easier. The third waveform is the total input current, and the fourth waveform shows the current flowing in and out of the input capacitors. The rms value of the capacitor current is significantly lower than the inphase case, which allows for smaller capacitors. D3 I3in D5 Iin I5in (c) 2005 Semtech Corp. P h ase l ead f r om 3V t o 5V Vin > 9.6 V 41% of switching period N o overlap between 3.3V and 5V 9.6V > Vin > 6.7V 59% of switching period Small overlap to prevent simultaneous 3V/5V switching 6.7 > Vin 64% of switching period Small overlap to prevent simultaneous 3V/5V switching average 0 Icap In p u t v ol t ag e 0 15 www.semtech.com SC1404 POWER MANAGEMENT Typical Characteristics PRELIMINARY IF_AVG Input ripple current can be calculated from the following equations. D3 = 3.3V/V IN = 3V duty cycle where 100nsec is the estimated time between the mosfet turnoff and the Schottky diode turn-on and Ts = 3.33uS.A Schottky diode with a forward current of 0.5A is sufficient for this design. D5 = 5V/V IN = 5V duty cycle I3 = 3V DC load current I5 = 5V DC load current Operation below 6V input The SC1404 will operate below 6V input voltage with careful design, but there are limitations. The first limitation is the maximum available duty cycle from the SC1404, which limits the obtainable output voltage. The design should minimize all circuit losses through the system in order to deliver maximum power to the output. DOVL = overlapping duty cycle of the 3V and 5V pulses (varies according to input voltage) DOVL = 0 for 9.6V VIN DOVL = (D5 - 0.41) for 6.7V VIN < 9.6V DOVL = (D5 - 0.36) for VIN < 6.7 A second limitation with operation below 6V is transient response. When load current increases rapidly, the output voltage drops slightly; the feedback loop normally increases duty cycle briefly to bring the output voltage back up. If duty cycle is already near the maximum limit, the duty cycle cannot increase enough to meet the demand, and the output voltage sags more than normal. This problem can not be solved by changing the feedback compensation, it is a function of the input voltage, duty cycle, and inductor and capacitor values. IIN = Average DC input current IIN = I3 D3 + I5 D5 ISW_RMS = RMS current drawn from VIN ISW_RMS2 = D3 I32 + D5 I52 + 2 DOVL I3 I5 IRMS_CAP = I SW_RMS 2 + IIN_AVE 2 If an application requires 5V output from an input voltage below 6V, the following guidelines should be used: 1 - Set the switching frequency to 200 kHz (Tie SYNC to ground). This increases the maximum duty cycle compared to 300 kHz operation. The worst-case ripple current varies by application. For the case 6A load on both outputs, the worst-case ripple occurs at Vin = 7.5V, and the rms capacitor current is 4.2A. The reference design uses 4 paralleled ceramic capacitors, (Murata GRM32NF51E106Z, 10 uF 25V, size 1210). Each capacitor is rated at 2.2A. 2 - Minimize the resistance in the power train. Select mosfets, inductor, and current sense resistor to provide the lowest resistance as is practical. Choosing Synchronous mosfet and Schottky Diode 3 - Minimize the pcb resistance for all traces carrying high current. This includes traces to the input capacitors, mosfetS and diodes, inductor, current sense resistor, and output capacitor. Since this is a buck topology, the voltage and current ratings of the synchronous mosfet are the same as the main switching mosfet. It makes sense cost- and volume-wise to use the same mosfet for the main switch as for the synchronous mosfet. Therefore, IRF7413 is used again in the design for synchronous mosfet. 4 - Minimize the resistance between the SC1404 circuit and the power source (battery, battery charger, AC adaptor). To improve overall efficiency, an external Schottky diode is used in parallel with the low side mosfet. The freewheeling current enters the Schottky diode instead of the inefficient body diode of the synchronous mosfet. It is really important when laying out the board to place the synchronous mosfet and Schottky diode close to each other to reduce the current ramp-up and ramp-down time due to parasitic inductance between the channel of the mosfet and the Schottky diode. The current rating of the Schottky diode can be determined by the following equation: (c) 2005 Semtech Corp. 100n =I = 0.2A LOAD TS 5 - Use low ESR capacitors on the input to prevent the input voltage dropping during on-time. 6 - If large load transients are expected, high capacitance and low ESR capacitors should be used on both the input and output. 16 www.semtech.com SC1404 POWER MANAGEMENT 5V Start-up with slow Vin ramp. The following guidelines for 12V loading apply to the typical circuit, page 22. Proper startup of the 5V output can be hampered by slow dV/dt on the input. The SC1404 will power up and attempt to generate an output when the input voltage exceeds 4.5 volts. If the input has a slow dV/dt, the input voltage will not rise significantly during the start-up sequence, leading to two conditions. First, the VL supply can be hundreds of mV below 5V, since the input may not yet be above 5V. Second, the duty cycle will be at maximum, leading to very small off-times. These two conditions tend to reduce the boost voltage; if continued indefinitely, the boost capacitor may be unable to recharge fully, and eventually the high-side driver loses its boost bias. To avoid this the following steps should be taken: 1. If possible the dV/dt of the input supply should exceed .02V/ usec. This dV/dt condition only applies when the input passes between 4 and 6 volts, the point at which the SC1404 begins a startup sequence. An alternative is to make sure the input voltage reaches 6 volts within 100 usec of SC1404 startup at approximately 4.2 volts. This is sufficiently fast to allow VL and duty cycle to achieve normal levels and prevents the boost voltage from falling. Vin range 12V load conditions >10V 12V load < 1/2 * 5V load 12V load = 200mA max 7V - 10V 12V load < 1/2 * 5V load Linearly derate 12V load: 200mA at 10V 100mA at 7V 6V - 7V 12V load < 1/2 * 5V load Linearly derate 12V load: 100mA at 10V 25mA at 7V 2. If the input dV/dt cannot meet condition 1, the startup of the SC1404 should be delayed until the input voltage reaches 6V. This can be done using either the SHDN# or ON5 pin. If the dV/dt is moderate (slews from 4 to 6 volts in several msecs), an RC delay on either the SHDN# or ON5 pin should be enough to delay turn-on until the input reaches 6V. 3. For slow dV/dt on the input (10's of msec), the SC1404 should be held off until the input reaches 6V. This can be done using a comparator or external logic to hold the SHDN# or ON5 pin low until the input reaches 6V. 12V Load Limitations The 12V regulator derives input power from a secondary winding on the 5V inductor. During the 5V off-time, the inductor transfers energy from the 5V winding to the secondary winding, thereby providing a crudely regulated 15V that feeds the 12V regulator. Note that duty cycle increases at low input voltages, and therefore the on-time decreases. At low input voltages, the duty cycle increases to maintain the 5V output. The off-time consequently decreases, which has two detrimental effects. It allows less time to recharge the raw 15V capacitor, and it also raises the peak 15V current required to maintain the average 12V load. The 15V winding needs higher peak current, delivered in less time. But the stray (leakage) inductance of the inductor resists rapid changes in winding current, and ultimately limits how much current can be drawn from 15V before the voltage falls. (c) 2005 Semtech Corp. 17 www.semtech.com SC1404 POWER MANAGEMENT PRELIMINARY Typical Characteristics Overvoltage Test Measuring the overvoltage trip point can be problematic. Any buck converter with synchronous mosfets can act as a boost converter, sending energy from output to input. In some cases the energy sent to the input is enough to drive the input voltage beyond normal levels, causing input overvoltage. To prevent this, enable the SC1404 PSAVE# feature, which effectively disables the low side mosfet drive so that little energy, if any, is transferred back to the input. 6V 0.1 1 10 6V 10V 19V Efficiency (%) Efficiency (%) 100 95 90 85 80 0.01 0.1 1 10 Load Current (A) to DVM Output under test D1 e.g. 1N4004 VL R1 75 1/2W 1K ON5 to DVM (c) 2005 Semtech Corp. 60 5V Efficiency Increase Lab Supply 1 in very small increments, monitoring both ON5 and the output under test. The overvoltage trip point is the highest voltage seen at the output before ON5 pulls low (approximately 0.3V). Do not record the voltage seen at the output after ON5 has pulled low; when ON5 pulls low, the current flowing in D1 changes, corrupting the voltage seen at the output. Lab Supply 2 70 Load Current (A) Slowly increase Lab Supply 1 until the output under test rises slightly above it's normal DC level. As Lab Supply 1 increases, switching activity at the phase node will cease. The ON5 pin should remain above 4V. SC1404 Evaluation Board 80 0.01 Set Lab Supply 2 to provide 10V at the SC1404 input. The phase node of the output being tested should show some switching activity. The ON5 pin should be above 4V. R2 470 1/2W 90 50 Initial conditions: Both lab supplies set to zero volts No load connected to 3V or 5V PSAVE# enabled (PSAVE# tied to GND) ON5 enabled ON3 enabled DVMs monitoring ON5 and the output under test. Oscilloscope probe connected to Phase Node of the output under test (not strictly required). Vin 19V 100 Semtech recommends the following circuit for measuring the overvoltage trip point. D1 prevents the output voltage from damaging lab supply 1. R1 limits the amount of energy that can be cycled from the output to the input. R2 absorbs the energy that might flow from output to input, and D2 protects lab supply from possible damage. The ON5 signal is monitored to indicate when overvoltage occurs. D1 e.g. 1N4004 10V 3.3V Efficiency Lab Supply 1 18 www.semtech.com SC1404 POWER MANAGEMENT Layout Guidelines b. Current Sense. As with any high frequency switching regulator design, a good PCB layout is essential to optimize performance of the converter. Before starting pcb layout, a careful layout strategy is strongly recommended. See the pcb layout in the SC1404 Evaluation Kit manual for example. In most applications, FR4 board material with 4 or more layers and at least 2-ounce copper is recommended(for output current up to 6A). Use at least one inner layer for ground connection. It is good practice to tie signal ground and power ground together at one single point so that the signal ground is not easily contaminated. Also be sure that high current paths have low inductance and resistance by making trace widths as wide as possible and lengths as short as possible. Use low-impedance bypassing for lines that pull large amounts of current in short periods of time. The following step by step layout strategy is recommended. Minimize the length of current sense signal traces. Keep them less than 15mm. Kelvin connections should be used; try to keep the traces parallel to each other and route them close to each other as much as possible. Even though SC1404 implements Virtual Current Sense scheme, the current sense signal is sampled by the SC1404 to determine the PSAVE threshold. See the following figure for a Kelvin connection of the current sense signal. L1 Step #1. Power train components placement. SC1404 a. Power train arrangement. CSH CSL Rcs Place power train components first. The figure below shows the recommended power train arrangement. Q1 is the main switching mosfet, Q2 is the low side mosfet, D1 is the Schottky diode and L1 is the output inductor. Q1 c. Gate Drive. D1 L1 SC1404 has built-in gate drivers capable of sinking/sourcing 1A peaks. Upper gate drive signals are noisier than the lower ones. Therefore, place them away from sensitive analog circuitries. Make sure the lower gate traces are as close as possible to the IC pins and both upper and lower gate traces as wide as possible. Q2 Step #2: PWM controller placement (pins) and signal ground island. The phase node is generally the largest source of noise in the converter circuit since it switches at very high rate of speed. The phase node connections should be kept to a minimum size consistent with its connectivity and current carrying requirements. Place the Schottky diode as close to the phase node as possible to minimize the trace inductance between it and the low side mosfet, to reduce the efficiency loss due to the current ramp-up and down time. This is important when the converter needs to handle high di/dt requirements. (c) 2005 Semtech Corp. Connect all analog grounds to a separate solid copper island plane, which connects to the SC1404's GND pin. This includes REF, COMP3, COMP5, SYNC, ON3, ON5, PSV# and RESET#. Step #3: Ground plane arrangement. There are several ways to tie the different grounds together. Since this is a buck topology converter, the output ground is relatively quieter than the input ground. Therefore connect analog ground to power ground at the output side. Often it is useful to use a separate ground symbol for the two grounds, and tie the two grounds together at a single point through a 0 resistor. The power ground for the input side and the power ground for the output side is the same ground and they can be tied together using internal planes. 19 www.semtech.com SHDN# T-ON5 ON3 SYNC GND +12V J15 1 1 1 1 J9 1 J26 1 J25 POS J13 J5 GND C18 CSL3 1 J17 NO_POP 180uF/4V 3_3V 1 J16 C17 GND 4.7uF/16V D2 C22 GND 3_3V C39 1uF +12V J11 1 B_JACK_PAIR J6 GND J4 C40 0.1uF C29 NO_POP R18 NO_POP R23 0 ohm 0.005 R6 1 CSH3 1 D3 140T3 2 D C35 0.1uF 2M R13 SYNC R19 NO_POP J21 6.8uH L1 LX3 1 J22 IRF7413 Q2 1 4 2 N EG 3_3V 1 J3 1 J2 1 2 N EG 2 1 C 30BQ 015 A 1 2 3 VIN C A 5 6 7 8 D 0.01uF C37 C43 NO_POP IR F 7413 4 CSH3 C36 0.1uF Q3 LX3 10 R1 0.22uF C15 DL3 U1 C27 0.01uF T-ON5 1k ON3 COMP3 SHDN# R16 DH3 BST3 4.7uF/35V C9 J27 V+ R4 0 C10 0.1uF V+ VIN VIN VDD C11 0 R5 BAT54A D1 4.7uF/16V SC1404ITS C SH 3 1 C2 10uF/25V C SL3 2 1 3 C1 10uF/25V 1 C OM P3 1 12O U T 4 C3 0.22uF 28 R U N /O N 3 1 27 DH3 5 5 6 7 8 1 2 3 1 2 26 VDD 2 24 BST 3R 25 BST3 PH ASE3 6 2 23 D L3 SYN C J24 VL 2M 2 R15 2M 2 2M 2 R14 R17 2M 2 R12 REF VL DIP_SW5_PTH S1 1 1 1 1 PSV# 1uF/16V C25 JP3 4 0.22uF C16 JP2 SEQ LX5 BST5 DH5 Q1 4 IRF7413 JP1 C12 0.1uF DL5 RESET# COMP5 20 PGN D VIN 18 1 PSAVE 10 VL CSH5 Q4 D5 0.1uF C26 140T3 D IRF7413 D C4 0.22uF 1 2 C28 NO_POP R21 NO_POP R22 0 Ohm T/L2 TTI8215 VDD JP4 C42 C20 C33 0.1uF CSL5 1 J20 NO_POP C19 150uF/6.3V 0.005 R7 4.7uF/25V D6 MBRS1100T3 C6 10uF/25V SC1404 EVB Schematic CSH5 1 J19 NO_POP R20 J23 LX5 C5 10uF/25V C34 0.1uF 1 1 2 7 POS R ESET 11 4 6 5 1 10 2 1 J1 2 1 22 V+ SH D N T IM E /O N 5 7 1 12 8 7 6 5 3 2 1 8 7 6 5 3 2 1 2 17 PH ASE5 C OM P5 19 R EF C A BST 5R 16 DH5 C SL5 13 SEQ 21 VL GND 8 15 C SH 5 14 D L5 9 2 1 BST5 5 4 3 2 1 2 1 C13 100pF J18 30BQ015 D4 5V 1 5V C38 1uF 1 5V POS 1 J8 REF VL VL PSV# REF J10 J14 1 1 1 RESET# J12 RESET# J7 B_JACK_PAIR C14 100pF COMP3 COMP5 C41 NO_POP C A VIN 1 2 POWER MANAGEMENT Evaluation Board Schematic 6 7 8 9 10 2 20 1 NEG (c) 2005 Semtech Corp. 2 B_JACK_PAIR SC1404 PRELIMINARY www.semtech.com SC1404 POWER MANAGEMENT Evaluation Board Bill of Materials ITEM QT Y DESIGNATION 1 4 C1,C2,C5,C6 2 1 PAR T NUMBER GRM230Y5V106Z025 DESCR IPTION MANUFACTUR ER FOR M FACTOR 10uF, 25V Murata 1210 C3, C4, C15, C16 0.22uF, 50V, Y5V Panasonic 805 3 C9 4.7uF, 35V 4 C10,C12,C26,C33,C34,C35,C36,C40 0.1uF,50V, X7R Panasonic 0603 5 C11,C22 Y475M250N 4.7uF, 16V N ovacap 1812 6 C14,C13 ECJ1VC1H101K 100pF, 50V Panasonic 0603 7 C17 EEF-UE0G181R 180uF, 4V Panasonic D_Case_7343 8 C19 EEF-UE0J151R 150uF, 6.3V Panasonic D_Case_7343 9 C25 ECJ3FB1C105 1uF, 16V Panasonic 1206 10 C37,C27 ECJ1VB1C104K 0.01uF, 50V Panasonic 0603 11 C39,C38 1uF 12 C42 4.7uF, 25V 13 1 D1 BAT54A 14 2 D2, D4 30BQ015 15 2 D3, D5 MBRS140T3 16 1 D6 MBRS1100T3 (c) 2005 Semtech Corp. 30V, 200ma, dual C_Anode 40V, 1A Schottky 21 B_case 0603 Zetex SOT-23 I. R . SMC Motorola SMB Motorola SMB www.semtech.com SC1404 POWER MANAGEMENT Evaluation Board Bill of Materials Cont. DESIGNATION PRELIMINARY ITEM QT Y 17 4 JP1, JP2, JP3, JP4 2 Pin Berg Connector 18 3 J1, J6, J7 Banana Jack Pair 19 24 J2-J5, J8-J27 Test Points 20 1 L1 DR127-6R8 SMT Inductor 6.8uH Coiltronics 21 4 Q1, Q2, Q3, Q4 IRF7413 30V N-channel MOSFET International Rectifier SO8 22 1 R1 Any 10ohm A ny 0603 23 4 R4, R5, R22, R23 Any 0ohm A ny 0603 24 2 R6, R7 WSL2512R005FB43 5mohm Vishay Dale 2512 25 5 R12, R13, R14, R15, R17 Any 2Megohm A ny 0603 26 1 R16 Any 1Kohm A ny 0603 27 1 SW1 5-position Dipswitch Any 28 1 T/L2 TTI-8215 Transpower Technologies 29 1 U1 SC1404ITS Semtech (c) 2005 Semtech Corp. PART NUMBER 22 DESCRIPTION MANUFACTURER FORM FACTOR Berg www.semtech.com SC1404 POWER MANAGEMENT Evaluation Board Gerber Plots Inner2 To p Bottom Inner1 (c) 2005 Semtech Corp. 23 www.semtech.com SC1404 POWER MANAGEMENT Outline Drawing - TSSOP-28 PRELIMINARY Land Pattern - TSSOP-28 (c) 2005 Semtech Corp. 24 www.semtech.com SC1404 POWER MANAGEMENT Outline Drawing - SSOP-28 Land Pattern - SSOP-28 X DIM (C) G C G P X Y Z Z Y DIMENSIONS INCHES MILLIMETERS .281 .216 .026 .017 .065 .346 (7.15) 5.50 0.65 0.43 1.65 8.80 P NOTES:1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. Contact Information for Semtech International AG Taiw an Branch Korea Branch Shanghai Office Tel: 886-2-2748-3380 Fax: 886-2-2748-3390 Tel: 81-3-6408-0950 Fax: 81-3-6408-0951 Tel: 82-2-527-4377 Fax: 82-2-527-4376 Semtech Limited (U.K.) Tel: 44-1794-527-600 Fax: 44-1794-527-601 Tel: 86-21-6391-0830 Fax: 86-21-6391-0831 Semtech France SARL Tel: 33-(0)169-28-22-00 Fax: 33-(0)169-28-12-98 Semtech Germany GmbH Tel: 49-(0)8161-140-123 Fax: 49-(0)8161-140-124 Semtech International AG is a wholly-owned subsidiary of Semtech Corporation, which has its headquarters in the U.S.A. (c) 2005 Semtech Corp. Semtech Sw itz erland GmbH Japan Branch 25 www.semtech.com