MR25H40CDFR - Everspin Technologies, Inc.

MR20H40 / MR25H40

MR20H40 / MR25H40 Revision 8, 5/2013

MR20H40 - 50MHz/20ns tSCK (Commercial and Industrial Temp Range) 4Mb SPI Interface MRAM

• No write delays

• Unlimited write endurance

• Data retention greater than 20 years

• Automatic data protection on power loss

• Fast, simple SPI interface, up to 50 MHz clock rate with MR20H40.

• 3.0 to 3.6 Volt power supply range

• Low-current sleep mode

• Commercial, Industrial and AEC-Q100 Grade 1 (-40 to 125°C) tem-

perature range options.

• Available in 8-pin DFN or 8-pin DFN Small Flag, RoHS-compliant

packages.

• Direct replacement for serial EEPROM, Flash, and FeRAM

MR2xH40 is a family of 4,194,304-bit magnetoresistive random access memory (MRAM) devices

organized as 524,288 words of 8 bits. They are the ideal memory solution for applications that must

store and retrieve data and programs quickly using a small number of I/O pins. They have serial EE-

PROM and serial Flash compatible read/write timing with no write delays and unlimited read/write

endurance. Unlike other serial memories, with the MR2xH40 family both reads and writes can occur

randomly in memory with no delay between writes.

The MR2xH40 family provides highly reliable data storage over a wide range of temperatures. The

MR20H40 (50MHz) is oered with Commercial (0 to +70 °C) and Industrial (-40° to +85 °C) range

options. The MR25H40 (40MHz) is oered with Industrial and AEC-Q100 Grade 1 (-40°C to +125 °C)

operating temperature range options.

Both are available in a 5 x 6mm, 8-pin DFN package. The pinout is compatible with serial SRAM,

EEPROM, Flash, and FeRAM products.

RoHS

8-DFN

8-DFN Small Flag

FEATURES

DESCRIPTION

MR25H40 - 40MHz/25ns tSCK (Industrial and AEC-Q100 Grade 1 Temp Range) 4Mb SPI Interface MRAM

For more information on product options, see “Table 16 – Ordering Part Numbers” on page 24.

MR20H40 / MR25H40

2MR20H40 / MR25H40 Revision 8, 5/2013

TABLE OF CONTENTS

OVERVIEW ............................................................................................................................................5

Figure 1 – Block Diagram ........................................................................................................................................... 5

System Conguration .....................................................................................................................5

Figure 2 – System Conguration ............................................................................................................................. 5

Pin Functions ...................................................................................................................................6

Figure 3 – DFN Package Pin Diagram (Top View) .............................................................................................. 6

Table 1 – Pin Functions ............................................................................................................................................... 6

SPI COMMUNICATIONS PROTOCOL ...................................................................................................7

Command Codes .............................................................................................................................. 7

Table 2 – Command Codes ....................................................................................................................................... 7

Status Register, Memory Protection and Block Write Protection ................................................7

Table 3 – Status Register Bit Assignments ........................................................................................................... 7

Memory Protection Modes .............................................................................................................8

Table 4 – Memory Protection Modes .................................................................................................................... 8

Block Protection Modes ..................................................................................................................8

Table 5 – Block Memory Write Protection ............................................................................................................ 8

Read Status Register (RDSR) ...........................................................................................................9

Figure 4 – Read Status Register (RDSR) Timing .................................................................................................. 9

Write Enable (WREN) .......................................................................................................................9

Figure 5 – Write Enable (WREN) Timing ................................................................................................................ 9

Write Disable (WRDI) .................................................................................................................... 10

Figure 6 – Write Disable (WRDI) Timing ..............................................................................................................10

Write Status Register (WRSR) ...................................................................................................... 10

Figure 7 – Write Status Register (WRSR) Timing ..............................................................................................10

Read Data Bytes (READ) ............................................................................................................... 11

Figure 8 – Read Data Bytes (READ) Timing ........................................................................................................ 11

MR20H40 / MR25H40

MR20H40 / MR25H40 Revision 8, 5/2013

Write Data Bytes (WRITE) ............................................................................................................. 11

Figure 9 – Write Data Bytes (WRITE) Timing ......................................................................................................12

Enter Sleep Mode (SLEEP) ............................................................................................................ 12

Figure 10 – Enter Sleep Mode (SLEEP) Timing ..................................................................................................12

Exit Sleep Mode (WAKE) ............................................................................................................... 13

Figure 11 – Exit Sleep Mode (WAKE) Timing .....................................................................................................13

ELECTRICAL SPECIFICATIONS ......................................................................................................... 14

Absolute Maximum Ratings ........................................................................................................ 14

Table 6 – Absolute Maximum Ratings ..............................................................................................................14

Table 7 – Operating Conditions .............................................................................................................................15

Table 8 – DC Characteristics ....................................................................................................................................15

Table 9 – Power Supply Characteristics ..............................................................................................................16

TIMING SPECIFICATIONS ................................................................................................................. 17

Capacitance ................................................................................................................................... 17

Table 10 – Capacitance ............................................................................................................................................. 17

AC Measurement Conditions ....................................................................................................... 17

Table 11 – AC Measurement Conditions ............................................................................................................17

Figure 12 – Output Load for Impedance Parameter Measurements .......................................................17

Figure 13 – Output Load for all Other Parameter Measurements .............................................................17

Power Up Timing .......................................................................................................................... 18

Table 12 – Power-Up Timing ................................................................................................................................... 18

Figure 14 – Power-Up Timing ................................................................................................................................ 18

AC Timing Parameters .................................................................................................................. 19

Table 13 – MR20H40 (fSCK = 50MHz) AC Timing Parameters .....................................................................19

Table 14 – MR25H40 (fSCK = 40MHz) AC Timing Parameters .....................................................................20

Table of Contents (Cont’d)

MR20H40 / MR25H40

4MR20H40 / MR25H40 Revision 8, 5/2013

Figure 15 – Synchronous Data Timing ................................................................................................................22

Figure 16 – HOLD Timing ........................................................................................................................................ 22

PART NUMBERS AND ORDERING .................................................................................................... 23

Table 15 – Part Numbering System ......................................................................................................................23

Table 16 – Ordering Part Numbers .......................................................................................................................24

PACKAGE OUTLINE DRAWINGS ....................................................................................................... 25

Figure 17 – DFN Package Outline ........................................................................................................................25

Figure 18 – DFN Small Flag Package ....................................................................................................................26

HOW TO REACH US ........................................................................................................................... 28

Table of Contents (Cont’d)

MR20H40 / MR25H40

MR20H40 / MR25H40 Revision 8, 5/2013

The MR2xH40 family is an SPI interface MRAM family with a memory array logically organized as 512Kx8

using the four pin interface of chip select (CS), serial input (SI), serial output (SO) and serial clock (SCK) of the

serial peripheral interface (SPI) bus. The MRAM implements a subset of commands common to SPI EEPROM

and SPI Flash components. This allows the SPI MRAM to replace these components in the same socket

and interoperate on a shared SPI bus. The SPI MRAM oers superior write speed, unlimited endurance, low

standby & operating power, and simple, reliable data retention compared to other serial memory alterna-

tives.

Figure 1 – Block Diagram

Single or multiple devices can be connected to the bus as shown in Figure 2. Pins SCK, SO and SI are com-

mon among devices. Each device requires CS and HOLD pins to be driven separately.

Figure 2 – System Conguration

OVERVIEW

System Conguration

MOSI

MISO

MOSI = Master Out Slave In

MISO = Master In Slave Out

SCK

SCKSISO SCKSISO

HOLD

HOLD HOLDCS CS

SPI

Micro Controller EVERSPIN SPI MRAM 1 EVERSPIN SPI MRAM 2

512Kb x 8

MRAM ARRAY

Instruction Decode

Clock Generator

Control Logic

Write Protect

HOLD

SCK

Instruction Register

Address Register

Counter

Data I/O Register

Nonvolatile Status

19 8

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6MR20H40 / MR25H40 Revision 8, 5/2013

Signal

Name Pin I/O Function Description

CS 1 Input Chip Select

An active low chip select for the serial MRAM. When chip select is high, the

memory is powered down to minimize standby power, inputs are ignored

and the serial output pin is Hi-Z. Multiple serial memories can share a com-

mon set of data pins by using a unique chip select for each memory.

SO 2 Output Serial Output

The data output pin is driven during a read operation and remains Hi-Z at

all other times. SO is Hi-Z when HOLD is low. Data transitions on the data

output occur on the falling edge of SCK.

WP 3 Input Write Protect A low on the write protect input prevents write operations to the Status

VSS 4Refer-

ence Ground Power supply ground pin.

SI 5 Input Serial Input

All data is input to the device through this pin. This pin is sampled on the

rising edge of SCK and ignored at other times. SI can be tied to SO to create

a single bidirectional data bus if desired.

SCK 6 Input Serial Clock

Synchronizes the operation of the MRAM. The clock can operate up to 50

MHz to shift commands, address, and data into the memory. Inputs are

captured on the rising edge of clock. Data outputs from the MRAM occur

on the falling edge of clock. The serial MRAM supports both SPI Mode 0

(CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1). In Mode 0, the clock is

normally low. In Mode 3, the clock is normally high. Memory operation is

static so the clock can be stopped at any time.

HOLD 7 Input Hold

A low on the Hold pin interrupts a memory operation for another task.

When HOLD is low, the current operation is suspended. The device will

ignore transitions on the CS and SCK when HOLD is low. All transitions of

HOLD must occur while CS is low.

VDD 8 Supply Power Supply Power supply voltage from +3.0 to +3.6 volts.

Table 1 – Pin Functions

Figure 3 – DFN Package Pin Diagram (Top View)

HOLD

SCK

Pin Functions

MR20H40 / MR25H40

MR20H40 / MR25H40 Revision 8, 5/2013

SPI COMMUNICATIONS PROTOCOL

Instruction Description Binary Code Hex Code Address Bytes Data Bytes

WREN Write Enable 0000 0110 06h 0 0

WRDI Write Disable 0000 0100 04h 0 0

RDSR Read Status Register 0000 0101 05h 0 1

WRSR Write Status Register 0000 0001 01h 0 1

READ Read Data Bytes 0000 0011 03h 3 1 to ∞

WRITE Write Data Bytes 0000 0010 02h 3 1 to ∞

SLEEP Enter Sleep Mode 1011 1001 B9h 0 0

WAKE Exit Sleep Mode 1010 1011 ABh 0 0

Table 2 – Command Codes

The status register consists of the 8 bits listed in Table 3. As seen in Table 4, the Status Register Write Disable

bit (SRWD) is used in conjunction with bit 1 (WEL) and the Write Protection pin (WP) to provide hardware

memory block protection. Bits BP0 and BP1 dene the memory block arrays that are protected as described

in Table 5. The fast writing speed of the MR2xH40 does not require write status bits. The state of bits 6,5,4,

and 0 can be user modied and do not aect memory operation. All bits in the status register are pre-set

from the factory in the “0” state.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SRWD Don’t Care Don’t Care Don’t Care BP1 BP0 WEL Don’t Care

Table 3 – Status Register Bit Assignments

The MR2xH40 can be operated in either SPI Mode 0 (CPOL=0, CPHA =0) or SPI Mode 3 (CPOL=1, CPHA=1).

For both modes, inputs are captured on the rising edge of the clock and data outputs occur on the falling

edge of the clock. When not conveying data, SCK remains low for Mode 0; while in Mode 3, SCK is high.

The memory determines the mode of operation (Mode 0 or Mode 3) based upon the state of the SCK when

CS falls.

All memory transactions start when CS is brought low to the memory. The rst byte is a command code.

Depending upon the command, subsequent bytes of address are input. Data is either input or output.

There is only one command performed per CS active period. CS must go inactive before another command

can be accepted. To ensure proper part operation according to specications, it is necessary to terminate

each access by raising CS at the end of a byte (a multiple of 8 clock cycles from CS dropping) to avoid partial

or aborted accesses.

Command Codes

Status Register, Memory Protection and Block Write Protection

MR20H40 / MR25H40

8MR20H40 / MR25H40 Revision 8, 5/2013

WEL SRWD WP Protected Blocks Unprotected Blocks Status

0 X X Protected Protected Protected

1 0 X Protected Writable Writable

1 1 Low Protected Writable Protected

1 1 High Protected Writable Writable

Table 4 – Memory Protection Modes

Table 5 – Block Memory Write Protection

The memory enters hardware block protection when the WP input is low and the Status Register Write Dis-

able (SRWD) bit is set to 0. The memory leaves hardware block protection only when the WP pin goes high.

While WP is low, the write protection blocks for the memory are determined by the status register bits BP0

and BP1 and cannot be modied without taking the WP signal high again.

If the WP signal is high (independent of the status of SRWD bit), the memory is in software protection mode.

This means that block write protection is controlled solely by the status register BP0 and BP1 block write pro-

tect bits and this information can be modied using the WRSR command.

Status Register Memory Contents

BP1 BP0 Protected Area Unprotected Area

0 0 None All Memory

0 1 Upper Quarter Lower Three-Quarters

1 0 Upper Half Lower Half

1 1 All None

Block Protection Modes

When WEL is reset to 0, writes to all blocks and the status register are protected. When WEL is set to 1,

BP0 and BP1 determine which memory blocks are protected. While SRWD is reset to 0 and WEL is set to 1,

status register bits BP0 and BP1 can be modied. Once SRWD is set to 1, WP must be high to modify SRWD,

BP0 and BP1.

Memory Protection Modes

MR20H40 / MR25H40

MR20H40 / MR25H40 Revision 8, 5/2013

The Read Status Register (RDSR) command allows the Status Register to be read. The Status Register can be

read at any time to check the status of write enable latch bit, status register write protect bit, and block write

protect bits. For MR2xH40, the write in progress bit (bit 0) is not written by the memory because there is no

write delay. The RDSR command is entered by driving CS low, sending the command code, and then driving

CS high.

Read Status Register (RDSR)

Figure 4 – Read Status Register (RDSR) Timing

SCK

Status Register Out

High Impedance High Z

Mode 3

Mode 0

10 2 3 4 5 6 7 0 1 2 3 4 5 6 7

00000101

MSB

76543210

The Write Enable (WREN) command sets the Write Enable Latch (WEL) bit in the status register (bit 1). The

Write Enable Latch must be set prior to writing either bit in the status register or the memory. The WREN

command is entered by driving CS low, sending the command code, and then driving CS high.

Write Enable (WREN)

Figure 5 – Write Enable (WREN) Timing

Instruction (06h)

High Impedance

Mode 3

Mode 0

Mode 3

Mode 0

10 234567

00000110

SCK

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The Write Status Register (WRSR) command allows new values to be written to the Status Register. The

WRSR command is not executed unless the Write Enable Latch (WEL) has been set to 1 by executing a WREN

command while pin WP and bit SRWD correspond to values that make the status register writable as seen in

Table 4 on page 8. Status Register bits are non-volatile with the exception of the WEL which is reset to 0

upon power cycling.

The WRSR command is entered by driving CS low, sending the command code and status register write data

byte, and then driving CS high.

The Write Disable (WRDI) command resets the Write Enable Latch (WEL) bit in the status register (bit 7) to 0.

This prevents writes to status register or memory. The WRDI command is entered by driving CS low, sending

the command code, and then driving CS high.

The Write Enable Latch (WEL) is reset to 0 on power-up or when the WRDI command is completed.

Figure 6 – Write Disable (WRDI) Timing

Figure 7 – Write Status Register (WRSR) Timing

Write Disable (WRDI)

Write Status Register (WRSR)

SCK

Instruction (04h)

High Impedance

Mode 3

Mode 0

Mode 3

Mode 0

10 234567

00000100

SCK

Status Register In

High Impedance

Mode 3

Mode 0

Instruction (01h)

0000000176543210

MSB

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

MR20H40 / MR25H40

MR20H40 / MR25H40 Revision 8, 5/2013

The Read Data Bytes (READ) command allows data bytes to be read starting at an address specied by the

24-bit address. Only address bits 0-18 are decoded by the memory. The data bytes are read out sequentially

from memory until the read operation is terminated by bringing CS high. The entire memory can be read in

a single command. The address counter will roll over to 0000H when the address reaches the top of memo-

ry.

The READ command is entered by driving CS low and sending the command code. The memory drives the

read data bytes on the SO pin. Reads continue as long as the memory is clocked. The command is termi-

nated by bringing CS high.

Figure 8 – Read Data Bytes (READ) Timing

Read Data Bytes (READ)

SCK

24-Bit Address

High Impedance

Instruction (03h)

Data Out 1 Data Out 2

0 0 0 0 0 0 1 1 212223 3

765432107

210

MSB

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39

The Write Data Bytes (WRITE) command allows data bytes to be written starting at an address specied by

the 24-bit address. Only address bits 0-18 are decoded by the memory. The data bytes are written sequen-

tially in memory until the write operation is terminated by bringing CS high. The entire memory can be

written in a single command. The address counter will roll over to 0000H when the address reaches the top

of memory.

Unlike EEPROM or Flash Memory, MRAM can write data bytes continuously at its maximum rated clock speed

without write delays or data polling. Back to back WRITE commands to any random location in memory can

be executed without write delay. MRAM is a random access memory rather than a page, sector, or block

organized memory so it is ideal for both program and data storage.

The WRITE command is entered by driving CS low, sending the command code, and then sequential write

data bytes. Writes continue as long as the memory is clocked. The command is terminated by bringing CS

high.

Write Data Bytes (WRITE)

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12 MR20H40 / MR25H40 Revision 8, 5/2013

Figure 9 – Write Data Bytes (WRITE) Timing

The Enter Sleep Mode (SLEEP) command turns o all MRAM power regulators in order to reduce the overall

chip standby power to 15 μA typical. The SLEEP command is entered by driving CS low, sending the com-

mand code, and then driving CS high. The standby current is achieved after time, tDP. If power is removed

when the part is in sleep mode, upon power restoration, the part enters normal standby. The only valid

command following SLEEP mode entry is a WAKE command.

Figure 10 – Enter Sleep Mode (SLEEP) Timing

SCK

24-Bit Address

High Impedance

Instruction (02h)

00000010232221 321076543210

MSB MSB

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39

SCK

Data Byte 3

High Impedance

Data Byte NData Byte 2

34 210 76543210

MSB

76543210765

MSB

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Mode 3

Mode 0

Enter Sleep Mode (SLEEP)

SCK

Standby CurrentActive Current

Mode 3

Mode 0

Sleep Mode Current

Instruction (B9h)

10111001

01234567

MR20H40 / MR25H40

MR20H40 / MR25H40 Revision 8, 5/2013

The Exit Sleep Mode (WAKE) command turns on internal MRAM power regulators to allow normal operation.

The WAKE command is entered by driving CS low, sending the command code, and then driving CS high.

The memory returns to standby mode after tRDP. The CS pin must remain high until the tRDP period is over.

WAKE must be executed after sleep mode entry and prior to any other command.

Figure 11 – Exit Sleep Mode (WAKE) Timing

Exit Sleep Mode (WAKE)

SCK

Sleep Mode Current

Mode 3

Mode 0

Standby Current

Instruction (ABh)

10101 011

01234567

RDP

MR20H40 / MR25H40

14 MR20H40 / MR25H40 Revision 8, 5/2013

This device contains circuitry to protect the inputs against damage caused by high static voltages or electric

elds. However, it is advised that normal precautions be taken to avoid application of any voltage greater

than maximum rated voltages to these high-impedance (Hi-Z) circuits.

The device also contains protection against external magnetic elds. Precautions should be taken to avoid

application of any magnetic eld more intense than the maximum eld intensity specied in the maximum

ratings.

Symbol Parameter Conditions Value Unit

VDD Supply voltage 2-0.5 to 4.0 V

VIN Voltage on any pin 2-0.5 to VDD + 0.5 V

IOUT Output current per pin ±20 mA

PDPackage power dissipation 30.600 W

TBIAS Temperature under bias

Commercial -45 to 95 °C

Industrial -45 to 95 °C

AEC-Q100 Grade 1 -45 to 135 °C

Tstg Storage Temperature -55 to 150 °C

TLead Lead temperature during solder (3 minute max) 260 °C

Hmax_write Maximum magnetic eld during write Write 12,000 A/m

Hmax_read

Maximum magnetic eld during read or

standby Read or Standby 12,000 A/m

Notes:

1. All voltages are referenced to VSS. The DC value of VIN must not exceed actual applied VDD by more than 0.5V. The AC value of

VIN must not exceed applied VDD by more than 2V for 10ns with IIN limited to less than 20mA.

2. Power dissipation capability depends on package characteristics and use environment.

Table 6 – Absolute Maximum Ratings

ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings

Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to

recommended operating conditions. Exposure to excessive voltages or magnetic elds could aect device reliability.

MR20H40 / MR25H40

MR20H40 / MR25H40 Revision 8, 5/2013

Symbol Parameter Temp Grade Min Max Unit

VDD Power supply voltage 3.0 3.6 V

VIH Input high voltage 2.2 VDD + 0.3 V

VIL Input low voltage -0.5 0.8 V

TAAmbient temperature under bias

Commercial 0 70 °C

Industrial -40 85 °C

AEC-Q100 Grade 1 1-40 125 °C

Notes:

1. AEC-Q100 Grade 1 temperature prole assumes 10 percent duty cycle at maximum temperature (2 years out of 20-year life.)

Table 7 – Operating Conditions

Symbol Parameter Conditions Min Max Unit

ILI Input leakage current - ±1 μA

ILO Output leakage current - ±1 μA

VOL Output low voltage

IOL = +4 mA - 0.4 V

IOL = +100 μA - VSS + 0.2v V

VOH Output high voltage

IOH = -4 mA 2.4 - V

IOH = -100 μA VDD - 0.2 - V

Table 8 – DC Characteristics

MR20H40 / MR25H40

16 MR20H40 / MR25H40 Revision 8, 5/2013

Symbol Parameter Conditions Typical Max Unit

IDDR Active Read Current

@ 1 MHz 5.0 11 mA

@ 40 MHz 12 17 mA

@ 50MHz 13.8 18.5 mA

IDDW Active Write Current

@ 1 MHz 9.0 25 mA

@ 40 MHz 28 42 mA

@ 50 MHz 33 46.5 mA

ISB1 AC Standby Current (CS High)

@ 40 MHz 250 400 μA

@ 50 MHz 650 750 μA

ISB2 CMOS Standby Current (CS High) 90 180 μA

IZZ Standby Sleep Mode Current (CS High) 15 40 μA

Table 9 – Power Supply Characteristics

MR20H40 / MR25H40

MR20H40 / MR25H40 Revision 8, 5/2013

Table 10 – Capacitance

Symbol Parameter Typical Max Unit

CIn Control input capacitance 1- 6 pF

CI/O Input/Output capacitance 1- 8 pF

Notes:

1. ƒ = 1.0 MHz, dV = 3.0 V, TA = 25 °C, periodically sampled rather than 100% tested.

Table 11 – AC Measurement Conditions

Figure 12 – Output Load for Impedance Parameter Measurements

Figure 13 – Output Load for all Other Parameter Measurements

Parameter Value Unit

Logic input timing measurement reference level 1.5 V

Logic output timing measurement reference level 1.5 V

Logic input pulse levels 0 or 3.0 V

Input rise/fall time 2 ns

Output load for low and high impedance parameters See Figure 12

Output load for all other timing parameters See Figure 13

TIMING SPECIFICATIONS

Output

L= 1.5 V

RL= 50 Ω

ZD= 50 Ω

Output

435 Ω

590 Ω

30 pF

3.3 V

Capacitance

AC Measurement Conditions

MR20H40 / MR25H40

18 MR20H40 / MR25H40 Revision 8, 5/2013

The MR2xH40 is not accessible for a start-up time, tPU= 400 μs after power up. Users must wait this time

from the time when VDD (min) is reached until the rst CS low to allow internal voltage references to become

stable. The CS signal should be pulled up to VDD so that the signal tracks the power supply during power-up

sequence.

Symbol Parameter Min Typical Max Unit

VWI Write Inhibit Voltage 2.2 - TBD V

tPU Startup Time 400 - - μs

Table 12 – Power-Up Timing

Figure 14 – Power-Up Timing

Power Up Timing

VDD

(max)

VDD(min)

tPU

Time

Normal Operation

Chip Selection not allowed

Reset state

of the

device

MR20H40 / MR25H40

MR20H40 / MR25H40 Revision 8, 5/2013

Symbol Parameter Temp Range Min Typical Max Unit

fSCK SCK Clock Frequency Commercial/Industrial 0 - 50 MHz

tRI Input Rise Time Commercial/Industrial - - 50 ns

tRF Input Fall Time Commercial/Industrial - - 50 ns

tWH SCK High Time Commercial/Industrial 7 - - ns

tWL SCK Low Time Commercial/Industrial 7 - - ns

Synchronous Data Timing see Figure 15

tCS CS High Time Commercial/Industrial 40 - - ns

tCSS CS Setup Time Commercial/Industrial 5 - - ns

tCSH CS Hold Time Commercial/Industrial 5 - - ns

tSU Data In Setup Time Commercial/Industrial 2 - - ns

tH Data In Hold Time Commercial/Industrial 5 - - ns

tVOutput Valid Commercial/Industrial 0 - 9 ns

tHO Output Hold Time Commercial/Industrial 0 - - ns

HOLD Timing see Figure 16

Table 13 – MR20H40 (fSCK = 50MHz) AC Timing Parameters

AC Timing Parameters

Commercial and Industrial Temperature Ranges, VDD=3.0 to 3.6 V, CL= 30 pF for all values.

tHD HOLD Setup Time Commercial/Industrial 5 - - ns

tCD HOLD Hold Time Commercial/Industrial 5 - - ns

tLZ HOLD to Output Low Impedance Commercial/Industrial - - 20 ns

tHZ HOLD to Output High Imped-

ance Commercial/Industrial - - 20 ns

Other Timing Specications

tWPS WP Setup To CS Low Commercial/Industrial 5 - - ns

tWPH WP Hold From CS High Commercial/Industrial 5 - - ns

tDP Sleep Mode Entry Time Commercial/Industrial 3 - - μs

tRDP Sleep Mode Exit Time Commercial/Industrial 400 - - μs

tDIS Output Disable Time Commercial/Industrial 12 - - ns

MR20H40 / MR25H40

20 MR20H40 / MR25H40 Revision 8, 5/2013

Table 14 – MR25H40 (fSCK = 40MHz) AC Timing Parameters

Industrial and AEC-Q100 Grade 1 Temperature Ranges, VDD=3.0 to 3.6 V, CL= 30 pF for all values.

Symbol Parameter Temp Grade Min Typical Max Unit

fSCK SCK Clock Frequency Industrial/AEC-Q100

Grade 1 0 - 40 MHz

tRI Input Rise Time Industrial/AEC-Q100

Grade 1 - - 50 ns

tRF Input Fall Time Industrial/AEC-Q100

Grade 1 - - 50 ns

tWH SCK High Time Industrial/AEC-Q100

Grade 1 11 - - ns

tWL SCK Low Time Industrial/AEC-Q100

Grade 1 11 - - ns

Synchronous Data Timing see Figure 15

tCS CS High Time Industrial/AEC-Q100

Grade 1 40 - - ns

tCSS CS Setup Time Industrial/AEC-Q100

Grade 1 10 - - ns

tCSH CS Hold Time Industrial/AEC-Q100

Grade 1 10 - - ns

tSU Data In Setup Time Industrial/AEC-Q100

Grade 1 5 - - ns

tH Data In Hold Time Industrial/AEC-Q100

Grade 1 5 - - ns

tVOutput Valid

Industrial 0 - 9 ns

AEC-Q100 Grade 1 0 - 10 ns

tHO Output Hold Time Industrial/AEC-Q100

Grade 1 0 - - ns

Table continues next page.

MR20H40 / MR25H40

MR20H40 / MR25H40 Revision 8, 5/2013

HOLD Timing see Figure 16

Symbol Parameter Temp Grade Min Typical Max Unit

tHD HOLD Setup Time Industrial/AEC-Q100

Grade 1 10 - - ns

tCD HOLD Hold Time Industrial/AEC-Q100

Grade 1 10 - - ns

tLZ HOLD to Output Low Impedance Industrial/AEC-Q100

Grade 1 - - 20 ns

tHZ HOLD to Output High Impedance Industrial/AEC-Q100

Grade 1 - - 20 ns

Other Timing Specications

tWPS WP Setup To CS Low Industrial/AEC-Q100

Grade 1 5 - - ns

tWPH WP Hold From CS High Industrial/AEC-Q100

Grade 1 5 - - ns

tDP Sleep Mode Entry Time Industrial/AEC-Q100

Grade 1 3 - - μs

tRDP Sleep Mode Exit Time Industrial/AEC-Q100

Grade 1 400 - - μs

tDIS Output Disable Time Industrial/AEC-Q100

Grade 1 12 - - ns

Table 14 (Cont’d) - MR25H40 (fSCK = 40MHz) AC Timing Parameters

Industrial and AEC-Q100 Grade 1 Temperature Ranges, VDD=3.0 to 3.6 V, CL= 30 pF for all values.

MR20H40 / MR25H40

22 MR20H40 / MR25H40 Revision 8, 5/2013

Figure 16 – HOLD Timing

Figure 15 – Synchronous Data Timing

SCK

High Impedance

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

CSS

tWL

CSH

tDIS

SCK

HOLD

MR20H40 / MR25H40

MR20H40 / MR25H40 Revision 8, 5/2013

PART NUMBERS AND ORDERING

Table 15 – Part Numbering System

Product Family Number MR 25H 40

Memory Interface Density Revision Temp Package Grade

Ordering Part Number MR 25H 40 C DC ES

MRAM MR

50 MHz Serial Family 20H

40 MHz Serial Family 25H

256 Kb 256

512 Kb 512

1 Mb 10

4 Mb 40

No Revision Blank

Revision A A

Revision B B

Commercial 0 to 70°C Blank

Industrial -40 to 85°C C

Extended -40 to 105°C V

AEC Q-100 Grade 1 -40 to 125°C M

8-pin DFN in Tray DC

8-pin DFN Tape and Reel DCR

8-pin DFN (small ﬂag) in Tray DF

8-pin DFN (small ﬂag) Tape and Reel DFR

Engineering Samples ES

Customer Samples Blank

Mass Producon Blank

Product Family Number and Ordering Part Number given are for illustraon only.

MR20H40 / MR25H40

24 MR20H40 / MR25H40 Revision 8, 5/2013

Speed

Grade Temp Grade Tempera-

ture Package Shipping Con-

tainer Order Part Number

50MHz

Commercial 0 to +70 C

8-DFN Small

Flag

Trays MR20H40DF

Tape and Reel MR20H40DFR

Industrial -40 to +85 C Trays MR20H40CDF

Tape and Reel MR20H40CDFR

40 MHz

Industrial -40 to +85 C

8-DFN Trays MR25H40CDC

Tape and Reel MR25H40CDCR

8-DFN Small

Flag

Trays MR25H40CDF

Tape and Reel MR25H40CDFR

AEC-Q100 Grade 1 -40 to +125 C 8-DFN Small

Flag

Trays MR25H40MDF Preliminary

Tape and Reel MR25H40MDFR Preliminary

Preliminary Products: These products are classied as Preliminary until the completion of all qualication tests. The specica-

tions in this data sheet are intended to be nal but are subject to change. Please check the Everspin web site www.everspin.com

for the latest information on product status.

Table 16 – Ordering Part Numbers

MR20H40 / MR25H40

MR20H40 / MR25H40 Revision 8, 5/2013

PACKAGE OUTLINE DRAWINGS

Figure 17 – DFN Package Outline

Exposed metal Pad. Do not

connect anything except VSS

Notes:

1. Reference JEDEC MO-229.

2. All dimensions are in mm. Angles in degrees.

3. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall be within 0.08 mm.

4. Warpage shall not exceed 0.10 mm.

Dimension A B C D E F G H I J K L M N

Max. 5.10 6.10 1.00 1.27

BSC

0.45 0.05 0.35

Ref.

0.70 4.20 4.20 0.261 C0.35 R0.20 0.05

Min. 4.90 5.90 0.90 0.35 0.00 0.50 4.00 4.00 0.195 0.00

DAP Size

4.4 x 4.4

Detail A

Pin 1 Index

MR20H40 / MR25H40

26 MR20H40 / MR25H40 Revision 8, 5/2013

Detail A

Pin 1 Index

0.10 C2X

Figure 18 – DFN Small Flag Package

Dimension A B C D E F G H I J K L M N

Max. 5.10 6.10 0.90 1.27

BSC

0.45 0.05 1.60 0.70 2.10 2.10 .210 C0.45 R0.20 0.05

Min. 4.90 5.90 0.80 0.35 0.00 1.20 0.50 1.90 1.90 .196 0.00

Notes:

1. Reference JEDEC MO-229.

2. All dimensions are in mm. Angles in degrees.

3. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall be within 0.08 mm.

4. Warpage shall not exceed 0.10 mm.

Exposed metal Pad. Do not

connect anything except VSS

MR20H40 / MR25H40

MR20H40 / MR25H40 Revision 8, 5/2013

Revision Date Description of Change

0 Jan 15, 2010 Product Concept Release

0 .1 Feb. 23, 2010 Fixed typos in text.

1 May 5, 2010 Removed commercial specications. All parts meet industrial specications.

2 Jan 11, 2011 Preliminary Product Release. Updated description of status register non-volatility, WAKE

command, Table 3.4.

3 Apr 25, 2011 Removed DIP package part to seperate datasheet. Added inset detail for mechanical pack-

age drawings.

4September 22,

2011

Added AEC-Q100 Grade 1 ordering option. Revised Table 3.1, Table 3.2, Table 3.4, Table 4.4

revised and Note 2 deleted, revised Figure 5.1 and Table 5.1.

5 Nov 18, 2011

Corrected VOL in Table 3.3 to read VOL Max = VSS + 0.2v. Corrected SI waveform in Figure 2.8.

New Small Flag DFN package option added to Page 1 Features and available parts Table 5.1.

DFN Small Flag drawing and dimensions table added as Figure 6.2. Figure 6.1, DFN Pack-

age, cleaned up with better quality drawing and dimension table. No specications were

changed in Figure 6.1.

6 August 23, 2012

CDF and CDFR options changed to Preliminary. Added Small Flag DFN illustrations. Refor-

matted all parametric tables. Revised 8-DFN package drawing to show correct proportion

for ag and package. Added MR20H40 as 50MHz speed option. Deleted large ag DFN

ordering option for AEC-Q100 products. Corrected errors in DFN package outline drawings.

7January 17,

2013 Removed Preliminary status from MR25H40CDF, CDFR.

8 May 24, 2013 Removed Preliminary status from MR20H40CDF(R), and from MR20H40DF(R).

REVISION HISTORY

MR20H40 / MR25H40

28 MR20H40 / MR25H40 Revision 8, 5/2013

Information in this document is provided solely to enable system and soft-

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express or implied licenses granted hereunder to design or fabricate any

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Everspin Technologies reserves the right to make changes without further

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lar purpose, nor does Everspin Technologies assume any liability arising

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or incidental damages. “Typical” parameters, which may be provided in

Everspin Technologies data sheets and/or specications can and do vary

in dierent applications and actual performance may vary over time. All

operating parameters including “Typicals” must be validated for each cus-

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File Name:

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Everspin Technologies, Inc.

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