‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Features
Preliminary
PDF: 09005aef824c99b3/Source: 009005aef824c99bb Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9V131_LDS_1.fm - Rev. B 3/07 EN 1©2006 Micron Technology, Inc. All rights reserved.
1/4-Inch SOC VGA CMOS Digital Image
Sensor
MT9V131I29STC (iCSP)
MT9V131C12STC (CLCC)
Features
•Micron
® DigitalClarity® CMOS imaging technology
System-On-a-Chip (SOC)—Completely integrated
camera system
Ultra low-power, high fidelity CMOS image sensor
Superior low-light performance
Up to 30 fps progressive scan at 27 MHz for high-
quality video at VGA resolution
On-chip image flow processor (IFP) performs
sophisticated processing: color recovery and
correction, sharpening, gamma, lens shading
correction, on-the-fly defect correction, 2X fixed
zoom
Automatic exposure, white balance and black
compensation, flicker avoidance, color saturation,
and defect identification and correction, auto frame
rate, back light compensation
Xenon and LED-type flash support
Two-wire serial programming interface
Progressive scan ITU_R BT.656 (YCbCr), YUV,
565RGB, 555RGB, and 444RGB output data formats
Applications
•Security
•Biometrics
Network cameras
Toys and other battery-powered products
The sensor is a complete camera-on-a-chip solution
and is designed specifically to meet the demands of
battery-powered products such as security cameras,
PDAs, and toys. It incorporates sophisticated camera
functions on-chip and is programmable through a
simple two-wire serial interface.
Ordering Information
Table 1: Key Performance Parameters
Parameter Typical Value
Optical format 1/4-inch (4:3)
Active imager size 3.58mm(H) x 2.69mm(V)
4.48mm (diagonal)
Active pixels 640H x 480V (VGA)
Pixel size 5.6µm x 5.6µm
Color filter array RGB Bayer pattern
Shutter type Electronic rolling shutter (ERS)
Maximum data rate/
master clock
1213.5 Mp/s/
2427 MHz
Frame
rate
VGA (640 x 480) 15 fps at 12 MHz (default),
programmable up to 30 fps
at 27 MHz
CIF (352 x 288) Programmable up to 60 fps
QVGA (320 x
240)
Programmable up to 90 fps
ADC resolution 10-bit, on-chip
Responsivity 1.9 V/lux-sec (550nm)
Dynamic range 60dB
SNRMAX 45dB
Supply voltage 2.8V +0.25V
Power consumption <80mW at 2.8V, 15 fps at 12MHz
Operating temperature –20°C to +60°C
Packaging 44-Ball iCSP, 48-Pin CLCC
Table 2: Available Part Numbers
Part Number Description
MT9V131I29STC 44-Ball iCSP
MT9V131C12STC ES 48-Pin CLCC ES (color)
MT9V131C12STCD ES Demo kit (color)
MT9V131C12STCH ES Demo kit headboard (color)
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
General Description
PDF: 09005aef824c99b3/Source: 009005aef824c99bb Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9V131_LDS_2.fm - Rev. B 3/07 EN 2©2006 Micron Technology, Inc. All rights reserved.
Preliminary
General Description
This SOC VGA CMOS image sensor features DigitalClarityMicrons breakthrough,
low-noise CMOS imaging technology that achieves CCD image quality (based on signal-
to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and
integration advantages of CMOS.
The MT9V131 is a fully-automatic, single-chip camera, requiring only a power supply,
lens, and clock source for basic operation. Output video is streamed through a parallel
8-bit port, as shown in Figure 2 on page 3. Output pixel clock is used to latch the data,
while FRAME_VALID and LINE_VALID signals indicate the active video. The sensor can
be put in an ultra-low power sleep mode by asserting the STANDBY pin. Output pads
can also be tri-stated by de-asserting the OE# pin. The MT9V131 internal registers can
be configured using a two-wire serial interface.
The MT9V131 can be programmed to output progressive scan images up to 30 fps in an
8-bit ITU_R BT.656 (YCbCr) formerly CCIR656, YUV, 565RGB, 555RGB, or 444RGB
formats. The FRAME_VALID and LINE_VALID signals are output on dedicated pins,
along with a pixel clock that is synchronous with valid data.
Table 3 lists typical values of MT9V131 performance parameters.
Table 3: MT9V131 Detailed Performance Parameters
Parameter Typ Unit
Pixel count
Active pixel 0.31 Million Pixels
Resolution 640 x 480 H X V
Optical format 1/4 Inches
Power consumption <80 mW
Dynamic range 60 dB
Shutter type Rolling Type
Output gain 28 e-/LSB
Read noise 6e-RMS at 16X
Dark current 150 e-/pix/sec at 55°C
Responsivity 2.5 V/lux-sec
Operating frequency
Master clock 24 to 27 MHz
Data rate 12 to 13.5 Mp/s
Operating temperature –20 to +60 °C
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
General Description
PDF: 09005aef824c99b3/Source: 009005aef824c99bb Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9V131_LDS_2.fm - Rev. B 3/07 EN 3©2006 Micron Technology, Inc. All rights reserved.
Preliminary
Figure 1 illustrates the MT9V131 quantum efficiency in relation to wavelength.
Figure 1: MT9V131 Quantum Efficiency vs. Wavelength
Figure 2: Chip Block Diagram
The MT9V131 can accept the input clock of up to 27 MHz, delivering 30 fps. With
power-on defaults, the camera is configured to deliver 15 fps at 12 MHz and automati-
cally slows down the frame rate in low-light conditions to achieve longer exposures and
better image quality.
Internally, the MT9V131 consists of a sensor core and an image flow processor. The
sensor core functions to capture raw Bayer-encoded images that are input into the IFP
as shown in Figure 2. The IFP processes the incoming stream to create interpolated,
color-corrected output and controls the sensor core to maintain the desirable exposure
and color balance.
0
5
10
15
20
25
30
35
40
45
50
350 400 450 500 550 600 650 700 750 800
Quantum Efficiency (%
Blue
Green
Red
Wavelength (nm)
D
OUT
(7:0)
PIXCLK
FRAME_VALID
LINE_VALID
FLASH
Communication Bus
Sensor Core
.
Based on MT9V011
. 668H x 496V (VGA+ Reference)
. 1/4-inch optical format
. Auto Black compensation
. Programmable analog gain
. Programmable exposure
. Low power, 10-bit ADCs
SRAM Line Buffers
Image Flow Processor
.
Color correction, gamma,
lens shading correction
. Auto exposure, white balance
.
Interpolation and defect
correction
. Flicker avoidance
SCLK
S
DATA
S
ADDR
CLK
STANDBY
OE#
V
DD
/D
GND
V
AA
/A
GND
VAAPIX
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
General Description
PDF: 09005aef824c99b3/Source: 009005aef824c99bb Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9V131_LDS_2.fm - Rev. B 3/07 EN 4©2006 Micron Technology, Inc. All rights reserved.
Preliminary
Figure 3 shows MT9V131 typical connections. For low-noise operation, the MT9V131
requires separate supplies for analog and digital power. Incoming digital and analog
ground conductors can be tied together right next to the die. Both power supply rails
should be decoupled to ground using capacitors. The use of inductance filters is not
recommended.
Figure 3: Typical Configuration (Connection)
Note: For two-wire serial interface, a 1.5KΩ resistor is recommended, but may be greater for
slower two-wire speed.
D
OUT
(7:0)
FRAME_ V ALI D
LINE_ V ALI D
PIXCLK
FLASH
T o CMO S
camera port
D
GND
A
GND
T o Xenon flas h
trigger or LED enable
V
DD
V
AA
10µF
Master
Clock
T wo-wir e
serial bus
{
{
A
GND
D
GND
S
ADDR
RESET#
S
DATA
SCLK
CLKIN
SCAN_EN
OE#
S T ANDB Y
V
DD
V
AA
VAAPIX
ADC_TEST
1KΩ
1.5KΩ
1.5KΩ
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Ball Assignment
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MT9V131_LDS_2.fm - Rev. B 3/07 EN 5©2006 Micron Technology, Inc. All rights reserved.
Preliminary
Ball Assignment
Figure 4: 44-Ball iCSP Pinout Diagram
Figure 5: 48-Pin CLCC Pinout Diagram
A
B
C
D
E
F
G
2
DOUT2
VDD
DOUT0
NC
FLASH
VDD
CLKIN
3
DOUT4
DOUT3
DOUT5
LINE_
SCLK
SDATA
1
DGND
DOUT1
NC
DGND
PIXCLK
FRAME_
VALID
DGND
4
DGND
VDD
SADDR
DGND
6
VDD
VDD
SCAN
OE#
RESET#
ADC_
VAA
7
DGND
VDD
DGND
DGND
STAND
VAAPIX
AGND
5
DOUT6
DOUT7
VDD
VDD
AGND
VAA
Top View
(Ball Down)
BY
VALID
_EN
TEST
12345644 43
19 20 21 22 23 24 25 2627 28 29 30
7
8
9
10
11
12
13
14
15
16
17
18
42
41
40
39
38
37
36
35
34
33
32
31
V
DD
D
OUT
1
D
OUT
0
D
OUT
_LSB1
D
OUT_
LSB0
D
GND
FLASH
PIXCLK
LINE_VALID
FRAME_VALID
V
DD
NC
NC
V
DD
V
DD
SCAN_EN
D
GND
VDD
D
GND
OE#
STANDBY
RESET#
VAAPIX
ADC_TEST
DGND
CLKIN
SCLK
S
DATA
S
ADDR
D
GND
V
DD
V
AA
A
GND
V
AA
A
GND
NC
NC
D
GND
D
OUT
2
D
OUT
3
D
OUT4
D
OUT
5
D
GND
V
DD
D
OUT
6
D
OUT
7
V
DD
D
GND
48 47 4645
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Ball Assignment
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MT9V131_LDS_2.fm - Rev. B 3/07 EN 6©2006 Micron Technology, Inc. All rights reserved.
Preliminary
Table 4: Ball and Pin Description
Symbol CLCC Pin iCSP Ball Type Description
CLKIN 20 G2 Input Master clock into sensor. Default is 12 MHz (27 MHz
maximum).
SCLK 21 F3 Input Serial clock.
SADDR 23 F4 Input Serial interface address select: Reg0xB8 when HIGH
(default).
Reg0x90 when LOW.
ADC_TEST 31 F6 Input Tie to VAAPIX (factory use only).
RESET# 33 E6 Input Asynchronous reset of sensor when LOW. All registers
assume factory defaults.
STANDBY 34 E7 Input When HIGH, puts the imager in ultra-low power
standby mode.
OE# 35 D6 Input Output_Enable_Bar pin. When HIGH, tri-state all
outputs except SDATA (tie LOW for normal operation).
SCAN_EN 39 C6 Input Tie to digital ground.
SDATA 22 G3 I/O Serial data I/O.
FLASH 13 E2 Output Flash strobe.
PIXCLK 14 E1 Output Pixel clock out. Pixel data output are valid during
rising edge of this clock. IFP Reg0x08 [9] inverts
polarity.
Frequency = Master clock.
LINE_VALID 15 E3 Output Active HIGH during line of selectable valid pixel data.
FRAME_VALID 16 F1 Output Active HIGH during frame of valid pixel data.
DOUT745 B5Output
ITU_R BT.656/RGB data bit 7 (MSB).
DOUT646 A5Output
ITU_R BT.656/RGB data bit 6.
DOUT51 C3Output
ITU_R BT.656/RGB data bit 5.
DOUT42 A3Output
ITU_R BT.656/RGB data bit 4.
DOUT33 B3Output
ITU_R BT.656/RGB data bit 3.
DOUT24 A2Output
ITU_R BT.656/RGB data bit 2.
DOUT18 B1Output
ITU_R BT.656/RGB data bit 1.
DOUT09 C2Output
ITU_R BT.656/RGB data bit 0 (LSB).
VDD 7, 17, 25, 40, 41, 44,
47
A6, B2, B4, B6,
B7, C5, E5, F2
Supply Digital power (2.8V).
VAA 26, 28 G5, G6 Supply Analog power (2.8V).
VAAPIX 32 F7 Supply Pixel array power (2.8V).
AGND 27, 29 F5, G7 Supply Analog ground.
DGND 5, 12, 24, 36, 38, 43,
48
A1, D1, A4, A7,
C7, D7, G1, G4
Supply Digital ground.
NC 6, 18, 30, 42 C1, D2 No connect.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Image Flow Processor
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MT9V131_LDS_2.fm - Rev. B 3/07 EN 7©2006 Micron Technology, Inc. All rights reserved.
Preliminary
Image Flow Processor
Overview of Architecture
The image flow processor consists of a color processing pipeline and a measurement
and control logic block, as shown in Figure 6 on page 8. The stream of raw data from the
sensor enters the pipeline and undergoes a number of transformations. Image stream
processing starts from conditioning the black level and applying a digital gain. The lens
shading block compensates for signal loss caused by the lens. Next, the data is interpo-
lated to recover missing color components for each pixel and defective pixels are
corrected. The resulting interpolated RGB data passes through the current color correc-
tion matrix (CCM), gamma, and saturation corrections and is formatted for final output.
The measurement and control logic continuously accumulates statistics about image
brightness and color. Indoor 50/60Hz flicker is detected and automatically updated
when possible. Based on these measurements, the IFP calculates updated values for
exposure time and sensor analog gains, which are sent to the sensor core through the
communication bus.
Color correction is achieved through linear transformation of the image with a 3 x 3
color correction matrix. Color saturation can be adjusted in the range from zero (black
and white) to 1.25 (125% of full color saturation).
Gamma correction compensates for nonlinear dependence of the display device output
versus driving signal (monitor brightness versus CRT voltage).
Output and Formatting
Processed video can be output in the form of a progressive scan ITU_R BT.656 or RGB
stream. ITU_R BT.656 (default) stream contains 4:2:2 data with optional embedded
synchronization codes. This kind of output is typically suitable for subsequent display
by standard video equipment. For JPEG/MPEG compression, YUV/ encoding is suitable.
RGB functionality is provided to support LCD devices. The MT9V131 can be configured
to output 16-bit RGB (RGB565) and 15-bit RGB (RGB555), as well as two types of 12-bit
RGB (RGB444). The user can configure internal registers to swap odd and even bytes,
chrominance channels, and luminance and chrominance components to facilitate
interface to application processors.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Image Flow Processor
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MT9V131_LDS_2.fm - Rev. B 3/07 EN 8©2006 Micron Technology, Inc. All rights reserved.
Preliminary
Figure 6: Image Flow Processor Block Diagram
The MT9V131 features smooth, continuous zoom and pan. This functionality is avail-
able when the IFP output is downsized in the decimation block. The decimation block
can downsize the original VGA image to any integer size, including QVGA, QQVGA, CIF,
and QCIF with no loss to the field of view. The user can program the desired size of the
output image in terms of horizontal and vertical pixel count. In addition, the user can
program the size of a region for downsizing. Continuous zoom is achieved every time
the region of interest is less than the entire VGA image. The maximum zoom factor is
equal to the ratio of VGA to the size of the region of interest. For example, an image
rendered on a 160 x 120 display can be zoomed by 640/160 = 480/120 = 4 times. Contin-
uous pan is achieved by adjusting the starting coordinates of the region of interest.
Also, a fixed 2X up-zoom is implemented by means of windowing down the sensor core.
In this mode, the IFP receives a QVGA-sized input data and outputs a VGA-size image.
The sub-window can be panned both vertically and horizontally by programming
sensor core registers.
The MT9V131 supports both LED and Xenon-type flash light sources using a dedicated
output pad. For Xenon devices, the pad generates a strobe to fire when the imager's
shutter is fully open. For LED, the pad can be asserted or de-asserted asynchronously.
Flash modes are configured and engaged over the two-wire serial interface using IFP.
IMAGE SENSOR
GAMMA CORRECTION
COLOR CORRECTION
DEMOSAICING
OUTPUT FORMATTING
FLASH CONTROL
AE, AWB,
FLICKER AVOIDANCE
LENS CORRECTION
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Sensor Core Overview
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MT9V131_LDS_2.fm - Rev. B 3/07 EN 9©2006 Micron Technology, Inc. All rights reserved.
Preliminary
Sensor Core Overview
The sensor consists of a pixel array of 668 x 496 total, analog readout chain, 10-bit ADC
with programmable gain and black offset, and timing and control.
Figure 7: Sensor Core Block Diagram
The sensor core image data is read-out in a progressive scan. Valid image data is
surrounded by horizontal and vertical blanking, as shown in Figure 8.
Figure 8: Spatial Illustration of Image Readout
Active Pixel
Sensor Array
Control Register
Analog Processing
Timing and Control
ADC
Communication
Bus to IFP
10-bit Data
to IFP
Clock
Sync. Signals
P
0,0
P
0,1
P
0,2
.....................................P
0,n-1
P
0,n
P
1,0
P
1,1
P
1,2
.....................................P
1,n-1
P
1,n
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
P
m-1,0
P
m-1,1
.....................................P
m-1,n-1
P
m-1,n
P
m,0
P
m,1
.....................................P
m,n-1
P
m,n
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
VALID IMAGE HORIZONTAL
BLANKING
VERTICAL BLANKING VERTICAL/HORIZONTAL
BLANKING
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Electrical Specifications
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MT9V131_LDS_2.fm - Rev. B 3/07 EN 10 ©2006 Micron Technology, Inc. All rights reserved.
Preliminary
Electrical Specifications
The recommended die operating temperature ranges from –20°C to +40°C. The sensor
image quality may degrade above +40°C.
Notes: 1. To place the chip in standby mode, first raise STANDBY to VDD, then wait two master clock
cycles before turning off the master clock. Two master clock cycles are required to place the
analog circuitry into standby, low-power mode.
2. When STANDBY is de-asserted, standby mode is exited immediately (within several master
clocks), but the current frame and the next two frames will be invalid. The fourth frame will
contain a valid image.
Table 5: DC Electrical Characteristics
VDD = VAA = 2.8 ± 0.25V; TA = 25°C
Symbol Definition Condition Min Typ Max Unit
VIH Input high voltage VDD - 0.25 VDD + 0.25 V
VIL Input low voltage –0.3 0.8 V
IIN Input leakage current No pull-up resistor; VIN = VDD or
DGND
–5 5.0 µA
VOH Output high voltage VDD - 0.2 V
VOL Output low voltage 0.2 V
IOH Output high current 15.0 mA
IOL Output low current 20.0 mA
IOZ Tri-state output leakage current 5.0 µA
IAA Analog operating supply current Default settings, CLOAD = 10pF
CLKIN = 12 MHz
CLKIN = 27 MHz
10.0
10.0
20.0
20.0
25.0
25.0
mA
IDD Digital operating supply current Default settings, CLOAD = 10pF
CLKIN = 12 MHz
CLKIN = 27 MHz
5.0
10.0
8.0
15.0
20.0
20.0
mA
IAA Standby Analog standby supply current STDBY = VDD 0.0 2.5 5.0 µA
IDD Standby Digital standby supply current STDBY = VDD 0.0 2.5 5.0 µA
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Electrical Specifications
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MT9V131_LDS_2.fm - Rev. B 3/07 EN 11 ©2006 Micron Technology, Inc. All rights reserved.
Preliminary
Notes: 1. For 30 fps operation with a 27 MHz clock, the user must have a precise duty cycle equal to
50%. With a slower frame rate and a slower clock, the clock duty cycle can be relaxed.
2. Typical is 1/2 of CLKIN period.
3. PIXCLK can be programmed to be inverted or non-inverted.
Table 6: AC Electrical Characteristics
VDD = VAA = 2.8 ± 0.25V; TA = 25°C
Definition Symbol Condition Min Typ Max Unit Notes
Input clock frequency fCLKIN 101227MHz
Clock duty cycle 50:50 455055%1
Input clock rise time tR125ns
Input clock fall time tF125ns
CLKIN to PIXCLK propagation
delay
LOW-to-HIGH tPLHP CLOAD = 10pF 6 12 14 ns 3
HIGH-to-LOW tPHLP61014ns
PIXCLK to DOUT[7:0] at 27 MHz Setup time tDSETUP CLOAD = 10pF 11 18 ns 2
Hold time tDHOLD 11 18 ns
PIXCLK to FRAME_VALID and
LINE_VALID propagation delay
LOW-to-HIGH tPLHF,L CLOAD = 10pF 4 9.0 13 ns
HIGH-to-LOW tPHLF, L 47.513ns
Output rise time tOUTRCLOAD = 10pF 5 7.0 15 ns
Output fall time tOUTFCLOAD = 10pF 5 9.0 15 ns
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Electrical Specifications
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MT9V131_LDS_2.fm - Rev. B 3/07 EN 12 ©2006 Micron Technology, Inc. All rights reserved.
Preliminary
Figure 9: 44-Ball iCSP Package Outline
Notes: 1. All dimensions in millimeters.
2. iCSP package information is preliminary.
SEATING PLANE
7.00 ±0.075
3.50 ±0.052.25
2.25
ENCAPSULANT: EPOXY
IMAGE SENSOR DIE
LID MATERIAL: BOROSILICATE GLASS 0.40 THICKNESS
OPTICAL AREA
OPTICAL
CENTER
PACKAGE
CENTER
1.17 ±0.10
0.22
(FOR REFERENCE ONLY)
0.100
(FOR REFERENCE
ONLY)
0.95 (FOR REFERENCE ONLY)
5.30 CTR
4.50
3.584 CTR
3.500 ±0.075
BALL A1
CORNER
5.30
CTR
2.688
CTR
3.400 ±0.075
3.50 ±0.05
0.75 TYP
0.75 TYP
7.00 ±0.075
0.375 ±0.075
0.575 ±0.050
0.175
(FOR REFERENCE ONLY)
C
L
C
L
4.50
SUBSTRATE MATERIAL: PLASTIC LAMINATE
SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2%Ag
OR 96.5% Sn, 3%Ag, 0.5% Cu
SOLDER MASK DEFINED BALL PADS: Ø 0.27
MAXIMUM ROTATION OF OPTICAL AREA RELATIVE TO PACKAGE EDGES: 1º
MAXIMUM TILT OF OPTICAL AREA RELATIVE TO : 0.3º
0.10 AA
BALL A1 ID
BALL A1
BALL A7
44X Ø0.35
DIMENSIONS APPLY TO SOLDER
BALLS POST REFLOW. THE PRE-
REFLOW DIAMETER IS Ø0.33
PIXEL
(0,0)
B
B
MAXIMUM TILT OF OPTICAL AREA RELATIVE TO TOP OF COVER GLASS: 0.3º
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, the Micron logo, and DigitalClarity are trademarks of Micron Technology, Inc. All other trademarks are
the property of their respective owners.
Preliminary: This data sheet contains initial characterization limits that are subject to change upon full characterization of
production devices.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Electrical Specifications
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MT9V131_LDS_2.fm - Rev. B 3/07 EN 13 ©2006 Micron Technology, Inc. All rights reserved.
Preliminary
Figure 10: 48-Pin CLCC Package Outline
Notes: 1. Optical center = package center.
2. All dimensions are in millimeters.
Seating
plane
4.4
11.43
5.215 5.715
Lid material: borosilicate glass 0.55 thickness
Wall material: alumina ceramic
Substrate material: alumina ceramic 0.7 thickness
8.8
4.4 5.715
4.84
5.215
0.8
TYP 1.75
0.8 TYP
8.8
48 1
10.9 ±0.1
CTR
47X
1.0 ±0.2
48X R 0.15
48X
0.40 ±0.05
11.43 10.9 ±0.1
CTR
Lead finish:
Au plating, 0.50 microns
minimum thickness
over Ni plating, 1.27 microns
minimum thickness
2.3 ±0.2
1.7
First
clear
pixel
Optical
center
1
C A
B
Optical
area
Optical area:
Maximum rotation of optical area relative to package edges: 1º
Maximum tilt of optical area relative to
seating plane A : 50 microns
Maximum tilt of optical area relative to
top of cover glass D : 100 microns
A
D
0.90
for reference only
1.400 ±0.125
0.35
for reference only
V CTR
Ø0.20 A B C
H CTR
Ø0.20 A B C
Image
sensor die:
0.675 thickness
0.10 A 0.05
0.2 4X
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Revision History
PDF: 09005aef824c99b3/Source: 009005aef824c99bb Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9V131_LDS_2.fm - Rev. B 3/07 EN 14 ©2006 Micron Technology, Inc. All rights reserved.
Preliminary
Revision History
Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3/28/2007
Updated package diagram