August 2017
DocID028296 Rev 2
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This is information on a product in full production.
www.st.com
LDBL20
200 mA very low quiescent current linear regulator IC in
(0.47x0.47) mm² STSTAMP™ package
Datasheet - production data
Features
Input voltage from 1.5 to 5.5 V
Ultra low dropout voltage (200 mV typ. at
200 mA load)
Very low quiescent current (20 µA typ. at
no-load, 0.03 µA typ. in off mode)
Output voltage tolerance: ± 1.5% @ 25 °C
200 mA guaranteed output current
High PSRR (80 dB@1 kHz, 50 db@
100 kHz)
Wide range of output voltages available on
request: from 0.8 V up to 5.0 V in 50 mV
step
Logic-controlled electronic shutdown
Internal soft-start
Optional output voltage discharge feature
Compatible with ceramic capacitor
COUT = 0.47 µF
Internal constant current and thermal
protections
Available in STSTAMP™ (0.47x0.47) mm²
package
Operating temperature range: -40 °C to
125 °C
Applications
Mobile phones
Tablet
Digital still cameras (DSC)
Wearable devices
Portable media players
Description
The LDBL20 high accuracy voltage regulator
provides 200 mA of maximum current from an
input voltage ranging from 1.5 V to 5.5 V, with a
typical dropout voltage of 200 mV.
It is available in the new STSTAMP™ package,
allowing the maximum space saving.
The device is stabilized with a ceramic capacitor
on the output. The ultra low drop voltage, low
quiescent current and low noise features,
together with the internal soft-start circuit, make
the LDBL20 suitable for low power battery-
operated applications.
An enable logic control function puts the LDBL20
in shutdown mode with a total current
consumption lower than 0.2 µA. Constant current
and thermal protection are provided.
Contents
LDBL20
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Contents
1 Diagram ............................................................................................ 3
2 Pin configuration ............................................................................. 4
3 Typical application .......................................................................... 5
4 Maximum ratings ............................................................................ 6
5 Electrical characteristics ................................................................ 7
6 Application information .................................................................. 9
6.1 Soft-start function .............................................................................. 9
6.2 Output discharge function ................................................................. 9
6.3 Input output capacitors ...................................................................... 9
7 Typical characteristics .................................................................. 10
8 Recommendation on PCB assembly ........................................... 14
8.1 PCB design recommendations ........................................................ 14
8.2 Stencil ............................................................................................. 14
8.3 Solder paste .................................................................................... 14
8.4 Placement ....................................................................................... 14
8.5 Reflow profile .................................................................................. 15
9 Package information ..................................................................... 16
9.1 STSTAMP™ (0.47x0.47) mm² package information ....................... 17
10 Ordering information ..................................................................... 19
10.1 Marking information ......................................................................... 19
11 Revision history ............................................................................ 20
LDBL20
Diagram
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1 Diagram
Figure 1: Block diagram
The output discharge MOSFET is optional.
Pin configuration
LDBL20
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2 Pin configuration
Figure 2: Pin connection
"#" indicates the marking digit. Refer to Table 7: "Order code". The top horizontal
bar identifies pin 1 on top right corner.
Table 1: Pin description
Pin
Symbol
Function
3
OUT
Output voltage
4
GND
Common ground
1
EN
Enable pin logic input: low = shutdown, high = active
2
IN
Input voltage
LDBL20
Typical application
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3 Typical application
Figure 3: Typical application circuits
VIN
GND
VI
EN
CIn
VOVOUT
COut
LDBL20
OFF
ON
GIPD310820151119MT
Maximum ratings
LDBL20
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4 Maximum ratings
Table 2: Absolute maximum ratings
Symbol
Parameter
Value
Unit
VIN
Input voltage
- 0.3 to 7
V
VOUT
Output voltage
- 0.3 to VIN + 0.3
V
VEN
Enable input voltage
- 0.3 to 7
V
IOUT
Output current
Internally limited
mA
PD
Power dissipation
Internally limited
mW
TSTG
Storage temperature range
- 40 to 150
°C
TOP
Operating junction temperature range
- 40 to 125
°C
Absolute maximum ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. All values
are referred to GND.
Table 3: ESD performance
Symbol
Parameter
Test conditions
Value
Unit
ESD
ESD protection voltage
HBM
4
kV
MM
400
V
CDM
500
V
Table 4: Thermal performance
Symbol
Parameter
Value
Unit
RthJA
Thermal resistance junction-ambient
230
°C/W
LDBL20
Electrical characteristics
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5 Electrical characteristics
TJ = 25 °C, VIN = VOUT(NOM) + 1 V or 1.5 V, whichever is greater, CIN = COUT = 1 µF,
IOUT = 1 mA, VEN = VIN, unless otherwise specified.
Table 5: LDBL20 electrical characteristics
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VIN
Operating input
voltage
1.5
5.5
V
VOUT
VOUT accuracy
IOUT = 1 mA,
TJ = 25 °C
-1.5
+1.5
%
IOUT = 1 mA,
-40 °C<TJ<125 °C
-3
+3
%
∆VOUT
Static line
regulation(1)
VOUT(NOM) + 1 V ≤ VIN ≤ 5.5 V,
IOUT = 10 mA
0.02
%/V
-40 °C<TJ<125 °C
0.2
∆VOUT
Static load
regulation
IOUT = 0 mA to 200 mA
10
mV
-40 °C<TJ<125 °C
0.01
%/mA
VDROP
Dropout voltage
IOUT = 30 mA,
VOUT = 2.8 V
35
mV
IOUT = 200 mA,
VOUT = 2.8 V
-40 °C<TJ<125 °C
200
350
eN
Output noise
voltage
10 Hz to 100 kHz,
IOUT = 10 mA
45
µVRMS/VOUT
SVR
Supply voltage
rejection
VIN = VOUT(NOM)+ 1 V +/- VRIPPLE
VRIPPLE = 0.2 V
Frequency =1 kHz
IOUT = 30 mA
80
dB
VIN = VOUT(NOM)+ 1 V +/- VRIPPLE
VRIPPLE = 0.2 V
Frequency = 100 kHz
IOUT = 30 mA
55
IQ
Quiescent
current
IOUT = 0 mA
20
40
µA
IOUT = 200 mA
100
IStandby
Standby current
VIN input current in OFF mode:
VEN = GND
0.03
0.2
µA
ISC
Short-circuit
current
RL = 0
250
350
mA
RON
Output voltage
discharge
MOSFET
100
Ω
VEN
Enable input
logic low
VIN = 1.5 V to 5.5 V
-40 °C<TJ<125 °C
0.4
V
Enable input
logic high
VIN = 1.5 V to 5.5 V
-40 °C<TJ<125 °C
1
Electrical characteristics
LDBL20
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Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
IEN
Enable pin
input current
VEN = VIN
100
nA
TON(2)
Turn-on time
100
µs
TSHDN
Thermal
shutdown
160
°C
Hysteresis
20
COUT
Output
capacitor
Capacitance
0.47
22
µF
Notes:
(1)Not applicable for Vout(nom) > 4.5 V
(2)Turn-on time is time measured between the enable input just exceeding VEN high value and the output voltage
just reaching 95 % of its nominal value
LDBL20
Application information
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6 Application information
6.1 Soft-start function
The LDBL20 has an internal soft-start circuit. By increasing the startup time up to 100 µs,
without the need of any external soft-start capacitor, this feature keeps the regulator inrush
current at startup under control.
6.2 Output discharge function
The LDBL20 integrates a MOSFET connected between VOUT and GND. This transistor is
activated when the EN pin goes to low logic level and has the function to quickly discharge
the output capacitor when the device is disabled by the user.
The device is available with or without the auto-discharge feature. See Table 7: "Order
code".
6.3 Input output capacitors
The LDBL20 requires external capacitors to assure the regulator control loop stability.
Any good quality ceramic capacitor can be used but, the X5R and the X7R are suggested
since they guarantee a very stable combination of capacitance and ESR overtemperature.
Locating the input/output capacitors as closer as possible to the relative pins is
recommended.
The LDBL20 requires an input capacitor with a minimum value of 1 μF.
This capacitor must be located as closer as possible to the input pin of the device and
returned to a clean analog ground.
The control loop of the LDBL20 is designed to work with an output ceramic capacitor.
This capacitor must meet the requirements of minimum capacitance and equivalent series
resistance (ESR), as shown in Figure 17: "Stability area vs (COUT, ESR)". To assure
stability, the output capacitor must maintain its ESR and capacitance in the stable region,
over the full operating temperature range.
The LDBL20 shows stability with a minimum effective output capacitance of 220 nF.
However, to keep stability in all operating conditions (temperature, input voltage and load
variations), a minimum output capacitor of 0.47 µF is recommended.
The suggested combination of 1 μF input and output capacitors offers a good compromise
among the stability of the regulator, optimum transient response and total PCB area
occupation.
Typical characteristics
LDBL20
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7 Typical characteristics
(CIN = COUT = 1 µF, VEN to VIN, TJ = 25 °C unless otherwise specified)
Figure 4: Output voltage vs temperature
(IOUT = 1 mA)
Figure 5: Output voltage vs temperature
(IOUT = 200 mA)
Figure 6: Line regulation vs temperature
Figure 7: Load regulation vs temperature
Figure 8: Quiescent current vs temperature
(IOUT = 0 mA)
Figure 9: Quiescent current vs temperature
(IOUT = 200 mA)
Load regulation
LDBL20
Typical characteristics
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Figure 10: Shutdown current vs temperature
Figure 11: Quiescent current vs load current
Figure 12: Quiescent current vs input voltage
Figure 13: Dropout voltage vs temperature
Figure 14: Supply voltage rejection vs
frequency
Figure 15: Supply voltage rejection vs input
voltage
Typical characteristics
LDBL20
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Figure 16: Output noise spectral density
Figure 17: Stability area vs (COUT, ESR)
Figure 18: Enable startup (VOUT = 1 V)
Figure 19: Enable startup (VOUT = 5 V)
Figure 20: Turn-on time (VOUT = 1 V)
Figure 21: Turn-off time (VOUT = 1 V)
LDBL20
Typical characteristics
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Figure 22: Turn-on time (VOUT = 5 V)
Figure 23: Turn-off time (VOUT = 5 V)
Figure 24: Line transient (VOUT = 1 V)
Figure 25: Line transient (VOUT = 5 V)
Figure 26: Load transient (VOUT = 1 V)
Figure 27: Load transient (VOUT = 5 V)
Recommendation on PCB assembly
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8 Recommendation on PCB assembly
8.1 PCB design recommendations
PCB PAD design: non solder mask defined
PCB pad size: see drawing in Figure 30: "STSTAMP™ (0.47x0.47) mm²
recommended footprint"
Solder mask opening: 50 μm between the edge of the pad and the edge of the solder
mask
To keep under control the solder paste amount, closed vias are recommended
instead of open vias
The position of tracks and open vias in the solder area should be well balanced. A
symmetrical layout is recommended, to reduce the effect of tilt phenomena caused by
asymmetrical solder paste amount due to the solder flowing away
8.2 Stencil
Stencil aperture: see drawing in Figure 31: "STSTAMP™ (0.47x0.47) mm²
recommended solder stencil"
Stencil thickness: 75 μm
8.3 Solder paste
95.8% Sn, 3.5% Ag, 0.7% Cu solder paste
Halide-free flux qualification ROL0 according to ANSI/J-STD-004
“No clean” solder paste is recommended.
Offers a high tack force to resist component movement during high speed
Solder paste with fine particles: powder particle size is 20-45 μm.• type 4
8.4 Placement
Manual positioning is not recommended
It is recommended to use the lead recognition capabilities of the placement system,
not the outline centering
Standard tolerance of ± 0.05 mm is recommended
3.5 N placement force is recommended. Too much placement force can lead to
squeezed out solder paste and cause solder joints to short. Too low placement force
can lead to insufficient contact between package and solder paste that could cause
open solder joints or badly centered packages
To improve the package placement accuracy, a bottom side optical control should be
performed with a high resolution tool
For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is
recommended during solder paste printing, pick and place and reflow soldering by
using optimized tools
LDBL20
Recommendation on PCB assembly
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8.5 Reflow profile
Figure 28: ST ECOPACK® recommended soldering reflow profile for PCB mounting
Minimize air convection currents in the reflow oven to avoid component
movement. Maximum soldering profile corresponds to the latest IPC/JEDEC
J-STD-020.
Package information
LDBL20
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9 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
LDBL20
Package information
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9.1 STSTAMP™ (0.47x0.47) mm² package information
Figure 29: STSTAMP™ (0.47x0.47) mm² package outline
Package information
LDBL20
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Table 6: STSTAMP™ (0.47x0.47) mm² mechanical data
Dim.
mm
Min.
Typ.
Max.
A
0.18
0.200
0.220
b
0.060
0.065
0.070
b1
0.109
0.114
0.119
E
0.450
0.480
0.510
E1
0.208
0.213
0.218
E2
0.019
0.024
0.029
E3
0.034
0.039
0.044
D
0.450
0.480
0.510
D1
0.252
0.257
0.262
D2
0.255
0.260
0.265
fE
0.095
0.101
0.106
fD
0.106
0.111
0.116
Figure 30: STSTAMP™ (0.47x0.47) mm² recommended footprint
Figure 31: STSTAMP™ (0.47x0.47) mm² recommended solder stencil
0.25 0.25
0.1
0.25 0.25
0.1
180 µm
180 µm
120 µm
180 µm 180 µm
120 µm
LDBL20
Ordering information
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10 Ordering information
Table 7: Order code
Order code
Output voltage (V)
Auto-discharge
Marking
Packing
LDBL20D-18R
1.8
Yes
A
Tape and reel
LDBL20D-25R
2.5
B
LDBL20D-33R
3.3
C
10.1 Marking information
Figure 32: Marking composition (marking view)
The symbol "#" indicates the marking digit, as per Table 7: "Order code".
Revision history
LDBL20
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11 Revision history
Table 8: Document revision history
Date
Revision
Changes
10-Nov-2015
1
Initial release
02-Aug-2017
2
Updated Section 2: "Pin configuration", Table 5: "LDBL20 electrical
characteristics ".
Added Section 8: "Recommendation on PCB assembly".
Updated Section 10: "Ordering information".
Minor text changes.
LDBL20
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