CYIL2SM1300AA
LUPA 1300-2: High Speed CMOS
Image Sensor
Cypress Semiconductor Corporation • 198 Champion Court • San Jose
,
CA 95134-1709 • 408-943-2600
Document Number: 001-24599 Rev. *C Revised September 18, 2009
Features
■
1280 x 1024 Active Pixels
■
14 µm X 14 µm Square Pixels
■
1” Optical Format
■
Monochrome or Color Digital Output
■
500 fps Frame Rate
■
On-Chip 10-Bit ADCs
■
12 LVDS Serial Outputs
■
Random Programmable ROI Readout
■
Pipelined and Triggered Snapshot Shutter
■
On-Chip Column FPN Correction
■
Serial to Parallel Interface (SPI)
■
Limited Supplies: Nominal 2.5V and 3.3V
■
0°C to 70°C Operational Temperature Range
■
168-Pin µPGA Package
■
Power Dissipation: 1350 mW
Applications
■
High Speed Ma chine Vision
■
Motion Analysis
■
Intelligent Traffic System
■
Medical Imaging
■
Industrial Imaging
Description
The LUPA 1300-2 is an integrated SXGA high speed, high
sensi¬tivity CMOS image sensor. This sensor targets high speed
machine vision and industrial monitoring applications. The LUP A
1300-2 sensor runs at 500 fps and ha s triggered and pipelined
shutter modes. It packs 24 p arallel 10-bit A/D converters with an
aggregate conversion rate of 740 MSPS. On-chip digital column
FPN correction enables the sensor to output ready to use image
data for most applications. To enable simple and reliable system
integration, the 12 channels, 1 sync channel, 8 Gbps, and LVDS
serial link protocol supports skew correction and serial link
integrity monitoring.
The peak responsivity of the 14 µm x 14 µm 6T pixel is 7350
V.m2/W.s. Dynamic range is measured at 57 dB. In full frame
video mode, the sensor consumes 1350 mW from the 2.5V
power supply. The sensors integrate A/D conversion, on-chip
timing for a wide range of operating modes, and has an LVDS
interface for easy system integration.
By removing the visually disturbing column patterned noise, this
sensor enables buil ding a camera with out any offline correction
or the need for memory. In addition, the on-chip column FPN
correction is more relia ble than an offline correction, because it
compensates for supply and temperature variations. The sensor
requires one master clock for operations up to 50 0 fps.
The LUPA 1300-2 is housed in a 168 pin µPGA package and is
available in a monochrome versi on and Bayer (RGB) patterned
color filter array. The monochrome version is available without
glass. Contact your local Cypress office.
Figure 1. LUPA 1300-2 Die Photo
Note
1. Contact your local sales office for the windowless option.
Ordering Information
Marketing Part Number Mono/Color Package
CYIL2SM1300AA-GZDC Mono with Glass 168 pin µPGACYIL2SM1300AA-GWCES Mono without Glass
[1]
CYIL2SC1300AA-GZDC Color with Glass
CYIL2SM1 300-EVAL Mono Demo Kit Demo Kit
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CYIL2SM1300AA
Document Number: 001-24599 Rev. *C Page 2 of 41
Overview
This data sheet describes the interface of the LUPA1300-2
image sensor. The SXG A resolution CMOS active pixel sensor
features synchronous shutter and a maximal frame rate of
500 fps in full resolution. The read out speed is boosted by sub
sampling and the windowed region of interest (ROI) readout.
FPN correction cannot be used in conjunction with sub-sampling
and windowed region of interest readout. High dynamic range
scenes can be captured using the double and multiple slope
functionality. User programmable row and column start and stop
positions enables windo wing. Sub sampling reduces resolution
while maintaining the constant field of view and an increased
frame rate.
The LUPA1300-2 sensor has 12 LVDS high speed outputs that
transfer image data over longer distances. This simplifies the
surrounding system. The L VDS interface can receive high speed
and wide bandwidth data signals and maintain low noise and
distortion. A special training mode enables the receiving system
to synchronize the coming data stream when switching to
master, slave, or triggered mode. The image sensor also
integrates a programmable offset and gain amplifier for each
channel.
A 10-bit ADC converts the analog data to a 10-bit digital word
stream. The sensor uses a 3-wire Serial-Parallel Interface (SPI).
It requires only one master clock for operation up to 500 fps.
The sensor is available in a monochrome version or Bayer (RGB)
patterned color filter array . It is placed in a 168-pin ceramic µPGA
package.
Specifications
Table 1. General Specifications
Parameter Specifications
Active Pixels 1280 (H) x 1024 (V)
Pixel Size 14 µm x 14 µm
Pixel Type 6T pixel architecture
Pixel Rate 630 Mbps per channel (12 serial
LVDS outputs)
Shutter Type Pipelined and Triggered Global
Shutter
Frame Rate 500 fps at 1.3 Mpixel (boosted by
subsampling and windowing)
Master Clock 315 MHz for 500 fps
Windowing (ROI) Randomly programmable ROI rea d
out up to four multiple windows
Read Out Windowed, flipped, mirrored, and
subsampled read out possible
ADC Resolution 10-bit, on-chi p
Sensitivity 10.16 V/lux.s at 550 nm
Extended Dynamic
Range Multiple slope (up to 90 dB optical
dynamic range)
Table 2. Electro Optical Specifications
Parameter Value
Conversion gain 34µV/e
-
Full well charge 30000e
-
Responsivity 7350 V.m
2
/W.s at 680 nm
Fill factor 40%
Parasitic light sensitivity < 1/10000
Dark noise 37e
-
QE x FF 35% at 680 nm
FPN 2% rms of the output swing
PRNU <1% rms of the output signal
Dark signal 170 mV/s at 30°C
Power dissipation 1350 mW
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Document Number: 001-24599 Rev. *C Page 5 of 41
Electrical Specifications
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 3. Absolute Ratings
[2]
Symbol Parameter Min Max Unit
s
V
DIG
Core digital supply voltage -0.5 5.5 V
V
IN
Analog supply voltage -0.5 5.5 V
I
IO
DC supply current mA
ESD: HBM Human Body Mode l 2000 V
ESD: CDM Charged Device Model 500 V
T
J
Tempe r ature range 0 70 °C
Table 4. Power Supply Ratings
[3, 4, 5]
Boldface limits apply for T
A
=T
MIN
to T
MAX
, all other li mits T
A
=+25°C. Clock = 315 MHz
Symbol Power Supply Parameter Condition Min Typ Max Units
V
ANA
, GND
ANA
Analog Supply Operating voltage -5% 2.5 +5% V
Dynamic Current Clock enabled, lux=0 7 20 mA
Peak Current Clock enabled, lux=0 16 mA
Standby current Shutdown mode, lux=0 1 mA
V
DIG
, GND
DIG
Digital Supply Operating voltage -5% 2.5 +5% V
Dynamic Current Clock enabled, lux=0 80 120 mA
Peak Current Clock enabled, lux=0 130
Standby current Shutdown mode, lux=0 52 mA
V
PIX,
GND
PIX
Pixel Supply Operating voltage -5% 2.5 +5% V
Dynamic Current Clock enabled, lux=0 6 50 mA
Peak Current during FOT Clock enabled, lux=0,
transient duration=9 µs 1.4 A
Peak Current during ROT Clock enabled, lux=0,
transient duration=2.5 µs 35 mA
Standby current Shutdown mode, lux=0 1 mA
V
LVDS
,
GND
LVDS
LVDS Supply Operating voltage -5% 2.5 +5% V
Dynamic Current Clock enabled, lux=0 220 275 mA
Peak current Clock enabled, lux=0 280 mA
Standby current Shutdown mode, lux=0 100 mA
V
ADC
, GND
ADC
ADC Supply Operating voltage -5% 2.5 +5% V
Dynamic Current Clock enabled, lux=0 210 275 mA
Peak Current Clock enabled, lux=0 260 mA
Standby current Shutdown mode, lux=0 3 mA
Notes
2. Absolute ratings are those values beyond which damage to the device may occur.
3. All parameters are characterized for DC conditions after thermal equilibrium is established.
4. Peak currents were measured without the load capacitor from the LDO (Low Dropout Regulator). The 100 nF capacitor bank was connected to the pin in question.
5. This device contains circuitry to prot ec t the inputs against damage due t o high static voltages o r electric f ields. However, it is recommended that normal precautions
be taken to avoid application of any voltages higher than the maximum rated voltages to this high impedance circuit.
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Every module in the image sensor has its own power supply and
ground. The grounds can be combined externally, but not all
power supply inputs may be combined. Some power supplies
must be isolated to reduce electrical crosstalk and improve
shielding, dynamic range, and output swing. Internal to the
image sensor , the ground lines of each module are kept separate
to improve shielding and electrical crosstalk between them.
The LUPA 1300-2 contains circuitry to protect the inputs against
damage due to high static voltages or electric fields. However,
take normal precautions to avoid voltages higher than the
maximum rated voltages in this high impedance circuit. Unused
inputs must always be tied to an appropriate logic level, for
example, V
DD
or GND. All cap_xxx pins must be connected to
ground through a 100 nF capacitor.
The recommended combinations of supplies are:
■
Analog group of +2.5V supply: V
SAMPLE
, V
RES_DS
, V
MEM_L
,
V
ADC
, V
pix
, V
ANA
, V
BUF
■
Digital Group of +2.5V supply: V
DIG
, V
LVDS
V
BUF
, GND
BUF
Buffer Supply Operating voltage -5% 2.5 +5% V
Dynamic Current Clock enabled, lux=0 30 50 mA
Peak Current Clock enabled, lux=0 85 mA
Standby current shutdown mode, lux=0 0.1 mA
V
SAMPLE
,
GND
SAMPLE
Sampling
Circuitry Supply Operating voltage -5% 2.5 +5% V
Dynamic Current Clock enabled, lux=0 2 mA
Peak Current Clock enabled, lux=0 42 mA
Standby current Shutdown mode, lux=0 1 mA
V
RES
Reset Supply Operating voltage -5% 3.5 +5% V
Dynamic Current Clock enabled, lux=0 2 15 mA
Peak Current Clock enabled, lux=0 65 mA
Standby current Shutdown mode, lux=0 2 mA
V
RES_AB
Antiblooming
Supply Operating voltage -10% 0.7 +10% V
Dynamic Current Clock enabled, lux=0 1 mA
Peak Current following
edge reset Clock enabled, lux=0 50 mA
Standby current Shutdown mode, lux=0 1 mA
V
RES_DS
Reset Dual
Slope Supply Operating voltage -5% 2.5 +5% V
Dynamic Current Clock enabled, lux=0 0.4 3 mA
Peak Current Clock enabled, lux=0 36 mA
V
RES_TS
Reset Triple
Slope Supply Operating voltage -5% 1.8 +5% V
Dynamic Current Clock enabled, lux=0 0.3 2 mA
Peak Current Clock enabled, lux=0 14 mA
V
MEM_L
Memory
Element low
level supply
Operating voltage -5% 2.5 +5% V
Dynamic Current Clock enabled, lux=0 0.2 1 mA
Peak Current during FOT Clock enabled, lux=0 62 mA
Peak Current during FOT Clock enabled, bright 30 mA
V
MEM_H
Memory
Element high
level supply
Operating voltage -5% 3.3 +5% V
Dynamic Current Clock enabled, lux=0 1 mA
Peak Current during FOT Clock enabled, lux=0 45 mA
V
PRECH
Pre_charge
Driver Supply Operating voltage -10% 0.7 +10% V
Dynamic Current Clock enabled, lux=0 0.3 3 mA
Peak Current during FOT Clock enabled, lux=0 32 mA
Peak Current during FOT Clock enabled, lux=brigh t 25 mA
Table 4. Power Supply Ratings
[3, 4, 5]
(continued)
Boldface limits apply for T
A
=T
MIN
to T
MAX
, all other li mits T
A
=+25°C. Clock = 315 MHz
Symbol Power Supply Parameter Condition Min Typ Max Units
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Document Number: 001-24599 Rev. *C Page 7 of 41
Sensor Architecture
The floor plan of the architecture is shown in F igure 5. The sen sor consists of a pixel array, analog front en d, data block, and LVDS
transmitters and receivers. Separate modules for th e SPI, clock division, and sequencer are also integrated. The image sensor of
1280 x 1024 pixels is read out in progressive scan.
This architecture enables programmable addressing in the x-direction in steps of 24 pixels, and in the y-direction in steps of one pixel.
The starting point of the address can be uploaded by the serial parallel interface (SPI).
The AFE prepares the signal for the digital data block when the data is multiplexed and prepared for the LVDS interface.
Figure 5. Floor Plan of the Sensor
Table 5. Power Dissipation
[3]
These specifications ap ply for V
DD
= 2.5V, Clock = 315 MHz, 500 fps
Symbol Parameter Condition Typ Units
P
DOWN
Power down no clock running 400 mW
Power Average Power Dissipation lux = 0 1350 mW
Table 6. AC Electrical Characteristics
[3]
The following specifications apply for VDD = 2.5V, Clock = 315 MHz, 500 fps.
Symbol Parameter Condition Typ Max Units
F
CLK
Input Clock Frequency fps = 500 315 MHz
DC
CLK
Clock Duty Cycle At maximum clock 50 %
fps Frame rate Maximum clock spee d 500 fps
Image core
1280 x 1024
24 analog channels 31.5 Msps
Analog front end
24x 10-bit digital channels 31.5 Msps
Data block
Local re gi ster
12x 10-bit digital channels 63 Msps
LVDS TX and RX
12x LVDS outputs at 630 Msps
Clock
Divider Clk out
Clk in
Sequencer
&
Logic
SPI
31.5 MHz
315 MHz
63 MHz
Clk X & Clk Y
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Document Number: 001-24599 Rev. *C Page 8 of 41
The 6T Pixel
To obtain the global shutter feature combined with a high
sensitivity and good parasitic light sensitivity (PLS), implement
the pixel architecture sho wn in Figure 6. This pixel architecture
is designed in a 14 µm x 14 µm pixel pitch. The pixel is designed
to meet the specifications listed in Table 1 and Table 2 on page
2. This architecture also enables pipelined or triggered mode, as
shown in Figure 6.
Figure 6. 6T Pixel Architecture
Frame Rate and Windowing
Frame Rate
The frame rate depends on the input clock, the frame overh ead
time (FOT), and the row overhead time (ROT). The frame period
is calculated by:
Frame period = FOT+Nr. Lines * (ROT + Nr. Pixels * clock period)
Example
Readout of the full resoluti on at nominal speed (756 MHz pixel
rate = 1.32 ns)
Frame period = 5 µs + (1025 * (206 ns+1.32 ns*1296) = 1.97 ms
=> 507 fps
The real speed of the LUPA1300-2 is reduced to 500 fps,
because overhead pixe ls are read ou t for bl ack level cali bration
and other on board features.
Windowing
Windowing is easily achieved by SPI. The starting point of the x
and y address and the window size can be uploaded. The
minimum step size in the x-direction is 24 pixels (choose only
multiples of 24 as start or stop addresses). The minimum step
size in the y-direction is one line (every line can b e addressed)
in normal mode, and two lines in sub sampling mode.
The section Sequencer on page 10 discusses the use of
registers to achieve the desired ROI.
Analog to Digital Converter
The sensor has 24 10-bit pi pelined ADCs on board. The AD Cs
nominally operate at 31.5 Msample s/s.
Programmable Gain Amplifiers
The PGAs amplify the signal before sending it to the ADCs.
The amplification inside the PGA is controlled by one SPI setting:
afemode [5:3].
Six gain steps can be selected by the afemode<5:3> register.
Table 10 lists the six gain settings. The unity gain selection of the
PGA is done by the default afemode<5:3> setting.
Table 7. Frame Rate Parameters
Parameter Comment Clarification
FOT Frame Overhead
Time Programmable: Default
315 MHz granularity clock
cycles (5 µs at 630 MHz)
ROT Row Overhead
Time Programmable: Default 13
granularity clock cycles
(206 ns at 630 MHz)
Nr. Lines Numbe r of lines
read out each
frame
Nr. Pixels Number of pixels
read out each line
Clock Period 1/63 MHz = 15.9 ns Every channel works at
63 MHz Æ12 channels
result in 756 MHz data rate
Vpix Vmem
Reset
Sample Select
Table 8. Typical Frame Rates for 630 MHz Clock
Image
Resolution (X*Y) Frame Rate
(fps) Frame Read
Out Time (µs)
1296x1025 507 1970
640 x 512 1842 550
256 x 256 6933 146
Table 9. ADC Parameters
Parameter Specification
Data rate 31.5 Msamples/s
Quantization 10 bit
DNL Typ. < 1 DN
INL Typ. < 1 DN
Table 10. Gain Settings
afemode<5:3> Gain
000 1
001 1.5
010 2
011 2.25
100 3
101 4
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Document Number: 001-24599 Rev. *C Page 9 of 41
Operation and Signaling
Digital Signals
Depending on the operation mode (Master or Slave), the pixel array of the image sensor requires different digital control signals. The
function of each signal is listed in this table.
Synchronous Shutter
In a synchronous (snapshot or global) shutter, light integration occurs on all pixels in parallel, although subsequent readout is
sequential. Figure 7 shows the integration and readout sequence for the synchronous shutter . All pixels are light sensitive at the same
period of time. The whole pixel core is reset simultaneously, and after the integration time , all pixel values are sampled together on
the storage node inside each pixel. The pixel core is read out line by line after integration. Note that the integration and readout cycle
can occur in parallel or in sequential mode (pipelined or triggered). Refer to the section Image Sensor Timing and Readout on page 18.
Figure 7. Synchronous Shutter Operation
Table 11. Overview of Digital Signals
Signal Name I/O Comments
MONITOR_1 Output Output pin for integration timin g, high during integration
MONITOR_2 Output Output pin for dual slope integration timing, high during integration
MONITOR_3 Output Output pin for triple slope integration timing, high during integration
INT_TIME_3 Input Integration pin triple slope
INT_TIME_2 Input Integration pin dual slop e
INT_TIME_1 Input Integration pin first slope
RESET_N Input Sequencer reset, active LOW
CLK Input System clock (630 MHz)
SPI_CS Input SPI chip select
SPI_CLK Input Clock of the SPI
SPI_IN Input Data line of th e SPI, serial input
SPI_OUT Output Data line of the SPI, serial output
Time axis
Line number
Integration Time Burst Readout
ti
COMM ON RESE T
COMMON SAM PLE&HOLD
Flash could occ ur here
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Non Destructive Readout (NDR)
Figure 8. Principle of Non Destructiv e Read out
The sensor can also be read out in a nondestructive method. After a pixel is initially reset, it can be read multiple times, without being
reset. You can record the initial reset level and all intermediate signals. High light levels saturate the pixels quickly, but a useful signal
is obtained from the early samples. For low light levels, the later or latest samples must be used. Essentially, an active pixel array is
read multiple times, and reset only once. Th e external system inte lligence interprets the data. Table 12 on page 10 summarizes the
advantages and disadvantages of nondestructive readout.
Note that the amount of sa mples taken with one initial reset is programmable in the nr_of_ ndr_steps register. If nr_of_nd r_steps is
one, the sensor operates in th e default met hod , that is one reset and one sampl e. This is calle d the disab le no ndestructive read out
mode.
When nr_of_ndr_steps is two, there is one reset and two samples, and so on. In the slave mode, nothing changes on the protocol of
the signals int_time_*. The sequencer suppresses the internal reset signal to the pixel array.
Sequencer
The sequencer generates th e complete internal timing of the pixel array and the readout. The timing can be controlled by the user
through the SPI register settings. The seq uencer opera tes on the same clock a s the data block. This is a division b y 10 of the input
clock (internally divided).
Table 13 lists the internal registers. These registers are discussed in detail in the section Detailed Description of Internal Registers on
page 15.
Table 12. Advantages and Disadvantages of Non Destructive Readout
Advantages Disadvantages
Low noise, because it is true CDS System memory required to record the reset level and the
intermediate samples
High sensitivity. The conversion capacitance is kept low. Requires multiples read ings of each pixel, so there is higher data
throughput
High dynamic range. The results include signals for short and
long integration times. Requires system level digital calculations
Table 13. Internal Registers
Block Register Name Address [6..0] Field Reset Value Description
MBS (reserved) Fix1 0 [7:0] 0x00 Reserved, fixed value
Fix2 1 [7:0] 0xFF Reserved, fixed value
Fix3 2 [7:0] 0x00 Reserved, fixed value
Fix4 3 [7:0] 0x00 Reserved, fixed value
Fix5 4 [7:0] ‘0x08’ Reserved, fixed value
time
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LVDS clk
divider lvdsmain 5 [3:0] ‘0110’ lvds trim
[7:4] 0 clkadc phase
lvdspwd1 6 [7:0] 0x00 Power down channel 7:0
lvdspwd2 7 [5:0] 0 Power down channel 13:8
[6] 0 Power down all channels
[7] 0 lvds test mode
Fix6 8 [7:0] 0x00 Reserved, fixed value
AFE afebias 9 [3:0] ‘1000’ afe current biasing
afemode 10 [2:0] ‘111’ vrefp, vrefm settings
[5:3] ‘000’ Pga settings
[6] 0 Power down AFE
afepwd1 11 [7:0 ] 0x00 Power down adc_channel_2x 7 to 0
afepwd2 12 [3:0] 0x00 Power down adc_channel_2x 11 to 8
Bias block bandgap 13 [0] ‘0’ Power down bandgap and currents
[1] ‘1’ External resist or
[2] ‘0’ External voltage reference
[5:3] ‘000’ Bandgap trimming
Image Core imcmodes 14 [0] 0 Power down
[1] ‘1’ Enable vrefcol regulator
[2] ‘1’ Enable precharge regulator
[3] 0 Disable internal bias for vprech
[4] ‘1’ Disable column load
[5] ‘0’ clkmain invert
Fix7 15 [7 :0] 0x00 Reserved, fixed value
Fix8 16 [7 :0] 0x00 Reserved, fixed value
imcbias1 17 [3:0] ‘1000’ Bias colfpn DAC buffer
[7:4] ‘1000’ Bias precharge regulator
imcbias2 18 [3 :0] ‘1000’ Bias pixel precharge level
[7:4] ‘1000’ Bias column ota
imcbias3 19 [3 :0] ‘1000’ Bias column unip fast
[7:4] ‘1000’ Bias column unip slow
Imcbias4 20 [3:0] ‘1000’ Bias column load
[7:4] ‘1000’ Bias column precharge
Table 13. Internal Registers (continued)
Block Register Name Address [6..0] Field Reset Value Description
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Data Block Fix9 21 [7:0] 0x20 Reserved, fixed value
Fix10 22 [7:0] 0xC0 Reserved, fixed value
dataconfig1 23 [1 :0] 0x00 Reserved, fixed value
[2] 0 ‘1’: Enables user upload of dacvrefadc register value
‘0’: Keeps default value
[3] 0 Enable PRBS generation
[4] 0 Reserved, fixed value
[5] 0 Reserved, fixed value
[7:6] 0x03 Training pattern inserted to sync LVDS receivers
dataconfig2 24 [7:0] 0x2A Training pattern inserted to sync LVDS receivers
Fix11 25 [7:0] 0 Reserved, fixed value
dacvrefadc 26 [7:0] 0x80 Input to DAC to set the offset at the input of the ADC
Fix12 27 [7:0] 0x80 Reserved, fixed value
Fix13 28 [7:0] Reserved, fixed value
Fix14 29 [7:0] Reserved, fixed value
datachannel0_1 30 [0] 0 Bypass the data block
[1] 0 Enables the FPN correction
[2] 0 Overwrite incoming ADC data by the data in the
testpat register
[3] 0 Reserved, fixed value
[5:4] 0x00 Pattern inserted to generate a test image
datachannel0_2 31 [7:0] 0x00 Pattern inser ted to generate a test image
datachannel1_1 32 [0] 0 Bypass the data block
[1] 0 Enables the FPN correction
[2] 0 Overwrite incoming ADC data by the data in the
testpat register
[3] 0 Reserved, fixed value
Data Block
(continued) [5:4] 0x00 Pa ttern inse r ted to generate a test image
datachannel1_2 33 [7:0] 0x00 Pattern inser ted to generate a test image
datachannel12_1 54 [0] 0 Bypass the data block
[1] 0 Enables the FPN correction
[2] 0 Overwrite incoming ADC data by the data in the
testpat register
[3] 0 Reserved, fixed value
[5:4] 0x00 Pattern inserted to generate a test image
datachannel12_2 55 [7:0] 0x00 Pattern inserted to generate a test image
Table 13. Internal Registers (continued)
Block Register Name Address [6..0] Field Reset Value Description
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Sequencer seqmode1 56 [0] 0 Enables image capture
[1] 1 ‘1’: Master mode, integration timing is generated
on-chip
‘0’: Slave mode, integration ti ming is controlled
off-chip through INT_TIME1, INT_TIME2 and
INT_TIME3 pins
[2] 0 ‘0’: Pipelined mode
‘1’: T riggered mode
[3] 0 Enables(‘1’)/disables(‘0’) subsampling
[4] 0 ‘1’: Color subsampling scheme: 1:1:0:0:1:1:0:0
‘0’: B&W subsampling scheme: 1:0:1:0:1
[5] 0 Enable dual slope
[6] 0 Enable triple slope
[7] 0 Enables continued row select (that is, assert row
select during pixel read out)
seqmode2 57 [4:0] ‘10000’ Must be overwritten with‘10001’ to this register after
startup, before readout.
[6:5] ‘00’ Number of active windows:
“00”: 1 window
“01”: 2 windows
“10”: 3 windows
“11”: 4 windows
seqmode3 58 [0] ‘1’ Enables the generation of the CRC10 on the data
and sync channels
[1] ‘0’ Not applicable
[2] ‘0’ Enable column fpn calibration
[5:3] “001” Number of frames in nondestructive read out:
“000”: invalid
“001”: one reset, one sample (defau lt mode)
“010”: one reset, two samples
…
[6] 0 Controls the granularity of the timer settings (only for
those that have ‘granularity selectable’ in the
description):
‘0’: Expressed in number of lines
‘1’: Expressed in clock cycles (multiplied by
2**seqmode4[3:0])
[7] 0 Allows delaying the syncing of eve nts that happen
outside of ROT to the next ROT. This avoids image
artefacts.
Table 13. Internal Registers (continued)
Block Register Name Address [6..0] Field Reset Value Description
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seqmode4 59 [3:0] 0x00 Multiplier factor (=2**seqmode4[3:0]) for the timers
when working in clock cycle mode
[5:4] 0x0 Selects the source signals to put on the digital test
pins (monitor pins):
“00”: integration time settings
“01”: EOS signals
“10”: frame sync signals
“11”: functional test mode
[6] ‘0’ Reverse read out in X direction
[7] ‘0’ Reverse read out in Y direction
window1_1 60 [7 :0 ] 0x00 Y start address for window 1
window1_2 61 [1 :0 ] 0x00 Y start address for window 1
[7:2] 0x00 X start address for window 1
window1_3 62 [ 7:0] 0xFF Y end address for window 1
window1_4 63 [1:0] 0x3 Y end address for window 1
[7:2] 0x36 X width for window 1
window2_1 64 [7:0] 0x00 Y start address for window 2
window2_2 65 [1:0] 0x00 Y start address for window 2
[7:2] 0x00 X start address for window 2
window2_3 66 [7:0] 0xFF Y end address for window 2
window2_4 67 [1:0] 0x3 Y end address for window 2
[7:2] 0x36 X width for window 2
window3_1 68 [7:0] 0x00 Y start address for window 3
window3_2 69 [1:0] 0x00 Y start address for window 3
[7:2] 0x00 X start address for window 3
window3_3 70 [7:0] 0xFF Y end address for window 3
window3_4 71 [1:0] 0x3 Y end address for window 3
[7:2] 0x36 X width for window 3
window4_1 72 [7:0] 0x00 Y start address for window 4
window4_2 73 [1:0] 0x00 Y start address for window 4
[7:2] 0x00 X start address for window 4
window4_3 74 [7:0] 0xFF Y end address for window 4
window4_4 75 [1:0] 0x3 Y end address for window 4
[7:2] 0x36 X width for window 4
res_length1 76 [7:0] 0x02 Length of pix_rst (granularity selectable)
res_length2 77 [7:0] 0x00 Length of pix_rst (granularity selectable)
res_dsts_length 78 [7:0] 0x01 Length of resetds and resetts (granularity
selectable)
tint_timer1 79 [7:0] 0xFF Length of integratio n time (granularity selectable)
tint_timer2 80 [7:0] 0x03 Length of integration ti me (granularity selectable)
tint_ds_timer1 81 [7:0] 0x40 Length of DS integration time (granularity
selectable)
tint_ds_timer2 82 [1:0] 0x00 Length of DS integration time (granularity
selectable)
tint_ts_timer1 83 [7:0] 0x0C Length of TS integration time (granularity
selectable)
tint_ts_timer2 84 [1:0] 0x00 Length of TS integration time (granularity
selectable)
Table 13. Internal Registers (continued)
Block Register Name Address [6..0] Field Reset Value Description
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Document Number: 001-24599 Rev. *C Page 15 of 41
Detailed Description of Internal Registers
The registers must be changed only during idle mode, that is,
when seqmode1[0] is ‘0’. Uploaded registers have an immediate
effect on how the frame is read out. Parameters uploaded during
readout may have an undesired effect on the data coming out of
the images.
MBS Block
The register block contains registers for sensor testing and
debugging. All registers in this block must remain unchanged
after startup.
LVDS Clock Divider Block
This block controls division of the input clock for the LVDS
transmitters or receivers. This block also enables shutting down
one or all LVDS channels. For normal operation, this register
block must remain untouched after startup.
AFE Block
This register block contains registers to shut down ADC
channels or the complete AFE block. This block also contains the
register for setting the PGA gain: AFE_mode[5:3]. Refer to
Electrical Specifications on page 5 for more details on the PGA
settings.
Biasing Blo ck
This block contains several registers for setting biasing currents
for the sensor. Default values after startup must remain
unchanged for normal operation of the sensor.
Image Core Block
The registers in this block have an impact on the pixel array itself.
Default settings after startup must remain unchanged for normal
operation of the image sensor.
Data Block
The data block is positioned in between the analog front end
(output stage + ADCs) and the LVDS interface. It muxes the
outputs of 2 ADCs to one LVDS block and performs some minor
data handling:
■
CRC calculation and insertion
■
Training and test pattern generation
The most important registers in this blo ck are :
Dataconfig. The dataconfig1[7:6] and dataconfig2[7:0] registers
insert a training pattern in the LVDS channels to sync the LVDS
receivers.
tint_black_timer 85 [7:0] 0x06 Reserved, fixed value
rot_timer 86 [7:0] 0x0D Length of ROT (granularity clock cycles)
fot_timer 87 [7:0] 0x36 Length of FOT (granularity clock cycles)
fot_timer 88 [1:0] 0x01 Length of FOT (granularity clock cycles)
prechpix_timer 89 [7:0] 0x7C Length of pixel precharge (gra nularity clock cycles)
prechpix_timer 90 [1:0] 0x00 Length of pixel precharge (gra nularity clock cycles)
prechcol_timer 91 [7:0] 0x03 Length of c olumn precharge (granularity clock
cycles)
rowselect_timer 92 [7:0] 0x09 Length of rowselect (granu larity clock cycles)
sample_timer 93 [7:0] 0xF8 Length of pixel_sample (granularity clock cycles)
sample_timer 94 [1:0] 0x00 L ength of pixel_sample (granularity clock cycles)
vmem_timer 95 [7:0] 0x10 Length of pixel_vmem (granula rity clock cycles)
vmem_timer 96 [1:0] 0x01 Length of pixel_vmem (granula rity clock cycles)
delayed_rdt_timer 97 [7:0] 0 Readout delay for testing purposes (granularity
selectable)
delayed_rdt_timer 98 [7:0] 0 Readout delay for testing purposes (granularity
selectable
Fix29 99 [0] 0 Re s erved, fixed value
Fix30 100 [0] 0 Reserved, fixed value
Fix31 101 [0] 0 Reserved, fixed value
Fix32 102 [0] 0 Reserved, fixed value
Fix33 103 [0] 0 Reserved, fixed value
Fix34 104 [0] 0 Reserved, fixed value , write 0x4 to it
Table 13. Internal Registers (continued)
Block Register Name Address [6..0] Field Reset Value Description
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Document Number: 001-24599 Rev. *C Page 16 of 41
Datachannels. DatachannelX_1 and DatachannelX_2 (with
X=0 to 12) are registers that allow you to enable or disable the
FPN correction (DatachannelX_1[1]), and generate a test
pattern if necessary (datachannelX_1[5:4] and
datachannelX_2[7:0]).
Sequencer Block
The sequencer block group registers allow enabling or disabling
image sensor features that are driven by the onboard sequencer.
This block consists of the following registers:
Seqmode1. The seqmode1 registers have the following
subregisters:
Seqmode1[0]: Enables image capture, must be '1' during image
acquisition.
Seqmode1[1]: Thi s subr egister has two modes:
'1': In this default mode the integration timing is generated
on-chip.
'0': In this slave mode, the integration timing must be generated
through the int_time1, int_time2, and int_time 3 pins.
Seqmode1[2]: This bit enables pipelined (0) or triggered (1)
mode.
Seqmode1[3]: En able (1) or disable (0) subsampling.
Seqmode1[4]: This bit sets the type of subsampling scheme
used when subsampling is enabled .
'1': Color (1:1:0:0:1:1:0:0:1…)
'0': Black and White (1:0:1:0:1)
Seqmode1[5]: This bit enables or disables the dual slope
integration.
Seqmode1[6]: This bit enables or disables the triple slope
integration.
Seqmode2. The seqmode2 register consists of only two
subregisters:
Seqmode2[4:0]: Default value after startup is '10000', but this
must be overwritten with the new value '10001' immediately after
startup.
Seqmode3[6:5]: These two bits set the number of active
windows:
'00': 1 window
'01': 2 windows
'10': 3 windows
'11': 4 windows (max)
Seqmode3. The seqmode3 register consists of the following
subregisters:
Seqmode3[0]: This bit enables or disables the CRC10
generation on the data and sync channels
Seqmode3[1]: Enables or disables black level calibration
Seqmode3[2]: Enables or disables column FPN correction
Seqmode3[5:3]: Enables or disables, and sets the number of
frames grabbed in nondestructive readout mo de.
'000': Invalid
'001': Default, 1 reset, 1 sample
'010': 1reset, 2 samples
'011 ': 1 reset, 3 samples
Seqmode3[6]: Controls the granularity of the timer settings (only
for those that have 'granularity selectable' in the description). As
a result, all timer settings are set either in number of applied clock
cycles, or in the number of 'readout lines'.
'0': expressed in number of lines
'1': expressed in clock cycles (multiplied by 2**se qmode4 [3:0])
Seqmode3[7]: Allows syncing of events that happen outside of
ROT to be delayed to the next ROT to avoid image artifacts.
Seqmode4. This register consists of four subregisters:
Seqmode4[3:0]: Multiplier factor (2**seqmode4[3:0]) for the
timers when working in clock cycle mode.
Seqmode4[5:4]: Selects the source signals to be put on the
digital test pins (monitor1, monitor2, and monitor3 pins)
"00": integration time settings
"01": EOS signals
"10": frame sync signals
"11": functional test mode
Seqmode4[6]: Enables (1) and disables (0) reverse X read out.
Seqmode4[7]: Enables (1) and disables (0) reverse Y read out.
Y1_start (60 and 61, 10 bit). These registers set the Y start
address for window 1 (default window).
X1_start (61, 6bit). This register sets the X start address for
window 1 (default window).
Y1_end (62 and 63, 10 bit). These registers set the Y end
address for window 1 (default window).
X1_kernels (63, 6 bit). This register sets the number of kernels
or X width to be read out for window 1 (default window).
Y2_start (64 and 65, 10 bit). These registers set the Y start
address for window 2 (if enabled).
X2_start (65, 6bit). This register sets the X start address for
window 2 (if enabled).
Y2_end (66 and 67, 10 bit). These registers set the Y end
address for window 2 (if enabled).
X2_kernels (67, 6 bit). This register sets the number of kernels
or X width to be read out for window 2 (if enabled).
Y3_start (68 and 69, 10 bit). These registers set the Y start
address for window 3 (if enabled).
X3_start (69, 6bit). This register sets the X start address for
window 3 (if enabled).
Y3_end (70 and 71, 10 bit). These registers set the Y end
address for window 3 (if enabled).
X3_kernels (71, 6 bit). This register sets the number of kernels
or X width to be read out for window 3 (if enabled).
Y4_start (72 and 73, 10 bit). These registers set the Y start
address for window 4 (if enabled).
X4_start (73, 6bit). This register sets the X start address for
window 4 (if enabled).
Y4_end (74 and 75, 10 bit). These registers set the Y end
address for window 4 (if enabled).
X4_kernels (75, 6 bit). This register sets the number of kernels
or X width to be read out for window 4 (if enabled).
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Document Number: 001-24599 Rev. *C Page 17 of 41
Res_length (76 and 77). This register sets the length of the
internal pixel array reset (how long are all pixel reset
simultaneously). This value is expressed in 'number of line s' or
in clock cycles (depends on seqmode3[6]).
Res_dsts_length. This register sets the length of the internal
dual and triple slope reset pulses when enabled. This value is
expressed in 'number of lines' or in clock cycles (depends on
seqmode3[6]).
Tint_timer (79 and 80). This register sets the length of the
integration time. This value is expressed in 'number of lines' or
in clock cycles (depends on seqmode3[6]).
Tint_ds_timer (81 and 82). This register sets the length of the
dual slope integration time. Th is value is expressed in 'number
of lines' or in clock cycles (depends on seqmode3[6]).
Tint_ts_timer (83 and 84). This register sets the length of the
triple slope integration time . This value is expressed in 'number
of lines' or in clock cycles (depends on seqmode3[6]).
Data Interface (SPI)
The serial 4-wire interface (or Serial to Parallel Interface) uses a
serial input or output to shift the data in or out the register buffer .
The chip's configuration registers are accessed from the outside
world through the SPI protocol. A 4-wire bus runs ove r the chip
and connects the SPI I/Os with the internal register blocks.
The interface consists of:
■
cs_n: chip select, when LOW the chip is selected
■
clk: the spi clock
■
in: Master out, Slave in, the se rial input of the register
■
out: Master in, Slave out, the serial output of the register
SPI Protocol
The informati on on the data 'in' line is:
■
A command bit C, indicating a write ('1') or a read ('0') access
■
7-bit address
■
8-bit data word (in case of a write access)
The data 'out' line is generally in High Z mode, except when a
read request is performed.
Data is always written on the bus on the falling edge of the clock,
and sampled on the rising edge, as seen in Figure 9 and
Figure 10. This is valid for both the 'in' and 'out' bus. The system
clock must be active to keep the SPI uploads stored on the chip.
The SPI clock speed must be slower by a factor of 30 when
compared to the system clock (315 MHz nominal speed).
Figure 9. Write Access (C='1')
The 'out' line is held to High Z. The data for the address A is transferred from the shift register to the active register bank (that is,
sampled) on a rising edge of cs_n. Only the register block with address A can write its data on the 'out' bus. The data on 'in' is ignored.
Figure 10. Read Access (C='0')
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Image Sensor Timing and Readout
The timing of the sensor consists of two parts. The first part is
related to the exposure time and the control of the pixel. The
second part is related to the read out of the image sensor.
Integration and readout are in parallel or triggered. In the first
case, the integration time of frame I is ongoing during the readout
of frame I-1. Figure 11 shows this parallel timing structure.
The readout of every frame starts with a FOT, during which the
analog value on the pixel diode is transferred to the pixel memory
element. After this FOT, the sensor is read out line by line. The
read out of every line starts with a ROT, during which the pixel
value is put on the column lines. Then the pixels are selected in
groups of 24 (12 on rising edge, and 12 on the falling edge of the
internal clock). So in total, 54 kernels of 24 pixels are read out
every line. The internal timing is generated by the sequencer.
The sequencer can operate in two modes: master mode and
slave mode. In master mode, all interna l timing is controlled by
the sequencer, based on the SPI settings. In slave mode, the
integration timing is directly controlled by over three pins, and the
readout timing is still controlled by the sequencer. The
seqmode1[1] register of the SPI selects between the master and
slave modes.
Figure 11. Global Readout Timing (Parallel)
Pipelined Shutter
Integration and readout occur in parallel and are continuous. You only need to start and stop the batch of i ma ge captures.
Integration of frame N is always ongoing during readout of frame N-1. The readout of every frame starts with a FOT, during which the
analog value on the pixel diode is transferred to the pixel memory element. After thi s FOT, th e sensor is read out line by line . The
readout of every line starts with a ROT, during which the pixel value is put on the column lines. Then the pixels are muxed in the correct
ADCs, processed, and then sent to the LVDS output block.
Figure 12. Integration and Readout for Pipelined Shutter
You have two options in the pipelined shutter mode. The first option is to program the reset and integration through the configuration
interface and let the sequencer handle integration time automatically . This mode is called master mode. The second option is to drive
the integration time through an exte rnal pin. This mode is called slave mode.
Readout Lines
Integration frame I+1 Integration frame I+2
Readout frame I Readout frame I+1
FOT L1 L2 L1024
...
ROT K1 K2 K54
...
Readout Pixels
Reset N Exposure Time N Reset
N+1 Exposure Time
Readout N-1 Readout N
FOT FOT
ROT
Line Readout
Int. Time
Handling
Readout
Handling
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Programming the Exposure Time
In master mode, the exposure time is configured in two distinct methods (controlled by register seqmode3[6]):
■
#lines: Obvious, changing signals that control integration time. They are always changed during ROT to avoid any image artefacts.
■
#clock cycles: Must be multiplied by (2**seqmode4[3:0]). When the counter expires, changes are put into effect immediately. Asserting
the configuration signal (seqmode 3[7]) forces delaying signal updates until the next ROT.
Table 14 lists the user programmable timer settings and how they are interpreted by the hardware.
Note that the seqmode3[7] can also be used to sync the user signals in slave mode. The behavior is exactly the same.
Master Mode
In master mode the reset and exposure time is written in registers.
Figure 13. Integration and Image Readout in Master Mode
Ensure that the added value of the regist ers res_l ength and tin t_timer always exceeds the numbe r of lin es that are re ad out. T his i s
because the sequencer sa mples a new ima ge after integration i s co mplete, without checking if image reado ut is finished. Enlargi ng
res_length to accommodate for this has no im pact on image capture.
Table 14. User Programmable Timer Settings
Setting Granularity
reg_res_length Lines/cycles
reg_tint_timer Lines/cycles
reg_tint_ds_timer Lines/cycles
reg_tint_ts_timer Lines/cycles
reg_rot_timer clock cycles
reg_fot_timer clock cycles
reg_sel_pre_timer clock cycles
reg_precharge_timer clock cycles
reg_sample_timer clock cycles
reg_vmem_timer clock cycles
reg_delayed_rdt_timer Lines/cycles
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Slave Mode
In slave mode, the register values of res_length and tint_timer are ignored. The integration time is controlled by the int_time pin. The
relationship between the input pin and the integration ti me is shown in Figure 14. Whe n the input pin in t_time is asserte d, the pixel
array goes out of reset and exposure can begin. When int_time goes low again and the desired exposure time is reached, the image
is sampled and read out can begin.
Figure 14. Integration and Image Reado ut in Sla ve Mod e
Changing a pixel's reset level during line readout might result in image artefacts during a small transient period. As a result, it is advised
to only change the value of int_time during ROT.
Triggered Shutte r
The two main differences in the pipelined shutter mode are:
■
One single image is read upon every user action.
■
Integration (and read out) is under control of the user through pin int_time.
This means that for every frame, you nee d to manually intervene. The pixel array is kept in re set state until you assert the int_time
input. Similar to the pipelined shutter mode, there is a master mode in which the sequencer can control the integration time, or a slave
mode in which you can define the integration time.
Figure 15. Integration and Readout for Triggered Shutter
The possible applica ti ons for this triggered shutter mode are:
■
Synchronize extern al flash with exposure
■
Apply extremely long integration times (only in slave mode)
Reset Exposure Time N Reset Exposure Time N
Int. Time
Handling
Readout
Handling Readout N
FOT
ROT
Line
Readout
int_time1
Read
out
N+1
N+1
FOT
Reset
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Master Mode
In this mode, a rising edge on int_time1 pin is used to trigger the
start of integration and read out. The tint_timer defines the
integration time independent of the assertion of the input pin
int_time1. After the integration time counter runs out, the FOT
automatically starts and the image readout is done. During
readout, the image array is kept in reset. A request for a new
frame is started again when a new rising edge on int_time is
detected. The time of the falling edge is not important in this
mode.
Slave Mode
Integration time control is identical to the pipelined shutter slave
mode. The int_time1 pin controls the start of integration. When
int_time is deasserted, the FOT starts (analog value on the pixel
diode is transferred to the pixel memory element). Only at that
time, image read out can start (similar to the pipelined read out).
During read out, the image array is kept in reset. A request for a
new frame is started when int_time goes high again.
Windowing
A fully configurable window can be sele cted for readout.
Figure 16. Window Selected for Readout
The parameters to configure this window are:
x_start. The sensor reads out 24 pixels in one single clock cycle.
The granularity of configuring the X start position is also 24.
Every value written to the windowX_2 register must be multiplied
by 24 to find the corresponding column in the pixel array.
x_kernels. The number of columns that is read out
(x_kernels*24 in full frame mode) in subsampling mode
x_kernels*48 represents the number of columns over which
subsampling is done. The x_kernels value must be written to the
windowX_4 register.
y_start. The starting line of the readout window , granularity of 1.
Note that in subsa mple mode, the correct y_start position must
be uploaded (exact value depends on color or B/W subsampling
mode). This value must be written to the windowX_1 and
windowx_2 register.
y_end. The end line of the read out window, granularity of 1. In
all cases (even in reverse scan), y_end are larger th an y_start.
Note that in subsample mode, the correct y_end position must
be uploaded (exact value depends on color or B/W subsampling
mode). This value must be written to the windowX_3 and
windowX_4 register.
In case of windowing, the effective readout time is smaller than
in full frame mode, becau se only the relevant part of the image
array is accessed. As a result, it is possible to achieve higher
frame rates.
1024
p
ixels
1280
p
ixels
xstar
t
xkernel
y_
en
d
y
star
t
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Reverse Scan
Reverse scanning is supported in the X and Y direction. Line 0 (first line on the output) is the top line in normal mode and the bottom
line in reverse scanning, as sh own in Figure 17. As a result, the line numbers always incre ment. When reverse scanning in X, the
operation is analogous. To enable reverse readout in X and Y, set the seqmode4[6:7] bits. In addition, the Y_start and X_start
addresses must be changed to the new starting address.
Figure 17. Normal and Revers e Scanning in Y
Multiple Windows
The sequencer supports the readout of four different windows, randomly positioned over the pixel array. The images are read out
sequentially. That is, window 1 is read out before window 2, even if both windo ws show some overlap. Next, windows 3 and 4 are
read out. You can configure the number of windows used in the application (one to four). Figure 18 shows how to configure two
windows spread over the image array.
Figure 18. Multiple Windows Read from the Same Pixel Array
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Figure 19 shows the sequence of integration and read out for multiple windows. The handling of integration time is identical to the
single window mode (except that in this case, the maximum integration time is equal to the sum of the y_widths of the two windows).
Read out starts with a FOT that is similar to single window mode. After the FOT, all lines of window 1 are read, followed by the lines
of window 2.
Figure 19. Exposu re and Read Out of Multiple Windows
If the X size of the windows are not identical, the integration time
in function of the number of lines read presents multiple slopes
(proportional to the X size of these windows). Because this can
cause confusion when programming the integration time, it is
easier to configure all timer registers using the clock cycle
configuration instead of the 'li ne' configuration.
Multiple Slopes
Dynamic range can be extended by the multiple slope
capabilities of the sensor. The four colored lines in Figure 20
represent analog signals of th e photo dio de of four pixels, which
decrease as a result of exposure. The slope is determined by the
amount of light at each pixel (the more light, the steeper the
slope). When the pixels reach the saturation level, the analog
does not change despite fu rther exposure. Without the mul tiple
slope capabilities, the pixels p3 and p4 are saturated before the
end of the exposure time, and no signal is received. However,
when using multiple slopes, the analog signal is reset to a
second or third
reset level (lower than the original) before the
integration time end s. The analog signal starts decreasing with
the same slope as before, and pixels that were saturated before
could be nonsaturated at read out time. For pixels that never
reach any of the reset levels (for example, p1 and p2) there is no
difference between single and multiple slope operation.
By choosing the time stamps of the double and triple slope resets
(typical at 90% and 9 9% of the integration, configurable by the
user), it is possible to have a nonsaturate d pixel value even for
pixels that receive a huge amount of light.
Figure 20. Dynamic Range Extended by Multiple Slop e Capability
Reset N
Exposure Time N Reset
N+1 Exposure Ti me
Int. Time
Handling
Readout
Handling
Readout N
FOT
FOT
ROT
Line Readout Window 1
Line Readout Window 2
Readout N
Window 2
Readout N-1
Window 1
Readout
N-1
Window
2
t
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The reset levels are configured through external (power) pins. In master mode, the time stamps of the double and triple slope resets
are configured in a method similar to configuring the exposure time. The time stamp s are enabled through the registers seqmode1[5]
and seqmode1[6], and their values are express ed in line or clock cycles in the registers reg_tint_ds_timer and reg_tint_ts_timer.
Figure 21. Triple Slope Timing in Master Mode
In slave mode, the values of res_length, tint_ timer, tint_DS_timer, a nd tint_TS_timer in the configuration registers are ignored. You
have full control through the pins int_time, int_time_ds, and int_time_ts. You must configure the multiple slope parameters for the
application and interpret the pixel data accordingly.
Figure 22. Triple Slope Timing in Slave Mode
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Column FPN Correction
The column FPN of the sensor is improved by the offset
correction of the columns. At the start of every frame, before read
out of the actual lines is done, a fixed voltage is applied at the
columns and these values are read out like a real data line. Inside
the data block, the 'pixel' data for that line is stored in an on-chip
FPN memory . When the correction is enabled, the corresponding
FPN value is subtracted from the incoming pixel data.
This FPN correction must be enabled for every output separately .
The registers used to configure the correction are:
■
datachannelX_1 with X from 0 to 11. The field [1] of these
registers enables the offset corrections of the specific output
channel.
Note Do not change the settings of datachannel12_1. This
channel contains synchronization data, not pixel data. If fpn
correction is enabled on this channel, the synchronization data
becomes corrupt.
■
seqmode3. The field[2] must be '1'. It enables the generation
of the line of reference voltages at the columns.
Figure 23 and Figure 24 show the effect of enabling the column
FPN correction. These images are magnified up to five times.
Figure 23. Dark Image Without FPN Correction (5x Amplified)
Figure 24. Dark Image With FPN Correction Enable d (5x Amplified)
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Image Format and Read Out Protocol
The active area read out by the sequencer in full frame mode is shown in Figure 25. Before the actual pixels are read out, one dummy
line is read to enable column FPN calibration. A reference voltage is applied to the columns and the entire line is read as if real pixel
values are placed on the columns.
Pixels are always read in multiples of 24 (one value to every channel in the AFE). The last time slot contains not only valid pixels, but
also two dummy columns, six grey columns, and eight black columns.
Figure 25. Sensor Read O ut Fo rmat
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Document Number: 001-24599 Rev. *C Page 27 of 41
The following sections discuss the appearance of the output (data and synchronization codes) in several relevant configurations.
Twelve output channels are connected to the 24 ADCs and handle the data. One additional channel contains all the synchronization
codes for the receiver. This indicate s, for example, th e start of a fra me, the end of a frame, w hether the data channel s contain data,
CRC, a training pattern, and so on. The sequencer provides the synchronization channel with the correct synchronization or protocol
signals, as shown in Figure 26. The synchronization codes are listed in Table 15. Note that a FS also serves as LS, and vice versa.
Figure 26. Data and Sync Channel Overv iew
Table 15. Synchronization Codes
Sync code Abbreviation 10-Bit Code
Frame Start FS 0x059
Line Start LS 0x056
Frame End FE 0x05A
Line End LE 0x055
Grey/Black Cols GBC 0x0A9
CRC CRC 0x0A6
FPN stored values FPN 0x13C
Normal Data D 0x193
Training Pattern T T
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Document Number: 001-24599 Rev. *C Page 28 of 41
Full Frame Mode
In this operation mode, the entire sensor shown in Figure 25 on page 26 is read out. Figure 27 shows the internal state of the
sequencer, and the behavior of the data and sync channels (overview and de tail of one line).
Figure 27. Full Frame Mode Read Out
Data Channel
Sync Channel
Data channel
Sync Channel
Sequencer
internal stat e
line 0
line 1
line
1022
line
1023
black
timeslot timeslot
timeslot
timeslot
53
timeslot
54
CRC
timeslot
T
T
FS
D
D
D
D
D
D
D
L
E
GB
C
CR
C
T
T
FOT ROT
ROT ROT
ROT
132
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Document Number: 001-24599 Rev. *C Page 29 of 41
This table provides a detailed overview of remapping one full row read out.
Table 16. Remapping Scheme for One Row
timeslot ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 ch9 ch10 ch11
1a 0246810121416182022
1b 1357911131517192123
2a 47 45 43 41 39 37 35 33 31 29 27 25
2b 46 44 42 40 38 36 34 32 30 28 26 24
3a 48 50 52 54 56 58 60 62 64 66 68 70
3b 49 51 53 55 57 59 61 63 65 67 69 71
4a 95 93 91 89 87 85 83 81 79 77 75 73
4b 94 92 90 88 86 84 82 80 78 76 74 72
5a 96 98 100 102 104 106 108 110 112 114 116 118
5b 97 99 101 103 105 107 109 111 113 115 117 119
6a 143 141 139 137 135 133 131 129 127 125 123 121
6b 142 140 138 136 134 132 130 128 126 124 122 120
7a 144 146 148 150 152 154 156 158 160 162 164 166
7b 145 147 149 151 153 155 157 159 161 163 165 167
8a 191 189 187 185 183 181 179 177 175 173 171 169
8b 190 188 186 184 182 180 178 176 174 172 170 168
9a 192 194 196 198 200 202 204 206 208 210 212 214
9b 193 195 197 199 201 203 205 207 209 211 213 215
10a 239 237 235 233 231 229 227 225 223 221 219 217
10b 238 236 234 232 230 228 226 224 222 220 218 216
11a 240 242 244 246 248 250 252 254 256 258 260 262
11b 241 243 245 247 249 251 253 255 257 259 261 263
12a 287 285 283 281 279 277 275 273 271 269 267 265
12b 286 284 282 280 278 276 274 272 270 268 266 264
... ... ... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ... ... ... ... ...
53a 1248 1250 1252 1254 1256 1258 1260 1262 1264 1266 1268 1270
53b 1249 1251 1253 1255 1257 1259 1261 1263 1265 1267 1269 1271
54a 1295 1293 1291 1289 1287 1285 1283 1281 1279 1277 1275 1273
54b 1294 1292 1290 1288 1286 1284 1282 1280 1278 1276 1274 1272
CRC
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Document Number: 001-24599 Rev. *C Page 30 of 41
Single Window Mode Containing Timeslot 54
In this operation mode, only part of the sensor is read out, as shown by the shaded area in Figure 28. A clear distinction is made with
the single window mode that does not contain the timeslot 54, because the outpu t synchronization protocol is slightly different.
Figure 28. Single Window Containing Timeslot 54
Figure 29 shows the internal state of the sequencer , and the behavior of the data and sync channels (overview and detail of one line)
for this window mode.
Figure 29. Waveform for Single Window Containing Timeslot 54
Data Channel
Sync Channel
Sequencer int er nal st ate
line Ys
Line
Ys+1
line Ye
black
timeslot
X timeslot
X+1 53 54 CRC
T L
S D
F
E GB
C CR
C
FOT
ROT
ROT
ROT
Data Channel
Sync Channel
timeslottimeslot timeslot
T
T
T
DD
DD
ROT
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Document Number: 001-24599 Rev. *C Page 31 of 41
Single Window Mode Not Containing Timeslot 54
In this operation mode, only part of the sensor is read out, as shown in Figure 30. Although the window is defined as not containing
any data from timeslot 54, it is read out to provide information on grey and black columns to the user. This results in some minor
differences between the waveforms from Figure 29 on page 30 and Figure 31.
Figure 30. Single Window Not Containing Timeslot 54
Figure 31 shows the internal state of the sequencer , and the behavior of the data and sync channels (overview and detail of one line)
for this window mode.
Figure 31. Waveform for Single Window NOT Containing Timeslot 54
Note that the dummy black line is read co mpletely.
Reading out multiple windows does not differ from combining the windowed modes in sections Single Window Mode Containing
T imeslot 54 on page 30 and Single Window Mode Not Containing T imeslot 54. The dummy black line again spans the entire width of
the sensor and is processed only once, before all configured windows are read. The dummy black line is independent of the window
sizes.
Data Chan nel
Sync Channel
Sequencer
internal state
line Ys
line
Ys+1 line Ye
black
timeslot
Xstart timeslot timeslot
Xend timeslot
54 CRC
timeslot
T
T L
S D D D D L
E T GB
C CR
C
T
T
FOT
ROT
ROT ROT
ROT
timeslot
Xend-1
D D
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Document Number: 001-24599 Rev. *C Page 32 of 41
Pin List
Table 17. Pin Placement Layout (Top View )
1 2 3 4 5 6 7 8 9 10 11 12131415161718192021222324
A 134 130 127 124 121 118 115 112 109 106 103 100 99 96 93 90 87 84 81 78 75 72 69 65
B * 131 128 125 122 119 116 113 110 107 104 101 98 95 92 89 86 83 80 77 74 71 68 *
C 133 132 129 126 123 120 117 114 111 108 105 102 97 94 91 88 85 82 79 76 73 70 67 66
D
E
F
G
H
J
K TOP VIEW
L
M
N
P
Q
R
S
T 135 139 140 137 145 * 5 7 * 17 19 * * 31 29 * 43 41 * 54 62 60 59 64
U 136 144 141 138 146 * 8 6 * 20 18 * * 30 32 * 42 44 * 53 61 55 58 63
V 149 147 142 * 1 3 9 11 13 15 21 23 25 27 33 35 37 39 45 47 * 52 57 50
W150148143 * 2 4 10 12 14 16 22 242628343638404648 * 515649
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Document Number: 001-24599 Rev. *C Page 33 of 41
Table 18. Pin List
nr Pin Name Type Direction Description Position
1 clkoutp LVDS O p clk output chan nel V5
2 clkoutn LVDS O n clk output chan nel W5
3 chp[0] LVDS O p ou tput channel [0] V6
4 chn[0] LVDS O n ou tput channel [0] W6
5 gndlvds Supply I/O LVDS ground T7
6 gndadc Supply I/O ADC ground U8
7 vddadc Supply I/O ADC power T8
8 vddlvds Supply I/O LVDS power U7
9 chp[1] LVDS O p ou tput channel [1] V7
10 chn[1] LVDS O n output channel [1] W7
11 chp[2] LVDS O p output channel [2] V8
12 chn[2] LVDS O n output channel [2] W8
13 chp[3] LVDS O p output channel [3] V9
14 chn[3] LVDS O n output channel [3] W9
15 chp[4] LVDS O p output channel [4] V10
16 chn[4] LVDS O n output channel [4] W10
17 gndlvds Supply I/O LVDS ground T10
18 gndadc Supply I/O ADC ground U11
19 vddadc Supply I/O ADC power T11
20 vddlvds Supply I/O LVDS power U10
21 chp[5] LVDS O p output channel [5] V11
22 chn[5] LVDS O n output channel [5] W11
23 chp[6] LVDS O p output channel [6] V12
24 chn[6] LVDS O n output channel [6] W12
25 chp[7] LVDS O p output channel [7] V13
26 chn[7] LVDS O n output channel [7] W13
27 chp[8] LVDS O p output channel [8] V14
28 chn[8] LVDS O n output channel [8] W14
29 gndlvds Supply I/O LVDS ground T15
30 gndadc Supply I/O ADC ground U14
31 vddadc Supply I/O ADC power T14
32 vddlvds Supply I/O LVDS power U15
33 chp[9] LVDS O p output channel [9] V15
34 chn[9] LVDS O n output channel [9] W15
35 chp[10] LVDS O p output channel [10] V16
36 chn[10] LVDS O n output channel [10] W16
37 chp[11] LVDS O p output channel [11] V17
38 chn[11] LVDS O n output channel [11] W17
39 n/a not assigned V18
40 n/a not assigned W18
41 gndlvds Supply I/O LVDS ground T18
42 gndadc Supply I/O ADC ground U17
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Document Number: 001-24599 Rev. *C Page 34 of 41
43 vddadc Supply I/O ADC power T17
44 vddlvds Supply I/O LVDS power U18
45 clkinp LVDS I LVDS input clock 315 MHz p-node V19
46 clkinn LVDS I LVDS input clock 315 MHz n-node W19
47 syncp LVDS O LVDS sync and outp ut V20
48 syncn LVDS O LVDS sync and output W20
49 gnddig Supply I/O digital ground W24
50 vdddig Supply I/O digital power supply V24
51 cap_vrefm Analog O lower limit ADC range decoupling W22
52 cap_vrefp Analog O higher limit ADC range decoupling V22
53 gndadc Supply I/O ADC ground U20
54 vddadc Supply I/O ADC power supply T20
55 gnddig Supply I/O digital ground U22
56 gndbuf Supply I/O column buffers ground W23
57 vddbuf Sup ply I/O column buffers supply V23
58 gndana Supply I/O column buffers ground U23
59 vddana Supply I/O column buffers supply T23
60 vpix Supply I/O pi xel core supply T22
61 gndpix Supply I/O pixel core ground U21
62 vsamp Supply I/O image core select and sample supply T21
63 gndadc Supply I/O ADC ground U24
64 vdddig Supply I/O digital power supply T24
65 nbias_colload Analog O c olumn bias decouple A24
66 test_ena CMOS I scan pin for sequ encer C24
67 int_time1 CMOS I integration pin first slope C23
68 int_time2 CMOS I integration pin dual slope B23
69 int_time3 CMOS I integration pin triple slope A23
70 monitor1 CMOS O output pin for inte gration timing, high during integration C22
71 monitor2 CMOS O output pin for dual slope integratio n timing, high during
integration B22
72 monitor3 CMOS O output pin for triple slope in tegration timing, high during
integration A22
73 cap_vrefadc Analog O ADC black reference decoupling C21
74 vpix Supply I/O pixel core supply B21
75 cap_vrefcm Analog O ADC common mode decoupling A21
76 reset_n CMOS I/O chip reset (active low) C20
77 scan_en CMOS I DFT scan enable B20
78 scan_clk CMOS I DFT clock A20
79 scan_clk_en CMOS I DFT clock enable C19
80 gndpix Supply I/O pixel core ground B19
81 gnddig S upply I/O digital ground A19
82 vdddig Supply I/O digital power supply C18
83 vpix Supply I/O pixel core supply B18
Table 18. Pin List (continued)
nr Pin Name Type Direction Description Position
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Document Number: 001-24599 Rev. *C Page 35 of 41
84 pixdiode Analog O pixel diode current pin A18
85 gndpix Supply I/O pixel core ground C17
86 vsamp Supply I/O image core select and sample supply B17
87 vresetab Supply I/O anti blooming lower reset level A17
88 vprech Supply I/O pixel precharge level/decoupling pin C16
89 vmemh Supply I/O pixel memory reference high B16
90 vmeml Supply I/O pixel memory reference low A16
91 vreset Supply I/O pixel reset level C15
92 vresetds Supply I/O pixel dual slope reset level/decoupling pin B15
93 vresetts Supply I/O pixel triple slope reset level/decoupling pin A15
94 vresetab Supply I/O anti blooming lower reset level C14
95 gndpix Supply I/O pixel core ground B14
96 vresetts Supply I/O pixel triple slope reset level/decoupling pin A14
97 vresetds Supply I/O pixel dual slope reset level/decoupling pin C13
98 vreset Supply I/O pixel reset level B13
99 vsamp Supply I/O image core select and sample supply A13
100 vmeml Supply I/O pixel memory reference low A12
101 vmemh Supply I/O pixel memory reference high B12
102 vprech Supply I/O pixel precharge level/decoupling pin C 12
103 n/a not assigned A11
104 gndpix Supply I/O pixel core ground B11
105 vresetab Supply I/O an ti blooming lower reset level C11
106 vresetts Supply I/O pixel triple slope reset level/decoupling pin A10
107 vresetds Supply I/O pixel dual slope reset level/decoupling pin B10
108 vreset Supply I/O pixel reset level C10
109 vmeml Supply I/O pixel memory reference low A9
110 vme mh Supply I/O pixel memory reference high B9
111 vprech Supply I/O pixel precha rge level/decoupling pin C9
112 vre setab Supply I/O anti blooming lower reset level A8
113 vsamp Supply I/O image core select and sample supply B8
114 gndpix Supply I/O pixel core ground C8
115 ibiaspre Analog I external curre nt bias for vprech (not connected by default) A7
116 vpix S upply I/O pixel core supply B7
117 vdddig Supply I/O digital power supply C7
118 gnddig Supply I/O digital ground A6
119 gndpix Supply I/O pixel core ground B6
120 n/a not assigned C6
121 n/a not assigned A5
122 n/a not assigned B5
123 n/a not assigned C5
124 cap_vrefcm Analog O ADC common mode decoupling A4
125 vpix Supply I/O pixel core suppl y B4
126 cap_vrefadc Analog O ADC black referenc e decoupling C4
Table 18. Pin List (continued)
nr Pin Name Type Direction Description Position
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Document Number: 001-24599 Rev. *C Page 36 of 41
127 spics CMOS I SPI chip select A3
128 spiclk CMOS I SPI clock B3
129 spiin CMOS I SPI serial input C3
130 spiout CMOS O SPI serial output A2
131 mbsbus[0] Analog I/O first mixed boundary scan bus B2
132 mbsbus[1] Analog I/O second mi xed boundary scan bus C2
133 refbg Analog I/O external bias resistor C1
134 cm dmbs Analog I bias current for mbs buffers A1
135 vdddig Supply I/O digital power supply T1
136 gndadc Supply I/O ADC ground U1
137 vsamp Supply I/O image core select and sample supply T4
138 gndpix Supply I/O pixel core ground U4
139 vpix Supply I/O pixel core suppl y T2
140 vddana Supply I/O analog power supply T3
141 gndana Supply I/O analog ground U3
142 vddbuf Supply I/O column buffers supply V3
143 gndbuf Supply I/O column buffers ground W3
144 gnddig Sup ply I/O digital ground U2
145 vddadc Supply I/O ADC power supply T5
146 gndadc Supply I/O ADC ground U5
147 cap_vrefp Analog I/O higher limit ADC range decoup ling V2
148 cap_vrefm Analog I/O lower limit ADC range decoupling W2
149 vdddig Supply I/O digital power supply V1
150 gnddig Sup ply I/O digital ground W1
Table 18. Pin List (continued)
nr Pin Name Type Direction Description Position
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Document Number: 001-24599 Rev. *C Page 40 of 41
Glass Lid
The LUPA 1300-2 monochrome and color image sensor uses a glass lid without any coatings. Figure 36 shows the transmission
characteristics of th e glass lid.
As seen in Figure 36, no infrared attenuating color filter glass is used. Y ou must provide this filter in the optical path when color devices
are used.
Figure 36. Transmission Charac teristics of the Glass lid
Handling Precautions
For proper handling and storage conditions, refer to the Cypress
application no te AN52561 at www.cypress.com.
Limited Warranty
Cypress Image Sensor Business Unit warrants that the image
sensor products mentioned here, if properly used and serviced,
conform to the seller's published specifications. They are free
from defects in material and workmanship for one (1) year
following the date of shipment.
Application Note References
■
AN54468: Interfacing the LUPA1300-2 with FPGA.
This application note describes the interface between the LUPA
1300-2 and the FPGA, as implemented in the LUPA 1300-2
demonstration kit CYIL2SM1300-EVAL. It also provides an
overview of the architecture of the demonstration kit and the
method used to synchronize chann els.
■
AN54214: High Speed Layout Guidelines for the LUP A 1300-2
Image Sensor
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Document Number: 001-24599 Rev. *C Revised September 18, 2009 Page 41 of 41
All products and company names mentioned in this document may be the trademarks o f t heir respect i ve holders.
CYIL2SM1300AA
© Cypress Semiconductor Corporation, 2007-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circui try oth er than circuit ry e mbod ied in a Cyp ress produc t. Nor do es it conve y or im ply any lic ense under paten t or ot her r ights. Cypr ess pr oducts are not wa rrante d nor in tende d to be us ed
for medical, life support, life saving, critical co ntr ol o r safe ty ap pl i cations, unless pursuant to an exp re ss w ritt en agr e em en t with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to th e user. Th e inclusion of Cypress produc ts in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright law s and inter nation al trea ty provisi ons. Cyp ress he reby gr ant s to license e a per sonal , non- exclus ive, no n-tran sferab le lic ense to cop y, use, mod ify, create d erivati ve works of ,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of lice nsee product to be used on ly in conjunction wit h a Cypress
integrated circui t as specified in the applicab le agreement. Any r eproduction, m odification, transl ation, compilatio n, or represent ation of this S ource Code exce pt as specified above is prohib ited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNE SS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liabil ity ar ising ou t of t he app licati on or us e of an y product or circ uit de scrib ed herei n. Cypr ess does n ot auth orize it s product s for use a s critical componen ts in life-suppo rt systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document History Page
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress offers standard and customized CMOS image sensors for consumer as well as industrial and professional applications.
Consumer applications include solutions for fast growing high speed machine vision, motion monitoring, medical imaging, intelli gent
traffic systems, security, and barcode applications. Cypress's customized CMOS image sensors are characterized by very high pixel
counts, large area, very high frame rates, large dynamic range, and high sensitivity.
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. For more
information on Image sensors, please contact imagesensors@cypress.com.
Document Title: CYIL2SM1300AA LUPA 1300-2: High Speed CMOS Image Sensor
Document Number: 001-24599
Revision ECN Orig. of Change Submission Date Description of Change
** 1438663 FPW 09/04/07 Initial Cypress release.
*A 2649816 NVEA/AESA 03/17/2009 Updated parameters in Table 4 on page 5.
Updated data sheet template.
Added Handling Precautions section.
*B 2745961 NVEA/AESA 07/29/2009 Updated “Features” on page 1, “Description” on page 1, and
“Overview” on page 2
Updated Table on page 1
Updated Table 13 on page 10
Modified “Handling Precautions” on page 40
Added “Application Note References” on page 40
*C 2765859 NVEA/AESA 09/18/2009 Updated Ordering Information table
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