Support  exible display interfacing

with DisplayPort to LVDS connectivity

Key features

Compliant to DP v1.1a and v1.2 standards

Compliant to eDP v1.1 and v1.2 standards

Supports DP Main Link operation with 1 or 2 lanes

@ 1.62 or 2.7 Gbit/s

Supports single- or dual-bus LVDS signaling

Supports LVDS pixel clock frequency up to 112 MHz and

Brightness control without additional components

HVQFN56 package (7 x 7 mm, 0.4 mm pitch)

Key bene ts

Signi cant BoM savings

- EDID ROM emulation

- No external timing reference

- Brightness control support

Non-volatile Flash memory supporting future upgradability

This highly con gurable,  eld-upgradable protocol converter gives computing OEMs and ODMs

an ef cient way to interface their (e)DP-capable CPUs and chipsets to a legacy LVDS display panel.

Flexible con guration options (con guring through I2C bus

or DP AUX channel and hardware pins) support a wide

choice of usage options and panel sizes

Firmware and EDID Upgrade through Flash-over-AUX utility

EDID Data Upgrade throughd Flash-over-DOS mode utility

Applications

interfaces. As a DP-to-LVDS bridge, the PTN3460 supports

DisplayPort and embedded DisplayPort, and is suitable for

notebooks. The PTN3460 processes the incoming DP stream,

performs protocol conversion, and then transmits

the processed data stream in LVDS format. It has two

high-speed ports: a Receive port facing the DP source (the

CPU/GPU chipset), and a Transmit port facing the LVDS

receiver (the LVDS controller).

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information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and

may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof

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Date of release: September 2011

Document order number: 9397 750 17180

Printed in the Netherlands

The device receives the DP stream link at a rate of 1.62 or

2.7 Gbps, and supports one- or two-lane operation. It interacts

with the DP source via DP Auxiliary (AUX) channel transactions

for DP link training and set-up. It supports single- or dual-bus

LVDS signaling with color depths of 18 or 24 bits per pixel, and

at a pixel clock frequency of up to 112 MHz.

EDID ROM behavior and thus avoid specic changes in the

system video BIOS. This also saves on the bill of materials.

Software packages support design-in at the customer factory.

There is a Flash-over-AUX utility for upgrading product

rmware and EDID data, and a Flash-over-DOS mode utility for