AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet
1.0 Key Features
Controller area network (CAN) is a serial communication protocol, which supports distributed real-time control and multiple xing wi t h
high safety level. Typical appl ications of CAN-based networks can be found in automotiv e and industrial environments.
The AMIS-42700 Dual-CAN tr ansceiver is the interfac e between up t o t wo physical b us lines and th e protocol c ontrolle r and will be
used for serial data interchan ge between diff erent electronic units at more than one bus l ine. It can be used for both 12V and 24V
systems.
The circuit consists of following blocks:
• Two differential line transmitters
• Two differential line receiver s
• Interface to the CAN protocol handler
• Interface to expand the number of CAN busses
• Logic block including repeater function and the feedback suppressio n
• Thermal shutdown circuit (TSD)
• Short to battery treatment circuit
Due to the wide common-mode voltage range of the receiver inputs, the AMIS-42700 is able to reach outstanding levels of
electromagnetic susceptibility (EMS). Similarly, extremely low electromagnetic emission (EME) is achieved by the excellent
matching of the output signals.
2.0 Key Features
• Fully compatible with the ISO 11898-2 standard
• Certified “Authentication on CAN Transceiver Conformanc e (d1.1)”
• High speed (up to 1 Mbit/s)
• Ideally suited for 12V and 24V industrial and automotive applications
• Low EME common-mode-choke is no longer required
• Differential receiver with wide common-mode range (+/- 35V) for high EMS
• No disturbance of the bus lin es with an un-powered node
• Transmit data (TxD) domina nt time-out function
• Thermal protection
• Bus pins protected against transients in an automotive environment
• Power down mode in which the transmitter is disabled
• Short circuit proof to supply voltage and ground
• Logic level inputs compatible with 3.3V devices
• ESD protection guaranteed up to ±8KV
3.0 Technical Characteristics
Table 1: Technical Characteristics
Symbol Parameter Conditions Min. Max. Unit
VCANH DC voltage at pin CANH 0 < VCC < 5.25V; no time limit -45 +45 V
VCANL DC voltage at pin CANL 0 < VCC < 5.25V; no time limit -45 +45 V
Vi(dif)(bus_dom) Differential bus output voltage in dominant state 42.5Ω < RLT < 60Ω 1.5 3 V
tpd(rec-dom) Propagation delay TxD to RxD See Figure 7 70 245 ns
t pd(dom-rec) Propagation delay TxD to RxD See Figure 7 100 245 ns
CM-range Input common-mode range for comparator Guaranteed differential receiver threshold and
leakage current -35 +35 V
VCM-peak Common-mode peak See Figure 8 and 9 (note) -500 500 mV
VCM-step Common-mode step See Figure 8 and 9 (note) -150 150 mV
Notes: The parameters VCM-peak and VCM-step guarantee low EME.
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AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet
4.0 Ordering Information
Marketing Name Package Temp. Range
AMIS 42700FHA SOIC-20 300 G -40°C…125°C
5.0 Block Diagram
CANH1
CANL1
AMIS-40700
GND
Rx0
VREF
19
18
Driver
control
2 x timer
clock
COMP
Vcc/2
+
Ri(cm)
Ri(cm)
Timer
VCC
Logic
Unit
8
Driver
control
Thermal
shutdown
COMP
Vcc/2+Ri(cm)
Ri(cm)
Timer
VCC
POR
10 3 47925
615 16 17
PC20050502.1
13
14
12
Feedbeck Surpression
Feedbeck Surpression
Rint
Tx0
TextENB1 ENB2
VCC
CANH2
CANL2
Figure 1: Block Diagram
6.0 Typical Application
6.1 Application Des cription
AMIS-42700 is especiall y designed to provid e the link bet ween a CAN co ntroller (protocol ic) and t wo physical busses. It is able to
operate in three different modes:
• Dual CAN
• A CAN bus extender
• A CAN bus repeater
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AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet
6.2 Application S c he ma tics
AMIS-42700
EN1
EN2
Text
Rx0
Tx0 7
9
2
3
10
Rint
4CANH2
CANL1
GND
Vref
VCC
18
13
12
19
14
8
PC20050511.6
5615 16 17 CANL2
CANH1
CD
RLT
60 Ω
CAN BUS 2
CAN BUS 1
RLT
60 Ω
100 nF
VBAT 5V-reg
Figure 2: Application Diagram CAN-Bus Repeater
AMIS-42700
EN1
EN2
Text
Rx0
Tx0 7
9
2
3
10
Rint
4
VBAT
CANH2
CANL1
GND
VCC Vref
VCC
18
13
12
19
14
8
GND
CAN
con-
troller
PC20050502.3
5V-reg
5615 16 17 CANL2
CANH1
CD
CD
RLT
60 Ω
CAN BUS 2
CAN BUS 1
RLT
60 Ω
100 nF100 nF
µC
Figure 3: Application Diagram Dual-CAN
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AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet
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AMIS-42700
EN1
EN2
Text
Rx0
Tx0 7
9
2
3
10
Rint
4
VBAT
CANH2
CANL1
GND
VCC Vref
VCC
18
13
12
19
14
8
GND
CAN
con-
troller
5V-reg
5615 16 17 CANL2
CANH1
CD
CD
RLT
60 Ω
CAN BUS 2
CAN BUS 1
RLT
60 Ω
100 nF100 nF
µC
PC20050502.9
AMIS-42700
EN1
EN2
Text
Rx0
Tx0 7
9
2
3
10
Rint
4CANH2
CANL1
GND
Vref
VCC
18
13
12
19
14
8
5615 16 17 CANL2
CANH1
CD
RLT
60 Ω
CAN BUS 4
CAN BUS 3
RLT
60 Ω
100 nF
+5
+5
Figure 4: Application Diagram CAN Bus Extender
AMI Semiconductor – Rev. 1.4, May 05 - Preliminary
AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet
6.3 Pin Description
6.3.1 Pinout (top view)
Tx0
GND
GND
14
15
16
17
18
19
201
2
3
4
5
6
7
NC
Rx0
Vref1
Rint
EN1
NC
GND
CANL1
CANH1
VCC
8
9
10
13
12
11
AMIS-42700
PC20050502.2
NC
GND
GND
CANL2
CANH2
Text
EN2
Figure 4: Pin Configuration
6.3.2 Pin Description
Table 2: Pinout
Pin Name Description
1 NC Not connected
2 ENB2 Enable input, bus system 2
3 Text Multi system transmitter input
4 Tx0 Transmitter input
5 GND Ground connection, note 1
6 GND Ground connection, note 1
7 Rx0 Receiver output
8 VREF1 Reference voltage
9 Rint Multi system receiver output
10 ENB1 Enable input, bus system 1
11 NC Not connected
12 VCC Positive supply voltage
13 CANH1 CANH transceiver I/O bus system 1
14 CANL1 CANL transceiver I/O bus system 1
15 GND Ground connection, note 1
16 GND Ground connection, note 1
17 GND Ground connection, note 1
18 CANL2 CANL transceiver I/O bus system 2
19 CANH2 CANH transceiver I/O bus system 2
20 NC Not connected
Notes:
1) In order to ensure the chip performance, these pins need to be connected to GND on the PCB.
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AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet
7.0 Functional Description
7.1 Overall Functional Description
The CAN transceiver is speciall y designed to provide the link between the protocol IC (CAN controller) and two physical bus li nes.
Data interchange between those two bus lines is realized via the interface. Bitwise arbitration is extended on both buses. A fault
like short circuit is limited to that bus line where it occurs. Data interchange from the protocol IC to the other bus system and on this
bus system itself can be continued.
The transceiver can also be used for only one bus system. If the connections for the second bus system are simply left open it
serves as a single transceiver for an electroni c unit. For correct operation it is necess ary to terminate an ope n bus. If not, the open
bus will disturb the other one, e.g. in case of open load.
The bus lines can have two logical states, dominant or recessive. A bus is in the recessive state when the driving sections of all
transceivers connected to t he bus are passiv e. The different ial voltage bet ween the t wo wires is appro ximately zero. If at le ast one
driver is active the bus chan ges into the domina nt state. This state is represented b y a differential voltage greater than a mi nimum
threshold and therefore b y a current flow through th e terminating r esistors of the bus line. The recessive state is over written by the
dominant state.
To provide an independe nt s witch-off of the transceiver units for both bus systems b y a third device (e.g. the µC) en abl es inpu ts for
the corresponding drivin g and receiving sections to be included.
7.2 Transmitter
The transceiver includes t wo transmitters, one for each bus line and a driver control circuit. Each transmitter is implemented as a
push and a pull driver. The drivers will be active if the transmission of a dominant bit is required. During the transmission of a
recessive bit all drivers are passive. The transmitters have a built-in current limiting circuit that protects the driver stages from
damage caused by accidental short circuit to either pos itive supply voltage or to ground. Addi tionally a thermal protecti on circuit is
integrated.
The driver control circuit ensures that the drivers are switched on and off with a controlled slope to limit EME. The driver control
circuit will be controlled itself by the thermal protection circuit, the timer circuit, the ENBx inputs, and the logic unit.
The dominant time out timer circuit prevents the output drivers from driving a permanent dominant state (blocking all network
communication) if pin Tx0 or the bus lines of the other bus are forced permanentl y dominant by a hardware and/or soft ware failure
(see tdom(TxD)).
The enable signal ENBx allows the transmitter to be switched off by a third device (e.g. the µC). In the disabled state (ENBx =
high) the corresponding transmitter behav es as in the recessive state and does not depend on t he input voltage at Tx0 nor on the
state of the other bus system.
7.3 Receiver
Two bus receiving sections sense the states of the bus lines. Each receiver section consists of an input filter and a fast and
accurate comparator. The aim of the input filter is to improve the immunity against high-frequency disturbances and also to
convert the voltage at the bus lines CANH x and CAN L x, which can var y from –12V to +12 V, to voltages i n the range 0 t o 5V, which
can be applied to the compara tors.
The output signal of the comparators is gated by the ENBx signal. In the disabled state (ENBX = high) the output signal of the
comparator will be replaced by a permanently recessive state and does not depend on the bus voltage. In the enabled state the
receiver signal sent to the logi c unit is identical to the comparator output signal.
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AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet
7.4 Feedback Suppression
To provide proper function a feedback su ppression must be incl uded. This circuit replaces the reception of a dominant bit detected
by the receiving section with a recessive bit if the corresponding transmitter is active.
The feedback suppressio n must be activat ed immediatel y after the tr ansmitter is requ ested to drive, i. e. before the receiv er detects
the dominant state at the bus. After deactivating the transmitter, the feedback suppression must stay active long enough to
guarantee that the corresponding receiver has sufficient time to change its state from dominant to recessive.
Including the feedback, suppression is possible because a transmitter becomes active if the other bus system or Tx0 is in the
dominant state, so the reception of a dominant bit is already realized and need not be done additionally by this receiving section.
Without feedback suppression the whole system would stay constantly in the dominant state after the occurrence of one domin ant
bit.
The logic is implem ented in such a way that the suppression bl ocks in the two busses work independently of each o ther, and are
identical so that both busses have the s ame priority. Furthermore the oscillatio n or single pulsing, that co uld occur at the dominant
to recessive edge when the transceiver has received acknowledges from both busses, is avoi ded with this implementation.
If both buses are driven exter nall y and g o fr om dom inant to recess ive with some delay b et ween each other, no spur iou s puls es are
seen at RINT and Rx0. However, it is possible to have the driving section of one bus going active while that bus is still driven
externally. To minimize the chance of this condition, an additional delay of typical 50ns is added that blocks the requirement to
drive the driving section after the bus is forced externally from dominant to recessive.
7.5 Logic Unit and CAN Controller Interface
The central logic unit provides data transfer from/to the digital interface to/from the two busses and from one bus to the other bus.
Digital input stages convert the input voltage at Tx0 and TEXT into a logical value for the logic unit. All digital inputs, including
ENBx, have an internal pull up resistor to ensure a recessive state when the input is not connected or is accidentally interrupted.
Output stages convert the logi cal value prov i ded b y the logi c unit i nto volta ges corr espon ding to the inp ut signal s pecif icatio n of the
CAN controller at Rx0 an d RINT . A dominant state on the bus li ne is repre sented by a low-level at th e digital int erface, a recessive
state is represented by a high-level.
Vref provides an analog voltage of Vcc/2 as a referenc e for CAN controller with analog inputs.
Input and output signals of the logic unit are related in such a way that a dominant state on any bus or Tx0 causes a dominant
state on both buses, RINT and Rx0.
The output signal at Rx0 corresponds to the inputs Tx0 and TEXT, independent of the state of the two enable inputs. This is
realized by an internal logical connection.
The pins TEXT and RINT are used for connecting the internal logics of several ICs to obtain versions with more than two bus
outputs. If a dominant bit is received from at least one of the two bus systems (under the condition of feedback suppression) or
from Tx0, RINT carries the low-level. Other wise RINT is high. A low-level at T EXT activates both transmitters causi ng a dominant
state on both busses and sets Rx0 to the low-level. A high-level at TEXT does not influence the transceiver.
7.6 Power-on-Reset (POR)
While Vcc voltage is below the POR level, the POR circuit makes sure that:
• The counter is kept in the reset mode and stable state without current consumption
• Inputs are disabled (don't care)
• Outputs are high impedant; only Rx0 = high-level
• Analog blocks are in power down
• Oscillator not running and in power down
• CANHx and CANLx are recessive
• VREF output high impedant for POR not released
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AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet
7.7 Time Out Timer
The Tx0 dominant time out timer circuit prevents the output drivers from driving a permanent dominant state (blocking all network
communication) if pin Tx0 or the bus lines of the other bus are forced perm anentl y dominant by a hard ware and/or soft ware failure.
The timer is triggered b y a negative edge of the T IMERIN signal. If the duration of the low-leve l on TIMERIN exceeds the internal
timer value TIMERDEL, the timer output TIMEROUT becomes high, dis abling the transmitter (bus returns into the recessive state).
The timer is reset by a positive edge of the TIMERIN signal.
7.8 Over Temperature Detection
A thermal protection circuit is integrated to prevent the transceiver from damage if the junction temperature exceeds thermal
shutdown level. Because the transmitter dissipates most of the total power, the transmitter will be switched off only to reduce
power dissipation and IC temperatur e. All other IC functions continue to operate.
7.9 Fault Behavior
A fault like a short circuit is limited to that bus line where it occurs, hence data interchange from the protocol IC to the other bus
system is not affected.
When the voltage at the bus lines is going out of the normal operating range (-12V to +12V), the receiver is not allowed to
erroneously detect a dominant state.
7.10 Short Circuits
As specified in the maximum ratings, short circuits of the bus wires CANHx and CANLx to the positive supply voltage Vbat or to
ground must not destroy the transceiver. To provide sufficient safety for automotive applications the voltage range for permanent
short circuits is extended to 50V dc. A short circuit between CANHx and CANLx must not destroy the IC as well.
The dedicated comparator (L2VBAT) on CANL pin detects the short to battery and after debounce time-out switches off the
affected driver only.
The receiver of the affected driver has to oper ate normally.
7.11 Faulty Supply
In case of a faulty supply (missing connection of the electronic unit or the transceiver to ground, missing connection of the
electronic unit to Vbat or missing connection of the tra nsceiver to Vcc) the power sup ply module of the electronic un it will operate
such that the transceiver is not supplied, i.e. the voltage Vcc is below the POR level. In this condition the bus connections of the
transceiver must be in the POR state.
If the ground line of the electronic unit is interrupted, Vbat may be appli ed to the Vcc pin (measured relativ e to the original ground
potential, to which the other units on the bus are connected).
7.12 Reverse Electronic Unit (ECU) Supply
If the connections for groun d and supply volt age of an electr onic unit (ECU) (max. 50V) which provides Vcc for the tra nsceiver are
exchanged, this transceiv er has a ground po tential which may be up to 50V higher th an that of the other transceivers. In this case
no transceiver must be destroyed even if several of them are connected via the bus system.
Any exchange among the six connections CANH1, CANH2, CANL1, CANL2, ground, and supply voltage of the electronic unit at
the connector of the unit must never lead to the destruction of any transceiver of the bus system.
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AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet
8.0 Electrical Characteristics
8.1 Definitions
All voltages are referenced to GND. Positive currents flow into the IC. Sinking current means that the current is flowing into the
pin. Sourcing current means that the current is flowing out of the pin.
8.2 Absolute Maximum Ratings
Stresses above those listed in the fol lowing table ma y cause p ermanent d evice failure. Exposure to absolute maximum ratings for
extended periods ma y affect device reliability.
Table 3: Absolute Maximum Ratings
Symbol Parameter Conditions Min. Max. Unit
VCC Supply voltage -0.3 +7 V
VCANH DC voltage at pin CANH 0 < VCC < 5.25V; no time limit -45 +45 V
VCANL DC voltage at pin CANL 0 < VCC < 5.25V; no time limit -45 +45 V
VTxD DC voltage at pin TxD -0.3 VCC + 0.3 V
VRxD DC voltage at pin RxD -0.3 VCC + 0.3 V
VSDC voltage at pin S -0.3 VCC + 0.3 V
VREF DC voltage at pin VREF -0.3 VCC + 0.3 V
Vtran(CANH) Transient voltage at pin CANH Note 1 -150 +150 V
Vtran(CANL) Transient voltage at pin CANL Note 1 -150 +150 V
Vtran(VSPLIT) Transient voltage at pin Vsplit Note 1 -150 +150 V
Vesd(CANL/CANH) ESD voltage at CANH and CANL pin Note 2
Note 4 -8
-500 +8
+500 kV
V
Vesd ESD voltage at all other pins Note 2
Note 4 -2
-250 +2
+250 kV
V
Latch-up Static latch-up at all pins Note 3 100 mA
Tstg Storage temperature -55 +155 °C
Tamb Ambient temperature -40 +125 °C
Tjunc Maximum junction temperature -40 +150 °C
Notes:
1) Applied transient waveforms in accordance with “ISO 7637 part 3”, test pulses 1, 2, 3a, and 3b (see Figure 4).
2) Standardized human body model (HBM) ESD pulses in accordan ce to MIL883 method 3015. Supply pin 8 is ±2 kV.
3) Static latch-up immunity: static latch-up protection level when tested according to EIA/JESD78.
4) Standardized charged device model ESD pulses when tested according to EOS/ESD DS5.3-1993.
8.3 Thermal Characteristics
Symbol Parameter Conditions Value Unit
Rth(vj-a) Thermal resistance from junction to ambient in SO8 package In free air 145 K/W
Rth(vj-s) Thermal resistance from junction to substrate of bare die In free air 45 K/W
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AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet
8.4 DC Characteristics
VCC = 4.75 to 5.25V; V33 = 2.9 to 3.6V; Tjunc = -40 to +150°C; RLT =60Ω unless specified otherwise.
Table 4: DC Characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
Supply (pin VCC)
ICC Supply current Dominant; VTXD =0V
Recessive; VTXD =VCC 45
4 65
8 mA
mA
Transmitter Data Input (pin TxD)
VIH High-level input voltage Output recessive 2.0 - VCC V
VIL Low-level input voltage Output dominant -0.3 - +0.8 V
IIH High-level input current VTxD =VCC -1 0 +1
µA
IIL Low-level input current VTxD =0V -75 -200 -350 µA
CiInput capacitance Not tested - 5 10 pF
Mode Select (pin S)
VIH High-level input voltage Silent mode 2.0 - VCC V
VIL Low-level input voltage High-speed mode -0.3 - +0.8 V
IIH High-level input current VS =2V 20 30 50
µA
IIL Low-level input current VSTB =0.8V 15 30 45 µA
Receiver Data Output (pin RxD)
VOH High-level output voltage IRXD = - 10mA 0.6 x VCC 0.75 x VCC V
VOL Low-level output voltage IRXD = 6mA 0.25 0.45 V
Ioh High-level output current Vo=0.7 x VCC -5 -10 -15 mA
Iol Low-level output current Vo=0.3 x VCC 5 10 15 mA
Reference Voltage Output (pin VREF)
VREF Reference output voltage -50µA < IVREF < +50µA 0.45 x VCC 0.50 x VCC 0.55 x VCC V
VREF_CM Reference output voltage for full common
mode range -35V <VCANH< +35V;
-35V <VCANL< +35V 0.40 x VCC 0.50 x VCC 0.60 x VCC V
Bus Lines (pins CANH and C ANL)
Vo(reces)(CANH) Recessive bus voltage at pin CANH VTxD =VCC; no load 2.0 2.5 3.0 V
Vo(reces)(CANL) Recessive bus voltage at pin CANL VTxD =VCC; no load 2.0 2.5 3.0 V
Io(reces) (CANH) Recessive output current at pin CANH -35V <VCANH< +35V;
0V <VCC < 5.25V -2.5 - +2.5 mA
Io(reces) (CANL) Recessive output current at pin CANL -35V <VCANL < +35V;
0V <VCC < 5.25V -2.5 - +2.5 mA
Vo(dom) (CANH) Dominant output voltage at pin CANH VTxD = 0V 3.0 3.6 4.25 V
Vo(dom) (CANL) Dominant output voltage at pin CANL VTxD = 0V 0. 5 1.4 1.75 V
VTxD = 0V; dominant;
42.5Ω < RLT < 60Ω 1.5 2.25 3.0 V
Vi(dif) (bus) Differential bus input voltage (VCANH - VCANL) VTxD =VCC; recessive;
no load -120 0 +50 mV
Io(sc) (CANH) Short circuit output current at pin CANH VCANH =0V;VTxD =0V -45 -70 -95 mA
Io(sc) (CANL) Short circuit output current at pin CANL VCANL =36V; VTxD =0V 45 70 120 mA
Vi(dif)(th) Differential receiver threshold voltage
-5V <VCANL < +12V;
-5V <VCANH < +12V;
see Figure 5 0.5 0.7 0.9 V
Vihcm(dif) (th) Differential receiver threshold voltage for high
common-mode
-35V <VCANL < +35V;
-35V <VCANH < +35V;
see Figure 5 0.3 0.7 1.05 V
Vi(dif) (hys) Differential receiver input voltage hysteresis -35V <VCANL < +35V;
-35V <VCANH < +35V;
see Figure 5 50 70 100 mV
Ri(cm)(CANH) Common-mode input resistance at pin CANH 15 26 37 KΩ
Ri(cm) (CANL) Common-mode input resistance at pin CANL 15 26 37 KΩ
Ri(cm)(m) Matching between pin CANH and pin CANL
common-mode input resistance VCANH =VCANL -3 0 +3 %
Ri(dif) Differential input resistance 25 50 75 KΩ
Ci(CANH) Input capacitance at pin CANH VTxD =VCC; not tested 7.5 20 pF
Ci(CANL) Input capacitance at pin CANL VTxD =VCC; not tested 7.5 20 pF
Ci(dif) Differential input capacitance VTxD =VCC; not tested 3.75 10 pF
ILI(CANH) Input leakage current at pin CANH VCC =0V; VCANH = 5V 10 170 250 µA
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AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet
Table 4: DC Characteristics (Continued)
Symbol Parameter Conditions Min. Typ. Max. Unit
Bus Lines (pins CANH and C ANL)
ILI(CANL) Input leakage current at pin CANL VCC =0V; VCANL = 5V 10 170 250 µA
VCM-peak Common-mode peak during transition from
dom → rec or rec → dom See Figure 8 and 9 -500 500 mV
VCM-step Difference in common-mode between dominant
and recessive state See Figure 8 and 9 -150 150 mV
Power-on-Reset
PORL POR level CANH, CANL, Vref in tri-
state below POR level 2.2 3.5 4.7 V
Thermal Shutdown
Tj(sd) Shutdown junction temperature 140 160 190 °C
Timing Characteristics (see Figure 6 and 7)
td(TxD-BUSon) Delay TxD to bus active Vs = 0V 40 85 130 ns
td(TxD-BUSoff) Delay TxD to bus inactive Vs = 0V 30 60 105 ns
td(BUSon-RXD) Delay bus active to RxD Vs = 0V 25 55 105 ns
td(BUSoff-RXD) Delay bus inactive to RxD Vs = 0V 65 100 155 ns
tpd(rec-dom) Propagation delay TxD to RxD from recessive
to dominant Vs = 0V 70 230 ns
td(dom-rec) Propagation delay TxD to RxD from dominant
to recessive Vs = 0V 100 245 ns
tdom(TXD) TXD dominant time for time out VTxD = 0V 250 450 750 µs
8.5 Measurement Setups an d Definition s
Schematics are given for single CAN transceiver.
AMIS-42700
EN1 EN2
Text
Rx0
Tx0
7
9
2
3
10
Rint
4
CANH2
CANL1
GND
Vref
VCC
18
13
12
19
14
8
PC20050502.5
CANL2
CANH1
100 nF
+5V
56151617
1 nF
1 nF
Transient
Generator
VRxD
Vi(dif)(hys)
High
Low
0,5 0,9
PC20040829.7
Hysteresis
Figure 5: Hysteresis of the Receiver
Figure 4: Test Circuit for Automotive Transients
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AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet
AMIS-42700
EN1 EN2
Text
Rx0
Tx0
7
9
2
3
10
Rint
4
CANH2
CANL1
GND
Vref
VCC
18
13
12
19
14
8
PC20050502.4
CANL2
CANH1
100 nF
+5V
56151617
RLT
60 Ω
RLT
60 Ω
CLT
100 pF
CLT
100 pF
Figure 6: Test Circuit for Timing Characteristics
CANHx
CANLx
Tx0
Rx0
dominant
0,9V 0,5V
recessive
0,7 x VCC
Vi(dif) =
VCANH - VCANL
td(TxD-BUSon)
td(BUSon-RxD)
tpd(rec-dom)
td(TxD-BUSoff) td(BUSoff-RxD)
tpd(dom-rec) PC20050502.7
0,3 x VCC
HIGH
LOW
Figure 7: Timing Diagram for AC Characteristics
AMI Semiconductor – Rev. 1.4, May 05 - Preliminary
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AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet
10 nF
30 Ω
Active Probe
30 Ω
6.2 kΩ
47 nF
6.2 kΩ
Spectrum Anayzer
PC20050502.6
AMIS-42700
EN1 EN2
Text
Rx0
Tx0
7
9
2
3
10
Rint
4
CANH2
CANL1
GND
Vref
VCC
18
13
12
19
14
8
CANL2
CANH1
100 nF
+5V
56151617
Gen
CANHx
CANLx
recessive
Vi(com) =
VCANHx + VCANLx
VCM-peak
PC20050502.8
VCM-peak
VCM-step
Figure 8: Basic Test Setup for Electromagnetic Measurement
Figure 9: Common-mode Voltage Peaks (see measurement setup Figure 8)
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AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet
9.0 Package Outline
SOIC-20: Plastic small outline; 20 leads; body width 300mil. AMIS reference: SOIC300 20 300 G
AMI Semiconductor – Rev. 1.4, May 05 - Preliminary
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AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet
10.0 Soldering
10.1 Introduction to Soldering Surface Mount Packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in the AMIS
“Data Handbook IC26; Integrated Circu it Packages” (d ocument ord er number 9398 65 2 90011) . There is no sol dering m ethod that
is ideal for all surface mount IC packages. Wave solderi ng is not al ways suitable for surf ace mou nt ICs, or for printed-circuit bo ard s
with high population densities. In these situations reflow soldering is often u sed.
10.2 Re-flow Soldering
Re-flow soldering requir es solder paste (a suspension of fine solder p articles, flux and binding agent) to be applie d to the printed-
circuit board by screen-printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for
re-flowing; for example, infrared/conv ection heating in a conve yor type oven. T hroughput times (preheat ing, soldering and c ooling)
vary between 100 and 200 seconds depending on heating method. T ypical re-flow peak temper atures range from 215 to 250°C.
The top-surface temperature of the packages should preferably b e kept below 230°C.
10.3 Wave Soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high
component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-
wave soldering method was specificall y deve loped. If wave soldering is used th e follo wing conditions m ust be obs erved for optim al
results:
• Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth
laminar wave.
• For packages with leads on two sides and a pitch (e):
o Larger than or equal to 1.27mm , the footprint longitudinal axis is preferred t o be parallel to the transport d irection
of the printed-circuit board;
o Smaller than 1.27mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-
circuit board. The footprint must incorporate solder thieves at the downstream end.
• For packages with lea ds on f our sides, the f ootprint must be placed at a 45º angl e to the transport direct ion of th e print ed-
circuit board. The footprint must incorporate solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by
screen-printing, pin transfer or syringe dispensing. T he package c an be soldered after the adhesive is cu red. Typical dwell time is
four seconds at 250°C. A mildly-activated flux will eliminate the nee d for removal of corrosive residues in most applicat ions.
10.4 Manual Soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24V or less) soldering iron applied to
the flat part of the lead. Contact time must be limited to 10 seconds at up to 300°C.
When using a dedicated tool, all other leads can be soldered in one operation within t wo to five secon ds between 270 and 320°C.
Table 11: Soldering Process Soldering Method
Package Wave Re-flow(1)
BGA, SQFP Not suitable Suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS Not suitable (2) Suitable
PLCC (3) , SO, SOJ Suitable Suitable
LQFP, QFP, TQFP Not recommended (3)(4) Suitable
SSOP, TSSOP, VSO Not recommended (5) Suitable
Notes:
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size
of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For
details, refer to the drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods.”
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and
as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder
thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8mm; it is definitely not suitable for packages with a
pitch (e) equal to or smaller than 0.65mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65mm; it is definitely not suitable for packages with a
pitch (e) equal to or smaller than 0.5mm.
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AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet
11.0 Company or Product Inquiries
For more information about AMI Semiconductor, our technology and our product, visit our website at: http://www.amis.com
North America
Tel: +1.208.233.4690
Fax: +1.208.234.6795
Europe
Tel: +32 (0) 55.33.22.11
Fax: +32 (0) 55.31.81.12
Devices sold by AMIS are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMIS makes no warranty, express,
statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMIS
makes no warranty of merchantability or fitness for any purposes. AMIS reserves the right to discontinue production and change specifications and prices at an
y
time and without notice. AMI Semiconductor's products are intended for use in commercial applications. Applications requiring extended temperature range,
unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not
recommended without additional processing by AMIS for such applications. Copyright ©2005 AMI Semiconductor, Inc.
AMI Semiconductor – Rev. 1.4, May 05 - Preliminary
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