Description
The A3946 is designed specifically for ap pli ca tions that require
high power unidirectional DC motors, three-phase brushless DC
motors, or other inductive loads. The A3946 provides two
high-current gate drive outputs that are capable of driving a
wide range of power N-channel MOSFETs. The high-side gate
driver switches an N-channel MOSFET that controls current to
the load, while the low-side gate driver switches an N-channel
MOSFET as a synchronous rectifier.
A bootstrap capacitor provides the above-battery supply voltage
required for N-channel MOSFETs. An internal top-off charge
pump for the high side allows DC (100% duty cycle) operation
of the half-bridge.
The A3946 is available in a power pack ag e: a 16-lead TSSOP
with ex posed thermal pad (suffix LP). It is lead (Pb) free, with
100% matte tin plated leadframe (suffix -T).
29319.150i
Features and Benefits
On-chip charge pump for 7 V minimum input
supply voltage
High-current gate drive for driving a wide range of
N-channel MOSFETs
Bootstrapped gate drive with top-off charge pump
for 100% duty cycle
Overtemperature protection
Undervoltage protection
–40ºC to 135ºC ambient operation
Half-Bridge Power MOSFET Controller
Package: 16-pin TSSOP with exposed
thermal pad (Suffix LP)
Typical Application
A3946
Approximate Scale 1:1
M
~FAULT
BOOT
V
BAT
GH
S
A3946
GL
PGND
CP1
CP2
VREG
PAD
IN1
ECU
IN2
RESET
LGND
DT
VREF
VBB
Half
-Bridge Power MOSFET Controller
A3946
2
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Absolute Maximum Ratings
Characteristic Symbol Notes Rating Units
Load Supply Voltage VBB 60 V
Logic Inputs Voltage VIN –0.3 to 6.5 V
Pin S Voltage VS–4 to 60 V
Pin GH Voltage VGH –4 to 75 V
Pin BOOT Voltage VBOOT –0.6 to 75 V
Pin DT Voltage VDT VREF V
Pin VREG Voltage VREG –0.6 to 15 V
Operating Ambient Temperature TARange K –40 to 135 ºC
Maximum Junction Temperature TJ(max) 150 ºC
Storage Temperature Tstg –55 to 150 ºC
ESD Rating, Human Body Model AEC-Q100-002, all pins 2000 V
ESD Rating, Charged Device Model AEC-Q100-011, all pins 1050 V
THERMAL CHARACTERISTICS
Characteristic Symbol Test Conditions* Value Units
Package Thermal Resistance RJA
Mounted on a 2-layer PCB with 3.8 in2. 2-oz copper both sides 43 ºC/W
Mounted on a 4-layer PCB based on JEDEC standard 34 ºC/W
*Additional thermal information available on Allegro Web site.
Selection Guide
Part Number Packing Package
A3946KLPTR-T 4000 pieces/reel 16-pin TSSOP with exposed thermal pad
Half
-Bridge Power MOSFET Controller
A3946
3
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Block Diagram
Control Logic Table
IN1 IN2 DT Pin RESET GH GL Function
X X X 0 Z Z Sleep mode
00R
DEAD - LGND 1 L H Low-side FET ON following dead time
01R
DEAD - LGND 1 L L All OFF
10R
DEAD - LGND 1 L L All OFF
11R
DEAD - LGND 1 H L High-side FET ON following dead time
0 0 VREF 1 L L All OFF
0 1 VREF 1 L H Low-side FET ON
1 0 VREF 1 H L High-side FET ON
1 1 VREF 1 H H CAUTION: High-side and low-side FETs ON
VBB
VREG
CBOOT
+VBAT
+5 Vref
BOOT
GH
S
GL
LGND
VREG
CP1CP2
Charge
Pump
RESET
Protection
VREG Undervoltage
Overtemperature
UVLOBOOT
IN2
~FAULT
DT
Control
Logic
Turn-On
Delay
IN1
RDEAD
VREF
VREF
Bootstrap
UVLO
10
k7
CREG
C1
0.47 uF, X7R
V rated to VBAT
RGATE
RGATE
ILIM
PGND
High Side
Driver
Low Side
Driver
C2
0.47 uF, X7R
V rated to VBAT
0.1 uF
X7R
10 V
P
LP
L
L
L
L
L
L
P
PL
P
P
Top-Off
Charge Pump
PAD
Half
-Bridge Power MOSFET Controller
A3946
4
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Characteristics Symbol Test Conditions Limits
Min. Typ. Max. Units
VBB Quiescent Current IVBB
RESET = High, Outputs Low –36mA
RESET = Low ––
10 A
VREG Output Voltage VREG
VBB > 7.75 V, Ireg = 0 mA to 15 mA 12.0 13 13.5 V
VBB = 7 V to 7.75 V, Ireg = 0 mA to 15 mA 11.0 –13.5 V
Charge Pump Frequency FCP CP1, CP2 –62.5 –kHz
VREF Output Voltage VREF IREF 4 mA, CREF = 0.1 F 4.5 –5.5 V
Top-Off Charge Pump
Current ITO VBOOT – VS = 8.5 V 20 ––
A
Gate Output Drive
Turn On Time trise CLOAD = 3300 pF, 20% to 80% –60 100 ns
Turn Off Time tfall CLOAD = 3300 pF, 80% to 20% –40 80 ns
Pullup On Resistance RDSUP
Tj = 25C–4–
Tj = 135C–68
Pulldown On Resistance RDSDOWN
Tj = 25C–2–
Tj = 135C–34
GH Output Voltage VGH tpw < 10 s, Bootstrap Capacitor fully charged VREG – 1.5 ––
V
GL Output Voltage VGL –VREG – 0.2 ––
V
Timing
Dead Time (Delay from
Turn Off to Turn On) tDEAD
Rdead = 5 k200 350 500 ns
Rdead = 100 k567s
Propagation Delay tPD Logic input to unloaded GH, GL. DT = VREF ––
150 ns
ELECTRICAL CHARACTERISTICS at TA = –40 to +135°C, VBB = 7 to 60 V (unless otherwise noted)
Half
-Bridge Power MOSFET Controller
A3946
5
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Limits
Characteristics Symbol Test Conditions Min. Typ. Max. Units
Protection
VREG Undervoltage VREGOFF VREG decreasing 7.8 8.3 8.8 V
VREGON VREG increasing 8.6 9.1 9.6 V
BOOT Undervoltage VBSOFF VBOOT decreasing 7.25 7.8 8.3 V
VBSON VBOOT increasing 8 8.75 9.5 V
Thermal Shutdown Temperature TJTSD Temperature increasing –170 –°C
Thermal Shutdown Hysteresis TJRecovery = TJTSD – TJ–15 –°C
Logic
Input Current IIN(1) IN1 VIN / IN2 VIN = 2.0 V –40 100 A
IIN(0) IN1 VIN / IN2 VIN = 0.8 V –16 40 A
RESET pin only ––1A
Logic Input Voltage VIN(1) IN1 / IN2 logic high 2.0 ––V
RESET logic high 2.2 ––V
VIN(0) Logic low ––
0.8 V
Logic Input Hysteresis –All digital inputs 100 –300 mV
Fault Output
Vol I = 1 mA, fault asserted ––
400 mV
Voh V = 5 V ––1A
ELECTRICAL CHARACTERISTICS at TA = –40 to +135°C, VBB = 7 to 60 V (unless otherwise noted)
Half
-Bridge Power MOSFET Controller
A3946
6
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
VREG. A 13 V output from the on-chip charge pump, used
to power the low-side gate drive circuit directly, provides the
current to charge the bootstrap capacitors for the high-side gate
drive.
The VREG capacitor, CREG, must supply the instantaneous cur-
rent to the gate of the low-side MOSFET. A 10 F, 25 V capaci-
tor should be adequate. This capacitor can be either electrolytic
or ceramic (X7R).
Diagnostics and Protection. The fault output pin,
~FAULT, goes low (i.e., FAULT = 1) when the RESET line is
high and any of the following conditions are present:
• Undervoltage on VREG (UVREG). Note that the outputs
become active as soon as VREG comes out of undervoltage,
even though the ~FAULT pin is latched until reset.
• Undervoltage on VREF (UVREF). Note that this condition
does NOT latch a fault.
• A junction temperature > 170°C (OVERTEMP). This condi-
tion sets a latched fault.
• An undervoltage on the stored charge of the BOOT capacitor
(UVBOOT). This condition does NOT set a latched fault.
An overtemperature event signals a latched fault, but does not
disable any output drivers, regulators, or logic inputs. The user
must turn off the A3946 (e.g., force the RESET line low) to
prevent damage.
The power FETs are protected from inadequate gate drive
voltage by undervoltage detectors. Either of the regulator
undervoltage faults (UVREG or UVREF) disable both output
drivers until both voltages have been restored. The high-side
driver is also disabled during a UVBOOT fault condition.
Under many operating conditions, both the high-side (GH)
and low-side (GL) drivers may be off, allowing the BOOT
capacitor to discharge (or never become charged) and create a
UVBOOT fault condition, which in turn inhibits the high-side
driver and creates a FAULT = 1. This fault is NOT latched. To
remove this fault, momentarily turn on GL to charge the BOOT
capacitor.
Latched faults may be cleared by a low pulse, 1 to 10 s
wide, on the RESET line. Throughout that pulse (despite a
possible UVBOOT), FAULT = 0; also the fault latch is cleared
immediately, and remains cleared. If the power is restored
(no UVREG or UVREF), and if no OVERTEMP fault exists,
then the latched fault remains cleared when the RESET line
returns to high. However, FAULT = 1 may still occur because a
UVBOOT fault condition may still exist.
Charge Pump. The A3946 is designed to ac com mo date a
wide range of power supply voltages. The charge pump output,
VREG, is regulated to 13 V nominal.
In all modes, this regulator is current-limited. When VBB < 8 V,
the charge pump operates as a voltage doubler. When 8 V <
VBB< 15 V, the charge pump operates as a voltage doubler/
PWM, current-controlled, voltage regulator. When VBB>15 V,
the charge pump operates as a PWM, current-controlled, volt-
age regulator. Effi ciency shifts, from 80% at VBB= 7 V, to 20%
at VBB = 50 V.
CAUTION. Although simple paralleling of VREG supplies
from several A3946s may appear to work correctly, such a
confi guration is NOT recommended. There is no assurance that
one of the regulators will not dominate, taking on all of the load
and back-biasing the other regulators. (For example, this could
occur if a particular regulator has an internal reference voltage
that is higher that those of the other regulators, which would
force it to regulate at the highest voltage.)
Sleep Mode/Power Up. In Sleep Mode, all circuits are
disabled in order to draw minimum current from VBB. When
powering up and leaving Sleep Mode (the RESET line is high),
the gate drive outputs stay disabled and a fault remains asserted
until VREF and VREG pass their undervoltage thresholds.
When powering up, before starting the fi rst bootstrap charge
cycle, wait until t = CREG ⁄ 4 (where CREG is in F, and t is in ns)
to allow the charge pump to stabilize.
When powered-up (not in Sleep Mode), if the RESET line is
low for > 10 s, the A3946 may start to enter Sleep Mode (VREF
< 4 V). In that case, ~FAULT = 1 as long as the RESET line
remains low.
If the RESET line is open, the A3946 should go into Sleep
Mode. However, to ensure that this occurs, the RESET line
must be grounded.
Functional Description
Half
-Bridge Power MOSFET Controller
A3946
7
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Dead Time. The analog input pin DT sets the delay to turn
on the high- or low-side gate outputs. When in struct ed to
turn off, the gate outputs change after an short internal propa-
gation delay (90 ns typical). The dead time controls the time
between this turn-off and the turn-on of the appropriate gate.
The duration, tDEAD, can be adjusted within the range 350 ns
to 6000 ns using the following formula:
tDEAD = 50 + (RDEAD ⁄ 16.7
)
where tDEAD is in ns, and RDEAD is in , and should be in the
range 5 k < RDEAD < 100 k.
Do not ground the DT pin. If the DT pin is left open, dead
time defaults to 12 s.
Control Logic. Two different methods of control are
possible with the A3946. When a resistor is connected from
DT to ground, a single-pin PWM scheme is utilized by short-
ing IN1 with IN2. If a very slow turn-on is required (greater
than 6 s), the two input pins can be hooked-up individually
to allow the dead times to be as long as needed.
The dead time circuit can be disabled by tying the DT pin
to VREF. This disables the turn-on delay and allows direct
control of each MOSFET gate via two control lines. This is
shown in the Control Logic table, on page 2.
Top-Off Charge Pump. An internal charge pump allows
100% duty cycle operation of the high-side MOSFET. This is
a low-current trickle charge pump, and is only operated after
a high-side has been signaled to turn on. A small amount of
bias current is drawn from the BOOT pin to operate the fl oat-
ing high-side circuit. The top-off charge pump simply pro-
vides enough drive to ensure that the gate voltage does not
droop due to this bias supply current. The charge required for
initial turn-on of the high-side gate must be supplied by boot-
strap capacitor charge cycles. This is described in the section
Application Information.
VREF. VREF is used for the internal logic circuitry and
is not intended as an external power supply. However,
the VREF pin can source up to 4 mA of current. A 0.1 F
capacitor is needed for decoupling.
Fault Response Table
Fault Mode RESET ~FAULT VREG VREF GH1GL1
No Fault 1 1 ON ON (IL) (IL)
BOOT Capacitor Undervoltage21 0 ON ON 0 (IL)
VREG Undervoltage31 0 ON ON 0 0
VREF Undervoltage41 0 OFF ON 0 0
Thermal Shutdown31 0 ON ON (IL) (IL)
Sleep50 1 OFF OFF High Z High Z
1(IL) indicates that the state is determined by the input logic.
2This fault occurs whenever there is an undervoltage on the BOOT capacitor. This fault is not latched.
3These faults are latched. Clear by pulsing RESET = 0. Note that outputs become active as soon as VREG comes out of undervoltage, even
though ~FAULT = 0.
4Unspecifi ed VREF undervoltage threshold < 4 V.
5During power supply undervoltage conditions, GH and GL are instructed to be 0 (low). However, with VREG < 4 V, the outputs start to be-
come high impedance (High Z). Refer to the section Sleep Mode/Power Up.
Half
-Bridge Power MOSFET Controller
A3946
8
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Application Information
Bootstrap Capacitor Selection. CBOOT must be cor-
rectly selected to ensure proper operation of the device. If
too large, time is wasted charging the capacitor, with the
result being a limit on the maximum duty cycle and PWM
frequency. If the capacitor is too small, the voltage drop can
be too large at the time the charge is trans ferred from the
CBOOT to the MOSFET gate.
To keep the voltage drop small:
QBOOT >> QGATE
where a factor in the range of 10 to 20 is reasonable. Using
20 as the factor:
QBOOT = CBOOT × VBOOT = QGATE × 20
and
CBOOT = QGATE × 20 / VBOOT
The voltage drop on the BOOT pin, as the MOSFET is being
turned on, can be approximated by:
Delta_v = QGATE / CBOOT
For example, given a gate charge, QGATE, of 160 nC, and the
typical BOOT pin voltage of 12 V, the value of the Boot
capacitor, CBOOT, can be determined by:
CBOOT = (160 nC × 20) / 12 V 0.266 F
Therefore, a 0.22 F ceramic (X7R) capacitor can be chosen
for the Boot capacitor.
In that case, the voltage drop on the BOOT pin, when the
high-side MOSFET is turned on, is:
Delta_v = 160 nC / 0.22 F = 0.73 V
Bootstrap Charging. It is good practice to ensure that the
high-side bootstrap capacitor is completely charged before a
high-side PWM cycle is re quest ed.
The time required to charge the capacitor can be ap prox i-
mat ed by:
tCHARGE = CBOOT (Delta_v / 100 mA)
At power-up and when the drivers have been disabled for
a long time, the bootstrap capacitor can be completely
discharged. In this case, Delta_v can be considered to be the
full high-side drive voltage, 12 V. Otherwise, Delta_v is the
amount of voltage dropped during the charge transfer, which
should be 400 mV or less. The capacitor is charged whenever
the S pin is pulled low, via a GL PWM cycle, and current
fl ows from VREG through the internal bootstrap diode
circuit to CBOOT.
Power Dissipation. For high ambient temperature
applications, there may be little margin for on-chip power
con sump tion. Careful attention should be paid to ensure that
the op er at ing conditions allow the A3946 to remain in a safe
range of junction temperature.
The power consumed by the A3946 can be es ti mat ed as:
P_total = Pd_bias + Pd_cpump + Pd_switching_loss
where:
Pd_bias = VBB × IVBB , typically 3 mA,
and
Pd_cpump = (2VBB – VREG) IAV E , for VBB < 15 V, or
Pd_cpump = (VBB – VREG) IAV E , for VBB > 15 V,
in either case, where
IAV E = QGATE × 2 × fPWM
and
Pd_switching_loss = QGATE × VREG × 2 × fPWM Ratio,
where
Ratio = 10 / (RGATE + 10 ).
Half
-Bridge Power MOSFET Controller
A3946
9
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
L
P
L
P
VREG
CBOOT
+VBAT
+5 Vref
BOOT
GH
S
GL
LGND
VREG
CP1CPVBB 2
RESET
Protection
VREG Undervoltage
Overtemperature
UVLOBOOT
IN2
~FAULT
DT
Control
Logic
Turn-On
Delay
IN1
RDEAD
15.8 k7
VREF
Bootstrap
UVLO
10
k7
CREG
C1
0.47 μF
RGATE
RGATE
ILIM
High Side
Driver
Low Side
Driver
C2
10 μF
0.1 uF
VREF
10 μF
IRF2807
IRF2807
0.47 μF
33 7
470
k7
33 7
External
+5 V
IN
IN
Brake
Forward
MDC
Motor
PGND
LP
L
L
L
L
P
PL
P
Charge
Pump
Top-Off
Charge Pump
Application Block Diagrams
Diagram A. Dependent drivers. Unidirectional motor control with braking and dead time. TDEAD = 1 s; QTOTAL = 160 nC.
Half
-Bridge Power MOSFET Controller
A3946
10
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Diagram B. Independent drivers. One high-side drive and one low-side drive.
VREG
CBOOT
+VBAT
+5 Vref
BOOT
GH
S
GL
LGND
VREG
CP1CPVBB 2
RESET
Protection
VREG Undervoltage
Overtemperature
UVLOBOOT
IN2
~FAULT
DT
Control
Logic
Turn-On
Delay
IN1
VREF
Bootstrap
UVLO
10
k7
CREG
C1
0.47 μF
RGATE
ILIM
High Side
Driver
Low Side
Driver
C2
10 μF
0.1 uF
VREF
10 μF
IRF2807
IRF2807
0.47 μF
33 7
External
+5 V
Slow
Decay
Forward
VREF
Forward
Slow
Decay
DC Motor #1
DC Motor #2
470
k7
M
DC Motor #2
M
DC Motor #1
PGND
P
L
P
LP
L
L
L
L
P
P
470
k7
RGATE
33 7
P
L
Charge
Pump
Top-Off
Charge Pump
Half
-Bridge Power MOSFET Controller
A3946
11
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
VREG
+VBAT
+5 Vref
BOOT
GH
S
GL
LGND
VREG
CP1CPVBB 2
RESET
Protection
VREG Undervoltage
Overtemperature
UVLOBOOT
IN2
~FAULT
DT
Control
Logic
Turn-On
Delay
IN1
VREF
Bootstrap
UVLO
10
k7
CREG
C1
0.47 F
RGATE
RGATE
ILIM
High Side
Driver
Low Side
Driver
C2
10 F
0.1 uF
VREF
10 F
IRF2807
IRF2807
33 7
33 7
External
+5 V
Slow
Decay
Forward
VREF
Forward
Slow
Decay
DC Motor #1
DC Motor #2
470
k7
470
k7
PGND
DC Motor
#2
M
DC Motor
#1
M
P
L
P
LP
L
L
L
L
P
PL
P
P
Charge
Pump
Top-Off
Charge Pump
PAD
Diagram C. Independent drivers. Two low-side drives.
Half
-Bridge Power MOSFET Controller
A3946
12
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Terminal List Table
Name Number Description
VREG 1 Gate drive supply.
CP2 2 Charge pump capacitor, positive side. When not using the charge pump, leave this pin open.
CP1 3 Charge pump capacitor, negative side. When not using the charge pump, leave this pin open.
PGND* 4 External ground. Internally connected to the power ground.
GL 5 Low-side gate drive output for external MOSFET driver. External series gate resistor can be used to control
slew rate seen at the power driver gate, thereby controlling the di/dt and dv/dt of the S pin output.
S6
Directly connected to the load terminal. The pin is also connected to the negative side of the bootstrap
capacitor and negative supply connection for the fl oating high-side drive.
GH 7 High-side gate drive output for N-channel MOSFET driver. External series gate resistor can be used to
control slew rate seen at the power driver gate, thereby controlling the di/dt and dv/dt of the S pin output.
BOOT 8 High-side connection for bootstrap capacitor, positive supply for the high-side gate drive.
~FAULT 9 Diagnostic output, open drain. Low during a fault condition.
IN1 10 Logic control.
IN2 11 Logic control.
RESET 12 Logic control input. When RESET = 0, the chip is in a very low power sleep mode.
LGND* 13 External ground. Internally connected to the logic ground.
DT 14 Dead Time. Connecting a resistor to GND sets the turn-on delay to prevent shoot-through. Forcing this
input high disables the dead time circuit and changes the logic truth table.
VREF 15 5 V internal reference decoupling terminal.
VBB 16 Supply Input.
PAD – Exposed thermal pad. Not connected to any pin, but should be externally connected to ground, to reduce
noise pickup by the pad.
The PGND pin (4) and LGND pin (13) grounds are NOT internally connected, and both must be connected to ground externally.
3
4
5
6
7
8
2
1
14
13
12
11
10
9
15
16
VREG
CP2
CP1
PGND PAD
GL
S
GH
BOOT
VBB
VREF
DT
LGND
RESET
IN2
IN1
~FAULT
LP package
Pin-out Diagram
Half
-Bridge Power MOSFET Controller
A3946
13
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
LP Package TSSOP with Exposed Thermal Pad
C
SEATING
PLANE
C0.10
16X
6.10
0.65
0.45
1.70
3.00
5.00 ±0.10
3.00
3.00
3.00
1.20 MAX
0.15 MAX
0.65
0.25
(1.00)
4.40 ±0.10 6.40 ±0.20 0.60 ±0.15
4° ±4
0.25 +0.05
–0.06
0.15 +0.05
–0.06
21
16
GAUGE PLANE
SEATING PLANE
B
A
16
21
ATerminal #1 mark area
B
For Reference Only
(reference JEDEC MO-153 ABT)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown Reference land pattern layout (reference IPC7351 SOP65P640X110-17M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
PCB Layout Reference View
Exposed thermal pad (bottom surface)
C
C
Half
-Bridge Power MOSFET Controller
A3946
14
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Copyright ©2003-2013 Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to
permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, LLC assumes no re spon si bil i ty for its
use; nor for any in fringe ment of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
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