93AA56B-E/P - Microchip Technology, Inc.

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C

93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C

93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C

Features:

• Densities from 1 Kbits through 16 Kbits

• Low-power CMOS technology

• Available with or without ORG function:

With ORG function:

- ORG pin at Logic Low: 8-bit word

- ORG pin at Logic High: 16-bit word

Without OR G func tion :

- ‘A’ version: 8-bit word

- ‘B’ versi on: 16-bit word

• Program Enable pin:

- Write-protect for entire array

(93XX76C and 93XX86C only)

• Self-timed Erase/Write cy cles

(including auto-erase)

• Automatic ERAL before WRAL

• Power-on/off data protection circuitry

• Industry standard 3-wire serial I/O

• Device Sta tus sign al (Ready/Busy)

• Seque nti al Read fun cti on

• 1,000,000 E/W cycles

• Data retention > 200 years

• Pb-free and RoHS co mpliant

• Temperature ranges supported:

Pin Function Table

Description:

Microchip Technology Inc. supports the 3-wire

Microwire bus with low-voltage serial Electrically

Erasable PROMs (EEPROM) that range in density

from 1 Kbits up to 16 Kbits. Each density is available

with and without the ORG functionality, and selected

by the part number ordered. Advanced CMOS technol-

ogy makes these devices ideal for low-power, nonvol-

atile memory applications. The entire series of

Microwire devices are available in the standard 8-lead

PDIP and SOIC packages, as well as the more

advanced packaging such as the 8-lead MSOP, 8-lead

TSSOP, 6-lead SOT-23, and 8-lead DFN (2x3). All

packages are Pb-free.

Pin Diagrams (not to scale)

- Industrial (I) -40°C to +85°C

- Automotive (E) -40°C to +125°C

Name Function

CS Chip Select

CLK Serial Data Clock

DI Serial Data Input

DO Serial Data Output

VSS Ground

PE Program Enable

ORG Memory Configuration

VCC Power Supply

Note: ORG and PE functionality not available in

all products. See Table 1-1, Device

Selection Ta ble.

PDIP/SOIC

(P, SN)

CLK DI

NC ORG

ROTATED SOIC

(ex: 93LC46BX)

TSSOP/MSOP

CLK

(2,3)

ORG

(1,3)

(ST, MS) SOT-23

CLK

(OT)

Note 1: ORG pin: Only on 93XX46C/56C/66C/76C/86C

2: PE pin: Only on 93XX76C/86C.

3: ORG/PE: No internal connections on 93XXA/B

DO V

ORG

CLK

CS V

(1,3

)

(1,3)

(2,3)

DFN (MC)

CLK

(2,3)

ORG

(1,3)

1K-16K Micr owire Compatible Serial EEPROMs

93XX46X/56X/66X/76X/86X

TABLE 1-1: DEVICE SELECTION TABLE

Part Number Density

(Kbits) VCC

Range ORG Pin Organization

(Words) PE Pin Temp

Range Packages

93XX46A/B/C

93AA46A 1 1.8-5.5 No 128 x 8 bits No I P, SN, ST, MS, OT, MC

93AA46B 1 1.8-5.5 No 64 x 16 bits No I P, SN, ST, MS, OT, MC

93AA46C 1 1.8-5.5 Yes Selectable x8 or x16 No I P, SN, ST, MS, MC

93LC46A 1 2.5-5.5 No 128 x 8 bits No I, E P, SN, ST, MS, OT, MC

93LC46B 1 2.5-5.5 No 64 x 16 bits No I, E P, SN, ST, MS, OT, MC

93LC46C 1 2.5-5.5 Yes Selectable x8 or x16 No I, E P, SN, ST, MS, MC

93C46A 1 4.5-5.5 No 128 x 8 bits No I, E P, SN, ST, MS, OT, MC

93C46B 1 4.5-5.5 No 64 x 16 bits No I, E P, SN, ST, MS, OT, MC

93C46C 1 4.5-5.5 Yes Selectable x8 or x16 No I, E P, SN, ST, MS, MC

93AA46AX/BX/CX, 93LC46AX/BX/CX, 93C46AX/BX/CX (Alternate pinout with die rotated 90°)

93AA46AX 1 1.8-5.5 No 128 x 8 bits No I P, SN, ST, MS, OT, MC

93AA46BX 1 1.8-5.5 No 64 x 16 bits No I P, SN, ST, MS, OT, MC

93AA46CX 1 1.8-5.5 Yes Selectable x8 or x16 No I P, SN, ST, MS, MC

93LC46AX 1 2.5-5.5 No 128 x 8 bits No I, E P, SN, ST, MS, OT, MC

93LC46BX 1 2.5-5.5 No 64 x 16 bits No I, E P, SN, ST, MS, OT, MC

93LC46CX 1 2.5-5.5 Yes Selectable x8 or x16 No I, E P, SN, ST, MS, MC

93C46AX 1 4.5-5.5 No 128 x 8 bits No I, E P, SN, ST, MS, OT, MC

93C46BX 1 4.5-5.5 No 64 x 16 bits No I, E P, SN, ST, MS, OT, MC

93C46CX 1 4.5-5.5 Yes Selectable x8 or x16 No I, E P, SN, ST, MS, MC

93XX56A/B/C

93AA56A 2 1.8-5.5 No 256 x 8 bits No I P, SN, ST, MS, OT, MC

93AA56B 2 1.8-5.5 No 128 x 16 bits No I P, SN, ST, MS, OT, MC

93AA56C 2 1.8-5.5 Yes Selectable x8 or x16 No I P, SN, ST, MS, MC

93LC56A 2 2.5-5.5 No 256 x 8 bits No I, E P, SN, ST, MS, OT, MC

93LC56B 2 2.5-5.5 No 128 x 16 bits No I, E P, SN, ST, MS, OT, MC

93LC56C 2 2.5-5.5 Yes Selectable x8 or x16 No I, E P, SN, ST, MS, MC

93C56A 2 4.5-5.5 No 256 x 8 bits No I, E P, SN, ST, MS, OT, MC

93C56B 2 4.5-5.5 No 128 x 16 bits No I, E P, SN, ST, MS, OT, MC

93C56C 2 4.5-5.5 Yes Selectable x8 or x16 No I, E P, SN, ST, MS, MC

93XX66A/B/C

93AA66A 4 1.8-5.5 No 512 x 8 bits No I P, SN, ST, MS, OT, MC

93AA66B 4 1.8-5.5 No 256 x 16 bits No I P, SN, ST, MS, OT, MC

93AA66C 4 1.8-5.5 Yes Selectable x8 or x16 No I P, SN, ST, MS, MC

93LC66A 4 2.5-5.5 No 512 x 8 bits No I, E P, SN, ST, MS, OT, MC

93LC66B 4 2.5-5.5 No 256 x 16 bits No I, E P, SN, ST, MS, OT, MC

93LC66C 4 2.5-5.5 Yes Selectable x8 or x16 No I, E P, SN, ST, MS, MC

93C66A 4 4.5-5.5 No 512 x 8 bits No I, E P, SN, ST, MS, OT, MC

93C66B 4 4.5-5.5 No 256 x 16 bits No I, E P, SN, ST, MS, OT, MC

93C66C 4 4.5-5.5 Yes Selectable x8 or x16 No I, E P, SN, ST, MS, MC

93XX46X/56X/66X/76X/86X

93XX76A/B/C

93AA76A 8 1.8-5.5 No 1024 x 8 bits No I OT

93AA76B 8 1.8-5.5 No 512 x 16 bits No I OT

93AA76C 8 1.8-5.5 Yes Selectable x8 or x16 Yes I P, SN, ST, MS, MC

93LC76A 8 2.5-5.5 No 1024 x 8 bits No I, E OT

93LC76B 8 2.5-5.5 No 512 x 16 bits No I, E OT

93LC76C 8 2.5-5.5 Yes Selectable x8 or x16 Yes I, E P, SN, ST, MS, MC

93C76A 8 4.5-5.5 No 1024 x 8 bits No I, E OT

93C76B 8 4.5-5.5 No 512 x 16 bits No I, E OT

93C76C 8 4.5-5.5 Yes Selectable x8 or x16 Yes I, E P, SN, ST, MS, MC

93XX86A/B/C

93AA86A 16 1.8-5.5 No 2048 x 8 bits No I OT

93AA86B 16 1.8-5.5 No 1024 x 16 bits No I OT

93AA86C 16 1.8-5.5 Yes Selectable x8 or x16 Yes I P, SN, ST, MS, MC

93LC86A 16 2.5-5.5 No 2048 x 8 bits No I, E OT

93LC86B 16 2.5-5.5 No 1024 x 16 bits No I, E OT

93LC86C 16 2.5-5.5 Yes Selectable x8 or x16 Yes I, E P, SN, ST, MS, MC

93C86A 16 4.5-5.5 No 2048 x 8 bits No I, E OT

93C86B 16 4.5-5.5 No 1024 x 16 bits No I, E OT

93C86C 16 4.5-5.5 Yes Selectable x8 or x16 Yes I, E P, SN, ST, MS, MC

TABLE 1-1: DEVICE SELECTION TABLE (CONTINUED)

Part Number Density

(Kbits) VCC

Range ORG Pin Organization

(Words) PE Pin Temp

Range Packages

93XX46X/56X/66X/76X/86X

2.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings(†)

VCC.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................ -40°C to +125°C

ESD protection on all pins ......................................................................................................................................................≥ 4kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device . This is a stress rating only and fun ction al ope rati on of th e dev ice at tho se or a ny oth er con dition s abov e thos e

indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

TABLE 2-1: DC CHARACTERISTICS

All parameters ap ply o ver the specif ied

ranges unless otherwise noted.

VCC = 1.8V to 5.5V

Industrial (I): TA = -40°C to +85°C

Automotive (E): TA = -40°C to +125°C

Param.

No. Symbol Parameter Min. Typ. Max. Units Conditions

D1 VIH1

VIH2High-level input voltage 2.0

0.7 VCC —

—VCC +1

VCC +1 V

VVCC ≥ 2.7V

VCC < 2.7V

D2 VIL1

VIL2Low-level input voltage -0.3

-0.3 —

—0.8

0.2 VCC V

VVCC ≥ 2.7V

VCC < 2.7V

D3 VOL1

VOL2Low-level ou tput voltage —

——

—0.4

0.2 V

VIOL = 2.1 mA, VCC = 4.5V

IOL = 100 μA, VCC = 2.5V

D4 VOH1

VOH2High-level output voltage 2.4

VCC-0.2 —

——

—V

VIOH = -400 μA, VCC = 4.5V

IOH = -100 μA, VCC = 2.5V

D5 ILI Input leakage current — — ±1 μAVIN = VSS to VCC

D6 ILO Output leakage current — — ±1 μAVOUT = VSS to VCC

D7 CIN,

COUT Pin cap ac itance

(all inputs/outputs) ——7pFVIN/VOUT = 0V (Note 1)

TA = 25°C, FCLK = 1 MHz

D8 ICC write Write current — — 2 mA FCLK = 3 MHz, VCC = 5.5V

(93XX46X/56X/66X)

—

500

—

μA

FCLK = 3 MHz, VCC = 5.5V

(93XX76X/86X)

FCLK = 2 MHz, VCC = 2.5V

D9 ICC read Read current —

—

100

500

—

μA

FCLK = 3 MHz, VCC = 5.5V

FCLK = 2 MHz, VCC = 3.0V

FCLK = 2 MHz, VCC = 2.5V

D10 ICCS Standby current —

——

—1

5μA

μAI-Temp (Note 2, 3)

E-Temp

CLK = Cs = 0V

ORG = DI = VSS or VCC

D11 VPOR VCC voltage detect —

—1.5V

3.8V —

—V

V93AAX6A/B/C, 93LCX6A/B/C,

93CX6A/B/C (Note 1)

Note 1: This parameter is periodically sampled and not 100% tested.

2: ORG and PE pins not available on ‘A’ or ‘B’ versions.

3: Ready/Busy status must be cleared from DO, see Section 4 .4 “Data Out (DO)”.

93XX46X/56X/66X/76X/86X

TABLE 2-2: AC CHARACTERISTICS

All parameters apply over the specified

ranges unless otherwise noted.

VCC = 1.8V to 5.5V

Industri al (I): TA = -40°C to +85°C

Automotive (E): TA = -40°C to +125°C

Param.

No. Symbol Parameter Min. Max. Units Conditions

A1 FCLK Clock frequency — 3

MHz

4.5V ≤ VCC < 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

A2 TCKH Clock high time 200

250

450

—ns

4.5V ≤ VCC < 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

A3 TCKL Clock low time 100

200

450

—ns

4.5V ≤ VCC < 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

A4 TCSS Chip Sele ct setup time 50

100

250

—ns

4.5V ≤ VCC < 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

A5 TCSH Chip Sele ct hol d time 0 — ns 1.8V ≤ VCC < 5.5V

A6 TCSL Chip Sele ct low tim e 250 — ns 1.8V ≤ VCC < 5.5V

A7 TDIS Data input setup time 50

100

250

—ns

4.5V ≤ VCC < 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

A8 TDIH Data input hold time 50

100

250

—ns

4.5V ≤ VCC < 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

A9 TPD Data output del ay time — 100 ns 4.5V ≤ VCC < 5.5V, CL = 100 pF

(93C76X/86X)

—200

250

400

4.5V ≤ VCC < 5.5V, CL = 100 pF

2.5V ≤ VCC < 4.5V, CL = 100 pF

1.8V ≤ VCC < 2.5V, CL = 100 pF

A10 TCZ Data output disable time — 100

200 ns

ns 4.5V ≤ VCC < 5.5V, (Note 1)

1.8V ≤ VCC < 4.5V, (Note 1)

A11 TSV Status valid time — 200

300

500

4.5V ≤ VCC < 5.5V, CL = 100 pF

2.5V ≤ VCC < 4.5V, CL = 100 pF

1.8V ≤ VCC < 2.5V, CL = 100 pF

A12 TWC Program cycle time — 5 ms Erase/Write mode

93XX76X/86X

(AA and LC versions)

— 6 ms 93XX46X/56X/66X

(AA and LC versions)

A13 TWC — 2 ms 93C46X/56X/66X/76X/86X

A14 TEC Program cycle time — 6 ms ERAL mode, 4.5V ≤ VCC ≤ 5.5V

A15 TWL — 15 ms WRAL mode, 4.5V ≤ VCC ≤ 5.5V

A16 — Endurance 1M — cycles 25°C, VCC = 5.0V, (Note 2)

Note 1: This parameter is periodically sampled and not 100% tested.

2: This application is not tested but ensured by characterization. For endurance estimates in a specific

applic ation, p lease co nsult t he Total Endura nce™ Mode l whi ch ma y be do wnlo aded fro m Microc hip’ s w eb

site at www.microc hip.com.

93XX46X/56X/66X/76X/86X

FIGU RE 2-1: SYNCH R ONO US DA TA T I MI NG

CS VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL

CLK

(Read)

(Program)

TCSS

TDIS

TCKH TCKL

TDIH

TPD

TCSH

TPD

TCZ

Status Valid

TSV

TCZ

Note: Status Valid Time (TSV) is relative to CS.

93XX46X/56X/66X/76X/86X

TABLE 2-4: INSTRUCTION SET FOR 93XX56A/B/C

TABLE 2-3: INSTRUCTION SET FOR 93XX46A/B/C

Instruction SB Opcode Address Data In Data Out Req.

CLK

Cycles

93XX46B OR 93XX46C WITH ORG = 1 (16-BIT WORD ORGANIZATION)

ERASE 1 11 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 9

ERAL 100 10xxxx — (RDY/BSY)9

EWDS 100 00xxxx —High-Z9

EWEN 100 11xxxx —High-Z9

READ 1 10 A5A4A3A2A1A0 — D15-D0 25

WRITE 1 01 A5 A4 A3 A2 A1 A0 D15-D0 (RDY/BSY)25

WRAL 100 01xxxxD15-D0 (RDY/BSY)25

93XX46A OR 93XX46C WITH ORG = 0 (8-BIT WORD ORGANIZATION)

ERASE 1 11 A6A5A4A3A2A1A0 — (RDY/BSY)10

ERAL 100 10xxxxx — (RDY/BSY)10

EWDS 100 00xxxxx —High-Z10

EWEN 100 11xxxxx —High-Z10

READ 1 10 A6A5A4A3A2A1A0 — D7-D0 18

WRITE 1 01 A6A5A4A3A2A1A0 D7-D0 (RDY/BSY

)18

WRAL 100 01xxxxxD7-D0 (RDY/BSY)18

Instruction SB Opcode Address Data In Data Out Req.

CLK

Cycles

93XX56B OR 93XX56C WITH ORG = 1 (16-BIT WORD ORGANIZATION)

ERASE 111 xA6 A5 A4 A3 A2 A1 A0 — (RDY/BSY)11

ERAL 100 10 xxxxxx — (RDY/BSY)11

EWDS 100 00 xxxxxx —High-Z11

EWEN 100 11 xxxxxx —High-Z11

READ 110 xA6 A5 A4 A3 S2 A1 A0 — D15-D0 27

WRITE 101 xA6 A5 A4 A3 S2 A1 A0 D15-D0 (RDY/BSY)27

WRAL 100 01 xxxxxxD15-D0 (RDY/BSY)27

93XX56A OR 93XX56C WITH ORG = 0 (8-BIT WORD ORGANIZATION)

ERASE 111 xA7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY)12

ERAL 100 10x xxxxxx — (RDY/BSY)12

EWDS 100 00x xxxxxx —High-Z12

EWEN 100 11x xxxxxx —High-Z12

READ 110 xA7 A6 A5 A4 A3 A2 A1 A0 — D7-D0 20

WRITE 101 xA7 A6 A5 A4 A3 A2 A1 A0 D7-D0 (RDY/BSY)20

WRAL 100 01x xxxxxxD7-D0 (RDY/BSY)20

93XX46X/56X/66X/76X/86X

TABLE 2-5: INSTRUCTION SET FOR 93XX66A/B/C

TABLE 2-6: INSTRUCTION SET FOR 93XX76A/B/C

Instruction SB Opcode Address Data In Data Out Req.

CLK

Cycles

93XX66B OR 93XX66C WITH ORG = 1 (16-BIT WORD ORGANIZATION)

ERASE 1 11 A7A6A5A4A3A2A1A0 — (RDY/BSY)11

ERAL 100 10xxxxxx — (RDY/BSY)11

EWDS 100 00xxxxxx —High-Z11

EWEN 100 11xxxxxx —High-Z11

READ 1 10 A7A6A5A4A3A2A1A0 — D15-D0 27

WRITE 1 01 A7A6A5A4A3A2A1A0 D15-D0 (RDY/BSY)27

WRAL 100 01xxxxxxD15-D0 (RDY/BSY)27

93XX66A OR 93XX66C WITH ORG = 0 (8-BIT WORD ORGANIZATION)

ERASE 1 11 A8A7A6A5A4A3A2A1A0 — (RDY/BSY)12

ERAL 100 10xxxxxxx — (RDY/BSY)12

EWDS 100 00xxxxxxx —High-Z12

EWEN 100 11xxxxxxx —High-Z12

READ 1 10 A8A7A6A5A4A3A2A1A0 — D7-D0 20

WRITE 1 01 A8A7A6A5A4A3A2A1A0 D7-D0 (RDY/BSY

)20

WRAL 100 01xxxxxxx D7-D0 (RDY/BSY)20

Instruction SB Opcode Address Data In Data Out Req.

CLK

Cycles

93XX76B OR 93XX76C WITH ORG = 1 (16-BIT WORD ORGANIZATION)

ERASE 111 xA8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY)13

ERAL 100 10xxxxxxxx — (RDY/BSY)13

EWDS 100 00xxxxxxxx —High-Z13

EWEN 100 11xxxxxxxx —High-Z13

READ 110 xA8 A7 A6 A5 A4 A3 A2 A1 A0 — D15-D0 29

WRITE 101 xA8 A7 A6 A5 A4 A3 A2 A1 A0 D15-D0 (RDY/BSY)29

WRAL 100 01xxxxxxxxD15-D0 (RDY/BSY)29

93XX76A OR 93XX76C WITH ORG = 0 (8-BIT WORD ORGANIZATION)

ERASE 111xA9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY)14

ERAL 1001 0xxxxxxxxx — (RDY/BSY)14

EWDS 1000 0xxxxxxxxx —High-Z14

EWEN 1001 1xxxxxxxxx —High-Z14

READ 110xA9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — D7-D0 22

WRITE 101xA9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7-D0 (RDY/BSY)22

WRAL 1000 1xxxxxxxxx D7-D0 (RDY/BSY)22

93XX46X/56X/66X/76X/86X

TABLE 2-7: INSTRUCTION SET FOR 93XX86A/B/C

Instructi on SB Opco de Addres s Dat a In Data Out Req.

CLK

Cycles

93XX86B OR 93XX86C WITH ORG = 1 (16-BIT WORD ORGANIZATION)

ERASE 1 11 A9A8A7A6A5A4A3A2A1A0 — (RDY/BSY)13

ERAL 100 10xxxxxxxx — (RDY/BSY)13

EWDS 100 00xxxxxxxx —High-Z13

EWEN 100 11xxxxxxxx —High-Z13

READ 1 10 A9A8A7A6A5A4A3A2A1A0 — D15-D0 29

WRITE 1 01 A9A8A7A6A5A4A3A2A1A0D15-D0(RDY/BSY)29

WRAL 100 01xxxxxxxxD15-D0 (RDY/BSY)29

93XX86A OR 93XX86C WITH ORG = 0 (8-BIT WORD ORGANIZATION)

ERASE 1 11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY)14

ERAL 1001 0xxxxxxxxx — (RDY/BSY)14

EWDS 1000 0xxxxxxxxx —High-Z14

EWEN 1001 1xxxxxxxxx —High-Z14

READ 1 10 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — D7-D0 22

WRITE 1 01 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7-D0 (RDY/BSY)22

WRAL 1000 1xxxxxxxxxD7-D0 (RDY/BSY)22

93XX46X/56X/66X/76X/86X

3.0 FUNCTIONAL DESCRIPTION

When the ORG pin is connected to VCC, the (x16)

organization is selected. When it is connected to

ground, the (x8) organization is selected. Instruc-

tions, addresses and write data are clocked into the

DI pin on the rising edge of the clock (CLK). The DO

pin is normally held in a High-Z state except when

reading data from the device, or when checking the

Ready/Busy status during a programming operation.

The Ready/Busy status can be verified during an

Erase/Wr ite operation by polling the DO pin; DO low

indicates that programming is still in progress, while

DO high indicates the device is ready. DO will enter

the High-Z state on the falling edge of CS.

3.1 Start Condition

The Start bit is detected by the device if CS and DI are

both high with respect to the positive edge of CLK for

the first time.

Before a Start condition is detected, CS, CLK and DI

may change in any combination (except to that of a

Start condition), without resulting in any device

operation (Read, Write, Erase, EWEN, EWDS, ERAL

or WRAL). As soon as CS is high, the device is no

longer in Standby mode.

An instruction following a Start condition will only be

execut ed if the required opcode, addr ess and data bit s

for any particular instruction are cloc ked in.

3.2 Data In/Data Out (DI/DO)

It is possible to connect the Data In and Data Out pins

together. However, with this configuration it is possible

for a “bus conflict” to occur during the “dummy zero”

that precedes the read operation, if A0 is a logic high

level. Under such a condition the voltage level seen at

Data Out is undefi ned and will depend upon the relative

impedances of Data Out and the signal source driving

A0. The higher the current sourcing capability of the

driver, the higher the voltage at the Data Out pin. In

order to limit this current, a resistor should be

connected between DI and DO.

3.3 Data Protection

All modes of operation ar e inhibited when VCC is below

a typical voltage of 1.5V for ‘93AAXX’ and ‘93LCXX’

devices or 3.8V for ‘93CXX’ devices.

The EWEN and EWDS commands give additional

protection against accidentally programming during

normal operation.

After power-up, the device is automatically in the

EWDS mode. Therefore, an EWEN instruction must be

performed before the initial ERASE or WRITE instruction

can be execu ted .

Block Diagram

Note: When preparing to transm it an i ns truc tion,

either the CLK or DI signal levels must be

at a logic low as CS is toggled active high.

Note: For added protection, an EWDS command

should be performed after every write

operation and an external 10 kΩ pull-down

protection resistor should be added to the

CS pin.

Note: To prevent accident al writes to the array in

the 93XX76C/86C devices, set the PE pin

to a logic low.

VCC

VSS HV Generator

EEPROM

Array

I/O Co n t r o l

Logic

Memory

Control

Logic

Dec Byte Latches

Y Decoder

Sense Amp.

R/W Control

CLK

ORG(1)

PE(2)

Note 1: ORG pin: Only on 93XX46C/56C/66C/76C/86C.

2: PE pin: Only on 93XX76C/86C.

93XX46X/56X/66X/76X/86X

3.4 ERASE

The ERASE instruction forces all data bits of the

specif ied addres s to the logic al ‘1’ state. CS is brought

low following the loading of the last address bit. This

falling edge of the CS pin initiates the self-timed

prog r am ming c yc le , e x ce pt on ‘ 9 3CX X’ d e vi ce s wh er e

the rising edge of CLK before the last address bit

init iate s the wr ite cy cl e.

The DO pin indicates the Ready/Busy status of the

device if CS is brought high after a minimum of 250 ns

low (TCSL). DO at logica l ‘0’ indicates that programming

is still in progress. DO at logical ‘1’ indicates that the

the device is ready for another instruction.

FIGU RE 3-1: ERASE T IMI NG FOR 93AAX X AND 93 LCX X DEVI CE S

FIGURE 3-2: ERASE TIMI NG FOR 93C XX DEVIC ES

Note: After the E rase cycl e is c omplet e, issu ing

a S t art bit and t hen ta king CS lo w will cle ar

the Ready/Busy status from DO.

CLK

TCSL

Check Status

111ANAN-1 AN-2 ••• A0

TSV TCZ

BUSY Ready High-Z

TWC

High-Z

CLK

TCSL

Check Status

111ANAN-1 AN-2 ••• A0

TSV TCZ

Busy Ready High-Z

TWC

High-Z

93XX46X/56X/66X/76X/86X

3.5 ERASE ALL (ERAL)

The Erase All (ERAL) instruction will erase the entire

memory array to the logical ‘1’ state. The ERAL cycle

is identical to the Erase cycle, except for the different

opcode. The ERAL cycle is completely self-timed and

commences at the falling edge of the CS, except on

‘93CXX’ devices where the rising edge of CLK before

the last data bit initiate s the writ e cycle. C lock ing of the

CLK pin is not necessary after the device has entered

the ERAL cycle.

The DO pin indicates the Ready/Busy status of the

device , if CS is brough t high a fter a mi nimum of 250 n s

low ( TCSL).

VCC must be ≥ 4.5V for proper operation of ERAL.

FIGURE 3-3: ERAL TIMING FOR 93AAXX AND 93LCXX DEVICES

FIGU RE 3-4: ERAL T IMIN G FOR 93 CXX DEV IC ES

Note: After the ERAL command is complete,

issuing a Start bit and then taking CS low

will clear the Ready/Busy status from DO.

CLK

TCSL

Check Status

100 10X••• X

TSV TCZ

Busy Ready High-Z

TEC

High-Z

Vcc must be ≥ 4.5V for proper operation of ERAL.

CLK

TCSL

Check Sta tus

10010X••• X

TSV TCZ

Busy Ready High-Z

TEC

High-Z

93XX46X/56X/66X/76X/86X

3.6 ERASE/WRITE DISABLE And

ENABLE (EWDS/EWEN)

The 93XX series devices power-up in the Erase/Write

Disable (EWDS) state. All programming modes must

be precede d by an Erase/W rite Enable (EWEN) instruc-

tion. Once the EWEN instruction is executed, program-

ming remains enabled until an EWDS instruction is

executed or VCC is removed from the device.

To protect against accidental data disturbance, the

EWDS instru ct ion c an be used to d isabl e all Erase/ Wri te

functions and should follow all programming

operations. Execution of a READ instruction is

independent of both the EWEN and EWDS instructions.

FIGURE 3-5: EWDS TIMING

FIGURE 3-6: EWEN TIMING

CLK

DI 10

000x ••• x

TCSL

CLK

DI 00 1 1x

TCSL

•••

93XX46X/56X/66X/76X/86X

3.7 READ

The READ instruction outputs the serial data of the

addressed memory location on the DO pin. A dummy

zero bit precedes the 8-bit (If ORG pin is low or A-version

devices) or 16-bit (If ORG pin is high or B-version

devic es) ou tput st ring. The outpu t da ta bi ts will togg le on

the r is in g e dg e of the CLK and ar e s t ab le after the spec -

ified time dela y (TPD). Sequ enti al r ead is p ossi ble w hen

CS is held high. The memory data will automatically cycle

to the next register and output sequentially.

FIGU RE 3- 7 : READ TIMING

CLK

110

An ••• A0

High-Z 0Dx ••• D0 Dx ••• D0 •••

Dx D0

93XX46X/56X/66X/76X/86X

3.8 WRITE

The WRITE instruction is followed by 8 bits (If ORG is

low or A-v ersi on device s) or 16 b its (If OR G pi n is hig h

or B-versi on devices) of data whi ch are writt en into th e

specified address. For 93AAXX and 93LCXX devices,

after the last data bit is clocked into DI, the fal ling edge

of CS initiates the self-timed auto-erase and program-

ming cycle. For 93CXX devices, the self-timed auto-

erase and programming cycle is initiated by the rising

edge of CLK on the last data bit.

The DO pin indicates the Ready/Busy status of the

device , if CS is brough t high a fter a mi nimum of 250 n s

low (TCSL). DO at logica l ‘0’ indicates that programming

is still in progress. DO at logical ‘1’ indicates that the

the data specified and the devi ce is ready for another

instruction.

FIGURE 3-8: W RITE TIMI NG FOR 93AAXX AND 93LCXX DEVICES

FIGURE 3-9: WRITE T IMI NG FOR 9 3CXX DEVI CES

Note: For devices with PE functionality such as

the 93XX76C or 93XX86C, the write

sequence requires a logic high signal on

the PE pin prior to the rising edge of cl oc k

on the last data bit.

Note: Aft er the W rite cy cle is c omplete, issuing a

Start bit and then taking CS low will clear

the Ready/Busy status from DO.

CLK

101An ••• A0 Dx ••• D0

Busy Ready High-Z

High-Z

Twc

TCSL

TCZ

TSV

CLK

101An ••• A0 Dx ••• D0

Busy Ready High-Z

High-Z

Twc

TCSL

TCZ

TSV

93XX46X/56X/66X/76X/86X

3.9 WRITE ALL (WRAL)

The Write All (WRAL) instruction will write the entire

memory array with the data specified in the command.

For 93AAXX and 93LCXX devices, after the last data

bit is clock ed in to DI, th e fall ing ed ge of CS in itiates the

self-timed auto-erase and programming cycle. For

93CXX devices, the self-timed auto-erase and pro-

grammi ng cycle is initiated by the rising edge of CLK on

the last data bit. Clocking of the CLK pin is not neces-

sary afte r the dev ice has ent ered the WRAL cy cle. Th e

WRAL command does include an automatic ERAL

cycle for the device. Therefore, the WRAL instruction

does not requ ire an ERAL instruction, but the chip must

be in the EWEN status.

The DO pin indicates the Ready/Busy status of the

device if CS is brought high after a minimum of 250 ns

low ( TCSL).

VCC must be ≥ 4.5V for proper operation of WRAL.

FIGURE 3-10: WRAL TIMING FOR 93AAXX AND 93LCXX DEVICES

FIGURE 3-11: WRAL TIMING FOR 93CXX DEVICES

Note: For devices with PE functionality such as

the 93XX76C or 93XX86C, the write

sequence requires a logic high signal on

the PE pin prior to the rising edge of cloc k

on the last data bit.

Note: After the Write All cycle is complete,

issuing a Start bit and then taking CS low

will clear the Ready/Busy status from DO.

CLK

DO HIGH-Z

10001 X••• xDx ••• D0

High-Z Busy Ready

TWL

VCC must be ≥ 4.5V for proper operation of WRAL.

TCSL

TSV TCZ

CLK

DO HIGH-Z

10001 X••• xDx ••• D0

High-Z Busy Ready

TWL

TCSL

TSV TCZ

93XX46X/56X/66X/76X/86X

4.0 PIN DESCRIPTIONS

TABLE 4-1: PIN DESCRIPTIONS

4.1 Chip Select (CS)

A high level selects the device; a low level deselects

the dev ice and fo rces it i nto S t andby mode. H owever , a

progra mmin g c yc le which is already i n pro gres s will be

completed, regardless of the Chip Select (CS) input

signal . I f C S is brou gh t low during a p rogra m c ycle, th e

device will go into Standby mode as soon as the

programming cycle is completed.

CS must be low for 250 ns minimum (TCSL) between

consecutive instructions. If CS is low, the internal

control logic is held in a Reset status.

4.2 Serial Clock (CLK)

The Serial Clock is used to synchronize the communi-

cation between a master device and the 93XX series

device. Opcodes, address and data bits are clocked in

on the pos itive edge of CL K. Dat a bit s are also c locke d

out on the positive edge of CLK.

CLK can be stopped anywhere in the transmission

sequence (at high or low level) and can be continued

anytime with respect to Clock High Time (TCKH) and

Clock Low Tim e (TCKL). Thi s g iv es the co ntro lli ng mas-

ter freedom in preparing opcode, address and data.

CLK is a “don't care” if CS is l ow (devic e desele cted). If

CS is high, but the Start condition has not been

detected (DI = 0), any number of clock cycles can be

received by the device without changing its status (i.e.,

waiting for a Start conditio n).

CLK cycles are not required during the self-timed Write

(i.e., auto Erase/Write) cycle.

After detec tion of a S tart condition the spe cified number

of clock cycles (respectively low-to-high transitions of

CLK) must be provided. These clock cycles are

required to clock in all required opcode, address and

dat a bits before an in stru ct ion is executed. CL K and DI

then bec om e “do n't care” inputs wa iti ng fo r a ne w Start

condition to be detected.

4.3 Data In (DI)

Data In (DI) is used to clock in a Start bit, opcode,

address and data synchronously with the CLK input.

4.4 Data Out (DO)

Dat a Out (DO) is used in the Re ad mode to ou tput dat a

synchronously with the CLK input (TPD after the

positive edge of CLK).

This pin also provides Ready/Busy status information

during Erase and Write cycles. Ready/Busy status

information is available on the DO pin if CS is brought

high after bein g low for minimum Chip Sele ct Low T ime

(TCSL) and an erase or write operation has been

initiated.

The Status signal is not available on DO, if CS is held

low during th e entire Erase or Write cycle . In thi s cas e,

DO is in the High -Z mode. If sta tus is check ed after th e

Erase/Write cycle, the data line will be high to indicate

the device is ready.

Name SOIC/PDIP/MSOP/

TSSOP/DFN SOT-23 Function

CS 1 5 Chip Select

CLK 2 4 Serial Clock

DI 3 3 Data In

DO 4 1 Data Out

VSS 5 2 Ground

ORG 6N/A

Organization (93XX46C/56C/66C/76C/86C)

NC(1) No connect on 93XXA/B devices

PE 7N/A

Program Enable (93XX7 6C/8 6C )

NC(1) No connect on 93XXA/B devices

VCC 8 6 Power Supply

Note 1: With no internal connection, logic levels on NC pins are “don’t cares.”

Note: Aft er the Read cy cle is comp lete, issuing a

Start bit and then taking CS low will clear

the Ready/Busy status from DO.

93XX46X/56X/66X/76X/86X

4.5 Organization (ORG)

When the ORG pin i s connected to VCC or Log ic HI, the

(x16) mem ory organiza tion is se lected. Whe n the ORG

pin is tied to VSS or Logic LO, the (x8) memory

organization is selected. For proper operation, ORG

must be tied to a valid logic level.

For devices without the ORG functionality, there is no

internal connection to the ORG pin. In these devices

the functionality has been set at the factory to support

a single word size.

‘A’ series devices – x8 organization

‘B’ series devices – x16 organization

4.6 Program Enable (PE)

A logic level on the PE pin will enable or disable the abil-

ity to w rite d ata to the memor y ar ray in only th e 8-l ead

93XX7 6C and 93XX86C devi ces. Fo r all ot her dev ices

the PE function is not present and the PE pin is a no

connect. When driving the PE pin to a logic High, the

device can be programmed, but when the PE pin is

driven L ow, progr amming is in hibited. Thi s pin is used

in parallel with the EWEN/EWDS latch to protect the

memory array from inadvertent writes, as shown in

Table 4-2.

In eithe r the 93XX76C or 93XX86 C device s, the PE pi n

must be tied to a specific logic level and cannot be

floated. In all other dev ices witho ut the PE function, th e

PE pin has no internal connections and prog ramming is

always enabled.

TABLE 4-2: WRITE PROTECTION SCHEME

EWEN/EWDS Latch PE Pin* Array WRITE

Enabled 1Yes

Disabled 1No

Enabled 0No

Disabled 0No

* PE pin level does not alter the state of the EWEN/EWDS latch.

Note: For de vice s wi th PE fun ctiona lity such as 93XX 76C o r 93XX86 C, the writ e sequ ence require s a lo gic hi gh

signal on the PE pin prior to the rising edge of clock on the last data bit.

93XX46X/56X/66X/76X/86X

APPENDIX A: REVISION HISTORY

Revision A

Original release of document. Combined all the 93-Series

Microwire Serial EEPROM device data sheets.

Revision B

Revised 2x3 (MC) DFN package drawing.

Revision C

Correction to Table 2-6, 93XX76A (EWDS).

Revision D (03/2007)

Revised Description; Delete Pb-free notes; Replaced

Package Drawings; Revised Product ID System.

93XX46X/56X/66X/76X/86X

5.0 PACKAGING INFORMATION

5.1 Package Marking Information

TXXXXNNN

XXXXXXXX

YYWW

8-Lead PDIP

I/P IL7

93LC46A

0528

Example: Pb-free

3-Wir e 8-L ead PDIP Package Mar kin g

Part Line 1 Marking Part Line 1 Marking Part Line 1 Marking

93AA46A 93AA46A 93LC46A 93LC46A 93C46A 93C46A

93AA46B 93AA46B 93LC46B 93LC46B 93C46B 93C46B

93AA46C 93AA46C 93LC46C 93LC46C 93C46C 93C46C

93AA56A 93AA56A 93LC56A 93LC56A 93C56A 93C56A

93AA56B 93AA56B 93LC56B 93LC56B 93C56B 93C56B

93AA56C 93AA56C 93LC56C 93LC56C 93C56C 93C56C

93AA66A 93AA66A 93LC66A 93LC66A 93C66A 93C66A

93AA66B 93AA66B 93LC66B 93LC66B 93C66B 93C66B

93AA66C 93AA66C 93LC66C 93LC66C 93C66C 93C66C

93AA76A 93AA76A 93LC76A 93LC76A 93C76A 93C76A

93AA76B 93AA76B 93LC76B 93LC76B 93C76B 93C76B

93AA76C 93AA76C 93LC76C 93LC76C 93C76C 93C76C

93AA86A 93AA86A 93LC86A 93LC86A 93C86A 93C86A

93AA86B 93AA86B 93LC86B 93LC86B 93C86B 93C86B

93AA86C 93AA86C 93LC86C 93LC86C 93C86C 93C86C

Note: Temperature range on second line.

Legend: XX...X Part number or part number code

T Temperature (I, E)

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn)

Note: For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

Note: In the even t the full Microchi p part number c annot be marked on one lin e, it will

be carried over to the next line, thus limiting the number of available

characte rs fo r customer-specific informat ion.

93XX46X/56X/66X/76X/86X

8-Lead SOIC

XXXXYYWW

XXXXXXXT

NNN

Example: Pb-free

SN 0528

93LC46AI

1L7

3-Wire 8-Lead SOIC (SN) Package Marking

Part Line 1 Marking Part Line 1 Marking Part Line 1 Marking

93AA46A 93AA46AT 93LC46A 93LC46AT 93C46A 93C46AT

93AA46B 93AA46BT 93LC46B 93LC46BT 93C46B 93C46BT

93AA46C 93AA46CT 93LC46C 93LC46CT 93C46C 93C46CT

93AA56A 93AA56AT 93LC56A 93LC56AT 93C56A 93C56AT

93AA56B 93AA56BT 93LC56B 93LC56BT 93C56B 93C56BT

93AA56C 93AA56CT 93LC56C 93LC56CT 93C56C 93C56CT

93AA66A 93AA66AT 93LC66A 93LC66AT 93C66A 93C66AT

93AA66B 93AA66BT 93LC66B 93LC66BT 93C66B 93C66BT

93AA66C 93AA66CT 93LC66C 93LC66CT 93C66C 93C66CT

93AA76A 93AA76AT 93LC76A 93LC76AT 93C76A 93C76AT

93AA76B 93AA76BT 93LC76B 93LC76BT 93C76B 93C76BT

93AA76C 93AA76CT 93LC76C 93LC76CT 93C76C 93C76CT

93AA86A 93AA86AT 93LC86A 93LC86AT 93C86A 93C86AT

93AA86B 93AA86BT 93LC86B 93LC86BT 93C86B 93C86BT

93AA86C 93AA86CT 93LC86C 93LC86CT 93C86C 93C86CT

Note: T = Temperature Range: I = Industrial, E = Extended

Legend: XX...X Part number or part number code

T Temperature (I, E)

Y Year code (last digit of calendar year)

YY Year code (las t 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn)

Note: For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

Note: In the event the full Microc hip p ar t numbe r cannot be marke d on one li ne, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

93XX46X/56X/66X/76X/86X

3-Wire 2x3 DFN Package Marking

Part Industrial

Line 1

Marking

E-Temp

Line 1

Marking Part Industrial

Line 1

Marking

E-T emp

Line 1

Marking Part Industrial

Line 1

Marking

E-Temp

Line 1

Marking

93AA46A 301 302 93LC46A 304 305 93C46A 307 308

93AA46B 311 312 93LC46B 314 315 93C46B 317 318

93AA46C 321 322 93LC46C 324 325 93C46C 327 328

93AA56A 331 332 93LC56A 334 335 93C56A 337 338

93AA56B 341 342 93LC56B 344 345 93C56B 347 348

93AA56C 351 352 93LC56C 354 355 93C56C 357 358

93AA66A 361 362 93LC66A 364 365 93C66A 367 368

93AA66B 371 372 93LC66B 374 375 93C66B 377 378

93AA66C 381 382 93LC66C 384 385 93C66C 387 388

93AA76C 3B1 3B2 93LC76C 3B4 3B5 93C76C 3B7 3B8

93AA86C 3E1 3E2 93LC86C 3E4 3E5 93C86C 3E7 3E8

8-Lead 2x3 DFN Example:

304

506

XXX

YWW

Legend: XX...X Part number or part number code

T Temperature (I, E)

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn)

Note: For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

Note: In the even t the full Microchip part number c annot be marked on one line, it wil l

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

93XX46X/56X/66X/76X/86X

Example:

6-Lead SOT-23

XXNN 1EL7

3-Wire 6-Lead SOT-23 Package Mar king

Part Industrial

Line 1

Marking

E-Temp

Line 1

Marking Part Industrial

Line 1

Marking

E-Temp

Line 1

Marking Part Industrial

Line 1

Marking

E-Temp

Line 1

Marking

93AA46A 1BNN 1CNN 93LC46A 1ENN 1FNN 93C46A 1HNN 1JNN

93AA46B 1LNN 1MNN 93LC46B 1PNN 1RNN 93C46B 1TNN 1UNN

93AA56A 2BNN 2CNN 93LC56A 2ENN 2FNN 93C56A 2HNN 2JNN

93AA56B 2LNN 2MNN 93LC56B 2PNN 2RNN 93C56B 2TNN 2UNN

93AA66A 3BNN 3CNN 93LC66A 3ENN 3FNN 93C66A 3HNN 3JNN

93AA66B 3LNN 3MNN 93LC66B 3PNN 3RNN 93C66B 3TNN 3UNN

93AA76A 4BNN 4CNN 93LC76A 4ENN 4FNN 93C76A 4HNN 4JNN

93AA76B 4LNN 4MNN 93LC76B 4PNN 4RNN 93C76B 4TNN 4UNN

93AA86A 5BNN 5CNN 93LC86A 5ENN 5FNN 93C86A 5HNN 5JNN

93AA86B 5LNN 5MNN 93LC86B 5PNN 5RNN 93C86B 5TNN 5UNN

Legend: XX...X Part number or part number code

T Temperature (I, E)

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn)

Note: For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

Note: In the event the full Mi croch ip p art numb er canno t be mark ed on one l ine, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

93XX46X/56X/66X/76X/86X

3-Wire 8-Lead MSOP Package Marking

Part Line 1 Marking Part Line 1 Marking Part Line 1 Marking

93AA46A 3A46AT 93LC46A 3L46AT 93C46A 3C46AT

93AA46B 3A46BT 93LC46B 3L46BT 93C46B 3C46BT

93AA46C 3A46CT 93LC46C 3L46CT 93C46C 3C46CT

93AA56A 3A56AT 93LC56A 3L56AT 93C56A 3C56AT

93AA56B 3A56BT 93LC56B 3L56BT 93C56B 3C56BT

93AA56C 3A56CT 93LC56C 3L56CT 93C56C 3C56CT

93AA66A 3A66AT 93LC66A 3L66AT 93C66A 3C66AT

93AA66B 3A66BT 93LC66B 3L66BT 93C66B 3C66BT

93AA66C 3A66CT 93LC66C 3L66CT 93C66C 3C66CT

93AA76A 3A76AT 93LC76A 3L76AT 93C76A 3C76AT

93AA76B 3A76BT 93LC76B 3L76BT 93C76B 3C76BT

93AA76C 3A76CT 93LC76C 3L76CT 93C76C 3C76CT

93AA86A 3A86AT 93LC86A 3L86AT 93C86A 3C86AT

93AA86B 3A86BT 93LC86B 3L86BT 93C86B 3C86BT

93AA86C 3A86CT 93LC86C 3L86CT 93C86C 3C86CT

Note: T = Temperature Range: I = Industrial, E = Extended

8-Lead MSOP (150 mil) Example:

XXXXXXT

YWWNNN 3L46AI

5281L7

Legend: XX...X Part number or part number code

T Temperature (I, E)

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn)

Note: For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

Note: In the eve nt the full Microchi p part number c annot be marked on one lin e, it will

be carried over to the next line, thus limiting the number of available

characte rs fo r customer-specific informat ion.

93XX46X/56X/66X/76X/86X

NNN

XXXX

TYWW

8-Lead TSSOP

1L7

L46A

I528

Example:

3-Wire 8-Lead TSSOP Package Marking

Part Line 1 Markin g Part Line 1 Marking Part Line 1 Markin g

93AA46A A46A 93LC46A L46A 93C46A C46A

93AA46B A46B 93LC46B L46B 93C46B C46B

93AA46C A46C 93LC46C L46C 93C46C C46C

93AA56A A56A 93LC56A L56A 93C56A C56A

93AA56B A56B 93LC56B L56B 93C56B C56B

93AA56C A56C 93LC56C L56C 93C56C C56C

93AA66A A66A 93LC66A L66A 93C66A C66A

93AA66B A66B 93LC66B L66B 93C66B C66B

93AA66C A66C 93LC66C L66C 93C66C C66C

93AA76A A76A 93LC76A L76A 93C76A C76A

93AA76B A76B 93LC76B L76B 93C76B C76B

93AA76C A76C 93LC76C L76C 93C76C C76C

93AA86A A86A 93LC86A L86A 93C86A C86A

93AA86B A86B 93LC86B L86B 93C86B C86B

93AA86C A86C 93LC86C L86C 93C86C C86C

Note: Temperature range on second line.

Legend: XX...X Part number or part number code

T Temperature (I, E)

Y Year code (last digit of calendar year)

YY Year code (las t 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn)

Note: For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

Note: In the event the full Microc hip p ar t numbe r cannot be marke d on one li ne, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

93XX46X/56X/66X/76X/86X

8-Lead Plastic Dual In-Line (P or PA) – 300 mil Body [PDIP]

otes:

. Pin 1 visual index feature may vary, but must be located with the hatched area.

. § Significant Characteristic.

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units INCHES

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e .100 BSC

Top to Seating Plane A – – .210

Molded Package Thickness A2 .115 .130 .195

Base to Seating Plane A1 .015 – –

Shoulder to Shoulder Width E .290 .310 .325

Molded Package Width E1 .240 .250 .280

Overall Length D .348 .365 .400

Tip to Seating Plane L .115 . 130 .150

Lead Thickness c .008 .010 .015

Upper Lead Width b1 .040 .060 .070

Lower Lead Width b .014 .018 .022

Overall Row Spacing § eB – – .430

NOTE 1

Microchip Technology Drawing C04-018

93XX46X/56X/66X/76X/86X

8-Lead Plastic Small Outl ine (SN or OA) – Narrow, 3.90 mm Body [SOIC]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e 1.27 BSC

Overall Height A – – 1.75

Molded Package Thickness A2 1.25 – –

Standoff §A1 0.10 – 0.25

Overall Width E 6.00 BSC

Molded Package Width E1 3.90 BSC

Overall Length D 4.90 BSC

Chamfer (optional) h 0.25 – 0.50

Foot Length L 0.40 – 1.27

Footprint L1 1.04 REF

Foot Angle φ0° – 8°

Lead Thickness c 0.17 – 0.25

Lead Width b 0.31 – 0.51

Mold Draft Angle Top α5° – 15°

Mold Draft Angle Bottom β5° – 15°

NOTE 1

12 3

Microchip Technology Drawing C04-057

93XX46X/56X/66X/76X/86X

8-Lead Plastic Dual Fla t, No Lead Package (MC) – 2x3x0.9 mm Body [DFN]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. Package may have one or more exposed tie bars at ends.

. Package is saw singulated.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimens ion, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e 0.50 BSC

Overall Height A 0.80 0.90 1.00

Standoff A1 0.00 0.02 0.05

Contact Thickness A3 0.20 REF

Overall Length D 2.00 BSC

Overall Width E 3.00 BSC

Exposed Pad Length D2 1.30 – 1. 75

Exposed Pad Width E2 1.50 – 1.90

Contact Width b 0.18 0.25 0.30

Contact Length L 0.30 0.40 0.50

Contact-to-Exposed Pad K 0.20 – –

NOTE 1

EXPOSED PAD

NOTE 1

A3A1

NOTE 2

BOTTOM VIEW

TOP VIEW

Microchip Technology Drawing C04-123

93XX46X/56X/66X/76X/86X

6-Lead Plastic Small Outline Transistor (CH or OT) [SOT-23]

otes:

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 6

Pitch e 0.95 BSC

Outside Lead Pitch e1 1.90 BSC

Overall Height A 0.90 – 1.45

Molded Package Thickness A2 0.89 – 1.30

Standoff A1 0.00 – 0.15

Overall Width E 2.20 – 3.20

Molded Package Width E1 1.30 – 1.80

Overall Length D 2.70 – 3.10

Foot Length L 0.10 – 0.60

Footprint L1 0.35 – 0.80

Foot Angle φ0° – 30°

Lead Thickness c 0.08 – 0.26

Lead Width b 0.20 – 0.51

PIN 1 ID BY

LASER MARK

123

A2 c

Microchip Technology Drawing C04-028

93XX46X/56X/66X/76X/86X

8-Lead Plastic Micro Small Outline Package (MS or UA) [MSOP]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e 0.65 BSC

Overall Height A – – 1.10

Molded Package Thickness A2 0.75 0.85 0.95

Standoff A1 0.00 – 0.15

Overall Width E 4.90 BSC

Molded Package Width E1 3.00 BSC

Overall Length D 3.00 BSC

Foot Length L 0.40 0.60 0.80

Footprint L1 0.95 REF

Foot Angle φ0° – 8°

Lead Thickness c 0.08 – 0.23

Lead Width b 0.22 – 0.40

NOTE 1

L1 L

Microchip Technology Drawing C04-111

93XX46X/56X/66X/76X/86X

8-Lead Plastic Thin Shri nk Small Outline (ST) – 4.4 mm Body [TSSOP]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimen sion, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e 0.65 BSC

Overall Height A – – 1.20

Molded Package Thickness A2 0.80 1.00 1.05

Standoff A1 0.05 – 0.15

Overall Width E 6.40 BSC

Molded Package Width E1 4.30 4.40 4.50

Molded Package Length D 2.90 3.00 3.10

Foot Length L 0.45 0.60 0.75

Footprint L1 1.00 REF

Foot Angle φ0° – 8°

Lead Thickness c 0.09 – 0.20

Lead Width b 0.19 – 0.30

NOTE 1

L1 L

Microchip Technology Drawing C04-086

93XX46X/56X/66X/76X/86X

NOTES:

93XX46X/56X/66X/76X/86X

THE MICROCHIP WEB SITE

Microc hip pro vides onl ine s upport v ia our W WW site at

www.microchip.c om . Thi s web si te i s us ed as a m ean s

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

•Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

docume nts , latest softw are releas es and archived

software

•General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online dis cu ss io n gr oups, Microchip con sultant

program member listing

•Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing o f seminars and ev ents, l istings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specif ied produ ct family or develo pment tool of interes t.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

CUSTOMER SUPPORT

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Development Systems Information Line

Customers should contact their distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

Technical suppo rt is avail able throug h the web si te

at: http://support.microchip.com

93XX46X/56X/66X/76X/86X

READER RESPONSE

It is ou r intention to pro vi de you w it h th e b es t do cumentation po ss ib le to ensure succes sfu l u se of y ou r M ic roc hip prod-

uct. If you wi sh to prov ide you r comment s on org anizatio n, clar ity, subject matter, and ways i n whic h our doc umenta tion

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To: Technical Publications Manager

RE: Reader Response Total Pages Sent ________

From: Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

Application (optional):

Would you like a reply? Y N

Device: Literature Number:

Questions:

FAX: (______) _________ - _________

DS21929D93XX46X/56X/66X/76X/86X

1. Wha t are the best features of t his document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

93XX46X/56X/66X/76X/86X

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

a) 93AA46A-I/MS: 1K, 128x8 Serial EEPROM,

Industrial Temperature, MSOP package, 1.8V

b) 93AA46BT-I/OT: 1K, 64x16 Serial EEPROM,

SOT-23 package, tape and re el, 1.8V

c) 93AA46CT-I/MS: 1K, 128x8 or 64x16 Serial

EEPROM, MSOP package, t ape and reel, 1.8V

d) 93AA46BX-I/SN: 1K, 128x8 Serial EEPROM,

Industrial temperature, SOIC package (alter-

nate pinout), tape and reel package, 1.8V

e) 93LC66A-I/MS: 4K, 512x8 Serial EEPROM,

MSOP package, 2. 5V

f) 93LC66BT-I/OT: 4K, 256x16 Serial EEPROM,

SOT-23 package, tape and re el, 2.5V

g) 93C86AT-I/OT: 16K, 2048x8 Serial EEPROM,

SOT-23 package, tape and re el, 5.0V

h) 93C86BT -I/OT: 16K, 1024x16 Serial EEPROM,

SOT-23 package, tape and re el, 5.0V

i) 93C86CT-I/MC: 16K, 2048x8 or 1024x16

Serial EEPROM, DFN Industrial temperature,

tape and reel package, 5.0V

EEPROM Package

Tape &

Reel

Series Voltage

Density Size

Word Temp

Range

AA = 1.8V -5.5V

LC = 2.5V- 5.5V

C = 4.5V-5.5V

46 = 1 Kbit

56 = 2 Kbit

66 = 4 Kbit

76 = 8 Kbit

86 = 16 Kbit

A = x8 bit

B = x16 bit

C = Selectable

Blank = Std Pkg

T = Tape & Reel

I = -40°C to +85°C

E = -40°C to +125°C

P = 8-Lead PDIP

SN = 8-Lead SOIC (3.90 mm)

MC = 8-Lead 2x3 DFN

CH or OT = 6-Lead SOT- 23

MS = 8-Lead MSOP

ST = 8-Lead TSSOP

93XX46X/56X/66X/76X/86X

NOTES:

Information contained in this publication regarding device

applications a nd t he like is p ro vided on ly f or yo ur conve nience

and may be su persed ed by upda t es . I t is y our responsibil ity to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PI C,

PICmic ro, PI C START, PR O MATE, PowerSmart, rfP IC , and

SmartShunt are registered trademark s of Microchip

Tec hnology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable

Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartS ensor

and The Embedded Control Solutions Company are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,

MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInf o, PowerMate, PowerTool, REAL ICE, rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that i t s family of products is one of the most secure families of it s kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microchip are committed to continuously improving t he c ode protect ion f eatures of our

products. Attempts to break Microchip’ s code protection f eature may be a violati on of t he Digit al Millennium Copyright Act. If such act s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

T empe, Arizona, Gresham, Oregon and Mountain View, California. The

Company’s quality system processes and procedures are for its PIC®

MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

AMERICAS

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EUROPE

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WORLDWIDE SALES AND SERVICE

12/08/06